Error Detection and Correction Method for Timing Errors in Registers

Indian Journal of Natural Sciences www.tnsroindia.org.in ©IJONS Vol.10 / Issue 57 / December / 2019 International Bimonthly ISSN: 0976 – 0997 RESEARCH ARTICLE Error Detection and Correction Method for Timing Errors in Registers M.Revathy1*, PN.Sundararajan1 and M.Kasthuri2 1Associate Professor, Department of ECE, PSNA College of Engineering and Technology, Dindigul, Tamilnadu, India. 2Assistant Professor Department of ECE, PSNA College of Engineering and Technology, Dindigul, Tamilnadu, India. Received: 31 Aug 2019 Revised: 02 Oct 2019 Accepted: 04 Nov 2019 *Address for Correspondence M.Revathy Associate Professor, Department of ECE, PSNA College of Engineering and Technology, Dindigul, Tamilnadu, India. Email:[email protected] This is an Open Access Journal / article distributed under the terms of the Creative Commons Attribution License (CC BY-NC-ND 3.0) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. All rights reserved. ABSTRACT Timing errors are an important concern in nanometer CMOS technologies. A promising way to overcome the timing errors is the development of error detection and correction techniques in registers. Normally timing failures occur in high complexity and high frequency integrated circuits. The reason behind this timing failures are test escapes, environmental conditions, operating conditions and process variations. A local error detection and correction technique is done in this work. It is based on a new bit flipping flip flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip flop. The addition of a multiplexer and a NOT gate replaces the need of an extra latch and an EX-OR gate in the modified EDC technique. An external OR gate indicates the presence of error in the registers. No extra memory element like latch is required here. This reduction in the elements of the circuit leads to the reduction of silicon area overhead and performance degradation is negligible. No extra circuitry is inserted in the design. Timing errors are identified and corrected within a single cycle and hence design complexity is reduced which results in reduced power consumption and low silicon area. The modified EDC technique is simulated using Modelsim 6.5b and synthesized using Xilinx ISE suite 12.1. Keywords: Multiplexer, EDC techniques, NOT gate, EX-OR gate, OR gate, registers, Timing errors, Flipflop. Coupling noise, Power supply disturbance, Jitter, Temperature fluctuations. 17763 Indian Journal of Natural Sciences www.tnsroindia.org.in ©IJONS Vol.10 / Issue 57 / December / 2019 International Bimonthly ISSN: 0976 – 0997 Revathy et al. INTRODUCTION Error occurs mainly due to CMOS technology scaling, process variations, various performance degradation mechanism, power supply reduction and increasing complexity that affect the reliability. Various mechanisms like coupling noise, power supply disturbance, jitter and temperature fluctuations are reasons for timing error generation. Transistor aging mechanisms significantly affect the performance of nanometer circuits, which results in the appearance of timing errors continuously. Negative – Positive Bias Temperature Instability (NBTI-PBTI) and hot carrier injection (HCI) degrade transistors’ threshold voltage over time increasing signal propagation delays and consequently timing error rate (1). Path delay deviations occurred due to process deviations and manufacturing defects affect the circuit speed also result in timing errors which are not easily detectable in high device count integrated circuits. EVOLUTION OF TESTING In the early times of electronics engineering, systems were composed of discrete components, testing of digital systems comprised of three distinct phases. They are: 1. Each discrete component was tested for concordance to its specifications 2. The components were assembled into more complex digital elements (i.e. flip flops etc.), and these are tested for correct functionality Testing and Built in Self Test 3. The higher level system was built up and was tested for functionality. The first applications of the structural test was discrete components on Printed Circuit Boards (PCBs), which then began to be applied to ICs as the electronics technology developed into higher levels of integration (2). Though the problems of IC testing was not very much different from that of the PCBs, the objective of testing had then changed to discard the faulty units rather than locating the defective components and replace them. In the case of Small Scale Integration (SSI) and Medium Scale Integration (MSI), the problems were relatively as simple as PCB testing, since: 1. Internal nodes of the devices were easily controlled and observed from the primary inputs and outputs of the devices 2. The simplicity of circuit functions permitted the use of exhaustive testing. 3. More complex systems were constructed from basic, thoroughly tested components. TYPES OF TESTING Without testing both prior to final installation and once installed onto a circuit board many devices would cease functioning earlier than the expected life spans. There are two main categories of IC testing, They are: 1. Functional testing. 2. Structural testing. Functional Testing The time required to verify anything more than logic functionally is beyond practical limits in terms of ATE time, cost of the chip etc. Also, the quality of test solution (i.e., proper binning of normal and faulty chips) is acceptable for almost all classes of circuits. This is called Functional Testing. Before structural testing was proposed, digital systems were tested to verify their compilance with their intended functionality, i.e. in this philosophy, a multiplier would be tested whether it would multiply and so forth (3). This testing of philosophy is termed as functional testing, which 17764 Indian Journal of Natural Sciences www.tnsroindia.org.in ©IJONS Vol.10 / Issue 57 / December / 2019 International Bimonthly ISSN: 0976 – 0997 Revathy et al. can be defined as, applying a series of determined meaningful inputs to check for the correct output responses in terms of the device functionality. Although this methodology imparts a good notion of circuit functionality, under the presence of a definitive fault model, it is very difficult to isolate certain faults in the circuits in order to verify their detection. Structural Testing Functional Testing cannot be performed due to extremely high testing time to solve this issue we perform Structural Testing, which takes many fold less time compared Functional Testing yet maintaining the quality of test solution. The Structural testing, introduced by Eldred, verifies the correctness of the specific structure of the circuit in terms of gates and interconnects (4). In other Word Structural testing does not check the functionality of the entire circuit rather verifies if all the structural units (gates) are fault free. So structural testing is a kind of functional testing at unit (gate) level with the proposal of structural testing, which might be defined as, consideration of possible faults that may occur in a digital circuit and applying a set of inputs tailored for detecting these specified faults. As obvious structural testing relies on the fault Testing and Built in Self Test models described for the Device Under Test (DUT), and any result obtained in this manner is unworthy without a proper description of used fault models. Related Works Various mechanisms like 1. Coupling noise 2. Power supply disturbance 3. Jitter 4. Temperature fluctuations are accused for timing error generation. Path delay deviations, due to process variations, and manufacturing defects that affect circuit speed may also result in timing errors that are not easily detectable in high device count ICs. Detection and Correction of Timing Errors in Registers Timing errors are an increasing reliability concern in Nanometer technology, high complexity and multi voltage/ frequency integrated circuits. A local error detection and correction technique is presented in this work that is based on a new bit flipping flip-flop (5). Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip-flop. The EDC technique is characterized by very low silicon area and power requirements compared to previous design schemes in the open literature. The new Error Detection / Correction Flip-Flop (EDC Flip-Flop) that is suitable to confront with timing errors. Apart from the original flip flop (Main Flip-Flop), it consists of two XOR gates and a Latch. The first XOR gate compares the input and the F output of the Main Flip-Flop and provides the result to the Latch. The Latch feeds the second XOR gate at the output of the Main Flip-Flop. Depending on the comparison result within a specified time interval, either the F signal of the Main Flip-Flop or its complement is propagated to the output Q of the EDC Flip Flop (6). The Q signal feeds the subsequent logic as shown in the Fig.1. A clock pulse (Pulse signal) is used to capture the comparison result of the first XOR gate in the Latch (memory state when the Pulse is low) (7). This clock pulse can be generated locally from the CLK signal using a single Pulse Generator per register like the one illustrated in Figure 3.2. Thus, the routing overhead of an extra clock signal is relaxed. The AND gate in Figure 3.2 ensures that a single pulse will be generated only during the first phase of every clock cycle. The pulse width is at least equal to the time required by the Latch to capture the comparison result. The time interval between the triggering edge of CLK and the falling edge of Pulse (minus the Latch set up time and the XOR propagation delay time) determines the maximum detectable signal delay. Every signal transition at the D input of an EDC Flip-Flop within this time interval is considered as a delayed response. So the circuit design must 17765 Indian Journal of Natural Sciences www.tnsroindia.org.in ©IJONS Vol.10 / Issue 57 / December / 2019 International Bimonthly ISSN: 0976 – 0997 Revathy et al.

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