Application to Timing Attacks

Total Page:16

File Type:pdf, Size:1020Kb

Application to Timing Attacks Template Attacks with Partial Profiles and Dirichlet Priors: Application to Timing Attacks Eloi de Chérisey1, Sylvain Guilley1;2, Olivier Rioul1, and Darshana Jayasinghe1 1 Télécom ParisTech, LTCI, CNRS, Université Paris-Saclay, 75 013 Paris, France. 2 Secure-IC, 15 rue Claude Chappe, Bâtiment B, 35 510 Cesson-Sévigné, France. ABSTRACT In this paper, we consider side-channel attacks that are performed in In order to retrieve the secret key in a side-channel attack, the attacker two phases: computes distinguisher values using all the available data. A profiling 1. a profiling phase where the attacker accumulates leakage from a stage is very useful to provide some a priori information about the device with a known secret key; leakage model. However, profiling is essentially empirical and may not 2. an attacking phase where the attacker accumulates leakage from be exhaustive. Therefore, during the attack, the attacker may come up on the device with an unknown secret key. previously unseen data, which can be troublesome. A lazy workaround is to ignore all such novel observations altogether. In this paper, we show This type of attack is known as a template attack [7]. It has been that this is not optimal and can be avoided. Our proposed techniques shown [7] to be very efficient under three conditions: (a) leakage eventually improve the performance of classical information-theoretic samples are independent and identically distributed (i.i.d.); (b) the noise distinguishers in terms of success rate. is additive white Gaussian; and (c) the secret key leaks byte by byte, which enables a divide-and-conquer approach. For some side-channels, such as power or electromagnetic radiations, condition (b) is met in 1. INTRODUCTION practice. However, for timing attacks, the noise cannot be Gaussian as The field of cryptography is currently very sensitive as it deals with timing is discrete. Moreover, the noise source is non-additive in this data protection and safety. Thus, in order to assess the security of case, since it arises from complex replacement policies in caches and cryptographic devices, it is crucial to know and test their weaknesses. processor-specific on-the-fly instructions reordering. For example, the Advanced Encryption Standard (AES) [1] is renowned The first proposed profiled timing attack is the seminal timing attack as trustworthy from a mathematical point of view—there is currently of Kocher [8]. The same methodology can be used on AES, as noted by no realistic way to cryptanalyze the AES-128. However, it is possible Bernstein in 2005 [9]. Further works used the same method [10, 11, 12]. to break the 128-bit secret key byte by byte using side-channel analysis To our best knowledge, all these works consist in profiling moments, (SCA). SCA exploits the physical fact that the secret key leaks some such as the average timing under a given plaintext and key. However, it information out of the device boundary through various “side-channels” is known [7] that the best attacks should use maximum likelihood. such as power consumption or timing—number of clock cycles to In this paper, as illustrated in Tab. 1, we focus on a profiling where perform a given operation. These leakages, correctly analyzed by SCA, the distribution is kept, and is not reduced to its moments. The attacker yield the secret key of a device. computes distributions using histogram methods. These distributions A good side-channel attack needs a good leakage model. Timing, for are then used to recover the correct secret key. example, can be modeled easily when the implementation is unbalanced: Several successful attacks [2, 3, 4, 5] exploit a timing leakage in the conditional extra-reductions of Montgomery modular multiplications. Table 1: State-of-the-art on profiled timing attacks Some conditional operations can also happen in AES, e.g. in field Profiling method Reference articles operations, as for instance discussed in [6, Alg. 1]. Even when the code is balanced—a recommended secure coding practice—some residual Moments [9, 10, 11, 12] unbalances in timing can result from the hardware which executes the Distributions Our paper (Caution about empty bins) code. Indeed, processors implement speed optimization mechanisms such as memory caching and out-of-order execution. As a consequence, The discrete nature of timing leakage leads to an empty bin issue it is not possible to predict with certainty how timing leaks information. which appears when a data value in the attacking phase has never been The attacker is then led to make predictions about the way the device seen during the profiling phase. Based on profiling only, this data should leaks. have a zero probability, which can be devastating for the attack. One known workaround is to use kernel distribution methods [13] to estimate Permission to make digital or hard copies of all or part of this work for personal or classroom probabilities since the smoothing can be such that no empty bins remain. use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. However, this method has very large computational complexity and its Copyrights for components of this work owned by others than ACM must be honored. performance highly depends on ad-hoc choices of several parameters Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or such as kernel type and bandwidth. to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. HASP 2016, June 18 2016, , Contributions. c 2016 ACM. ISBN 978-1-4503-4769-3/16/06...$15.00 In this paper we show that even when all requirements (a), (b), (c) DOI: http://dx.doi.org/10.1145/2948618.2948625 above are not present, timing attacks with incomplete profiling can be achieved successfully by adapting the maximum likelihood distinguisher where 1A = 1 if A is true, = 0 otherwise. and keeping the histogram method for probabilities estimation. We build six different distinguishers which are all good answers to the empty DEFINITION 2.1 (PROBABILITIES). We define three2 different bin issue. For some of them, new histograms are built, such that the types of probabilities P, Pb and Pe. P is the actual (real) underlying empty bin issue totally disappears. Furthermore, we compare these probability distribution, but it is generally not available and has to be distinguishers and show which one of them is the best in every specific estimated by either Pb or Pe. context. Finally, we provide some theoretical results proving how optimal some of the distinguishers can be. • Pb is computed using the profiling data: q Organization. 1 b nx;t b(x;t) = 1 = b ; (2) P ∑ bxi=x;bti=t The paper is organized as follows. Section 2 provides mathemati- bq i=1 bq cal tools to understand distinguishers and notations. Section 3 intro- 1 bq n duces new distinguishers that are suitable in the context of empty bins. (x) = 1 = bx : (3) Pb ∑ bxi=x Section 4 provides simulations for these distinguishers and Section 5 bq i=1 bq investigates real attacks on an ARM processor. Section 6 concludes. • Pe is computed using the attacking data: 2. MATHEMATICAL DERIVATIONS q 1 e nx;t e(x;t) = 1 = e ; (4) 2.1 Notations and Assumptions P ∑ exi=x;eti=t eq i=1 eq We consider a side-channel attack with a profiling stage and use the 1 eq n following notations: (x) = 1 = ex : (5) Pe ∑ exi=x eq i=1 eq • during the profiling phase, a vectorbt of bq text bytes is sent and the profiler garners a vector of x measurements; b In practice, as the secret key leaks through the function via a XOR • during the attacking phase, a vectoret of eq text bytes is sent and (Equation (1)), we shall often consider P(x;t ⊕k). the attacker gathers a vector ex of leakage measurements—also For a fair comparison between distinguishers, Standaert et al. [14] customarily known as traces; have put forward the success rate as a measure of efficiency of a given distinguisher. • we use simplified notations t, q and x when discussing either profiling data or attacking data; DEFINITION 2.2 (SUCCESS RATE). The success rate SR is prob- • the probability of a vector x with i.i.d. components xi is denoted ability, averaged over all possible keys, of obtaining the correct key. by P(x) = ∏i P(xi); 2n−1 1 ∗ SR = ∗ (k = k ); (6) • we define the following sets: n ∑ Pk e 2 k∗=0 1. Xc, Tc, Xf and Tf are the sets of possible values of com- where ek is the key guess obtained by the distinguisher during the attack. ponents bx,bt, ex andet, respectively; 2. X = Xc [Xf and T = Tc [Tf; It has been proven [15, Theorem 1, equation (3)] that for equiprobable keys the optimal distinguisher maximizes likelihood: 3. K is the set of all possible values for the key k. • k and t are made of n bits (in particular, they are “bytes” when DOptimal(ex;et) = arg max P(exjet⊕k): (7) k2K n = 8). In real life, however, the attacker does not know the leakage model per- Here all sample components of one vector are i.i.d. and belong to some fectly and thus P(xjet⊕k) is not available. In order to get an estimation discrete set. Typically, X is a finite subset of and T is equal to e N of , we use the profiling data to build defined in Equation (2).
Recommended publications
  • Cache-Timing Attack Against Aes Crypto System - Countermeasures Review
    Edith Cowan University Research Online Australian Information Security Management Conference Conferences, Symposia and Campus Events 2014 Cache-timing attack against aes crypto system - countermeasures review Yaseen H. Taha University of Khartoum Settana M. Abdulh University of Khartoum Naila A. Sadalla University of Khartoum Huwaida Elshoush University of Khartoum Follow this and additional works at: https://ro.ecu.edu.au/ism Part of the Information Security Commons DOI: 10.4225/75/57b65fd1343d3 12th Australian Information Security Management Conference. Held on the 1-3 December, 2014 at Edith Cowan University, Joondalup Campus, Perth, Western Australia. This Conference Proceeding is posted at Research Online. https://ro.ecu.edu.au/ism/166 CACHE-TIMING ATTACK AGAINST AES CRYPTO SYSTEM - COUNTERMEASURES REVIEW Yaseen.H.Taha, Settana.M.Abdulh, Naila.A.Sadalla, Huwaida Elshoush University of Khartoum, Sudan [email protected], [email protected], [email protected], [email protected] Abstract Side channel attacks are based on side channel information, which is information that is leaked from encryption systems. Implementing side channel attacks is possible if and only if an attacker has access to a cryptosystem (victim) or can interact with cryptosystem remotely to compute time statistics of information that collected from targeted system. Cache timing attack is a special type of side channel attack. Here, timing information caused by cache effect is collected and analyzed by an attacker to guess sensitive information such as encryption key or plaintext. Cache timing attack against AES was known theoretically until Bernstein carry out a real implementation of the attack. Fortunately, this attack can be a success only by exploiting bad implementation in software or hardware, not for algorithm structure weaknesses, and that means attack could be prevented if proper implementation has been used.
    [Show full text]
  • Some Comments on the First Round AES Evaluation Of
    Some Comments on the First Round AES Evaluation of RC6 1 2 1 Scott Contini , Ronald L. Rivest , M.J.B. Robshaw , 1 and Yiqun Lisa Yin 1 RSA Lab oratories, 2955 Campus Drive, San Mateo, CA 94403, USA fscontini,matt,yiqung@rsa. com 2 M.I.T. Lab oratory for Computer Science, 545 Technology Square, Cambridge, MA 02139, USA [email protected] 1 Intro duction The rst round of the AES pro cess is coming to an end. Since August of 1998, the cryptographic community has had the opp ortunity to consider each of the fteen prop osed AES candidates. In this note, we take the opp ortunity to answer some of the questions and to resp ond to some of the issues that have b een raised ab out the suitabilityofRC6 as an AES candidate. 2 Encryption/Decryption Performance of RC6 Since the publication of RC6 a variety of researchers and implementors have examined RC6 and considered its p erformance in a wide range of environments. 2.1 32-bit architectures RC6 is one of the fastest AES prop osals on 32-bit architectures, particularly so on the NIST reference platform of a 200 MHz Pentium Pro. It is argued by many that the most reasonable way to assess the p erformance of an algorithm is to consider its sp eed in an assembly language implementation. We agree that this is the case. However it is also interesting to consider how the p erformance of RC6 compares when using di erent compilers. It is imp ortant to note that to take advantage of compiler-sp eci c optimizations the source co de provided to the compiler might need to b e changed.
    [Show full text]
  • An Adaptive-Ciphertext Attack Against I XOR C Block Cipher Modes With
    A A-C A “I ⊕ C” B C M W O Jon Passki Tom Ritter [email protected] [email protected] May 24, 2012 Abstract Certain block cipher confidentiality modes are susceptible to an adaptive chosen-ciphertext attack against the underlying format of the plaintext. When the application decrypts altered ciphertext and attempts to process the manipulated plaintext, it may disclose information about intermediate values resulting in an oracle. In this paper we describe how to recognize and exploit such an oracle to decrypt ciphertext and control the decryption to result in arbitrary plaintext. We also discuss ways to mitigate and remedy the issue. 1 I Quoting from [1]: Adaptive chosen-ciphertext attacks on cryptographic protocols allow an attacker to decrypt a cipher- text C, getting the plaintext M, by submitting a series of chosen-ciphertexts C0= 6 C to an oracle which returns information on the decryption. The ciphertexts can be adaptively chosen so that information on previous decryptions is available before the next chosen ciphertext is submitted. Adaptive chosen-ciphertext attacks against different confidentiality modes are not novel. The CBC confidentiality mode can suffer from a side channel attack against padding verification [2], popularized by [3]. A variant of the Cipher Feedback (CFB) confidentiality mode has been attacked in different encryption mail protocols by [4, 5, 1], and the padding schemes of asymmetric ciphers are another source of such attacks [6, 7]. In some form, they rely on the use of an oracle that leaks or communicates information back to attackers. We examine four different confidentiality modes encrypting plaintext that is separated by a delimiter, and the absence or inclusion of that delimiter generates an oracle by the application.
    [Show full text]
  • Cs 255 (Introduction to Cryptography)
    CS 255 (INTRODUCTION TO CRYPTOGRAPHY) DAVID WU Abstract. Notes taken in Professor Boneh’s Introduction to Cryptography course (CS 255) in Winter, 2012. There may be errors! Be warned! Contents 1. 1/11: Introduction and Stream Ciphers 2 1.1. Introduction 2 1.2. History of Cryptography 3 1.3. Stream Ciphers 4 1.4. Pseudorandom Generators (PRGs) 5 1.5. Attacks on Stream Ciphers and OTP 6 1.6. Stream Ciphers in Practice 6 2. 1/18: PRGs and Semantic Security 7 2.1. Secure PRGs 7 2.2. Semantic Security 8 2.3. Generating Random Bits in Practice 9 2.4. Block Ciphers 9 3. 1/23: Block Ciphers 9 3.1. Pseudorandom Functions (PRF) 9 3.2. Data Encryption Standard (DES) 10 3.3. Advanced Encryption Standard (AES) 12 3.4. Exhaustive Search Attacks 12 3.5. More Attacks on Block Ciphers 13 3.6. Block Cipher Modes of Operation 13 4. 1/25: Message Integrity 15 4.1. Message Integrity 15 5. 1/27: Proofs in Cryptography 17 5.1. Time/Space Tradeoff 17 5.2. Proofs in Cryptography 17 6. 1/30: MAC Functions 18 6.1. Message Integrity 18 6.2. MAC Padding 18 6.3. Parallel MAC (PMAC) 19 6.4. One-time MAC 20 6.5. Collision Resistance 21 7. 2/1: Collision Resistance 21 7.1. Collision Resistant Hash Functions 21 7.2. Construction of Collision Resistant Hash Functions 22 7.3. Provably Secure Compression Functions 23 8. 2/6: HMAC And Timing Attacks 23 8.1. HMAC 23 8.2.
    [Show full text]
  • Side-Channel Attacks
    Side-Channel Attacks Aleksei Ivanov 26th November 2005 1 Introduction and patches the result with all 0's.This results in small, constant time when compared to complete Side-channel attacks are described in [5] as follows. multiplication. Timing side channel information Side-channel attacks are attacks that are based on can be obtained either by precisely measuring the side channel information. Side channel Information time taken by one encryption or by averaging the that can be retrieved from the encryption device time taken over several encryptions [4]. that is neither plain text to be encrypted nor the cipher text resulting from the encryption process. There are several kind of side-channel attacks, in 2.2 Power Consumption Attacks the [2] timing attack is referred to as the most Devices consume power and the power dissipated common one. Then There is one kind of informa- by a device is an other side channel. Dierential tion leakage referred to in [1] as power consumption power analysis (DPA) is a power consumption side leakage, that is a big help to the timing attacks. It channel attack that divides the encryption into a is even harder to protect a system against the power number of time slots and measures power in each consumption attacks when attacker has direct ac- slot for dierent plain text input. A small number cess to the encryption device. of the power measurements correlate with each bit The purpose of this paper is to get an overview of the interval stage during encryption [4]. of attacks on encryption systems where an attacker This attack requires little knowledge of the device is using other ways to obtain the encryption key and is dicult to hide the channel information if than breaking the mathematical algorithm.
    [Show full text]
  • Research on Microarchitectural Cache Attacks
    Advances in Computer Science Research (ACSR), volume 90 3rd International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2019) Research on Microarchitectural Cache Attacks Yao Lu a, Kaiyan Chen b, Yinlong Wang c Simulation Center of Ordnance Engineering College Army Engineering University Shijiazhuang, Hebei Province, China [email protected], [email protected], [email protected] Abstract. This paper summarizes the basic concepts and development process of cache side- channel attack, analyses three basic methods (Evict and Time, Prime and Probe, Flush and Reload) from four aspects: Attack conditions, realization process, applicability, and characteristics, then I expound how to apply side-channel attack methods on CPU vulnerability. Keywords: Side-channel attacks; Cache; CPU vulnerability; Microarchitecture. 1. Background Cryptography is a technique used to confuse plaintext [1], It transforms normally identifiable information (plaintext) into unrecognizable information (ciphertext). At the same time, the encrypted ciphertext can be transferred back to the normal information through the key, the privacy information of users at this stage is mostly realized by encryption technology [28], so the security of personal information depends on the security of the encryption algorithm. 1.1 Cryptographic Algorithms Cryptographic algorithms have always been an important research object in cryptography, in recent years has also been rapid development, these algorithms are: RIJINDAEL, MARS, RC6, Twofish, Serpent, IDEA, CS-Cipher, MMB, CA-1.1, SKIPJACK Symmetric cryptographic algorithms such as Karn and backpack public key cryptography, RSA, ElGamal [29], ECC [19], NTRU and other asymmetric cryptographic algorithms [27]. in the opinion of the development trend of international mainstream cryptographic algorithms at present [25]: The symmetric cryptographic algorithm transitions from DES-3 to AES, and the password length is gradually increased: 128, 192, 256.
    [Show full text]
  • Public Evaluation Report UEA2/UIA2
    ETSI/SAGE Version: 2.0 Technical report Date: 9th September, 2011 Specification of the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3. Document 4: Design and Evaluation Report LTE Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3. page 1 of 43 Document 4: Design and Evaluation report. Version 2.0 Document History 0.1 20th June 2010 First draft of main technical text 1.0 11th August 2010 First public release 1.1 11th August 2010 A few typos corrected and text improved 1.2 4th January 2011 A modification of ZUC and 128-EIA3 and text improved 1.3 18th January 2011 Further text improvements including better reference to different historic versions of the algorithms 1.4 1st July 2011 Add a new section on timing attacks 2.0 9th September 2011 Final deliverable LTE Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3. page 2 of 43 Document 4: Design and Evaluation report. Version 2.0 Reference Keywords 3GPP, security, SAGE, algorithm ETSI Secretariat Postal address F-06921 Sophia Antipolis Cedex - FRANCE Office address 650 Route des Lucioles - Sophia Antipolis Valbonne - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N° 348 623 562 00017 - NAF 742 C Association à but non lucratif enregistrée à la Sous-Préfecture de Grasse (06) N° 7803/88 X.400 c= fr; a=atlas; p=etsi; s=secretariat Internet [email protected] http://www.etsi.fr Copyright Notification No part may be reproduced except as authorized by written permission. The copyright and the foregoing restriction extend to reproduction in all media.
    [Show full text]
  • CRYPTREC Report 2001
    CRYPTREC 2001 CRYPTREC Report 2001 March 2002 Information-technology Promotion Agency, Japan Telecommunications Advancement Organization of Japan CRYPTREC 2001 Contents Introduction 1 On the CRYPTREC Evaluation Committee Report 3 Note on the use of this report 7 1 Overview of Cryptographic Technique Evaluation 8 1.1 Evaluation Organs and Schedule ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・8 1.2 How cryptography evaluation was carried out. ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・12 1.3 Terminology ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・13 1.4 Evaluation Committee Members ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・14 2 Evaluation of public key cryptographic techniques 17 2.1 Target of Evaluation and Evaluation Method ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・17 2.1.1 Evaluated Cryptographic Techniques ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・17 2.1.2 Evaluation Policy・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・17 2.1.3 Evaluation Method ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・19 2.2 Evaluation result ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・21 2.2.1 Outline of evaluation result ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・21 2.2.2 General Evaluation of the Difficulty of Arithmetic Problems・・・・・・・・・・・・・・・・・23 2.2.3 Overall Judgment of Cryptographic Techniques that were the Target of Detailed Evaluation ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・23 2.2.4 Overall Judgment of Cryptographic Techniques under Observation ・・・・・・・・・・・26 2.2.5 Overall Judgment of Cryptosystems that were Targets of Screening Evaluations in 2001
    [Show full text]
  • PAGE—Practical AES-GCM Encryption for Low-End Microcontrollers
    applied sciences Article PAGE—Practical AES-GCM Encryption for Low-End Microcontrollers Kyungho Kim 1, Seungju Choi 1, Hyeokdong Kwon 1, Hyunjun Kim 1 and Zhe Liu 2 and Hwajeong Seo 1,* 1 Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea; [email protected] (K.K); [email protected] (S.C.); [email protected] (H.K.); [email protected] (H.K.) 2 Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China; [email protected] * Correspondence: [email protected]; Tel.: +82-2-760-8033 Received: 25 March 2020; Accepted: 28 April 2020; Published: 30 April 2020 Abstract: An optimized AES (Advanced Encryption Standard) implementation of Galois Counter Mode of operation (GCM) on low-end microcontrollers is presented in this paper. Two optimization methods are applied to proposed implementations. First, the AES counter (CTR) mode of operation is speed-optimized and ensures constant timing. The main idea is replacing expensive AES operations, including AddRound Key, SubBytes, ShiftRows, and MixColumns, into simple look-up table access. Unlike previous works, the look-up table does not require look-up table updates during the entire encryption life-cycle. Second, the core operation of Galois Counter Mode (GCM) is optimized further by using Karatsuba algorithm, compact register utilization, and pre-computed operands. With above optimization techniques, proposed AES-GCM on 8-bit AVR (Alf and Vegard’s RISC processor) architecture from short-term, middle-term to long-term security levels achieved 415, 466, and 477 clock cycles per byte, respectively. Keywords: AES; fast software encryption; Galois Counter Mode of operation; low-end microcontrollers; side channel attack countermeasure 1.
    [Show full text]
  • Timing Side-Channel Attack on AES Student: Adam Zahumenský Supervisor: Ing
    ASSIGNMENT OF BACHELOR’S THESIS Title: Timing side-channel attack on AES Student: Adam Zahumenský Supervisor: Ing. Jiří Buček, Ph.D. Study Programme: Informatics Study Branch: Computer Security and Information technology Department: Department of Computer Systems Validity: Until the end of summer semester 2019/20 Instructions Study the topic of timing side-channel attacks of the AES cipher on modern CPUs with caches. Measure the times of a naive AES implementation and an AES implementation using T-boxes and analyze the dependence of the calculation time on data, key, and possibly other factors, and try to break the key. The final work will take the form of a laboratory exercise assignment for teaching in computer security subjects. References Will be provided by the supervisor. prof. Ing. Pavel Tvrdík, CSc. doc. RNDr. Ing. Marcel Jiřina, Ph.D. Head of Department Dean Prague February 14, 2019 Bachelor’s thesis Timing side-channel attack on AES Adam Zahumenský Department of Information Security Supervisor: Ing. Jiří Buček, Ph.D. May 16, 2019 Acknowledgements I thank my supervisor Jiří Buček for his time and ideas which helped me delve deeper into my discoveries. Furthermore, I thank all of my friends for their unending support when I needed it the most. Declaration I hereby declare that the presented thesis is my own work and that I have cited all sources of information in accordance with the Guideline for adhering to ethical principles when elaborating an academic final thesis. I acknowledge that my thesis is subject to the rights and obligations stip- ulated by the Act No.
    [Show full text]
  • Side Channel Analyses of CBC Mode Encryption
    Side Channel Analyses of CBC Mode Encryption Arnold K. L. Yau Thesis submitted to the University of London for the degree of Doctor of Philosophy Information Security Group Department of Mathematics Royal Holloway, University of London 2009 Declaration These doctoral studies were conducted under the supervision of Professor Kenneth G. Paterson and Professor Chris J. Mitchell. The work presented in this thesis is the result of original research carried out by myself, in collaboration with others, whilst enrolled in the Department of Mathematics as a candidate for the degree of Doctor of Philosophy. This work has not been submitted for any other degree or award in any other university or educational establishment. Arnold K. L. Yau 2 Acknowledgements It was my great fortune to have met my supervisor Kenny Paterson during my undergrad- uate studies, who introduced to me the fascinating world of cryptography and security, and who subsequently encouraged me to pursue a doctorate in the subject. Over the course of my studies, his guidance, patience and encouragement have been invaluable and indeed indispensable. His uncompromising pursuit of conducting quality and thorough research has not only helped me to develop as a researcher, but has also taken the result of our research much further than I had anticipated. His depth and breath of knowledge in information security has been inspirational and influential for my career development. I wish to express my deepest gratitude to Kenny. I am also grateful to my academic advisor Chris Mitchell whose knowledge and expe- rience in international standards have given me a level of access to the standardisation process that would otherwise have been unavailable.
    [Show full text]
  • AES-GCM for Efficient Authenticated Encryption – Ending the Reign of HMAC-SHA-1?
    Workshop on Real-World Cryptography Stanford University Jan. 9-11, 2013 AES-GCM for Efficient Authenticated Encryption – Ending the Reign of HMAC-SHA-1? Shay Gueron University of Haifa Department of Mathematics, Faculty of Natural Sciences, University of Haifa, Israel Intel Corporation Intel Corporation, Israel Development Center, Haifa, Israel [email protected], [email protected] 1 Agenda • Why is the ecosystem using HMAC SHA-1 for authenticated encryption? – What can be done to change this? • AES-GCM dirty secrets… and how to optimize it (… and save the honor of AES-GCM after Adam’s talk) S. Gueron. RWC 2013 2 Optimizing cryptographic primitives • Why care? Who cares? – The need for end-to-end security in the internet, constantly increases the world-wide number (and percentage) of SSL/TLS connections. – Why aren’t all connections https:// ? Overheads’ costs • Cryptographic algorithms for secure communications = computational overhead • Mainly on the servers side – Any latency client side influences (indirectly) the ecosystem • Authenticated Encryption: a fundamental cryptographic primitive • Is the ecosystem using an efficient AE scheme? – Apparently no… a better alternative exists S. Gueron. RWC 2013 3 Ciphers in use in SSL/TLS connections Today’s most frequently used AE in browser/server connections DES-CBC3- RC4 + HMAC-MD5 (don’t care) RC4-SHA-128 SHA-168 3% 2% RC4 + HMAC-SHA-1 RC4-MD5-128 AES + HMAC-SHA-1 15% ASE256-SHA-1 authentication: mostly HMAC SHA-1 44% AES128-SHA-1 Is it the best AE (performance wise)? 36% No – a faster alternative exists We already know that HMAC is not an efficient MAC scheme, and as an ingredient in AE – it makes an inefficient AE • Akamai serves service millions of requests per sec.
    [Show full text]