20F026L00 E2 2019-10-22
F26L Embedded Single Board Computer with Intel Apollo Lake-I 3U CompactPCI PlusIO
User Manual Contents
Contents
Contents...... 2 About this Document ...... 6 Product Safety ...... 8 Product Compliance ...... 9 Disclaimer ...... 10 Contacts ...... 11 1 Product Overview ...... 12 1.1 Product Description ...... 12 1.2 Product Architecture ...... 13 1.2.1 Interfaces...... 13 1.3 Functions ...... 15 1.4 Technical Data ...... 16 1.5 Product Identification...... 19 2 Getting Started ...... 20 2.1 Configuring the Hardware...... 20 2.1.1 Installing an mSATA Disk...... 20 2.1.2 Installing a microSD Card ...... 21 2.2 Connecting and Starting ...... 22 2.2.1 Configuring the UEFI Firmware for PXE Boot...... 22 2.3 Troubleshooting at Start-up ...... 23 2.3.1 Errors Signaled by the Front-Panel Status LED ...... 23 2.4 Installing Operating System Software ...... 23 2.5 Installing Driver Software ...... 23 2.6 Using the F26L under Linux...... 24 2.6.1 F26L Linux BSP ...... 24 2.6.2 Accessing SMBus/I2C Devices using Standard Linux I2C Tools. . . 24 2.6.3 Managing RTC Time Adjustments ...... 24 2.7 Using the F26L under Windows ...... 25 2.7.1 Accessing SMBus/I2C Devices ...... 25 2.7.2 Managing RTC Time Adjustments ...... 26 3 Functional Description...... 27 3.1 Power Supply...... 27 3.2 CPU ...... 27 3.2.1 Processor Core ...... 27 3.2.2 Thermal Considerations ...... 27 3.3 Trusted Platform Module (TPM) ...... 27 3.4 Supervision and Management ...... 28 3.4.1 Watchdog ...... 28 3.4.2 Temperature Measurement ...... 28 3.4.3 Status LEDs ...... 28 3.4.4 Software Support ...... 29 3.5 Reset ...... 29 3.6 Real-Time Clock (RTC)...... 30 3.6.1 Software Support ...... 30
20F026L00 E2 2019-10-22 Page 2 Contents
3.7 Memory ...... 31 3.7.1 System RAM ...... 31 3.7.2 Boot Flash ...... 31 3.8 Mass Storage ...... 32 3.8.1 mSATA Slot ...... 32 3.8.2 microSD Card Slot ...... 32 3.8.3 Serial ATA (SATA) ...... 32 3.9 Video...... 33 3.9.1 VGA...... 33 3.9.2 DDI ...... 33 3.10 Audio...... 34 3.10.1 Side-Card Connection ...... 34 3.11 USB ...... 35 3.11.1 Front Connection ...... 35 3.11.2 Side-Card Connection ...... 35 3.11.3 Rear Connection...... 35 3.12 Ethernet ...... 36 3.12.1 Front Connection ...... 36 3.12.2 Rear Connection...... 38 3.12.3 Signal Mnemonics ...... 38 3.12.4 Ethernet MAC Addresses ...... 38 3.12.5 Ethernet Status LEDs ...... 39 3.13 PCI Express ...... 40 3.13.1 Side-Card Connection ...... 40 3.13.2 Rear Connection...... 40 3.14 Side-Card Interface ...... 41 3.14.1 Onboard Connection...... 41 3.15 CompactPCI ...... 44 3.15.1 J1...... 44 3.15.2 J2 (CompactPCI PlusIO) ...... 44 4 UEFI Firmware ...... 46 4.1 Accessing the Firmware ...... 46 4.2 Setup Menus ...... 46 4.3 Setup Modes ...... 46 4.3.1 Main Menu ...... 47 4.3.2 MEN Menu...... 48 4.3.3 Advanced Menu ...... 51 4.3.4 Chipset...... 52 4.3.5 Security Menu...... 53 4.3.6 Boot Menu...... 55 4.3.7 Save and Exit Menu ...... 56 5 Hardware/Software Interface ...... 57 5.1 SMBus/I2C Devices ...... 57 5.2 BMC API (Application Programming Interface)...... 58 5.2.1 Command Packets ...... 58 6 Maintenance ...... 80 6.1 Lithium Battery ...... 80
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Figures
Figure 1. Front interfaces ...... 13 Figure 2. Board layout – top view...... 14 Figure 3. Board layout – bottom view ...... 14 Figure 4. Functional diagram ...... 15 Figure 5. Product labels...... 19 Figure 6. Position of lithium battery on F26L ...... 80
Tables
Table 1. CPU status LED at front panel ...... 28 Table 2. Error codes signaled via status LED flashes...... 29 Table 3. Connector types – VGA ...... 33 Table 4. Pin assignment – VGA ...... 33 Table 5. Signal mnemonics – VGA...... 33 Table 6. Connector types – USB 3.0 ...... 35 Table 7. Pin assignment – USB 3.0 ...... 35 Table 8. Signal mnemonics – USB 3.0 ...... 35 Table 9. Connector types – Ethernet (RJ45) ...... 36 Table 10. Pin assignment – Ethernet (RJ45)...... 36 Table 11. Connector types – Ethernet (8-pin M12 A-coded) ...... 36 Table 12. Pin assignment – Ethernet (8-pin M12)...... 36 Table 13. Connector types – Ethernet (4-pin, M12, D-coded) ...... 37 Table 14. Pin assignment – Ethernet (4-pin M12 D-coded) ...... 37 Table 15. Connector types – Ethernet (8-pin M12 X-coded) ...... 37 Table 16. Pin assignment – Ethernet (8-pin M12 X-coded) ...... 37 Table 17. Ethernet cable requirements ...... 38 Table 18. Signal mnemonics – Ethernet...... 38 Table 19. Ethernet MAC addresses...... 38 Table 20. Ethernet status LEDs ...... 39 Table 21. Connector types – Side-card interface ...... 41 Table 22. Pin assignment – Side-card interface, pins 1 - 38 ...... 41 Table 23. Pin assignment – Side-card interface, pins 39 - 76 ...... 42 Table 24. Pin assignment – Side-card interface, pins 77 - 114 ...... 42 Table 25. Signal mnemonics of 114-pin side-card connector...... 43 Table 26. Pin assignment – CompactPCI J2 ...... 44 Table 27. Signal mnemonics – CompactPCI connector J2 – CompactPCI and CompactPCI PlusIO rear I/O ...... 45 Table 28. Functions in the MEN Menu ...... 49 Table 29. Sub-menu BMC Settings ...... 49 Table 30. Sub-Menu Network Settings...... 50 Table 31. Sub-Menu Memory Settings...... 50 Table 32. Sub-Menu SATA Settings...... 50 Table 33. Sub-Menu USB Settings...... 50 Table 34. Setting passwords ...... 53 Table 35. Security modes...... 54 Table 36. SMBus/I2C devices...... 57 Table 37. API – Packet types ...... 58 Table 38. API – Packet types mapping on SMBus...... 59 Table 39. BMC API – Watchdog commands...... 59 Table 40. BMC API – Power resume mode commands ...... 61 Table 41. BMC API – Power resume modes ...... 61 Table 42. BMC API – External power supply failure mode commands ...... 63 Table 43. BMC API – Reset signal blocking commands ...... 64 Table 44. BMC API – External power supply control commands ...... 65
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Table 45. BMC API – Software reset commands...... 66 Table 46. BMC API – Power button commands ...... 67 Table 47. BMC API – Voltage supervision commands ...... 68 Table 48. BMC API – Error counters ...... 70 Table 49. BMC API – Error counter commands...... 70 Table 50. BMC API – Firmware version commands ...... 72 Table 51. BMC API – Backplane slot geographical address command ...... 73 Table 52. BMC API – Last error command...... 74 Table 53. BMC API – Power failure flags command ...... 75 Table 54. BMC API – Reset reason command ...... 76 Table 55. BMC API – Clear error registers command...... 77 Table 56. BMC API – Power cycle counter command...... 77 Table 57. BMC API – Operating hours counter command ...... 78 Table 58. BMC API – Status LED control command ...... 79
20F026L00 E2 2019-10-22 Page 5 About this Document
About this Document
This document is intended only for system developers and integrators. It describes the design, functions and connection of the product. The manual does not include detailed information on individual components (data sheets etc.).
F26L product page with up-to-date information and downloads: www.men.de/products/f26l/
History
Issue Comments Date E1 First issue 2017-06-06 E2 . Added details on firmware and software 2019-10-22 . Added chapter Trusted Platform Module (TPM) . Added information on Ethernet . Updated chapter Reset . Corrected data retention for RTC
20F026L00 E2 2019-10-22 Page 6 About this Document
Conventions
Indicates important information or warnings concerning situations which could result in personal injury, or damage or destruction of the component.
Indicates important information concerning electrostatic discharge which could result in damage or destruction of the component.
Indicates important information or warnings concerning proper functionality of the product described in this document.
The globe icon indicates a hyperlink that links directly to the Internet. When no globe icon is present, the hyperlink links to specific information within this document.
Italics Folder, file and function names are printed in italics.
Comment Comments embedded into coding examples are shown in green text. IRQ# Signal names followed by a hashtag "#" or preceded by a forward slash "/" /IRQ indicate that this signal is either active low or that it becomes active at a falling edge. In/Out Signal directions in signal mnemonics tables generally refer to the corresponding board or component, "in" meaning "to the board or component", "out" meaning "from the board or component". 0xFF Hexadecimal numbers are preceded by "0x". 0b1111 Binary numbers are preceded by "0b".
20F026L00 E2 2019-10-22 Page 7 Product Safety
Product Safety
Read the user manual carefully before using the product. Keep the user manual for later reference.
Conditions for Use, Field of Application
The product is designed to function correctly in the market, application area and environmental conditions specified in the applicable standards which are listed in the Technical Data. Use cases in environments exceeding the specifications in the applicable standards and the Technical Data have to be agreed upon between MEN and the customer. The product is not suitable for use in areas where children might be present.
Lithium Battery
Some product models may be equipped with a lithium battery. There is a danger of explosion if the battery is incorrectly replaced!
Electrostatic Discharge (ESD)
Computer boards and components contain electrostatic sensitive devices. Electrostatic discharge (ESD) can damage components. To protect the PCB and other components against damage from static electricity, follow some precautions whenever you work on your computer. . Power down and unplug your computer system when working on the inside. . Hold components by the edges and try not to touch the IC chips, leads, or circuitry. . Use a grounded wrist strap before handling computer components. . Place components on a grounded antistatic pad or on the bag that came with the component whenever the components are separated from the system. . Only store the product in its original ESD-protected packaging. Retain the original packaging in case you need to return the product to MEN for repair.
Qualified Personnel
The product/system described in this documentation may be operated only by personnel qualified for the specific task in accordance with the relevant documentation, in particular its warning notices and safety instructions. Qualified personnel are those who, based on their training and experience, are capable of identifying risks and avoiding potential hazards when working with these products/systems.
20F026L00 E2 2019-10-22 Page 8 Product Compliance
Product Compliance
MEN products are tested according to the standards given in the Technical Data and thus enable you to achieve certification of the product according to the standards applicable in your field of application. If the product delivered was certified by MEN and is modified by the customer, e.g., by installing an additional hardware component, the certification achieved by MEN becomes invalid and may have to be repeated for the new product configuration.
RoHS
MEN is committed to develop and produce environmentally compatible products according to the Restriction of Hazardous Substances (RoHS) Directive 2011/65/EU (formerly 2002/95/EC) of the European Union. Since July 1, 2006 all MEN standard products comply with RoHS legislation.
REACH
MEN is a manufacturer of electronic products and thus a so-called "downstream user" in terms of REACH. The products MEN supplies are solely non-chemical goods. Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied shall not release any substance. Beyond that, according to REACH – Art.33, MEN will inform the customer immediately should a substance contained in an MEN product (with a content of > 0.1%) be classified alarming by the European Chemicals Agency (ECHA).
WEEE Application
The WEEE directive does not apply to fixed industrial plants and tools. The compliance is the responsibility of the company which puts the product on the market, as defined in the directive; components and sub- assemblies are not subject to product compliance. Since MEN does not deliver ready-made products to end users, the WEEE directive is not applicable for MEN. Users are nevertheless recommended to properly recycle all electronic boards which have passed their life cycle.
Nevertheless, MEN is registered as a manufacturer in Germany. The registration number can be provided on request.
20F026L00 E2 2019-10-22 Page 9 Disclaimer
Disclaimer
Changes
MEN Mikro Elektronik GmbH ("MEN") reserves the right to make changes without further notice to any products herein.
Liability
MEN makes no warranty, representation or guarantee of any kind regarding the suitability of its products for any particular purpose, nor does MEN assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including, without limitation, consequential or incidental damages. TO THE EXTENT APPLICABLE, SPECIFICALLY EXCLUDED ARE ANY IMPLIED WARRANTIES ARISING BY OPERATION OF LAW, CUSTOM OR USAGE, INCLUDING WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR USE. In no event shall MEN be liable for more than the contract price for the products in question. If buyer does not notify MEN in writing within the foregoing warranty period, MEN shall have no liability or obligation to buyer hereunder. Should the customer purchase or use MEN products for any unintended or unauthorized application, the customer shall indemnify and hold MEN and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim or personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that MEN was negligent regarding the design or manufacture of the part. In no case is MEN liable for the correct function of the technical installation where MEN products are a part of. The publication is provided on the terms and understanding that: 1. MEN is not responsible for the results of any actions taken on the basis of information in the publication, nor for any error in or omission from the publication; and 2. MEN is not engaged in rendering technical or other advice or services. MEN expressly disclaims all and any liability and responsibility to any person, whether a reader of the publication or not, in respect of anything, and of the consequences of anything, done or omitted to be done by any such person in reliance, whether wholly or partially, on the whole or any part of the contents of the publication.
20F026L00 E2 2019-10-22 Page 10 Contacts
Contacts
Germany France MEN Mikro Elektronik GmbH MEN Mikro Elektronik SAS Neuwieder Straße 1-7 18, rue René Cassin 90411 Nuremberg ZA de la Châtelaine Phone +49-911-99 33 5-0 74240 Gaillard Phone +33-450-955-312 [email protected] [email protected] www.men.de www.men-france.fr
USA China MEN Micro Inc. MEN Mikro Elektronik (Shanghai) Co., Ltd. 860 Penllyn Blue Bell Pike Room 1212, #993 West Nanjing Road Blue Bell, PA 19422 Shanghai 200041 Phone 215-542-9575 Phone +86-21-5058-0963 [email protected] [email protected] www.menmicro.com www.men-china.cn
Copyright © 2019 MEN Mikro Elektronik GmbH. All rights reserved.
20F026L00 E2 2019-10-22 Page 11 Product Overview
1 Product Overview
1.1 Product Description
Low-Power Intel Atom CPU The F26L low-power CPU board is a member of the scalable family of Intel CPU boards which ensures future-safety and long-term availability. It is equipped with an Intel Atom Apollo Lake-I dual-core or quad-core System-on-a-Chip (SoC). Due to the low power architecture on the Intel Atom processor, the CPU card has a total power consumption of max. 6.5 Watts to 12 Watts, while having a clock frequency of up to 1.6 GHz. An excellent graphics performance, thermal supervision of the processor and a watchdog for the operating system top off the functionality of the F26L. Furthermore, a Trusted Platform Module is assembled for security purposes.
Designed for Extreme Temperatures The CompactPCI PlusIO board has been designed for applications with extreme temperatures, where high reliability and long-term availability are essential requirements. This kind of application is common in the rail market, in industrial automation and in the power and energy sector, for example. To fulfill these extreme temperature requirements, the F26L has been equipped with a specially outlined heat sink, which efficiently takes away the heat from the board.
CompactPCI PlusIO (PICMG 2.30) The F26L supports the CompactPCI PlusIO (PICMG 2.30) specification, meaning it can be used in a hybrid system for control of both CompactPCI and CompactPCI Serial peripheral boards. Compliant to the standard, four USB 2.0, four PCI Express x1 as well as two Gigabit Ethernet interfaces are accessible on the J2 rear I/O connector.
Versatile Front I/O The standard I/O available at the front panel of the F26L includes VGA, two Gigabit Ethernet and two USB 3.0 ports. The F26L can be extended by different side cards. Additional functions include a variety of different UARTs or another four USBs, SATA for hard disk connection and HD audio.
Linux and Windows Support The F26L operates in Windows 10 and Linux environments as well as under real-time operating systems that support Intel's multi-core architecture. The AMI UEFI BIOS was specially designed for embedded system applications.
Long-Term Availability Long-term availability until 2031 minimizes life-cycle management by making the F26L available at least for this period of time.
20F026L00 E2 2019-10-22 Page 12 Product Overview
1.2 Product Architecture
1.2.1 Interfaces
Figure 1. Front interfaces
® CompactPCI CompactPCI ® RST RST STA STA ETH1 1 1 2 2 3 3 4 4 VGA ETH2 VGA
F26L F26L
02F026L10 02F026L11
20F026L00 E2 2019-10-22 Page 13 Product Overview
Figure 2. Board layout – top view
CompactPCI connector J2 mSATA slot Side card connector
USB connectors
Ethernet connector ETH1 Ethernet connector
ETH2 1
VGA connector
Heat sink CompactPCI connector J1 Op onal ba ery (under the heat sink)
Figure 3. Board layout – bottom view
microSD card slot
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1.3 Functions
Figure 4. Functional diagram
ECC DDR3 SDRAM SATA (6 Gb) DDI ECC DDR3 SDRAM HD Audio Side 4 USB 2.0 Card
PCIe 2.0 x1 2 PCIe 2.0 x1 SATA (6 Gb) PCIe Switch mSATA Slot B B
SDIO Intel Atom microSD Slot PCIe x1 B E3900 Series PCIe-to-PCI J1 R
4 USB 2.0 USB 3.0 F 4 PCIe 2.0 x1 USB 3.0 PCIe 2.0 x2 F PCIe Switch I2C VGA DisplayPort- DisplayPort F J2 to-VGA VGA
PCIe 2.0 x2 Gigabit Ethernet Gigabit Ethernet F Ethernet Ctrl Ethernet Ctrl PCIe Switch Gigabit Ethernet Gigabit Ethernet F Ethernet Ctrl Ethernet Ctrl R
FFrontR Rear BOnboard Options
20F026L00 E2 2019-10-22 Page 15 Product Overview
1.4 Technical Data
CPU . The following CPU types are supported: - Intel Atom x5-E3930, 2 cores, 2 threads, 1.3 GHz, 1.8 GHz Turbo Boost, 6.5 W, 2 MB cache - Intel Atom x5-E3940, 4 cores, 4 threads, 1.6 GHz, 1.8 GHz Turbo Boost, 9.5 W, 2 MB cache - Intel Atom x7-E3950, 4 cores, 4 threads, 1.6 GHz, 2.0 GHz Turbo Boost, 12 W, 2 MB cache
Memory . System RAM - Soldered DDR3, ECC - 8 GB max.
Security . Trusted Platform Module 2.0
Mass Storage . The following mass storage devices can be assembled: - mSATA - microSD card
Graphics . Processor graphics
Interfaces . This product includes interface options - Different front connectors - Front or rear connection for some interfaces (assembly option) - I/O expansion using a side card plugged via board-to-board connector . SSD/HDD slot - 1 × mSATA; SATA Revision 3.x . SD/microSD card slot - 1 × microSD card; UHS-I (104 MB/s (SDR104)) . SATA - 1 × SATA Revision 3.x, board to board . Video - 1 × VGA - 1 × DDI board to board . Audio - 1 × board to board - HD Audio
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. USB - 2 × USB 3.0, Type A - 4 × USB 2.0, board to board - 4 × USB 2.0, backplane . Ethernet - 2 × 10/100/1000BASE-T, RJ45 - 2 × 10/100/1000BASE-T, M12, A-coded, receptacle - 2 × 10/100BASE-T, M12, D-coded, receptacle - 2 × 10/100/1000BASE-T, M12, X-coded, receptacle - 2 × 10/100/1000BASE-T, backplane . PCI Express - 2 × PCIe 2.0, x1, board to board - 4 × PCIe 2.0, x1, backplane . I2C - 1 × backplane . Reset - Reset button . LED - Status: board status (BMC) - Ethernet: activity, link . Power - 1 × button
Supervision and Control . Board management controller . Temperature measurement . Watchdog timer . Real-time clock, buffered by supercapacitor (3 days) or battery (1 year)
Product Standard . CompactPCI: CompactPCI Core Specification PICMG 2.0 R3.0 . CompactPCI PlusIO: CompactPCI PlusIO Specification PICMG 2.30 . 1PCI33/4PCIE2.0/0SATA/4USB2/2ETH1G . System slot . 32-bit/33-MHz CompactPCI bus . V(I/O): +3.3 V (+5 V tolerant)
Electrical Specifications . Supply voltage - +5 V (-3 % / +5 %) - +3.3 V (-3 % / +5 %) - +12 V (-10 % / +10 %) . Power consumption: 22 W max.
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Mechanical Specifications . Dimensions - 3U, 4 HP - 3U, 8 HP - 3U, 12 HP (8 HP with M12 connectors, up to 12 HP with side card) . Weight: 350 g (4 HP with RJ45 connectors) . Cooling - Air cooling - Conduction cooling
Product Compliance: Rail - Rolling Stock . Operating temperature: -40 °C to +85 °C (EN 50155:2007, class TX, board) . Storage temperature: -40 °C (EN 60068-2-1:2007, Ab) to +85 °C (EN 60068-2-2:2007, Bb) . Altitude: -300 m to +3000 m . Relative humidity (operation): max. 95% non-condensing . Relative humidity (storage): max. 95% non-condensing . Shock: 50 m/s² / 30 ms (EN 61373:2010, vehicle body, cat. 1, class B) . Vibration: 10 min @ 1.01 m/s² and 5 h @ 5.72 m/s² (EN 61373:2010, vehicle body, cat. 1, class B)
Product Compliance: Information Technology Equipment . Electrical safety: EN 62368-1:2014 + AC:2015 . Flammability (PCBs): UL 94 V-0
EMC . EN 55022 (radio disturbance) . IEC 61000-4-2 (ESD) . IEC 61000-4-3 (electromagnetic field immunity) . IEC 61000-4-4 (burst) . IEC 61000-4-5 (surge) . IEC 61000-4-6 (conducted disturbances)
Reliability . 365 000 h predicted @ 40 °C according to IEC/TR 62380 (RDF 2000)
BIOS/Boot Loader . AMI Aptio UEFI Firmware
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Software Support . Linux - Supported kernel: 4.8 or higher. For older kernels (e.g., 4.4.x), patches for the Apollo Lake platform are also available. - Yocto BSP - Tested with: Yocto BSP (Sumo 2.5, Linux kernel 4.15) . Windows - Windows 10 IoT Enterprise 64-bit . VxWorks - BSP on request . QNX - BSP on request
See the MEN website for available packages and more details on supported functions: www.men.de/products/f26l/#downl
1.5 Product Identification
MEN documentation may describe several different models and design revisions of the F26L. You can find the article number, design revision and serial number affixed to the F26L. . Article number: Indicates the product family and model. This is also MEN’s main ordering number. To be complete it must have 9 characters. . Revision number: Indicates the design revision of the product. . Serial number: Unique identification assigned during production. If you need support, you should communicate these numbers to MEN.
Figure 5. Product labels
Complete article number
Revision number Serial number
20F026L00 E2 2019-10-22 Page 19 Getting Started
2 Getting Started
2.1 Configuring the Hardware
Check your hardware requirements before installing the board in a system. Modifications are difficult or impossible to do when the board is integrated in a system.
MEN offers suitable accessory articles for F26L. See the MEN website for ordering information: www.men.de/products/f26l/#ord
2.1.1 Installing an mSATA Disk
See Figure 2, Board layout – top view on page 12 for the slot position.
The following steps are necessary: » Put the board on a flat surface. » Align the mSATA card properly at a 30° angle to the mSATA connector on the F26L. » Firmly push the mSATA card down while plugging it in the mSATA connector on the F26L. » Make sure the mounting holes are aligned with the screw holes. » Fasten the mSATA card to the board from the top side using two M2.5x4 screws. Use screws with thread locker to ensure vibration resistance.
3
3 mSATA disk
1 2
Card connector
.
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2.1.2 Installing a microSD Card
See Figure 3, Board layout – bottom view on page 13 for the slot position.
The following steps are necessary: » Put the board on a flat surface. » Insert the card into the slot with the contacts facing the PCB.
PCB
Card slot
microSD card
» Make sure the card clicks into place properly. » To eject the card, push it until it springs out, then pull the card out of the slot.
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2.2 Connecting and Starting
You can use the following check list when installing the board in a system for the first time and with minimum configuration. » Power down the system. » Remove all boards from the CompactPCI system. » Insert the F26L into the system slot of your system, making sure that the backplane connectors are properly aligned. Note: The system slot of every system is marked by a triangle on the backplane and/or at the front panel: It also has red guide rails. » Connect a USB keyboard and mouse to the USB connectors at the front panel. » Connect a display to the VGA connector at the front panel. » Power up the system. » You can start up the UEFI firmware setup menu by hitting the
See Chapter 4 UEFI Firmware on page 46.
2.2.1 Configuring the UEFI Firmware for PXE Boot To enable PXE booting of the F26L, configure the UEFI firmware as follows: . For UEFI mode: - Menu MEN: Setup Mode [Extended] - Menu Advanced: Network Stack Configuration > Network Stack [Enabled] > IPV4 PXE Support [Enabled] . For Legacy BIOS mode: - Menu Advanced: CSM Configuration > CSM Support [Enabled] - Menu Advanced: CSM Configuration > Option ROM Execution > Network [Legacy] - Menu Advanced: CSM Configuration > Option ROM Execution > Video [Legacy]
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2.3 Troubleshooting at Start-up
2.3.1 Errors Signaled by the Front-Panel Status LED If you have any problems at start-up of the F26L, you can do the following: . Check if the front-panel status LED gives an error flash code.
See Chapter 2.3.1 Errors Signaled by the Front-Panel Status LED on page 23.
. Start the board with firmware default settings for troubleshooting.
See Chapter 4 UEFI Firmware on page 46.
2.4 Installing Operating System Software
By default, no operating system is installed on the F26L.
. Please refer to the respective manufacturer's documentation on how to implement the operating system. . See the MEN website for all available software: www.men.de/products/f26l/#downl
2.5 Installing Driver Software
For a detailed description on how to install driver software, please refer to the respective documentation of the software package to be installed.
See the MEN website for all available software: www.men.de/products/f26l/#downl
20F026L00 E2 2019-10-22 Page 23 Getting Started
2.6 Using the F26L under Linux
2.6.1 F26L Linux BSP MEN offers a Linux BSP supporting the F26L.
. More information and download: www.men.de/products/f26l/#downl . BSP documentation: www.men.de/products/f26l/#doc
2.6.2 Accessing SMBus/I2C Devices using Standard Linux I2C Tools For detailed information how to access SMBus/I2C devices using standard Linux I2C tools:
See the MEN website for application note Using the Standard I2C Tools on MEN CPUs under Linux.
More information on supported functions and hardware implementation
. See Chapter 5.1 SMBus/I2C Devices on page 57.
2.6.3 Managing RTC Time Adjustments During the boot process, the CPU firmware gets the time from the system RTC (ERTC) and sets the CRTC (Chipset Real-Time Clock) accordingly. In the next step, the operating system (OS) gets the time from the CRTC and sets the system time accordingly. Now the OS system time is updated independently of the CRTC via periodic clock interrupts. Thus, over time (i.e. as the system runs), the system time may become out of sync with the CRTC/ERTC time. If the system time is adjusted (e.g. by the user), the ERTC time will not be automatically adjusted by the time management, because the OS is not aware of the additional ERTC. The ERTC time will not be updated and is out of date. During the next system boot, the OS would use the outdated time. MEN provides a dedicated ERTC driver to manage system time adjustments.
See the MEN website for application note Using the System RTC (ERTC) on MEN CPUs under Linux.
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2.7 Using the F26L under Windows
2.7.1 Accessing SMBus/I2C Devices MEN provides the Windows ERTC/SMB Support Package (13Y021-70) for accessing SMBus/I2C devices, e.g., board management functions. » Install the Windows ERTC/SMB Support Package 13Y021-70.
See the MEN website for detailed information and documentation for 13Y021-70: www.men.de/software/13y021-70/
. All necessary drivers are installed automatically. All available devices are visible in the device manager as "MDIS5 devices", e.g.: . smb2_1 provides generic access to all SMB devices . xm01bc_1 provides access to some specific board management controllers (BMC) . lm63_1 provides access to the LM63 temperature and fan controller Note: Not all MEN products provide the devices above. Therefore, not all MDIS5 devices may be available in your system. Note: The device name suffix number (e.g., _1, _2) is assigned during the driver installa- tion. It is an increasing number (1, 2, 3, ...) and may change after a driver update. E.g., if your CPU product provides two SMBus controllers, you may see smb2_3 and smb2_4 in your device manager.
More information on supported functions and hardware implementation
. See Chapter 3.4 Supervision and Management on page 28. . See Chapter 3.6 Real-Time Clock (RTC) on page 30. . See Chapter 5.1 SMBus/I2C Devices on page 57.
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2.7.1.1 Accessing SMBus/I2C Devices via Generic Access using smb2_ctrl The smb2_ctrl tool provides direct access to any SMBus/I2C device. The tool provides two different operation modes: . Command Line Interface (CLI) Mode: The tool operates in this mode when you call smb2_ctrl only with the device name parameter, e.g.: smb2_ctrl smb2_1. Then you will get a CLI that asks you for further actions. . Command Mode: Call smb2_ctrl with the device name parameter and at least the action (i.e. the command) you want to perform. E.g.: smb2_ctrl smb2_1 rb Note: The command mode is useful to script the tool. For a detailed description about all supported tool options, just call smb2_ctrl, e.g.: C:\MEN\ErtcSmb\Applications> smb2_ctrl
Usage Examples . List all available SMB devices at SMBus instance smb2_1: > smb2_ctrl smb2_1 list
. Access the board information EEPROM (SMB address 0xAC) to read byte at offset 8: > smb2_ctrl smb2_1 rbd -a=0xac -o=0x8
. Access the CPU board BMC (in this example at SMB address 0x9C) to read out the operating hours counter: > smb2_ctrl smb2_1 rbk -a=0x9c -o=0x94
. Access the CPU board BMC (in this example at SMB address 0x9C) to set the upper limit of the watchdog to 200 ms: > smb2_ctrl smb2_1 wwd -a=0x9c -o=0x14 -d=0x0002
2.7.2 Managing RTC Time Adjustments During the boot process, the CPU firmware gets the time from the system RTC (ERTC) and sets the CRTC (Chipset Real-Time Clock) accordingly. In the next step, the operating system (OS) gets the time from the CRTC and sets the system time accordingly. Now the OS system time is updated independently of the CRTC via periodic clock interrupts. Thus, over time (i.e. as the system runs), the system time may become out of sync with the CRTC/ERTC time. If the system time is adjusted (e.g. by the user), the ERTC time will not be automatically adjusted by the time management, because the OS is not aware of the additional ERTC. The ERTC time will not be updated and is out of date. During the next system boot, the OS would use the outdated time. MEN provides a dedicated ERTC driver to manage system time adjustments.
See the MEN website for user manual Windows ERTC/SMB Support Package.
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3 Functional Description
3.1 Power Supply
The F26L is supplied via the backplane. There are two possible ways to do this: . Option 1: +5V, +3.3V and +12V via CompactPCI connector J1 . Option 2: +5V only via CompactPCI connector J1
If +3.3 V are supplied via CompactPCI connector J1, the +12 V supply always has to be present. If the +12 V are not present, the board automatically generates +3.3 V and feeds it to the backplane. This creates a conflict with the external +3.3 V supply and may cause serious damage to the board or the system.
3.2 CPU
3.2.1 Processor Core The following CPU types are supported: . Intel Atom x5-E3930, 2 cores, 2 threads, 1.3 GHz, 1.8 GHz Turbo Boost, 6.5 W, 2 MB cache . Intel Atom x5-E3940, 4 cores, 4 threads, 1.6 GHz, 1.8 GHz Turbo Boost, 9.5 W, 2 MB cache . Intel Atom x7-E3950, 4 cores, 4 threads, 1.6 GHz, 2.0 GHz Turbo Boost, 12 W, 2 MB cache
3.2.2 Thermal Considerations The power dissipation of F26L heavily depends on its processor and I/O configuration and on the workload. A suitable heat sink is provided to meet thermal requirements.
If you use a heat sink not specifically designed for the F26L, or no heat sink at all, warranty on functionality and reliability of the F26L may cease. Please contact MEN if you have any questions or problems regarding thermal behavior.
3.3 Trusted Platform Module (TPM)
A trusted platform module for authenticating the hardware to ensure platform integrity is available on the F26L. The TPM module is compliant to the TPM v2.0 specification.
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3.4 Supervision and Management
The F26L provides an intelligent board management controller (BMC) with the following main features: . System watchdog . Operating hours counter . Power cycle counter . Voltage supervision . Error state logging
3.4.1 Watchdog The watchdog device monitors the CPU board on operating system level. If enabled, the watchdog must be triggered by application software. If the trigger is overdue, the watchdog initiates a board reset and in this way can put the system back into operation when the software hangs. The watchdog unit can be enabled or disabled, as required and the watchdog timeout can be set in 100-ms steps from 100 ms up to 1:49:10 (hh:mm:ss) - 65536 steps.
3.4.2 Temperature Measurement The F26L uses a temperature device to measure the local CPU board temperature.
3.4.3 Status LEDs
3.4.3.1 CPU Board Status LED
Table 1. CPU status LED at front panel Label Color Function STA Yellow Indicates F26L status messages: . On: F26L firmware starting . Off: F26L is switched off . Blinking: F26L is in stand-by (S3) status . Blinking with n flashes: Error code During normal operation the LED can be switched on and off using software.
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Error Codes In case of an error, the LED displays the following error messages by repeatedly flashing n times, then pausing for one second, and then repeating the error code:
Table 2. Error codes signaled via status LED flashes Number of Flashes Error 1 +3.3 V failure 2 Input voltage failure 3 External power supply failure 4CPU too hot 5 F26L firmware timeout >5 Internal error
See the ACPI Specification for more details on the power states S0 to S5: Advanced Configuration and Power Interface Specification Version 6.1 January, 2016 Unified EFI Forum uefi.org/specifications
3.4.4 Software Support
See Chapter Getting Started for more information on software support: . Linux: Chapter 2.6.2 Accessing SMBus/I2C Devices using Standard Linux I2C Tools on page 24 . Windows: Chapter 2.7.1 Accessing SMBus/I2C Devices on page 25
3.5 Reset
The F26L has a reset button at the front panel. It is recessed within the front panel and requires a tool, e.g., paper clip to be pressed, to prevent activation by mistake. The F26L can be reset using the reset button at the front panel or the PBRST# signal on the backplane.
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3.6 Real-Time Clock (RTC)
The F26L includes a real-time clock connected to the processor as a system RTC (ERTC). The RTC has an accuracy of approximately 1.7 seconds/day (11 minutes/year) at 25°C and supports operation up to the year 2199, which prevents the year 2038 bug on 32-bit systems. The real-time clock device is connected to the CPU via SMBus.
. ERTC (External Real-Time Clock) is a real-time clock additionally connected to the processor as a system RTC. . CRTC (Chipset Real-Time Clock) is the real-time clock of the processor.
For data retention during power off the RTC is backed up by a supercapacitor. The supercapacitor gives an autonomy of up to 72 hours (3 days) when fully charged. As an option, the RTC can be backed by a battery. This can buffer the RTC for approx. one year, if the F26L remains fully unpowered.
See the MEN website for ordering information: www.men.de/products/f26l/#ord
3.6.1 Software Support Please note that the real-time clock integrated in the processor is not used. Configuring the date and time through the means provided by the operating system does not set the system RTC. You can set the system date and time through the UEFI firmware.
See Chapter 4.3.1 Main Menu on page 47 for the configuration in firmware.
If you use dedicated MEN driver software supporting the system RTC, you can use the functions provided there to set the system RTC also via software.
See Chapter Getting Started for more information on software support: . Linux: Chapter 2.6 Using the F26L under Linux on page 24 . Windows: Chapter 2.7.1 Accessing SMBus/I2C Devices on page 25
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3.7 Memory
3.7.1 System RAM The DRAM system memory of F26L is scalable.
. See Chapter 1.4 Technical Data on page 16. . See the MEN website for available standard configurations: www.men.de/products/f26l/#ord
3.7.2 Boot Flash The boot Flash memory contains the UEFI firmware and the Intel Trusted Execution Engine (Intel TXE) firmware.
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3.8 Mass Storage
3.8.1 mSATA Slot
MEN offers suitable accessory articles for F26L. See the MEN website for ordering information: www.men.de/products/f26l/#ord
.
See Chapter 2.1.1 Installing an mSATA Disk on page 20.
3.8.2 microSD Card Slot Supported standards: . Secure Digital 1.0 specification (microSD) . Secure Digital 2.0 specification (microSDHC) . Secure Digital 3.0 specification (microSDXC) Supported speed classes: . Class 2 / 4 / 6 / 8 / 10 . UHS-I
MEN offers suitable accessory articles for F26L. See the MEN website for ordering information: www.men.de/products/f26l/#ord
See Chapter 2.2 Connecting and Starting on page 22.
3.8.3 Serial ATA (SATA) The F26L supports . AHCI operation . RAID operation
3.8.3.1 Side-Card Connection
See Chapter 5.1.1 Side-Card Interface on page 53.
See the MEN website for available side cards and board versions: www.men.de/products/f26l/#ord
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3.9 Video
3.9.1 VGA
3.9.1.1 Front Connection
Table 3. Connector types – VGA Connector Type On F26L 15-pin HD-Sub receptacle according to DIN41652/MIL-C-24308, with thread bolt UNC 4-40 Mating 15-pin HD-Sub plug according to DIN41652/MIL-C-24308, available for ribbon cable (insulation piercing connection), hand-soldering connection or crimp connection
Table 4. Pin assignment – VGA 10 15 SCL 10 GND 5 GND 15 5 14 VSYNC 9 - 4 - 13 HSYNC 8 GND 3 B 11 1 12 SDA 7 GND 2 G 6 11 - 6 GND 1 R
Table 5. Signal mnemonics – VGA Signal Direction Function GND - Digital ground HSYNC out Horizontal synchronization R, G, B out Analog monitor interface (red, green, blue) SCL out Monitor I2C interface SDA in/out VSYNC out Vertical synchronization
3.9.1.2 Rear Connection (optional)
. Refer to the CompactPCI PlusIO standard PICMG 2.30 for the exact position of the VGA ports on the rear I/O connectors. . See Chapter 3.15 CompactPCI on page 44 for the exact position of the VGA ports in a CompactPCI PlusIO system.
3.9.2 DDI
3.9.2.1 Side-Card Connection
See Chapter 5.1.1 Side-Card Interface on page 53.
See the MEN website for available side cards and board versions: www.men.de/products/f26l/#ord
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3.10 Audio
3.10.1 Side-Card Connection
See Chapter 5.1.1 Side-Card Interface on page 53.
See the MEN website for available side cards and board versions: www.men.de/products/f26l/#ord
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3.11 USB
3.11.1 Front Connection
Table 6. Connector types – USB 3.0 Connector Type On F26L 9-pin USB 3.0 Standard-A receptacle according to Universal Serial Bus Specification Mating 9-pin USB 3.0 Standard-A plug according to Universal Serial Bus Specification
Table 7. Pin assignment – USB 3.0 1 +5V 9 StdA_SSTX+
1 9 2 D- 8 StdA_SSTX- 8 2 7 3D+7GND 3 6 4 5 4 GND 6 StdA_SSRX+ 5 StdA_SSRX-
Table 8. Signal mnemonics – USB 3.0 Signal Direction Function +5V out +5 V power supply GND - Digital ground D+, D- in/out USB 3.0 lines StdA_SSTX+, StdA_SSTX- out SuperSpeed transmit lines StdA_SSRX+, StdA_SSRX- in SuperSpeed receive lines
3.11.2 Side-Card Connection
See Chapter 3.14 Side-Card Interface on page 41.
See the MEN website for available side cards and board versions: www.men.de/products/f26l/#ord
3.11.3 Rear Connection
. Refer to the CompactPCI PlusIO standard PICMG 2.30 for the exact position of the USB ports on the rear I/O connectors. . See Chapter 3.15 CompactPCI on page 44 for the supported interfaces in a CompactPCI PlusIO system.
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3.12 Ethernet
Implementation: . Intel I211 Gigabit Ethernet controller
3.12.1 Front Connection
3.12.1.1 RJ45
Table 9. Connector types – Ethernet (RJ45) Connector Type On F26L Modular 8/8-pin receptacle according to FCC68 Mating Modular 8/8-pin plug according to FCC68
Table 10. Pin assignment – Ethernet (RJ45) 1000BASE-T 10/100BASE-T 1BI_DA+TX+ 2BI_DA-TX- 3BI_DB+RX+ 1 4BI_DC+- 5BI_DC-- 8 6BI_DB-RX- 7 BI_DD+ - 8 BI_DD- -
3.12.1.2 M12 A-Coded
Table 11. Connector types – Ethernet (8-pin M12 A-coded) Connector Type On F26L 8-pin M12 receptacle A-coded e.g., Phoenix Contact SACC-CI-M12FS-8CON-L90 SCO - 1436990 Mating 8-pin M12 plug A-coded
Note: For railway rolling stock installation, the mating connector must be an approved crimp connector.
Table 12. Pin assignment – Ethernet (8-pin M12) 1000BASE-T 10/100BASE-T 1BI_DC- 2 BI_DD+ 3 BI_DD- 8 1 7 2 4BI_DA-TX- 6 3 5BI_DB+RX+ 5 4 6BI_DA+TX+ 7BI_DC+- 8BI_DB-RX-
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3.12.1.3 M12 D-Coded
Table 13. Connector types – Ethernet (4-pin, M12, D-coded) Connector Type On F26L 4-pin M12 receptacle, D-coded e.g., Conec SAL-12D-FKHW4/A0353 Mating 4-pin M12 plug D-coded
Note: For railway rolling stock installation, the mating connector must be an approved crimp connector.
Table 14. Pin assignment – Ethernet (4-pin M12 D-coded)
2 3 1TX+ 2RX+
4 3TX- 1 4RX-
3.12.1.4 M12 X-Coded
Table 15. Connector types – Ethernet (8-pin M12 X-coded) Connector Type On F26L 8-pin M12 receptacle, X-coded e.g., Phoenix Contact SACC-CI-M12FSX-8CON-L90 - 1424180 Mating 8-pin M12 plug, X-coded
Note: For railway rolling stock installation, the mating connector must be an approved crimp connector.
Table 16. Pin assignment – Ethernet (8-pin M12 X-coded) 1000BASE-T 1BI_DA+ 2BI_DA- 3BI_DB+ 4 5 3 6 4BI_DB-
2 7 5 BI_DD+ 1 8 6 BI_DD- 7BI_DC- 8BI_DC+
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3.12.1.5 Cable Requirements
Table 17. Ethernet cable requirements Requirement Value UL AWM style 20963 (80 °C / 30 V) Signal type / category Ethernet CAT6A, 10 Gbit/s Cable design 4x2xAWG26/7; S/FTP Isolation resistance 500 MΩ/km Loop impedance 290.00Ω/km Line capacity 47 nF/km Characteristic impedance 100 Ω ± 5 Ω (@ 100 MHz)
3.12.2 Rear Connection
See Chapter 3.15 CompactPCI on page 44 for the supported interfaces in a CompactPCI system.
3.12.3 Signal Mnemonics
Table 18. Signal mnemonics – Ethernet Signal Direction Function BI_Dx+/- in/out Data lines for 1000BASE-T RX+/- in Receive data lines for 10/100BASE-T TX+/- out Transmit data lines for 10/100BASE-T
3.12.4 Ethernet MAC Addresses
The unique MAC address is set at the factory and should not be changed. Any attempt to change this address may create node or bus contention and thereby render the board inoperable.
The naming of the interfaces may differ depending on the operating system. The MAC addresses on F26L are:
Table 19. Ethernet MAC addresses Interface Position Base Address ETH1 Upper front 0x 00 C0 3A D1 00 00 ETH2 Lower front 0x 00 C0 3A D1 40 00 ETH3 CompactPCI PlusIO 1_ETH 0x 00 C0 3A D1 80 00 ETH4 CompactPCI PlusIO 2_ETH 0x 00 C0 3A D1 C0 00
"00 C0 3A" is the MEN vendor code. The last six digits form the unique MAC address for each board. The serial number is added by the last three digits in the range: Serial number 42 (ETH1): 0x0000 + 0x002A = 0x002A.
See Chapter 1.5 Product Identification on page 19.
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3.12.5 Ethernet Status LEDs
See Figure 1, Front interfaces on page 13 for the position of the LEDs.
Table 20. Ethernet status LEDs Appearance Color Function Green Indicates the link status .
STA On: Link up . Off: No link
1 . Blinking: n/a 2
3 Yellow Indicates Ethernet activity . On: Transmit/Receive activity 4 . Off: No activity . Blinking: Transmit/Receive activity
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3.13 PCI Express
3.13.1 Side-Card Connection
See Chapter 3.14 Side-Card Interface on page 41.
See the MEN website for available side cards and board versions: www.men.de/products/f26l/#ord
3.13.2 Rear Connection
See Chapter 3.15 CompactPCI on page 44 for the supported interfaces in a CompactPCI system.
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3.14 Side-Card Interface
See Figure 2, Board layout – top view on page 14 for the position of the side-card connector.
See the MEN website for available side cards: www.men.de/products/f26l/#ord
Use this connector exclusively for attachment of a side card! Neither the +3.3V nor the +5V pins of the expansion interface connector are protected against a short circuit.
3.14.1 Onboard Connection
Table 21. Connector types – Side-card interface Connector Type On F26L 114-pin matched impedance receptacle connector, MICTOR 0.64 mm grid Mating 114-pin matched impedance plug connector, MICTOR 0.64 mm grid
Table 22. Pin assignment – Side-card interface, pins 1 - 38 1 GND 2 GND 3 SATA_A_TX+ 4 - 5 SATA_A_TX- 6 - 7 GND 8 GND
129 SATA_A_RX+ 10 - 11 SATA_A_RX- 12 - 13 GND 14 GND 15 PCIE1_TX+ 16 - 17 PCIE1_TX- 18 - 19 GND GND 20 GND 21 PCIE1_RX+ 22 - 23 PCIE1_RX- 24 - 39 40 25 GND 26 GND 27 PCIE0_TX+ 28 - 29 PCIE0_TX- 30 - 31 GND 32 GND 33 PCIE0_RX+ 34 - 35 PCIE0_RX- 36 - 37 GND 38 GND
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Table 23. Pin assignment – Side-card interface, pins 39 - 76 39 +3.3V 40 +3.3V
1241 USB_3_4_OC# 42 HDA_SYNC 43 USB_1_2_OC# 44 HDA_BIT_CLK 45 GND 46 HDA_RST# 47 USB_D4- 48 HDA_SDOUT 49 USB_D4+ 50 HDA_SDIN 51 GND 52 GND 53 USB_D3- 54 PCIE_WAKE# 55 USB_D3+ 56 PLT_RST# 39 40 57 GND+5V 58 - 59 USB_D2- 60 SMB_CLK 61 USB_D2+ 62 SMB_DATA 63 GND 64 GND 65 USB_D1- 66 DPB_OB_AUX+ 67 USB_D1+ 68 DPB_OB_AUX- 69 GND 70 GND 71 PCIE_CLK_A_REF+ 72 PCIE_CLK_B_REF+ 77 78 73 PCIE_CLK_A_REF- 74 PCIE_CLK_B_REF- 75 GND 76 GND
Table 24. Pin assignment – Side-card interface, pins 77 - 114 77 GND 78 GND 79 - 80 - 81 - 82 - 83 GND 84 GND 85 DDIB_[2]- 86 - 87 DDIB_[2]+ 88 - 89 GND 90 GND 91 DDIB_[1]- 92 - 77 78 93 DDIB_[1]+ 94 - 95 GND GND 96 GND 97 DDIB_[0]- 98 - 99 DDIB_[0]+ 100 - 101 GND 102 GND 103 DDIB_[3]- 104 - 105 DDIB_[3]+ 106 - 113 114 107 GND 108 GND 109 DDIB_AUX_EN# 110 - 111 - 112 - 113 DDIB_HPD 114 -
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Table 25. Signal mnemonics of 114-pin side-card connector Signal Direction Function Power +3.3V out +3.3 V power supply +5V out +5 V power supply GND - Digital ground of respective interface SATA SATA_A_RX+, SATA_A_RX- in SATA receive lines, port A SATA_A_TX+, SATA_A_TX- out SATA transmit lines, port A PCI Express PCIE_CLK_A_REF+, out Reference clock A 100 MHz PCIE_CLK_A_REF- PCIE_CLK_B_REF+, out Reference clock B 100 MHz PCIE_CLK_B_REF- PCIE0_RX+, PCIE0_RX- in PCIe receive lines, port 0 PCIE0_TX+, PCIE0_TX- out PCIe transmit lines, port 0 PCIE1_RX+, PCIE1_RX- in PCIe receive lines, port 1 PCIE1_TX+, PCIE1_TX- out PCIe transmit lines, port 1 PCIE_WAKE# in Wake signal from PCIe device to wake F26L from sleep state USB USB_D[1]+, USB_D[1]- in/out USB lines, port 1 USB_D[2]+, USB_D[2]- in/out USB lines, port 2 USB_D[3]+, USB_D[3]- in/out USB lines, port 3 USB_D[4]+, USB_D[4]- in/out USB lines, port 4 USB_1_2_OC# in USB overcurrent, ports 1and 2 USB_3_4_OC# in USB overcurrent, ports 3 and 4 HD Audio HDA_BIT_CLK in/out HD Audio serial data clock HDA_RST# out HD Audio reset HDA_SDIN in HD Audio serial data in HDA_SDOUT out HD Audio serial data out HDA_SYNC out HD Audio synchronization DDI (Digital DDIB_[x]+, DDIB_[x]- out Digital display interface B data lines Display Interface) DPB_OB_AUX+, in/out Digital display interface auxiliary lines DPB_OB_AUX- DDIB_AUX_EN# in Configuration 1: auxiliary enable Other PLT_RST# out Platform reset (global reset) SMB_CLK out System Management Bus clock SMB_DATA in/out System Management Bus data
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3.15 CompactPCI
3.15.1 J1 The pin assignment of rear connector J1 complies with the CompactPCI specification.
CompactPCI Specification PICMG 2.0 R3.0: 1999; PCI Industrial Computers Manufacturers Group (PICMG) www.picmg.org
3.15.2 J2 (CompactPCI PlusIO)
Table 26. Pin assignment – CompactPCI J2 FE D C B AZ 22 GND GA0 GA1 GA2 GA3 GA4 GND 21 GND 1_ETH_B+ 1_ETH_D+ 2_ETH_B+ GND CLK6 GND 20 GND 1_ETH_B- 1_ETH_D- 2_ETH_B- GND CLK5 GND 19 GND 1_ETH_A+ 1_ETH_C+ 2_ETH_A+ GND GND GND FZEDCBA 18 GND 1_ETH_A- 1_ETH_C- 2_ETH_A- 2_ETH_C+ 2_ETH_D+ GND 22 21 17 GND GNT6# REQ6# PBRST# 2_ETH_C- 2_ETH_D- GND CRT_R_D- 16 GND GND DEG# 2_PE_CLK+ 4_PE_CLK- GND DC_CLK 15 GND GNT5# REQ5# FAIL# 2_PE_CLK- 4_PE_CLK+ GND 14 GND PWRBTN# SATA_SCL 4_PE_CLKE# 1_PE_CLK+ 3_PE_CLK- GND 13 GND SATA_SL SATA_SDO 3_PE_CLKE# 1_PE_CLK- 3_PE_CLK+ GND 12 4_SATA_Rx+ SATA_SDI 2_PE_CLKE# 1_PE_CLKE# 4_PE_Rx00+ 11 GND 4_SATA_Rx- 4_SATA_Tx+ 4_USB2+ 4_PE_Tx00+ 4_PE_Rx00- GND 10 3_SATA_Rx+ 4_SATA_Tx- 4_USB2- 4_PE_Tx00- 3_PE_Rx00+ 9 3_SATA_Rx- 3_SATA_Tx+ 3_USB2+ 3_PE_Tx00+ 3_PE_Rx00- 8 2_SATA_Rx+ 3_SATA_Tx- 3_USB2- 3_PE_Tx00- 2_PE_Rx00+ 7 2_SATA_Rx- 2_SATA_Tx+ 2_USB2+ 2_PE_Tx00+ 2_PE_Rx00- 1 6 1_SATA_Rx+ 2_SATA_Tx- 2_USB2- 2_PE_Tx00- 1_PE_Rx00+ 5 1_SATA_Rx- 1_SATA_Tx+ 1_USB2+ 1_PE_Tx00+ 1_PE_Rx00- CRT_R_ 4 1_SATA_Tx- 1_USB2- 1_PE_Tx00- V_IO DDC_DATA 3 GNT4# REQ4# GNT3# GND CLK4 2 REQ3# GNT2# SYSEN# CLK3 CLK2 1 REQ2# GNT1# REQ1# GND CLK1
Note: Signals in gray font are not connected.
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Table 27. Signal mnemonics – CompactPCI connector J2 – CompactPCI and CompactPCI PlusIO rear I/O Signal Direction Function CompactPCI CLK[6:1] out Clocks 1 to 6 PBRST# in Push button reset DEG# in Power supply degenerate FAIL# in Power supply fail PWRBTN# in Power button REQ#/GNT#[6:1] in/out Request/grant pairs 1 to 6 Ethernet 1_ETH_A+, 1_ETH_A- in/out Ethernet port 1, data pair 0 1_ETH_B+, 1_ETH_B- in/out Ethernet port 1, data pair 1 1_ETH_C+, 1_ETH_C- in/out Ethernet port 1, data pair 2 1_ETH_D+, 1_ETH_D- in/out Ethernet port 1, data pair 3 2_ETH_A+, 2_ETH_A- in/out Ethernet port 2, data pair 0 2_ETH_B+, 2_ETH_B- in/out Ethernet port 2, data pair 1 2_ETH_C+, 2_ETH_C- in/out Ethernet port 2, data pair 2 2_ETH_D+, 2_ETH_D- in/out Ethernet port 2, data pair 3 USB 1_USB2+, 1_USB2- in/out USB lines, port 1 2_USB2+, 2_USB2- in/out USB lines, port 2 3_USB2+, 3_USB2- in/out USB lines, port 3 4_USB2+, 4_USB2- in/out USB lines, port 4 PCI Express 1_PE_Rx00+, 1_PE_Rx00- in PCIe receive lines, lane 1 1_PE_Tx00+, 1_PE_Tx00- out PCIe transmit lines, lane 1 2_PE_Rx00+, 2_PE_Rx00- in PCIe receive lines, lane 2 2_PE_Tx00+, 2_PE_Tx00- out PCIe transmit lines, lane 2 3_PE_Rx00+, 3_PE_Rx00- in PCIe receive lines, lane 3 3_PE_Tx00+, 3_PE_Tx00- out PCIe transmit lines, lane 3 4_PE_Rx00+, 4_PE_Rx00- in PCIe receive lines, lane 4 4_PE_Tx00+, 4_PE_Tx00- out PCIe transmit lines, lane 4 [1:4]_PE_CLKE# in Presence detect, PCIe lane 1..4 [1:4]_PE_CLK-, out 100 MHz Reference Clock, PCIe lane 1:4 [1:4]_PE_CLK+ VGA (optional) CRT_R_DDC_CLK Display Data Channel clock CRT_R_DDC_DATA Display Data Channel data lines
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4 UEFI Firmware
The F26L is equipped with the UEFI-based Aptio firmware from AMI. For more user- friendliness it has been modified by MEN. The firmware settings can be entered using a setup menu.
4.1 Accessing the Firmware
Carry out the following steps to enter the setup menu: » Power up the system. » Wait until the following message appears on the screen: Press or
» Press the 1 key. » A dialog appears for entering the password, if passwords have been set. » Enter the user or the administrator password.
See Chapter 4.3.5 Security Menu on page 53.
» The setup menu appears. You can now navigate through the tabs and menus via the keyboard.
4.2 Setup Menus
The UEFI firmware has 7 menus which can be selected via the tabs at the top of the screen. On the right side of the screen, you can find information regarding the functions of the function keys and the selected menu item. In the following, only the MEN-specific MEN menu and the most important features in the other tabs are described. Default values are printed in bold type in the following tables.
4.3 Setup Modes
There are two setup modes for both the user and the administrator profile. Using the standard mode, menu items can be hidden which normally do not have to be modified. The mode can be switched under the MEN tab.
See Chapter 4.3.2 MEN Menu on page 48.
1 When accessing the F26L via a serial console only the
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4.3.1 Main Menu In the Main menu you can look up system parameters and set system language, date and time.
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc. Main Advanced Chipset Security Boot Save & Exit MEN /------+------\ | BIOS Information ^|Choose the system | | BIOS Vendor American Megatrends *|default language | | Core Version 5.12 *| | | Compliancy UEFI 2.5; PI 1.4 *| | | Project Version 1ATJS 0.32 x64 *| | | Build Date and Time 07/25/2017 14:37:29 *| | | Access Level Administrator *| | | *| | | Platform firmware Information *| | | BXT SOC B1 *| | | MRC Version 0.56 *| | | PUNIT FW 28 ^| | | PMC FW 03.28 +| | | TXE FW 3.0.20.1139 +| | | ISH FW 4.1.0.3364 +| | | GOP 0.0.0036 +| | | CPU Flavor BXT Notebook/Desktop ... +| | | Board ID Oxbow Hill CRB (06) +| | | Fab ID FAB A *| | | *| | | *|------| | Memory Information *|><: Select Screen | | Total Memory 4096 MB *|^v: Select Item | | Memory Speed 1600 MHz *|Enter: Select | | *|+/-: Change Opt. | | System Language [English] *|F1: General Help | | *|F2: Previous Values | | System Date [Sat 05/16/2099] *|F3: Optimized Defaults | | System Time [12:24:09] v|F4: Save & Exit | | |ESC: Exit | \------+------/ Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
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4.3.2 MEN Menu The MEN menu has been adapted in order to simplify access to important functions. You can find information regarding board name, board revision and serial number as well as several sub-menus.
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc. Main Advanced Chipset Security Boot Save & Exit MEN /------+------\ | MEN Mikro Elektronik Board Information |SATA Settings Help | | | | | Board Name
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4.3.2.1 MEN Menu – Sub-Functions
Table 28. Functions in the MEN Menu Function Options Setup Mode Standard Extended
4.3.2.2 MEN Menu – Sub-Menu BMC Settings In the sub-menu BMC Settings you can find board information that is read out via the Board Management Controller (BMC), as well as the following sub-functions:
Table 29. Sub-menu BMC Settings Sub-menu Function Options MEN BMC Settings WatchDog Disabled 1 min 2 min 5 min 10 min 15 min 20 min 30 min Power Resume Mode On Off Former State EXT_PWRGD Mode Check at Start-Up only Check always EXT_PS_ON Mode Always on Switched RESET_IN Enabled Blocked MEN BMC Registers For information: displays values from the BMC, e.g. error information
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4.3.2.3 MEN Menu – Sub-Menu Network Settings In the sub-menu Network Settings you can activate and deactivate the Ethernet controllers and the PXE boot functionality.
Table 30. Sub-Menu Network Settings Sub-menu Function Options MEN Network Settings Front Gigabit Ethernet ETH1/ ETH2 Gigabit Ethernet ETH1/ETH2 Enabled Disabled PXE Boot for ETH1/ETH2 Enabled Disabled Backplane - Gigabit Ethernet ETH3/ETH4 Gigabit Ethernet ETH3/ETH4 Enabled Disabled PXE Boot for ETH3/ETH4 Enabled Disabled
4.3.2.4 MEN Menu – Sub-Menu Memory Settings
Table 31. Sub-Menu Memory Settings Sub-menu Function Options MEN Memory Settings ECC Support Auto Disabled Enabled
4.3.2.5 MEN Menu – Sub-Menu SATA Settings In the sub-menu SATA Settings you can set the SATA speed and delay.
Table 32. Sub-Menu SATA Settings Sub-menu Function Options MEN SATA Settings SATA Speed Limit Unlimited Gen1 Gen2 Gen3 SATA Delay No Delay 1 s 2 s
4.3.2.6 MEN Menu – Sub-Menu USB Settings In the sub-menu USB Settings you can set the USB boot.
Table 33. Sub-Menu USB Settings Sub-menu Function Options MEN USB Settings USB Boot Enabled Disabled
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4.3.3 Advanced Menu In the Advanced menu you can change configurations regarding Console Redirection, CPU, Network Stack, CSM, SDIO Configuration and Trusted Platform Memory.
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc. Main Advanced Chipset Security Boot Save & Exit MEN /------+------\ |> Serial Port Console Redirection |> CPU Configuration |CPU Configuration | |> Network Stack Configuration |Parameters | |> CSM Configuration |> SDIO Configuration |> Platform Trust Technology | | | | | | | | | | | | | | | | | | |------| | |><: Select Screen | | |^v: Select Item | | |Enter: Select | | |+/-: Change Opt. | | |F1: General Help | | |F2: Previous Values | | |F3: Optimized Defaults | | |F4: Save & Exit | | |ESC: Exit | \------+------/ Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
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4.3.4 Chipset Most of the functions in this menu normally do not have to be changed during operation. If necessary, by entering the configuration menu you can change the settings regarding, e.g, HD-Audio or PCI Express.
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc. Main Advanced Chipset Security Boot Save & Exit MEN /------+------\ |> South Cluster Configuration |South Cluster | | |Configuration | | | | | | | | | | | | | | | | | | | | | | | |------| | |><: Select Screen | | |^v: Select Item | | |Enter: Select | | |+/-: Change Opt. | | |F1: General Help | | |F2: Previous Values | | |F3: Optimized Defaults | | |F4: Save & Exit | | |ESC: Exit | \------+------/ Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
.
Setting items on this screen to incorrect values can lead to malfunction of the system.
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4.3.5 Security Menu In the Security menu you can enter passwords for the user profiles User and Administrator.
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc. Main Advanced Chipset Security Boot Save & Exit MEN /------+------\ | Password Description |Set Setup Administrator | | |Password | | If ONLY the Administrator's password is set, | | | then this only limits access to Setup and is | | | only asked for when entering Setup. | | | If ONLY the User's password is set, then this | | | is a power on password and must be entered to | | | boot or enter Setup. In Setup the User will | | | have Administrator rights. | | | The password length must be |------| | in the following range: |><: Select Screen | | Minimum length 3 |^v: Select Item | | Maximum length 20 |Enter: Select | | |+/-: Change Opt. | | Setup Administrator Password |F1: General Help | | User Password |F2: Previous Values | | |F3: Optimized Defaults | | Secure Boot |F4: Save & Exit | | |ESC: Exit | \------+------/ Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
Table 34. Setting passwords Function Description Setup Administrator Sets, changes or deletes the administrator password. Password If an administrator password is set the systems asks for this first. For deleting the password enter nothing and press the enter key. For entering a new password enter it twice and press the enter key. User Password Sets, changes or deletes the user password. If a user password is set the system asks for this first. For deleting the password enter nothing and press the enter key. For entering a new password enter it twice and press the enter key.
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Table 35. Security modes Setting Description No password is set Booting the system and opening the UEFI setup is not protected. Only administrator password Booting the system is not protected. is set For opening the UEFI setup, the administrator password is required. Only user password is set Booting the system is not protected. The user password is required for opening the UEFI setup. The user password has to be entered at every system start. Administrator and user Booting the system is not protected. password is set The administrator or the user password is required for opening the UEFI setup. The user password allows only limited access to the setup. The administrator password allows full access to the setup.
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4.3.6 Boot Menu In the boot menu you can make settings regarding boot behavior and boot order.
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc. Main Advanced Chipset Security Boot Save & Exit /------+------\ | Boot Configuration |Number of seconds to | | Setup Prompt Timeout 1 |wait for setup | | Bootup NumLock State [On] |activation key. | | Quiet Boot [Disabled] |65535(0xFFFF) means | | |indefinite waiting. | | Boot Option Priorities | | | Boot Option #1 [UEFI: Built-in EFI ...] | | | Fast Boot [Enable] | | | | | | New Boot Option Policy [Default] |------| | |><: Select Screen | | |^v: Select Item | | |Enter: Select | | |+/-: Change Opt. | | |F1: General Help | | |F2: Previous Values | | |F3: Optimized Defaults | | |F4: Save & Exit | | |ESC: Exit | \------+------/ Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
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4.3.7 Save and Exit Menu In the Save and Exit menu you can set how to handle changes made within the setup and exit the setup. Using the Boot Override function you can boot from a medium different from the one set in the boot order.
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc. Main Advanced Chipset Security Boot Save & Exit MEN /------+------\ | Save Options |Exit system setup after | | Save Changes and Exit |saving the changes. | | Discard Changes and Exit | | | | | | Save Changes and Reset | | | Discard Changes and Reset | | | | | | Save Changes | | | Discard Changes | | | |------| | Default Options |><: Select Screen | | Restore Defaults |^v: Select Item | | Save as User Defaults |Enter: Select | | Restore User Defaults |+/-: Change Opt. | | |F1: General Help | | Boot Override |F2: Previous Values | | UEFI: Built-in EFI Shell |F3: Optimized Defaults | | Launch EFI Shell from filesystem device |F4: Save & Exit | | |ESC: Exit | \------+------/ Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
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5 Hardware/Software Interface
This chapter is intended for software developers or board integrators who need deeper knowledge of the implementation details of the F26L interfaces and its internal connections.
5.1 SMBus/I2C Devices
Table 36. SMBus/I2C devices 8-Bit Address 7-Bit Address Function 0x3E 0x1F Board temperature sensor 0x64 0x32 System RTC (ERTC) 0x9A 0x4D Board Management Controller (BMC) 0xA0 0x50 EEPROM channel A 0xA4 0x52 EEPROM channel B 0xAE 0x57 Board information EEPROM with thermal sensor
Note on 8-Bit/7-Bit Addressing . 8-bit addressing is compliant to the Windows nomenclature. The last bit, which is used as the read/write bit, is added to the address (0 = write, 1 = read). If you use MDIS driver software, use 8-bit addresses, with any OS. . 7-bit addressing is used, e.g., under Linux. A ’0’ is added at the beginning of the address so that all consecutive address bits are moved one bit to the right. If you use standard I2C commands under Linux, use 7-bit addresses.
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5.2 BMC API (Application Programming Interface)
The F26L uses a generic command interface for communication between the host (CPU) and the controller (BMC). Application software uses command packets to communicate with the BMC. The application software controls the BMC via I2C/SMBus. The device address is 0x4D (in 7-bit, non-shifted notation) or 0x9A/0x9B (in 8-bit, shifted notation, write/read).
5.2.1 Command Packets
5.2.1.1 Command Packet Protocol From a logical point of view, the command protocol has the following characteristics: . Commands are always initiated by the host. The controller never sends packets without the host requesting it to do so. . Packets are either - unidirectional from host to controller, without an answer from the controller - bidirectional, with an answer from the controller . Each command has a unique identifier, consisting of the command opcode and a packet type:
Table 37. API – Packet types Request Data Response Data Packet Type Description Host > Controller > Error Signaling Controller Host PT_SB Send Byte: Send command only None No response - PT_RBD Read Byte Data: Send command None 1 byte Response byte = and get one data byte from 0xFF controller PT_WBD Write Byte Data: Send command 1 byte No response - and send one data byte to controller PT_RWD Read Word Data: Send command None 2 bytes Response byte = and get two data bytes from 0xFFFF controller PT_WWD Write Word Data: Send command 2 bytes No response - and send two data bytes to controller PT_RB1 Read Block: Send command and None 1 length byte, First Response get length and up to 32 bytes 1 to 32 data bytes byte = 0xFF PT_WB Write Block: Send command and 1 length byte, No response - send length and up to 32 bytes 1 to 32 data bytes 1 PT_RB always provides the block length as the first byte. The size of the entire block is always one byte greater than the received block length because the block length byte itself is not counted in the length. Do not use the received length byte directly for read block commands, because if there was an error this would lead to an undefined state. It is better to always read a predefined length and use the received length byte to check if the block was correctly transmitted.
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The packet types are directly mapped to the corresponding SMBus “bus protocols” as defined in the System Management Bus Specification.
Table 38. API – Packet types mapping on SMBus Packet Type SMBus Protocol PT_SB Send byte PT_RBD Read byte PT_WBD Write byte PT_RWD Read word PT_WWD Write word PT_WB Block write PT_RB Block read
5.2.1.2 Watchdog Control Commands
Table 39. BMC API – Watchdog commands Command Packet Type Opcode Functional Description WDOG_ON PT_SB 0x11 Enable watchdog WDOG_OFF PT_WBD 0x12 Disable watchdog WDOG_TRIG PT_SB 0x13 Trigger watchdog WDOG_TIME_SET PT_WWD 0x14 Set watchdog timeout value WDOG_TIME_GET PT_RWD 0x14 Get watchdog timeout value WDOG_STATE_GET PT_RBD 0x17 Get watchdog state WDOG_ARM PT_SB 0x18 Arm watchdog and BIOS timeouts ARM_STATE PT_RBD 0x19 Get watchdog arming state
Command WDOG_ON
Opcode: 0x11 Packet Type: PT_SB
Command WDOG_OFF
Opcode: 0x12 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data 0x69
Command WDOG_TRIG
Opcode: 0x13 Packet Type: PT_SB
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Commands WDOG_TIME_SET and WDOG_TIME_GET Command WDOG_TIME_SET
Opcode: 0x14 Packet Type: PT_WWD
Bit 7 6 5 4 3 2 1 0
Data 0 WD_TOUT (LSB)
Data 1 WD_TOUT (MSB)
Command WDOG_TIME_GET
Opcode: 0x14 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 WD_TOUT (LSB)
Data 1 WD_TOUT (MSB)
Bit Field Description
WD_TOUT Trigger timeout, in steps of 100 ms . 0x0001: 100 ms . 0x0002: 200 ms . ... . 0xFFFF: Error
Command WDOG_STATE_GET
Opcode: 0x17 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data WD_STATE
Bit Field Description
WD_STATE Watchdog state . 0x00: Off . 0x01: On . 0xFF: Error
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Command WDOG_ARM
Opcode: 0x18 Packet Type: PT_SB
Command WDOG_ARM_STATE
Opcode: 0x19 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data ARM_STATE
Bit Field Description
ARM_STATE Watchdog arming state . 0x00: Not armed . 0x01: Armed . 0xFF: Error
5.2.1.3 Power Resume Mode Commands These commands allow configuring the behavior of the F26L in case the power is reapplied after a power failure and input voltages return to their allowed limits. The setting is persistent, i.e. it is stored in non-volatile memory. The default resume mode after factory programming is "On".
Table 40. BMC API – Power resume mode commands Command Packet Type Opcode Functional Description RESUME_MODE_SET PT_WBD 0x20 Set power resume mode RESUME_MODE_GET PT_RBD 0x20 Get power resume mode
Table 41. BMC API – Power resume modes Resume Mode System State at Power Loss Resume Action On On Start power-up sequence Off Start power-up sequence Off On Stay in S4/S5 state Off Stay in S4/S5 state Former On Start power-up sequence Off Stay in S4/S5 state
S0 to S5 are the power states as defined in the ACPI specification, or an equivalent state.
See the ACPI Specification for more details on the power states S0 to S5: Advanced Configuration and Power Interface Specification Version 6.1 January, 2016 Unified EFI Forum uefi.org/specifications
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Commands RESUME_MODE_SET and RESUME_MODE_GET Command RESUME_MODE_SET
Opcode: 0x20 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data RES_MODE
Command RESUME_MODE_GET
Opcode: 0x20 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data RES_MODE
Bit Field Description
RES_MODE Resume mode . 0x00: Off . 0x01: On . 0x02: Former
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5.2.1.4 External Power Supply Failure Mode These commands allow configuring the behavior of the F26L upon assertion of an external power supply fail signal. Modes: . Ignore: Assertion of external power failure signal is completely ignored. . Treat as error: Assertion of external power failure is treated as an error; i.e. event is counted as an error and F26L is reset. The setting is persistent, i.e. it is stored in non-volatile memory. The default external power supply fail signal mode after factory programming is "Ignore".
Table 42. BMC API – External power supply failure mode commands Command Packet Type Opcode Functional Description EXT_PWR_FAIL_MODE_SET PT_WBD 0x21 Set external power supply failure mode EXT_PWR_FAIL_MODE_GET PT_RBD 0x21 Get external power supply failure mode
Commands EXT_PWR_FAIL_MODE_SET and EXT_PWR_FAIL_MODE_GET Command EXT_PWR_FAIL_MODE_SET
Opcode: 0x21 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data EXT_PWR_FAIL_MODE
Command EXT_PWR_FAIL_MODE_GET
Opcode: 0x21 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data EXT_PWR_FAIL_MODE
Bit Field Description
EXT_PWR_FAIL_MODE External power supply failure mode . 0x00: Ignore . 0x01: Treat as error . 0xFF: Error
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5.2.1.5 Reset Signal Blocking These commands allow blocking of F26L reset inputs. The setting is persistent, i.e. it is stored in non-volatile memory. In a system with master and slave CPU boards, normally the slave boards will get a reset whenever the master board resets. With "Reset Signal Blocking" configuration it is possible to decide at runtime for the slave boards whether they should get a reset whenever the master board resets or whether the slave board should operate independently. Additionally with this functionality it is possible to disable external reset for the master board where needed. The default mode after factory programming is "Reset enabled".
Table 43. BMC API – Reset signal blocking commands Command Packet Type Opcode Functional Description RESET_IN_MODE_SET PT_WBD 0x22 Set reset input mode RESET_IN_MODE_GET PT_RBD 0x22 Get reset input mode
Commands RESET_IN_MODE_SET and RESET_IN_MODE_GET Command RESET_IN_MODE_SET
Opcode: 0x22 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data RESET_IN_MODE
Command RESET_IN_MODE_GET
Opcode: 0x22 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data RESET_IN_MODE
Bit Field Description
RESET_IN_MODE Reset input mode . 0x00: Reset enabled . 0x01: Reset masked . 0xFF: Error
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5.2.1.6 External Power Supply Control In Master mode, the BMC uses the EXT_PS_ON signal to switch the external power supply on and off. In Slave mode, the BMC does not control the EXT_PS_ON signal.
Table 44. BMC API – External power supply control commands Command Packet Type Opcode Functional Description EXT_PS_ON_MODE_SET PT_WBD 0x23 Set EXT_PS_ON mode EXT_PS_ON_MODE_GET PT_RBD 0x23 Get EXT_PS_ON mode
Commands EXT_PS_ON_MODE_SET and EXT_PS_ON_MODE_GET Command EXT_PS_ON_MODE_SET
Opcode: 0x23 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data EXT_PS_ON_MODE
Command EXT_PS_ON_MODE_GET
Opcode: 0x23 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data EXT_PS_ON_MODE
EXT_PS_ON_MODE External power supply on/off mode . 0x00: Invalid . 0x01: Always . 0x02: Switched . 0xFF: Error
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5.2.1.7 Software Reset These commands allow performing CPU resets under application software control. Different types of resets are available: . SW_RESET issues a “warm reset”. . SW_COLD_RESET issues a “cold reset”. . SW_RTC_RESET issues a “cold reset”, together with an RTC reset. Resets will be performed by writing the data word 0xDEAD, see below.
Table 45. BMC API – Software reset commands Command Packet Type Opcode Functional Description SW_RESET PT_WWD 0x31 Initiate software reset (warm reset) SW_COLD_RESET PT_WWD 0x32 Initiate cold reset SW_RTC_RESET PT_WWD 0x35 Initiate cold reset combined with RTC reset
Command SW_RESET
Opcode: 0x31 Packet Type: PT_WWD
Bit 7 6 5 4 3 2 1 0
Data 0 0xAD
Data 1 0xDE
Command SW_COLD_RESET
Opcode: 0x32 Packet Type: PT_WWD
Bit 7 6 5 4 3 2 1 0
Data 0 0xAD
Data 1 0xDE . Command SW_RTC_RESET
Opcode: 0x35 Packet Type: PT_WWD
Bit 7 6 5 4 3 2 1 0
Data 0 0xAD
Data 1 0xDE
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5.2.1.8 Power Button These commands allow initiating power button events.
Table 46. BMC API – Power button commands Command Packet Type Opcode Functional Description PWRBTN PT_WBD 0x33 Perform pressing of power button PWRBTN_OVRD PT_WBD 0x34 Perform power button override, i.e. assert the power button for more than 4 seconds to initiate system shutdown
Command PWRBTN
Opcode: 0x33 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data 0x69
Command PWRBTN_OVRD
Opcode: 0x34 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data 0x69
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5.2.1.9 Voltage Supervision The voltage supervision commands allow the customer application to monitor different voltages on the F26L.
Table 47. BMC API – Voltage supervision commands Command Packet Type Opcode Functional Description VOLT_LOW(0) PT_RWD 0x40 Get lower limit of +3.3 V (in mV) VOLT_LOW(1) PT_RWD 0x41 Get lower limit of +5 V (in mV) VOLT_LOW(2) PT_RWD 0x42 Get lower limit of +12 V (in mV) VOLT_LOW(3) PT_RWD 0x43 Get lower limit of +5 V standby (in mV) VOLT_LOW(4) PT_RWD 0x44 Get lower limit of battery voltage (in mV) VOLT_HIGH(0) PT_RWD 0x50 Get upper limit of +3.3 V (in mV) VOLT_HIGH(1) PT_RWD 0x51 Get upper limit of +5 V (in mV) VOLT_HIGH(2) PT_RWD 0x52 Get upper limit of +12 V (in mV) VOLT_HIGH(3) PT_RWD 0x53 Get upper limit of +5 V standby (in mV) VOLT_HIGH(4) PT_RWD 0x54 Get upper limit of battery voltage (in mV) VOLT_ACT(0) PT_RWD 0x60 Get actual value of +3.3 V (in mV) VOLT_ACT(1) PT_RWD 0x61 Get actual value of +5 V (in mV) VOLT_ACT(2) PT_RWD 0x62 Get actual value of +12 V (in mV) VOLT_ACT(3) PT_RWD 0x63 Get actual value of +5 V standby (in mV) VOLT_ACT(4) PT_RWD 0x64 Get actual value of battery voltage (in mV) NUM_VOLTS PT_RBD 0x8E Get number of supervised voltages
Command VOLT_LOW(x)
Opcode: 0x40 + x Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Lower limit of voltage x (LSB)
Data 1 Lower limit of voltage x (MSB)
Command VOLT_HIGH(x)
Opcode: 0x50 + x Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Upper limit of voltage x (LSB)
Data 1 Upper limit of voltage x (MSB)
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Command VOLT_ACT(x)
Opcode: 0x60 + x Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Actual value of voltage x (LSB)
Data 1 Actual value of voltage x (MSB)
Command NUM_VOLTS
Opcode: 0x8E Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data Number of supervised voltages
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5.2.1.10 Error Counters The error counter commands allow querying and clearing error counters. The BMC provides error counters for each type of error that can occur. Using this information, the application software can determine how often certain errors have occurred, but it is not possible to determine the chronological order of the errors. You can determine the actual number of error counters using NUM_ERR_CNTRS, up to a theoretical maximum of 255 error counters. All counters are set to zero during factory programming or using command ERR_CNT_CLR.
Table 48. BMC API – Error counters Counter Error Condition / Error Clearing 1 External BMC watchdog timeout (application software timeout) 2 Internal BMC watchdog timeout 3 Internal brown-out (BMC undervoltage) 4 External power failure 5 BIOS life sign timeout 6Processor too hot 7 Shutdown while too hot 8 Internal power failure 9Handshake timeout 10 Platform reset timeout 11 Error cleared using system reset 12 Error cleared using power cycling 13 Error cleared using power cycling with resume reset 14 Error cleared using power cycling with RTC reset 15 Error could not be corrected
Table 49. BMC API – Error counter commands Command Packet Type Opcode Functional Description ERRCNT_01 PT_RBD 0x70 Get error counter 1 ERRCNT_xx 0x70 + x Get error counter xx ERRCNT_15 0x7E Get error counter 15 ERR_CNT_CLR PT_WBD 0x7F Clear error counters NUM_ERR_CNTRS PT_RBD 0x8D Get number of error counters
Command ERRCNT_xx (1 to 15)
Opcode: 0x70 + x Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data Value of error counter number xx
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Command ERRCNT_xx (16 to 32)
Opcode: 0xB0 + x Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data Value of error counter number xx
Command ERR_CNT_CLR This command clears all error counters.
Opcode: 0x7F Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data 0x69
Command NUM_ERR_CNTRS
Opcode: 0x8D Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data Number of error counters
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5.2.1.11 Firmware Revision The firmware revision commands allow querying the separate parts of the BMC firmware revision.
Table 50. BMC API – Firmware version commands Command Packet Type Opcode Functional Description GETREV_WORD0 PT_RWD 0x80 Get firmware revision major part GETREV_WORD1 PT_RWD 0x81 Get firmware revision minor part GETREV_WORD2 PT_RWD 0x82 Get firmware revision maintenance part GETREV_WORD3 PT_RWD 0x83 Get firmware revision build part GETREV_WORD4 PT_RWD 0x84 Get firmware revision verification marker
Command GETREV_WORD0
Opcode: 0x80 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Firmware Revision Major Part (LSB)
Data 1 Firmware Revision Major Part (MSB)
Command GETREV_WORD1
Opcode: 0x81 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Firmware Revision Minor Part (LSB)
Data 1 Firmware Revision Minor Part (MSB)
Command GETREV_WORD2
Opcode: 0x82 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Firmware Revision Maintenance Part (LSB)
Data 1 Firmware Revision Maintenance Part (MSB)
Command GETREV_WORD3
Opcode: 0x83 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Firmware Revision Build Part (LSB)
Data 1 Firmware Revision Build Part (MSB)
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Command GETREV_WORD4
Opcode: 0x84 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 Firmware Revision Verification Marker (LSB)
Data 1 Firmware Revision Verification Marker (MSB)
Table 51. BMC API – Backplane slot geographical address command Command Packet Type Opcode Functional Description CPCI_SLOT_ADDRESS PT_RBD 0x8C Get CompactPCI peripheral slot address
5.2.1.12 Hardware Board Type This command allows the BMC to query the board type, i.e. a unique ID that MEN assigns to each hardware board the generic BMC is implemented on. The board type is programmed into the BMC during production. The setting is persistent, i.e. is stored in a non-volatile memory.
Command HW_BOARD_GET
Opcode: 0x8F Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 BOARD (LSB)
Data 1 BOARD (MSB)
Bit Field Description
BOARD Unique MEN board ID
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5.2.1.13 Last Error This command allows querying the last error.
Table 52. BMC API – Last error command Command Packet Type Opcode Functional Description ERR_LAST PT_RBD 0x90 Get last error
Command ERR_LAST
Opcode: 0x90 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data LAST_ERR_CODE
Bit Field Description
LAST_ERR_CODE Last error . 0x00: Initial value; no error was registered by the BMC since the Last Error Register was cleared . 0x01: +3.3 V voltage failure . 0x02: Input voltage failure . 0x03: External power supply failure . 0x04: CPU too hot . 0x05: BIOS life sign timeout . 0x06: System reset timeout . 0x07: Platform reset failure . 0x08: Chipset handshake failure . 0x09: System power OK failure . 0xFF: Error
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5.2.1.14 Power Failure Flags This command allows querying the power failure flags of the F26L.
Table 53. BMC API – Power failure flags command Command Packet Type Opcode Functional Description ERR_PWR_FLAGS PT_RBD 0x91 Get power failure flags
Command ERR_PWR_FLAGS Whenever a power failure occurs, the respective flag is set to 1 until the Power Failure Flag Register is cleared.
Opcode: 0x91 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
SYS_ Data BATT - EXT 12V 5V_ STDBY 5V 33V PWROK
Bit Field Description
Initial Value 0x00: No power failure was registered by the BMC since the Power Failure Flag Register was cleared.
BATT Battery failure
EXT External power supply failure
SYS_PWROK System power OK failure
12V +12 V input voltage failure
5V_STDBY +5 V standby voltage failure
5V +5 V input voltage failure
33V +3.3 V voltage failure
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5.2.1.15 Reset Reason This command allows querying the reason of the last reset. The BMC maintains a Reset Reason Register that stores the reason for the last reset issued by the BMC.
Table 54. BMC API – Reset reason command Command Packet Type Opcode Functional Description ERR_RST_RSN PT_RBD 0x92 Get reason of last reset
Command ERR_RST_RSN
Opcode: 0x92 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data RST_REASON
Bit Field Description
RST_REASON Reason of last reset . 0x00: Initial value; no reset was issued by the BMC since the Reset Reason Register was cleared . 0x01: Regular reset . 0x02: External BMC watchdog timeout (application software timeout) . 0x03: Internal BMC watchdog timeout . 0x04: Internal brown-out reset (BMC undervoltage) . 0x05: External reset . 0x06: Platform reset . 0x07: Software warm reset . 0x08: Software cold reset . 0x09: Software cold reset with RTC reset . 0x0A: Power failure . 0x0B: Chipset handshaking timeout . 0x0C: PLT_RST timeout . 0x0D: BIOS life sign timeout
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5.2.1.16 Clear Error Registers This command allows clearing the Reset Reason Register, Last Error Register and Power Failure Flag Register, collectively called ’error registers’.
Table 55. BMC API – Clear error registers command Command Packet Type Opcode Functional Description ERR_REG_CLR PT_WBD 0x9F Clear error registers
Command ERR_REG_CLR
Opcode: 0x9F Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data 0x69
5.2.1.17 Power Cycle Counter The power cycle counter counts the number of power cycles of the external power supply, i.e. the number of times the system changes from S5 into S0 state. S0 to S5 are the power states as defined in the ACPI specification, or an equivalent state.
See the ACPI Specification for more details on the power states S0 to S5: Advanced Configuration and Power Interface Specification Version 6.1 January, 2016 Unified EFI Forum uefi.org/specifications
The counter is set to zero during factory programming.
Table 56. BMC API – Power cycle counter command Command Packet Type Opcode Functional Description PWRCYCL_CNT PT_RWD 0x93 Get power cycle counter
Command PWRCYCL_CNT
Opcode: 0x93 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 PWR_CYCLES (LSB)
Data 1 PWR_CYCLES (MSB)
Bit Field Description
PWR_CYCLES Number of power cycles on the external power supply
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5.2.1.18 Operating Hours Counter This command allows querying the operating hours counter. The operating hours counter counts the number of hours and minutes the board has been (at least partly) powered on, i.e. when the system is in S3 or S0 state. S0 to S5 are the power states as defined in the ACPI specification, or an equivalent state.
See the ACPI Specification for more details on the power states S0 to S5: Advanced Configuration and Power Interface Specification Version 6.1 January, 2016 Unified EFI Forum uefi.org/specifications
The counter is set to zero during factory programming.
Table 57. BMC API – Operating hours counter command Command Packet Type Opcode Functional Description OP_HRS_CNT PT_RWD 0x94 Get Operating Hours Counter
Command OP_HRS_CNT
Opcode: 0x94 Packet Type: PT_RWD
Bit 7 6 5 4 3 2 1 0
Data 0 OP_TIME (LSB)
Data 1 OP_TIME (MSB)
Bit Field Description
OP_TIME Number of hours the board has been powered on
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5.2.1.19 Status LED Control This command allows controlling status LEDs, depending on implementation on the product.
Table 58. BMC API – Status LED control command Command Packet Type Opcode Functional Description LED_CTRL_SET PT_WBD 0xA0 Set LED state LED_CTRL_GET PT_RBD 0xA0 Get LED state
Command LED_CTRL_SET
Opcode: 0xA0 Packet Type: PT_WBD
Bit 7 6 5 4 3 2 1 0
Data - STA
Command LED_CTRL_GET
Opcode: 0xA0 Packet Type: PT_RBD
Bit 7 6 5 4 3 2 1 0
Data - STA
Bit Field Description
STA Status LED at front panel . 0: Off . 1: On
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6Maintenance
6.1 Lithium Battery
Some models of the F26L include a lithium battery. The following is valid only for F26L models with a battery.
The F26L is equipped with a lithium battery. There is a danger of explosion if the battery is incorrectly replaced! . Replace only with the same or equivalent type. . Manufacturer: Renata . Type: CR1025 . Capacity: 30 mAh . The battery has to be UL listed.
Used batteries have to be disposed of according to the local regulations concerning the disposal of hazardous waste.
Figure 6. Position of lithium battery on F26L
CompactPCI connector J2 mSATA slot Side card connector
USB connectors
Ethernet connector ETH1 Ethernet connector
ETH2 1
VGA connector
Heat sink CompactPCI connector J1 Op onal ba ery (under the heat sink)
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