AMD-K6 Processor Data Sheet

Preliminary Information AMD-K6® Processor Data Sheet Preliminary Information © 1998 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. (“AMD”) reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of AMD products, except as provided in AMD’s Terms and Conditions of Sale for such products. Trademarks AMD, the AMD logo, and combinations thereof, K86, AMD-K5, and the AMD-K6 logo are trademarks, and RISC86 and AMD-K6 are registered trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks, and Windows NT is a trademark of Microsoft Corporation. Netware is a registered trademark of Novell, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. The TAP State Diagram is reprinted from IEEE Std 1149.1-1990 “IEEE Standard Test Access Port and Boundary-Scan Architecture,” Copyright © 1990 by the Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Information is reprinted with the permission of the IEEE. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Preliminary Information 20695H/0—March 1998 AMD-K6® Processor Data Sheet Contents Revision History . xvii About This Data Sheet . 1 Part One AMD-K6® Processor Family 3 1 AMD-K6® Processor . 5 2 Internal Architecture . 7 2.1 Introduction . 7 2.2 AMD-K6® Processor Microarchitecture Overview . 7 Enhanced RISC86® Microarchitecture . 8 2.3 Cache, Instruction Prefetch, and Predecode Bits . 11 Cache . 11 Prefetching. 12 Predecode Bits . 12 2.4 Instruction Fetch and Decode . 13 Instruction Fetch . 13 Instruction Decode . 14 2.5 Centralized Scheduler . 16 2.6 Execution Units . 17 2.7 Branch-Prediction Logic . 19 Branch History Table. 19 Branch Target Cache . 19 Return Address Stack . 20 Branch Execution Unit . 20 3 Software Environment . 21 3.1 Registers . 21 General-Purpose Registers . 21 Integer Data Types . 23 Segment Registers. 24 Segment Usage . 24 Instruction Pointer . 25 Floating-Point Registers . 25 Floating-Point Register Data Types. 28 MMX™ Registers. 29 EFLAGS Register . 31 Control Registers. 32 Debug Registers. 34 Model-Specific Registers (MSR) . 37 Contents iii Preliminary Information AMD-K6® Processor Data Sheet 20695H/0—March 1998 Memory Management Registers . 39 Task State Segment . 41 Paging . 42 Descriptors and Gates. 45 Exceptions and Interrupts . 48 3.2 Instructions Supported by the AMD-K6 Processor . 49 4 Logic Symbol Diagram . 77 5 Signal Descriptions . 79 5.1 A20M# (Address Bit 20 Mask) . 79 5.2 A[31:3] (Address Bus) . 80 5.3 ADS# (Address Strobe) . 81 5.4 ADSC# (Address Strobe Copy) . 81 5.5 AHOLD (Address Hold) . 82 5.6 AP (Address Parity) . 83 5.7 APCHK# (Address Parity Check) . 84 5.8 BE[7:0]# (Byte Enables) . 85 5.9 BF[2:0] (Bus Frequency) . 86 5.10 BOFF# (Backoff) . 87 5.11 BRDY# (Burst Ready) . 88 5.12 BRDYC# (Burst Ready Copy) . 89 5.13 BREQ (Bus Request) . 90 5.14 CACHE# (Cacheable Access) . 90 5.15 CLK (Clock) . 91 5.16 D/C# (Data/Code) . 91 5.17 D[63:0] (Data Bus) . 92 5.18 DP[7:0] (Data Parity) . 93 5.19 EADS# (External Address Strobe) . 94 5.20 EWBE# (External Write Buffer Empty) . 95 5.21 FERR# (Floating-Point Error) . 96 5.22 FLUSH# (Cache Flush) . 97 5.23 HIT# (Inquire Cycle Hit) . 98 5.24 HITM# (Inquire Cycle Hit To Modified Line) . 98 5.25 HLDA (Hold Acknowledge) . 99 5.26 HOLD (Bus Hold Request) . 99 5.27 IGNNE# (Ignore Numeric Exception) . 100 5.28 INIT (Initialization) . 101 5.29 INTR (Maskable Interrupt) . 102 5.30 INV (Invalidation Request) . 102 5.31 KEN# (Cache Enable) . 103 5.32 LOCK# (Bus Lock) . 104 5.33 M/IO# (Memory or I/O) . 105 5.34 NA# (Next Address) . 106 5.35 NMI (Non-Maskable Interrupt) . 106 5.36 PCD (Page Cache Disable) . 107 5.37 PCHK# (Parity Check) . 108 5.38 PWT (Page Writethrough) . 109 iv Contents Preliminary Information 20695H/0—March 1998 AMD-K6® Processor Data Sheet 5.39 RESET (Reset) . 110 5.40 RSVD (Reserved) . 110 5.41 SCYC (Split Cycle) . 111 5.42 SMI# (System Management Interrupt) . 111 5.43 SMIACT# (System Management Interrupt Active) . 112 5.44 STPCLK# (Stop Clock) . 113 5.45 TCK (Test Clock) . 113 5.46 TDI (Test Data Input) . 114 5.47 TDO (Test Data Output) . 114 5.48 TMS (Test Mode Select) . 114 5.49 TRST# (Test Reset) . 115 5.50 VCC2DET (VCC2 Detect) . 115 5.51 W/R# (Write/Read) . 115 5.52 WB/WT# (Writeback or Writethrough) . ..

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