The world’s first and leading dedicated semiconductor foundry is looking for
Process R&D IC Design Manufacturing
Module(Litho/Etch/CMP/Epi) Automatic Placement and Module(Litho/Etch/CMP/Epi) Routing Process Integration Specialty Technology Techfile/Process Design Kit (CIS/e- flash/HV) Nano-Patterning Technology Design Flow Development FinFET Device
Sign-up for private interviews by emailing your resume to tsmchr@tsmc.com , marking ” Albany/Fishkill Job Fair ” in the subject line. TSMC recruiter will contact you.
Any questions, please contact Dr. P.Y. Lin at 518-461-0282
Details will be announced on our website: http://www.tsmc.com/english/default.htm TSMC Job Openings
Function No. Position Location General Requirements
R01 Device Engineer Engineer Position. 1. Master or PhD in EE, Physics, Chemical R02 Integration Engineer Engineering, Chemistry, Materials or related field. R03 Module Engineer 2. Good communication skill, fluent in both English and Mandarin is preferred R04 SPICE Modeling Engineer 3. 2-3 years of related work experiences is R05 EUV Technology Development Engineer preferred.
R06 Multiple E-Beam engineer Manager position 1. Master or PhD in EE, Physics, Chemical R07 CMOS Image Sensor Engineer Engineering, Chemistry, Materials or R08 BEOL Metallization Integration Manager related field. 2. Minimum 6 years of related work R&D R09 Defect Manager Hsinchu (Taiwan) experience 3. Good communication skill, fluent in both R10 Design Rule Manager English and Mandarin is preferred R11 SRAM Development Manager
R12 Dual Epitaxy Loop Development Manager
R13 TCAD Process Calibration Manger
R14 Advanced Logic Device Manager
R15 MEB System Designer
R16 Nano Patterning Technology Manager
R17 Advanced Process Development Manager
Hsinchu (Taiwan), Engineer position D01 Layout Engineer San Jose, Austin (US) 1. Master or PhD degree in EE, CS or related field. D02 Automatic Place & Routing Technical Manager/Engineer Hsinchu (Taiwan), 2. Work experience in related fields is a San Jose (US) D03 Techfile/PDK Technical Manager/Engineer plus.
D04 SRAM Technical Manager/Designer San Jose, Austin (US) Manager position 1. Master or PhD degree in EE, CS or D05 Standard Cell Library Design Engineer IC Design related field. D06 Design Flow Development Technical Manager/Engineer 2. Minimum 8 years of related experiences.
D07 ESD Device Technical Manager Hsinchu (Taiwan) D08 Design Application & support Technical Manager
D09 Library/IP Quality Management Manager
D10 Memory Design Engineer
O01 Litho Technical Manager/Engineer Engineer position 1. Master or PhD degree in Material O02 Etch Technical Manager/Engineer science, Physics, Chemistry, EE and Hsinchu, Taichung, engineering related field. Tainan (Taiwan) O03 Epitaxy Technical Manager/Engineer 2. Fluent in English and Mandarin.
O04 CMP Technical Manager/Engineer Manufacturing Manager position O05 Specialty Technology Manager/Director(CIS/e-flash/HV) 1. Master or PhD degree in Material Hsinchu, Tainan science, Physics, Chemistry, EE and (Taiwan) O06 Advanced Hardware Development Manager/Director engineering related field. 2. Minimum 10 years of related O07 Design For Test Engineering Technical Manager experiences. Hsinchu (Taiwan) O08 FinFET Device Technical Manager 3. Fluent in English and Mandarin.