Design of Bias Tees for a Pulsed-Bias, Pulsed-Rf Test System Using Accurate Component Models

DESIGN OF BIAS TEES FOR A PULSED-BIAS, PULSED-RF TEST SYSTEM USING ACCURATE COMPONENT MODELS

In this article, a design of custom bias tees to be used in a pulsed-bias, pulsed-RF measurement system is described. The bias tee design is such that the DC path allows bias pulses to pass through to the device unchanged, while still allowing RF measurements at as low a frequency as possible. The use of accurate component models led to a successful simulation-based development of a bias tee with a (three-port) frequency response that allows accurate pulsed S-parameter and pulsed IV measurement results to be achieved in the desired bandwidth.

his article describes the design of a bias itor, as shown in Figure 1. The function of the tee for a pulsed-bias, pulsed-RF test bias tee is to simultaneously allow a DC bias T system. The cut-off frequency of the voltage and an RF test signal to be applied to DC path was raised to allow pulsing of the the port of a transistor during measurement. bias signal. The theory of bias tee design for For example, in an S-parameter measurement pulsed measurements is first presented. The system, the DC bias is applied at the port la- simulation results for the design without the beled “DC,” and the RF test signal from the use of component models are presented, fol- vector network analyzer is applied to the port lowed by simulation results obtained using ac- labeled “RF.” At the RF + DC port, both the curate parasitic models for the inductor and RF and DC voltages are applied to the device. capacitor used. The simulation results are then compared with S-parameter measurements obtained using a TRL calibration and CHARLES BAYLIS found to show good agreement. Finally, illus- University of South Florida trations of the accurate use of the bias tees in Tampa, FL ▼ Fig. 1 Bias tee circuit. performing both pulsed IV and pulsed S- LAWRENCE DUNLEAVY University of South Florida DC parameter measurements are provided. and Modelithics Inc. Tampa, FL BIAS TEE DESIGN WILLIAM CLAUSEN RF DC + RF A typical bias tee circuit con- Modelithics Inc. sists of an inductor and a capac- Tampa, FL

Port 2 test setup. In opera- enough that the entire frequency tion, however, the content of the pulse can pass through + value of the input re- the DC path without distortion; this Z=50Ω sistance will be fairly will allow the integrity of the pulse L1=27nH - large, changing the shape to be maintained. cut-off frequency. Initial values for the inductor and However, in a 50 capacitor were chosen and simulations Port 1 C1=100pF Ω Port 3 test system, 50 Ω is containing ideal elements were per- + + the impedance at all formed to ensure the selection of Z=50Ω Z=50Ω test ports. This setup component values that will provide ad- - - will be used for the equate cut-off frequencies for the DC purpose of bench- and RF paths. The simulations were ▲ Fig. 2 Circuit with ideal components and without microstrip lines marking the behav- performed using Agilent Technologies’ used in simulation. ior of the device Advanced Design System (ADS). The through measure- simulation circuit and results for ideal The purpose of the inductor is to pre- ment and simulation. Thus, R = 50 + 50 component values of C = 100 pF and vent the RF signal from entering the = 100 Ω for this case. L = 27 nH are shown in Figures 2 DC path, and the purpose of the ca- The cut-off frequency of the DC and 3, respectively. For these compo- pacitor is to keep the DC signal from path, assuming that the capacitor ap- nent values, the 3 dB cut-off frequen- entering the RF path. The inductor pears as an open circuit, is given by cy of the RF path is shown to be 151 and capacitor should be designed MHz and the cut-off frequency of the R such that the upper cut-off frequency DC path is shown to be 61 MHz. fcAC, = ()2 of the low pass DC path is lower than 2πL the lower cut-off frequency of the In this case, R is equal to the sum of SIMULATION RESULTS high pass RF path. If this is true, then the impedance presented by the bias Simulations were performed for the lower cut-off frequency of the RF equipment and the input impedance the selected component values L = 27 path containing the capacitor (consid- to the device under test. For a 50 Ω nH and C = 100 pF. The simulation ering the inductor to be an open cir- test system, R = 50 + 50 = 100 Ω. was performed at three different lev- cuit) is given by The outstanding factor for a els. At each level, both S-parameters pulsed bias tee design is that the cut- and transient simulations were run. 1 off frequency of the DC path must be The purpose of the S-parameters fcAC, = ()1 2πRC high enough to allow the pulsed bias simulation is to ensure that the RF where R is the total resistance seen at signal to proceed unabated from the path of the bias tee passes the signal the capacitor terminals. In this case, the DC to the RF + DC ports. In this while the DC path does not at RF termination at the RF port is 50 Ω and case, the smallest pulse length to be frequencies. The transient simulation the termination at the RF + DC port is used for pulsing the bias is approxi- is used to show that the pulse can ac- large (either the input or output im- mately 100 ns. The frequency content curately reach the RF + DC port pedance of the device) in normal oper- of this pulse is a (sin x)/x function without being significantly distorted ation but will be 50 Ω in the bias tee centered at a frequency of 1/(100 × in the time domain. Three levels of –9 10 ) = 10 MHz. Thus, the upper cut- simulation were incorporated into RF to RF + DC PATH off frequency of the bias network this effort: (1) ideal components and 0 should be greater than 10 MHz, large no transmission lines; (2) ideal com-

) 10 B

) 1 s PULSE

d − 0 B

( µ

 20 ( ) 6

1 V  3 − 10 (

1 5 S

3 

− N

30 S

I 4 

− , 20 3 , ) )

40 B − 2 V d ( (

− 0 100 200 300 400 500 30 1

T 

− U

1 0 O FREQUENCY (MHz) 2

S 1

40 V  − 0206810 − FREQUENCY (GHz) 012345678 910 DC to RF + DC PATH TIME (µs) 0 0 0.1 s PULSE

) 10 µ B

) 10 ) 6

d − B V ( −

(

d 5

 20 (

2 20 N

I 4 3 −  1 V S −

1  3 30 , S )

 30 2 − V − ( 1 40 T

40 U 0

0 100 200 300 400 500 O − − 0206810 1 FREQUENCY (GHz) V − FREQUENCY (MHz) 0 0.2 0.4 0.6 0.8 1.0 TIME ( s) ▲ Fig. 3 Simulated S-parameters for the ▲ Fig. 4 Simulated S-parameters for the µ ideal circuit. ideal circuit. ▲ Fig. 5 Simulated transient results. TECHNICAL FEATURE

Port 2

TL3 + MSub1 W=3.03mm L=5mm Z=50Ω - MSub H=1.58mm L=1 r=4.3 L=27nH Mur=1ε Cond=1.0E+50 Hu=3.9e+0.34mil T=0.035mm TL4 Tanδ=0.02 MSub1 Rough=0mil W=3.03mm L=5mm

Port 1 Port 3 + + TL 1 C1=100pF TL2 Tee1 MSub1 MSub1 MSub1 Z=50 TL5 Z=50 Ω W=3.03mm W=3.03mm W1=3.03mm MSub1 Ω - L=5mm L=5mm W2= 3.03mm W=3.03mm - W3=3.03mm L=5mm

▲ Fig. 6 Simulated circuit with microstrip lines and ideal components. ponents with microstrip (FR-4 sub- ) 1 s PULSE

B 0 µ d 6 strate) transmission lines; and (3) ) (

 5 (

1 10 lumped component parasitic models 3 N

I 4 S −  V

developed by Modelithics, combined ,

20 , 3 ) ) B − V 2 with microstrip transmission line ( d

( T 30 1 U  models built-in to Agilent ADS. The 1

− O

2 0 V S  40 1 first level was used to assess the opti- − 02 46810 − 012345678910 mum inductance and capacitance val- FREQUENCY (GHz) TIME (µs) ues, as shown in the previous section; the second and third levels are used 0 0.1 s PULSE 6 µ to view non-idealities introduced by ) V ) 5

10 (

B the substrate (second level) and com- N d − I 4 ( V

ponent parasitics (third level).

 20 , 3 1 )

1 − V

S 2 For the first-level schematic, the (  30 T 1 − U simulation results are displayed in O 0 40 V Figures 4 and 5. They show that the − 1 02 46810 − 00.2 0.4 0.6 0.8 1.0 S-parameter results are as desired. FREQUENCY (GHz) TIME (µs) From approximately 500 MHz and ▲ Fig. 7 Simulated S-parameters for the ▲ Fig. 8 Simulated transients from DC to RF above, S31 is high (which means that circuit with microstrip lines. + DC ports for the circuit with microstrip lines. most of the input signal is getting to

Port 2

TL3 + MSub MSub1 W=3.03mm Z=50 H=1.58mm L=5mm Ω r=4.3 Step3 - Mε ur=1 MSub1 Cond=1.0E+50 W1=3.03mm Hu=3.9e=0.34mil W2=0.8mm T=0.035mm Tanδ=0.02 L=27nH Rough=0mil H=1.58mm r=4.3 T=0.03ε 5mm Tan =0.02 Sim_mode=0δ C=100pf Step 4 Tolerance=1 H=1.58mm MSub1 r=4.3 W1=0.8mm Mε ur=1 W2=3.03mm T=0.035mm TL4 Tan =0.02 MSub1 Sim_modδ e=0 W=3.03mm Tolerance=1 L=5mm

Port 1 Port 3 + + TL1 Step 1 Step 2 TL2 Tee1 TL5 Z=50 MSub1 MSub1 MSub1 MSub1 MSub1 MSub1 Ω W=3.03mm W1=3.03 W1=1.1mm W=3.03mm W1=3.03mm W=3.03mm Z=50Ω - L=5mm W2=1.1mm W2=3.03mm L=5mm W2=3.03mm L=5mm - W3=3.03mm

▲ Fig. 9 Simulated circuit with parasitic models for lumped components and microstrip lines. TECHNICAL FEATURE

the RF + DC output) and S21 is low surements, it appears that this bias put. This is likely due to the non-ideal (very little signal is going from the tee is designed correctly with regard resistance of the components that is in- RF port to the DC port). Also, S11 is to the DC path passband. cluded in the models but is not taken below approximately –20 dB for all The next step was the incorpora- into account in the ideal component frequencies greater than approxi- tion of microstrip lines into the simu- definitions used for the simulations mately 1.7 GHz. These results show lation. Ideal components, however, whose results were previously dis- that the choice of component values were still used for the inductor and played. The use of three levels of simu- seems reasonable for a large RF pass- capacitor, as shown in Figure 6. The lation has shown that both the trans- band. The transient simulation re- substrate parameters used in the mission line elements and the parasitic veals whether the bias tee will allow “MSUB” element are those for the effects of the components have a sub- accurate transmission of pulses from FR-4 substrate to be used in milling stantial impact on the S-parameters the DC port to the RF + DC port. the circuit. Figure 7 shows the S-pa- simulation results. With the addition of The results show that a 1 µ s square rameters simulation results for the the transmission line elements and pulse sent from the DC port appears microstrip circuit. While the circuit component models, it was seen that virtually undistorted at the RF + DC behavior is still close to ideal up to some non-ideal effects are expected to port, and a 0.1 µ s pulse also goes approximately 5 GHz, there is a steep occur above 4 GHz. through the system with only minimal drop in S31 at approximately 8 GHz. overshoot at the rising and falling In addition, the input match becomes LAYOUT AND FABRICATION edges of the pulse. Since 0.1 µ s is worse as the frequency increases, The bias tees were constructed by short enough for isodynamic mea- reaching a peak at the same location mounting the components on a 59-mil as the notch in S . However, these thick FR4 substrate. The circuit board

) 31

B 0

d simulations indicate that the bias tee was fabricated in the University of (

10 

1 − should be useful in applications up to South Florida (USF) Wireless and Mi- 3 20 S 

− 6 GHz. The transient simulations are crowave Instructional (WAMI) Labora-

, 30 )

B −40 shown in Figure 8. Excellent pulse tory. The layout for milling was gener- d (

−

 50 integrity is obtained at the RF DC ated using a schematic in Advanced

1 +

2 − S 60 port. Design System with the components  − 0246810 Finally, the simulations were per- replaced by bond pads and a small gap. FREQUENCY (GHz) formed using detailed models for the The bond pads were not part of the 0 components to be used in the circuit: a previous schematics used for simula- 5 TDK 27 nH size 0603 inductor and an tion because the effects of the bond ) − B 10 ATC 100 pF size 0603 capacitor. The pads were included in the models for d ( −15  models include the bond pads, so these the simulations. The schematic used to 1

1 −20 S  − were not included in the microstrip generate the layout is shown in Figure 25 components. However, it is necessary 12 and the layout generated by ADS −30 − 0246810 to include these bond pads in the for milling is shown in Figure 13. FREQUENCY (GHz) schematic for the layout generation. ▲ Fig. 10 Simulated S-parameters for the Figure 9 shows the schematic used S-PARAMETER MEASUREMENTS circuit with parasitic models for lumped for the simulation. Figure 10 displays OF BIAS TEES components and microstrip lines. the S-parameters simulation results. To test the accuracy of the models 1.0 s PULSE The plots show that the response con- in predicting the behavior of the bias 4 µ cerning the RF to DC port and RF to tees, S-parameter measurements were ) V

( RF DC port transmissions is ade- performed over a frequency range of 3 + N I

V quate at frequencies below 4 GHz. 40 MHz to 6 GHz using an Anritsu

2 , )

V However, at 4.5 GHz, more transmis- 37397C “Lightning” vector network

( 1

T sion is occurring from the RF port to analyzer. A through-reflect-line (TRL) U 0 O

V the DC port than from the RF port to calibration was used for the measure- 1 − 0 1234567 8910 the RF + DC port. In addition, the in- ment. The 59-mil FR4 standards used TIME (µs ) put match at this frequency is relatively for this calibration have coaxial-to-mi- poor, as evidenced in the S11 plot. crostrip adapters at each port. The 0.1 s PULSE These non-ideal effects are due to the length of the standards was measured 4 µ ) component parasitics, since the mi- in the USF laboratory. The through V (

3 N

I crostrip line elements added in the sec- standard was measured to be 10.00 V

2 , ond simulation stage did not cause such mm, while the delay standard was ) V

( 1 effects at these frequencies. They will measured as 18.64 mm. The open was T U

O 0 limit the frequency range for which the offset by half of the through standard V 1 bias tee will be able to be accurately line length. The calibration was per- − 0 0.2 0.4 0.6 0.8 1.0 TIME ( s ) used in S-parameter measurements. formed using the Multical Software µ Figure 11 shows the transient simula- created by the National Institute of ▲ Fig. 11 Simulated transients from DC to tion results for the bias tee. It appears Standards and Technology (NIST). A RF + DC ports for the circuit with microstrip lines and parasitic lumped components that the height of the pulse at the RF + reference impedance of 50 Ω and an models. DC port is slightly lower than at the in- effective relative permittivity of 3.3 TECHNICAL FEATURE

Port 2

TL3 + MSub1 W=3.03mm L=5mm Z=50Ω Step3 - MSub1 W1=3.03mm W2=0.8mm

TL8 MSub1 W=0.8mm L=0.63mm

Gap2 MSub1 MSub W=0.8mm S=0.63mm H=1.58mm r=4.3 TL9 Mur=1ε MSub1 Cond=1.0E+50 W=0.8mm Hu=3.9e+0.34mil L=0.63mm T=0.035mm Step 4 Tan =0.02 MSub1 Rougδh=0mil W1=0.8mm W2=Wmm TL4 MSub1 W=3.03mm L=5mm

Port 1 Port 3 + + TL1 Step 1 TL6 Gap1 TL7 Step 2 TL2 Tee1 TL5 Z=50 MSub1 MSub1 MSub1 MSub1 MSub1 MSub1 MSub1 MSub1 MSub1 ΩW=3.03mm W1=3.03 W=1.1mm W=1.1mm W=1.1mm W1=1.1mm W=3.03mm W1=3.03mm W=3.03mm Z=50Ω - L=5mm W2=1.1mm L=0.67mm S=0.63mm L=0.67mm W2=0.67mm L=5mm W2=3.03mm L=5mm - W3=3.03mm

▲ Fig. 12 ADS schematic for layout generation.

were used. The reference plane was results for S21 (the RF to DC transmis- set to be 5 mm from the center of the sion) are shown in Figure 15. The through, placing it at the beginning of magnitude of S21 should be low at all the microstrip line, just on the mi- frequencies. A very good agreement is crostrip side of the coaxial-to-mi- obtained between the measured and crostrip adapter at each port. Figure simulated data in both magnitude and 14 shows plots of S31, the RF to RF + phase. Measured and simulated results DC transmission, in dB magnitude and for S32 (DC to RF + DC transmission) phase. The largest difference between are shown in Figure 16. The magni- the results in both magnitude and tude of this transmission is expected to phase occurs between 5 and 6 GHz. be low except at low frequencies. The ▲ Fig. 13 Bias tee layout for FR4 milling. The measured versus simulated magnitude match is excellent between (without microstrip-to-coaxial adapters) MEASURED SIMULATED MEASURED MEASURED SIMULATED 0 SIMULATED 0 ) 0 B 10

5 ) d ) ( 10 B − − B 20 d  − d ( 1 20

(

3 −

 30 S 10 −  2

 30 1 3 −

− 2 40 − S  S 40  −50 15 −50 012345 − − −60 60 FREQUENCY (GHz) − 01 2345 − 012345 FREQUENCY (GHz) FREQUENCY (GHz) 200 200 200

) 100 °

) 100 ( ° ) 100 ( ° 1

( 3 0

 S 1 2

0 2 0 3 ∠ S S

100 ∠ ∠ 100 − 100 − 200 − 200 − 012345 200 012345 − 01 2345 FREQUENCY (GHz) − FREQUENCY (GHz) FREQUENCY (GHz) ▲ ▲ ▲ Fig. 14 Measured and simulated S31 Fig. 15 Measured and simulated S21 Fig. 16 Measured and simulated S32 (RF to RF + DC transmission). (RF to DC transmission). (DC to RF + DC transmission). TECHNICAL FEATURE

MEASURED SIMULATED

S11 S22 S33

x13

▲ Fig. 17 Measured and simulated S11, S22 and S33 (F = 40 MHz to 5.0 GHz).

MEASURED SIMULATED the performance of the design on the first pass. 0 200 5

) 100 − ) PULSED IV MEASUREMENT B 10 ° ( d

(

− 1 THROUGH BIAS TEES

1 0  15 S 1

1 − S

20 ∠ In addition to testing the RF perfor-  − 100 −25 − mance of the bias tee, it is also impor- 30 200 tant to ensure that the circuit allows a − 012345− 012345 FREQUENCY (GHz) FREQUENCY (GHz) pulsed bias to be correctly applied to a ▲ Fig. 18 Simulated and measured S11 parameters. device under test. A good test method for this is to attempt to perform pulsed measured and simulated results over quencies, especially S33. This may be IV measurements through the bias tees the entire measurement band for both due to the difficulty of obtaining a as attempted previously;1 if the bias S21 and S32. good reflection calibration using a 59- tees do not distort the IV curves, they Figure 17 shows the measured mil FR4 substrate with SMA-to-mi- are adequate for applying a pulsed bias and simulated input reflection coeffi- crostrip adapters at higher frequen- to an RF measurement system. In this cient results for all three ports. The cies. Figures 18, 19 and 20 display experiment, pulsed IV measurements simulation and measured reflection the reflection parameters as mag- with pulse lengths varying from 0.1 to parameters match well at lower fre- nitude and phase versus frequency. 1000 µ s were performed on a GaAs quencies; however, some differences In general, the S-parameter results MESFET, using an Accent Optical exist at higher frequencies. The simu- show good agreement from 40 MHz to Technologies Dynamic i(V) Analyzer lated parameters have larger magni- 5 GHz. This data seems to indicate that (DiVA) model D225. The measure- tude in each case at the higher fre- the models have accurately predicted ments were performed for three setups: (1) no bias tees; (2) a set of com- MEASURED MEASURED mercially available bias tees; and (3) a SIMULATED SIMULATED set of USF custom bias tees. In the bias 0 0 tee setups, the DiVA was connected to 2 the DC ports of the bias tees and the ) 10 ) B − B d 4 − RF ports of the bias tees were termi- d ( 20

− (

 6 

2 −

3 nated in 50 loads. The measurement 2 − 3 30 Ω

S 8 S   − Figure 21 10− 40 setup is shown in . For the − − commercially available bias tees, the 12 50 − 012345 − 01 2 34 5 measurements were performed for FREQUENCY (GHz) FREQUENCY (GHz) pulse lengths varying from 1000 to 5 µ s. When attempting to measure at 2 µ s, 200 200 the instrument reported that it could ) ) 100 ° 100 °

( not complete the measurement due to (

 2 3 2 0 3 0 the large amount of gate current. Mea- S

∠ 100 ∠ 100 surements were performed for the cus- − − tom USF bias tees from 1000 to 0.1 s. 200 200 µ − 01234 5 − 01 2 34 5 From simulation and initial transient FREQUENCY (GHz) FREQUENCY (GHz) measurement results, it was expected ▲ ▲ Fig. 19 Simulated and measured S22 Fig. 20 Simulated and measured S33 that the bias tee would function very parameters. parameters. well for pulse lengths as low as 0.1 µ s. TECHNICAL FEATURE

In addition, it is desired to perform out bias tees. At 1000 µ s, there is a pulsed IV measurements within the “jog” in the knee region characteristic DiVA D225 Data pulsed S-parameter system, so it is crit- of the curves without bias tees. For Bus ical that the IV characteristics be accu- measurements made with the commer- rately measurable through the bias cial bias tees, this jog is not measured; Personal Computer tees. Figure 22 shows pulsed IV however, the USF bias tees correctly CLY-5 Running curves taken with different pulse depict this shift in the curves. The GaAs FET in Windows with Coaxial DiVA Software lengths for the commercially available physical phenomenon behind this shift Fixture Surrounded bias tees and the custom USF designed may be due to trapping effects. The by Bias Tees bias tees. In each plot, the dashed sets commercial bias tees may lengthen the ▲ Fig. 21 Measurement set-up. of curves are the measurements with- resetting time between pulses, so this effect is likely not due to the pulse (a) Pulse Length = 1000 µs length, but the pulse separation, as 1000 1000 shown in Reference [3] for this device. If the pulse separation were length- 800 800 ened, this result would likely to im- prove. However, even in this situation, ) 600 ) 600 A A it is interesting to note that the custom m m ( (

D 400 D bias tees more closely represent the

i 400 i measurement environment where no 200 200 bias tees are used. The figure also shows that the 0 0 0 2 4 6 8 0 2 4 6 8 commercially available bias tees can- vDS (V) vDS (V) not allow accurate pulsed IV mea- (b) Pulse Length = 20 µs surement for pulse lengths below 1000 1000 about 20 µ s. Both bias tees allow accurate measurement of the 20 µ s 800 800 curves. At 10 µ s, the IV curves measured through the commercial bias ) 600 ) 600 A A tees are too greatly sloped (g is too

m ds m ( (

D 400 D large), while the custom bias tees al-

i 400 i low accurate measurement of the 200 200 curves. For a pulse length of 5 µ s, the commercial bias tees are very clearly 0 0 0 2 4 6 8 0 2 4 6 8 in error. The 0.1 µ s pulse length mea- vDS (V) vDS (V) surement through the custom bias (c) Pulse Length = 10 s µ tees is compared to a 0.1 µ s pulse 1000 1000 length measurement without bias tees in Figure 23. 800 800 In the custom bias tee measurements, the knee appears to occur at a ) 600 ) 600 A A slightly larger value of V than for m m DS ( (

D 400 D the measurements without bias tees.

i 400 i This is likely due to the fact that both 200 200 the inductor and the coaxial-to-mi-

0 0 crostrip adapters, the FR4 substrate 0 2 4 6 8 0 2 4 6 8 microstrip transmission lines, the sol- vDS (V) vDS (V) (d) Pulse Length = 5 s 1000 µ Vgs = 0v 1000 800 1000 -0.5v

800 800 ) 600 A -1.0v m (

s ) ) 600 d 400

600 I -1.5v A A m m ( (

-2.0v D 400 D 200 i 400 i -2.5v 200 200 0 0 1 2 3 4 5 6 7 8 9 0 0 Vds (V) 0 2 4 6 8 0 2 4 6 8 ▲ Fig. 23 Pulsed IV measurements with vDS (V) vDS (V) pulse length = 0.1 µ s and without bias tee ▲ Fig. 22 Pulsed IV curves measured with no bias tees, commercially available bias tees and (dashed lines) or with custom USF bias tees custom USF bias tees at different pulse lengths. (solid lines). TECHNICAL FEATURE

both situations; however, the bias sig- 2. C. Baylis, “Improved Current-voltage PULSED V gs nal is pulsed in one case and is held Methods for RF Transistor Characteriza- CONSTANT Vgs tion,” Master’s Thesis, University of South continuous in the other case. As docu- Florida, 2004. 10 mented by Parker, et al., the difference 3. C. Baylis, L. Dunleavy and A.D. Snider,

) 5 “The Normalized Difference Unit as a B in |S21| can be attributed to self-heating

d th ( in the device.5 This can be predicted Metric for Comparing IV Curves,” 64 Au-  0 1 tomatic RF Techniques Group Conference, 2

S from the IV curves of the device,  5 Orlando, FL, December 2004. − which are shown in Figure 25. The 4. C. Baylis, L. Dunleavy and J. Martens, 10 − 0 0.5 1.0 1.5 2.0 2.5 3.0 bias point A is the “pulse-from” bias, “Constructing and Benchmarking a FREQUENCY (GHz) while the bias point B is the “pulse-to” Pulsed-RF, Pulsed-bias S-parameter Sys- bias, the bias at which the measure- tem,” 66th Automatic RF Techniques Group Conference, Washington, DC, De- 200 ment is performed. For the gate-volt- cember 2005.

) 100 age, drain-voltage combination given 5. A. Parker, J. Scott, J. Rathmell and M. ° (

1 by the bias point B, the difference Sayed, “Determining Timing for Isother- 2 0 S between the current values is substan- mal Pulsed-bias S-parameter Measure- ∠ 100 ments,” 1996 IEEE MTT-S International − tial. Notice also that the spacing be- Microwave Symposium Digest, Vol. III, 200 tween the surrounding curves is vastly − 0 0.5 1.0 1.5 2.0 2.5 3.0 pp. 1707–1710. FREQUENCY (GHz) different, which indicates a significant ▲ difference in the small-signal value for Fig. 24 S21 parameters of a SW Si Charles Baylis received g at this bias point between the his BS degree in electrical LDMOSFET for pulsed Vgs (from 3.2 to 7 V) m pulsed- and continuous-bias cases. engineering and a minor and Vds = 10 V constant and continuous bias (Vgs 7 V, V 10 V). This manifests itself in a lower gain for in mathematics, summa = ds = cum laude, from the the continuous-bias case, because the University of South 1400 Ggs=8V value of gm is lower. This is exactly Florida in 2002 and his MS degree in electrical 1200 7V what is observed in the previous figure. V =8V engineering in 2004. He is 1000 gs 7V now pursuing his PhD ) B CONCLUSION degree in the Center for A 800 Wireless and Microwave m 6V ( 6V A custom bias tee design has been Information Systems at the D 600 i obtained with the assistance of accurate University of South Florida. He serves as an adjunct 400 passive component models to accom- instructor and a research assistant under the guidance 5V of Lawrence Dunleavy, where he is focusing on the 200 modate pulsed-bias, pulsed-RF S-para- A development and applications of pulsed measurement 0 4V meters measurements with pulse and electrothermal transistor characterization 0 2 4 6 8 10 12 14 16 18 20 22 24 26 lengths on the order of 1 s and lower. methods. vDS (V) µ ▲ The simulation results for the time and Fig. 25 Static and pulsed IV for the 5 W frequency domains are found to com- Lawrence P. Dunleavy Si LDMOSFET; quiescent bias: V 3.5 V, gs = pare remarkably well with the use of received his BSEE degree Vbs = 0 V; pulsed bias: start A; end B. from the Michigan the models. An incremental design pro- Technological Institute in der joints and the inductors them- cedure for this circuit has been demon- 1982 and his MSEE and PhD degrees from the selves add resistance to the drain side strated, followed by the results of mea- University of Michigan in of the device, causing a lower voltage suring pulsed IV characteristics 1984 and 1988, to be applied to the device than in through the bias tees. The pulsed IV respectively. He has worked in industry for E- the case where no bias tees are used. results for the custom bias tees are far Systems (1982–1983) and This DC resistive effect can be easily more accurate than those performed Hughes Aircraft Co. (1984–1990), and was a corrected using a Mathcad sheet if through commercially available bias Howard Hughes doctoral fellow (1984–1988). In the resistance is measured. In addi- tees, which are not normally designed 1990, he joined the electrical engineering department tion, the figure shows that the curves to allow pulses to pass through the bias at the University of South Florida, where he is now a professor and co-founder of the University’s Center measured through the bias tees are path. Finally, initial pulsed-bias, pulsed- for Wireless and Microwave Information Systems. In slightly higher than the curves mea- RF S-parameter measurement results 2001, he co-founded Modelithics Inc. to provide sured without bias tees. are shown and found to correlate with practical commercial modeling solutions and microwave measurement services for RF and expectations. The design of custom bias microwave designers. PULSED S-PARAMETERS tees for pulsed applications using accu- MEASUREMENT RESULTS rate component models has provided William Clausen received The pulsed bias tee has been used first-pass success with the construction his BSEE and MSEE successfully in the design of a pulsed- of this pulsed measurement system. ■ degrees from the University of South RF, pulsed-bias S-parameter measure- Florida in 2003. He has ment system, as documented by a re- been a member of the cent conference paper.4 Figure 24 References technical staff at Modelithics Inc. since shows the S21 measurement results for 1. C. Baylis and L. Dunleavy, “Understanding 2002. His current interests a 5 W Si laterally diffused MOSFET Pulsed IV Measurement Waveforms,” include microwave (LDMOSFET) under both pulsed- 2003 IEEE International Symposium on measurements, active and Electron Devices for Microwave and Opto- passive component and continuous-bias measurement electronic Applications Digest, Orlando, modeling, and amplifier conditions. The RF signal is pulsed in FL. design.