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Design of Bias Tees for a Pulsed-Bias, Pulsed-Rf Test System Using Accurate Component Models

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Design of Bias Tees for a Pulsed-Bias, Pulsed-Rf Test System Using Accurate Component Models DESIGN OF BIAS TEES FOR A PULSED-BIAS, PULSED-RF TEST SYSTEM USING ACCURATE COMPONENT MODELS In this article, a design of custom bias tees to be used in a pulsed-bias, pulsed-RF measurement system is described. The bias tee design is such that the DC path allows bias pulses to pass through to the device unchanged, while still allowing RF measurements at as low a frequency as possible. The use of accurate component models led to a successful simulation-based development of a bias tee with a (three-port) frequency response that allows accurate pulsed S-parameter and pulsed IV measurement results to be achieved in the desired bandwidth. his article describes the design of a bias itor, as shown in Figure 1. The function of the tee for a pulsed-bias, pulsed-RF test bias tee is to simultaneously allow a DC bias T system. The cut-off frequency of the voltage and an RF test signal to be applied to DC path was raised to allow pulsing of the the port of a transistor during measurement. bias signal. The theory of bias tee design for For example, in an S-parameter measurement pulsed measurements is first presented. The system, the DC bias is applied at the port la- simulation results for the design without the beled “DC,” and the RF test signal from the use of component models are presented, fol- vector network analyzer is applied to the port lowed by simulation results obtained using ac- labeled “RF.” At the RF + DC port, both the curate parasitic models for the inductor and RF and DC voltages are applied to the device. capacitor used. The simulation results are then compared with S-parameter measure- ments obtained using a TRL calibration and CHARLES BAYLIS found to show good agreement. Finally, illus- University of South Florida trations of the accurate use of the bias tees in Tampa, FL M Fig. 1 Bias tee circuit. performing both pulsed IV and pulsed S- LAWRENCE DUNLEAVY University of South Florida DC parameter measurements are provided. and Modelithics Inc. Tampa, FL BIAS TEE DESIGN WILLIAM CLAUSEN RF DC + RF A typical bias tee circuit con- Modelithics Inc. sists of an inductor and a capac- Tampa, FL Reprinted with permission of MICROWAVE JOURNAL® from the October 2006 issue. ©2006 Horizon House Publications, Inc. TECHNICAL FEATURE Port 2 test setup. In opera- enough that the entire frequency tion, however, the content of the pulse can pass through + value of the input re- the DC path without distortion; this Z=50Ω sistance will be fairly will allow the integrity of the pulse L1=27nH - large, changing the shape to be maintained. cut-off frequency. Initial values for the inductor and However, in a 50 capacitor were chosen and simulations Port 1 C1=100pF Ω Port 3 test system, 50 Ω is containing ideal elements were per- + + the impedance at all formed to ensure the selection of Z=50Ω Z=50Ω test ports. This setup component values that will provide ad- - - will be used for the equate cut-off frequencies for the DC purpose of bench- and RF paths. The simulations were L Fig. 2 Circuit with ideal components and without microstrip lines marking the behav- performed using Agilent Technologies’ used in simulation. ior of the device Advanced Design System (ADS). The through measure- simulation circuit and results for ideal The purpose of the inductor is to pre- ment and simulation. Thus, R = 50 + 50 component values of C = 100 pF and vent the RF signal from entering the = 100 Ω for this case. L = 27 nH are shown in Figures 2 DC path, and the purpose of the ca- The cut-off frequency of the DC and 3, respectively. For these compo- pacitor is to keep the DC signal from path, assuming that the capacitor ap- nent values, the 3 dB cut-off frequen- entering the RF path. The inductor pears as an open circuit, is given by cy of the RF path is shown to be 151 and capacitor should be designed MHz and the cut-off frequency of the R such that the upper cut-off frequency DC path is shown to be 61 MHz. fcAC, = ()2 of the low pass DC path is lower than 2πL the lower cut-off frequency of the In this case, R is equal to the sum of SIMULATION RESULTS high pass RF path. If this is true, then the impedance presented by the bias Simulations were performed for the lower cut-off frequency of the RF equipment and the input impedance the selected component values L = 27 path containing the capacitor (consid- to the device under test. For a 50 Ω nH and C = 100 pF. The simulation ering the inductor to be an open cir- test system, R = 50 + 50 = 100 Ω. was performed at three different lev- cuit) is given by The outstanding factor for a els. At each level, both S-parameters pulsed bias tee design is that the cut- and transient simulations were run. 1 off frequency of the DC path must be The purpose of the S-parameters fcAC, = ()1 2πRC high enough to allow the pulsed bias simulation is to ensure that the RF where R is the total resistance seen at signal to proceed unabated from the path of the bias tee passes the signal the capacitor terminals. In this case, the DC to the RF + DC ports. In this while the DC path does not at RF termination at the RF port is 50 Ω and case, the smallest pulse length to be frequencies. The transient simulation the termination at the RF + DC port is used for pulsing the bias is approxi- is used to show that the pulse can ac- large (either the input or output im- mately 100 ns. The frequency content curately reach the RF + DC port pedance of the device) in normal oper- of this pulse is a (sin x)/x function without being significantly distorted ation but will be 50 Ω in the bias tee centered at a frequency of 1/(100 × in the time domain. Three levels of –9 10 ) = 10 MHz. Thus, the upper cut- simulation were incorporated into RF to RF + DC PATH off frequency of the bias network this effort: (1) ideal components and 0 should be greater than 10 MHz, large no transmission lines; (2) ideal com- ) 10 B ) 1 s PULSE d − 0 B ( µ d 20 ( ) 6 1 V 3 − 10 ( 1 5 S 3 − N 30 S I 4 V − , 20 3 , ) ) 40 B − 2 V d ( ( − 0 100 200 300 400 500 30 1 T − U 1 0 O FREQUENCY (MHz) 2 S 1 40 V − 0206810 − FREQUENCY (GHz) 012345678 910 DC to RF + DC PATH TIME (µs) 0 0 0.1 s PULSE ) 10 µ B ) 10 ) 6 d − B V ( − ( d 5 20 ( 2 20 N I 4 3 − 1 V S − 1 3 30 , S ) 30 2 − V − ( 1 40 T 40 U 0 0 100 200 300 400 500 O − − 0206810 1 FREQUENCY (GHz) V − FREQUENCY (MHz) 0 0.2 0.4 0.6 0.8 1.0 TIME ( s) L Fig. 3 Simulated S-parameters for the L Fig. 4 Simulated S-parameters for the µ ideal circuit. ideal circuit. L Fig. 5 Simulated transient results. TECHNICAL FEATURE Port 2 TL3 + MSub1 W=3.03mm L=5mm Z=50Ω - MSub H=1.58mm L=1 r=4.3 L=27nH Mur=1ε Cond=1.0E+50 Hu=3.9e+0.34mil T=0.035mm TL4 Tanδ=0.02 MSub1 Rough=0mil W=3.03mm L=5mm Port 1 Port 3 + + TL 1 C1=100pF TL2 Tee1 MSub1 MSub1 MSub1 Z=50 TL5 Z=50 Ω W=3.03mm W=3.03mm W1=3.03mm MSub1 Ω - L=5mm L=5mm W2= 3.03mm W=3.03mm - W3=3.03mm L=5mm L Fig. 6 Simulated circuit with microstrip lines and ideal components. ponents with microstrip (FR-4 sub- ) 1 s PULSE B 0 µ d 6 strate) transmission lines; and (3) ) ( V 5 ( 1 10 lumped component parasitic models 3 N I 4 S − V developed by Modelithics, combined , 20 , 3 ) ) B − V 2 with microstrip transmission line ( d ( T 30 1 U models built-in to Agilent ADS. The 1 − O 2 0 V S 40 1 first level was used to assess the opti- − 02 46810 − 012345678910 mum inductance and capacitance val- FREQUENCY (GHz) TIME (µs) ues, as shown in the previous section; the second and third levels are used 0 0.1 s PULSE 6 µ to view non-idealities introduced by ) V ) 5 10 ( B the substrate (second level) and com- N d − I 4 ( V ponent parasitics (third level). 20 , 3 1 ) 1 − V S 2 For the first-level schematic, the ( 30 T 1 − U simulation results are displayed in O 0 40 V Figures 4 and 5. They show that the − 1 02 46810 − 00.2 0.4 0.6 0.8 1.0 S-parameter results are as desired. FREQUENCY (GHz) TIME (µs) From approximately 500 MHz and L Fig. 7 Simulated S-parameters for the L Fig. 8 Simulated transients from DC to RF above, S31 is high (which means that circuit with microstrip lines. + DC ports for the circuit with microstrip lines. most of the input signal is getting to Port 2 TL3 + MSub MSub1 W=3.03mm Z=50 H=1.58mm L=5mm Ω r=4.3 Step3 - Mε ur=1 MSub1 Cond=1.0E+50 W1=3.03mm Hu=3.9e=0.34mil W2=0.8mm T=0.035mm Tanδ=0.02 L=27nH Rough=0mil H=1.58mm r=4.3 T=0.03ε 5mm Tan =0.02 Sim_mode=0δ C=100pf Step 4 Tolerance=1 H=1.58mm MSub1 r=4.3 W1=0.8mm Mε ur=1 W2=3.03mm T=0.035mm TL4 Tan =0.02 MSub1 Sim_modδ e=0 W=3.03mm Tolerance=1 L=5mm Port 1 Port 3 + + TL1 Step 1 Step 2 TL2 Tee1 TL5 Z=50 MSub1 MSub1 MSub1 MSub1 MSub1 MSub1 Ω W=3.03mm W1=3.03 W1=1.1mm W=3.03mm W1=3.03mm W=3.03mm Z=50Ω - L=5mm W2=1.1mm W2=3.03mm L=5mm W2=3.03mm L=5mm - W3=3.03mm L Fig.
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