Optimized Threshold Implementations: Securing Cryptographic Accelerators for Low-Energy and Low-Latency Applications Dušan Božilov1,2, Miroslav Knežević1 and Ventzislav Nikov1 1 NXP Semiconductors, Leuven, Belgium 2 COSIC, KU Leuven and imec, Belgium
[email protected] Abstract. Threshold implementations have emerged as one of the most popular masking countermeasures for hardware implementations of cryptographic primitives. In the original version of TI, the number of input shares was dependent on both security order d and algebraic degree of a function t, namely td + 1. At CRYPTO 2015, a new method was presented yielding to a d-th order secure implementation using d + 1 input shares. In this work, we first provide a construction for d + 1 TI sharing which achieves the minimal number of output shares for any n-input Boolean function of degree t = n − 1. Furthermore, we present a heuristic for minimizing the number of output shares for higher order td + 1 TI. Finally, we demonstrate the applicability of our results on d + 1 and td + 1 TI versions, for first- and second-order secure, low-latency and low-energy implementations of the PRINCE block cipher. Keywords: Threshold Implementations · PRINCE · SCA · Masking 1 Introduction Historically, the field of lightweight cryptography has been focused on designing algorithms that leave as small footprint as possible when manufactured in silicon. Small area implicitly results in low power consumption, which is another, equally important, optimization target. Hitting these two targets comes at a price since the performance and energy consumption of lightweight cryptographic primitives are far from being competitive and, for most online applications, they are often not meeting the requirements.