The Development of High-Temperature Stable Amorphous Metal Alloy Gates for the Reduction of Threshold Voltage Variability in Short Channel Cmos Devices

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THE DEVELOPMENT OF HIGH-TEMPERATURE STABLE AMORPHOUS METAL ALLOY GATES FOR THE REDUCTION OF THRESHOLD VOLTAGE VARIABILITY IN SHORT CHANNEL CMOS DEVICES

A DISSERTATION SUBMITTED TO THE DEPARTMENT OF MATERIALS SCIENCE AND ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

Melody Ellen Grubbs December 2011

This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/mj693yp8026

ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Bruce Clemens, Primary Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Yoshio Nishi, Co-Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Paul McIntyre

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Michael Deal

Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives.

iii Abstract

Polycrystalline metal gates have replaced polycrystalline silicon gates in complementary metal oxide semiconductor (CMOS) devices for high speed performance applications. This is because the decreased capacitance caused by the gate electrode depletion layer in polycrystalline silicon gates was a pressing concern for device performance and continued scaling. Metal gates do not have this depletion issue; however, work function tuning is an issue. Consequently, a focus in the metal gate area is placed on work function engineering and the effect of processing conditions on the effective work function.

The first project in this thesis studies the effect oxygen on the work function of tungsten electrodes. As expected, it was found that the presence of the meta-stable A15 phase is correlated with oxygen concentration. Tungsten films with minimal oxygen content contain only the stable bcc phase. However, after a forming gas anneal was performed on MOS capacitors made from these films, it was found that the A15 phase converts completely to a strained bcc phase. Despite this uniform transformation, it was found that the work function of the tungsten gate electrodes varies from 4.5–4.9 eV depending on the partial pressure of oxygen that the tungsten films were grown in. It is hypothesized that the observed variation is due solely to the incorporation of oxygen from the growth environment into the W layer at the SiO2/W interface. This work shows that stochastic fluctuations in processing conditions could also cause wafer-to- wafer variability, even in long channel devices.

Another concern with metal gates is that due to their polycrystalline nature, device variability could become a problem as the gate dimensions are scaled down and become

iv comparable to the grain size since work function can vary significantly with varying grain orientation. The main project in this thesis is to develop amorphous metal gates that have the potential to reduce work function variability with respect to polycrystalline gates in nano-scale MOS devices. Since gate-first processing is advantageous, the amorphous alloys to be characterized need to have high temperature stability

(Tcrystallization > 1000˚C). Consequently, refractory transition metal-metalloid bulk metallic glasses of the form (TaxW1-x)80Si10B10 were chosen as the first gate electrode materials to be developed. These alloys have nMOS-compatible work functions and the amorphous phase is stable at 1000oC; however, secondary ion mass spectrometry showed that boron diffused into the channel region at temperatures above 800oC. The development of Ta40W40Si10C10 solved this problem. This material also has an nMOS- compatible work function and is stable at temperatures in excess of 1000˚C. When

Ta40W40Si10C10 is integrated in long channel transistor devices, the effective channel mobility also appears to be enhanced with respect to crystalline tantalum and

Ta47.5W47.5Si2.5C2.5 gates. Also, methods to produce pMOS compatible amorphous alloys and the ALD development of amorphous materials are recommended as future work.

Table of Contents

Abstract ...... iii

Chapter 1: Introduction ...... 1

1.1. History of Transistor Gates ...... 2 1.2. Ideal Gate Properties ...... 4 1.3. Gate Work Function and Transistor Operation...... 4 1.4. Gate Integration: Gate-First and Gate-Last Processes ...... 6 1.5. The Case for Amorphous Metal Gates...... 7 1.6. Summary ...... 13 1.7. Thesis Objectives and Organization ...... 13 References ...... 15

Chapter 2: Experimental Procedures ...... 16

2.1. Introduction to Sputter Deposition...... 16 2.2. X-ray Diffraction of Amorphous Materials ...... 17 2.3. XPS Analysis ...... 21 2.4. MOS Capacitor Process Flow ...... 21 2.5. MOS Capacitor Analysis ...... 23 2.6. Ring Gate Transistor Process Flow...... 25 2.7. MOS Transistor Analysis...... 28 References ...... 30

Chapter 3: The Effect of O2 on the Tungsten Work Function ...... 31

3.1. Introduction ...... 31 3.2. Experimental Procedure ...... 34 3.3. Results ...... 34 3.4. Discussion ...... 40 3.5. Conclusions ...... 41 References ...... 43

Chapter 4: Amorphous Metal Alloy Gates: Initial Synthesis and Characterization of Ta-W-Si-B on SiO2 and HfO2……………...…………………….44

4.1. Previous Work on Amorphous Metal Gates ...... 44

4.2. Initial Material Choice...... 46 4.3. Ta-W-Si-B Synthesis ...... 47

4.4. Ta-W-Si-B Alloy Characterization on SiO2 ...... 48 4.4.1. XRD and RTA Analysis ...... 48 4.4.2. Work Function Analysis ...... 49

4.5. Ta-W-Si-B Alloy Characterization on HfO2 ...... 51 4.5.1. XRD and RTA Analysis ...... 52 4.5.2. Work Function Analysis ...... 52 4.6 Composition vs. Thermal Stability ...... 54 4.7. SIMS Analysis of select Ta-W-Si-B alloys: Boron Penetration ...... 58 4.7.1. Sample Selection and Prep ...... 58 4.7.2. SIMS Analysis ...... 60 4.8 Conclusions ...... 61 References ...... 62

Chapter 5: Amorphous Metal Alloy Gates: Synthesis and Characterization of Ta-W-Si-C………..……………………………………..………………………….63

5.1. Growth and Structural Characterization of Ta-W-Si-C...... 63 5.2. Electrical Characterization of Ta-W-Si-C ...... 65 5.3. Long Channel Transistors with Ta-W-Si-C Gates ...... 67 5.4. Collaboration with AMAT and IMEC: Development of Ta-W-Si-C Alloy Single Targets ...... 72 References ...... 75

Chapter 6: Amorphous Metal Alloy Gates - Future work...... 76

6.1. Development of pMOS Compatible Amorphous Metals ...... 76 6.2. Atomic Layer Deposition (ALD) of Amorphous Alloys ...... 81 References ...... 84

Chapter 7: Conclusions ...... 85

Appendix 1 ...... 87

vii

Table of Figures

Fig. 1.1. The number of transistors per microprocessor as a function of time. From: www.intel.com/technology/mooreslaw/ ...... 1

Fig. 1.2. This figure shows the number of transistors/microprocessor as a function of time. From www.intel.com/technology/mooreslaw/ ...... 2

Fig. 1.3. An illustration of the depletion effect. M = the polysilicon gate, O = the oxide, and S = the substrate.2 ...... 3

Fig. 1.4. Gate leakage as a function of oxide thickness at various technology nodes.1 ...... 3

Fig. 1.5. Fermi and vacuum levels for a metal/semiconductor before and after 2 contact. Note that ΦM is the metal work function, ΦS is the semiconductor work function, Efm is the Fermi level of the metal, Efs is the Fermi level of the semiconductor, Ev is the valence band, Ec is the conduction band, and the dotted line is the vacuum level...... 4

Fig. 1.6. Schematic of p-type transistor operation2 ...... 5

Fig.1.7. Bulk metal work functions relative to the silicon bandgap.9 ...... 5

Fig. 1.8. Transistors fabricated by gate-first (left) and gate-last (right) methods.3 6

Fig. 1.9. The dependence of the tungsten work function on crystallographic orientation.10...... 9

Fig. 1.10. From [6]. The comparison between different sources of variability for NMOS(Left) and PMOS(Right), W=Lmin, LER=3nm. At the 22nm node, the WFV is predicted to become the predominant contribution to the threshold voltage variability...... 9

Fig. 1.11. Polycrystalline (left) vs. amorphous metal gates. The white outlined rectangles indicate gates the hexagons represent individual grains, and the different shades of grey represent different crystallographic orientations. This is a graphic representation of how amorphous gates could eliminate work function related threshold voltage variability...... 10

Fig. 1.12. From [8]. TEM images of nano-crystalline and large-grained Ru-Mo alloys...... 11

Fig. 1.13. From [8]. σVth comparisons between large-grained and nano-crystalline transistors...... 11

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Fig. 1.14. Potential fluctuation due to different grain orientations in the gate electrode...... 12

Fig. 1.15. An illustration of roughness caused by grain boundary grooves...... 12

Fig. 2.1. Direct current sputtering of a Ta target ...... 16

Fig. 2.2. Schematic of the Kobe sputtering chamber ...... 17

Fig. 2.3. A schematic of x-ray diffraction in an ordered material...... 18

Fig. 2.4. X-ray diffraction patterns of crystalline and amorphous films of equivalent thicknesses...... 18

Fig. 2.5. XRD spectra of films deposited at different magnetic fields (a) 0G and (b) 100G. From [3] The authors were partially studying the effect of magnetic field on crystallite growth...... 19

Fig. 2.6. XRD spectra of silicon films. The two traces above the bottom trace are completely amorphous. Note that that crystalline silicon stick pattern is shown at the bottom of the figure. Note the similarity of these spectra to those in Fig. 5.10. From [4] ...... 20

Fig. 2.7. Cross-section view of the MOS capacitor structures...... 22

Fig. 2.8. An example of capacitance vs. voltage data. VFB indicates the flat band voltage...... 23

Fig. 2.9. A plot of the EOT vs. VFB. The y-intercept is the difference between the metal and semiconductor work functions...... 24

Fig. 2.10. An H-terminated silicon wafer...... 25

Fig. 2.11. Dielectric layer (HfO2) on Si ...... 25

Fig. 2.12. Metal/HfO2/Si stack ...... 25

Fig. 2.13. Photoresist/Metal/HfO2/Si stack ...... 26

Fig. 2.14. Metal gate defined...... 26

Fig. 2.15. SPR 3612 + LOL 2000 Photoresist/Metal/HfO2/Si stack. Prep for lift- off...... 27 Fig. 2.16. Deposition of the source/drain contacts ...... 27

Fig. 2.17. Finished device. A,5 B, and C sections correspond to Fig. 2.18...... 28

Fig. 2.18. Plan view of a ring gate transistor. A = the source, B = the gate, and C = the drain...... 28

Fig. 2.19. An example plot of the drain current vs. the gate voltage...... 29

Fig. 3.1. The top crystal structure (a) is body-centered cubic (BCC) and the bottom one (b) is A15...... 32

Fig. 3.2. From [1]. Tungsten phase as a function of the oxygen partial pressure during film growth...... 32

Fig. 3.3. XRD comparison of sputtered and evaporated tungsten...... 33

Fig. 3.5. Out-of-plane XRD of as-deposited tungsten films. Peaks due to the A15 phase are denoted by β; peaks due to the BCC phase are denoted by α ...... 35

Fig. 3.6. PDF card data for the BCC and A15 W. Note that the BCC(110) and the A15(210) peak positions overlap...... 36

Fig. 3.7. In-plane XRD of as-deposited tungsten film. No oxygen was added to the growth atmosphere for this sample. Peaks due to the A15 phase are denoted by β; peaks due to the BCC phase are denoted by α...... 36

Fig. 3.8. XRD of the tungsten films after the 400oC, 30 minute FGA. Note that only the α phase remains and that the films that were grown in an oxygen ambient exhibit strain (manifested by a shift of the (110) peak)...... 37

Fig. 3.9. Flatband Voltage (VFB) vs. Effective Oxide Thickness (EOT) plots and EWF for W films grown in the listed partial pressure of oxygen. Note that there is a trend for increasing slope with increasing oxygen concentration. This indicates that the interface charge increases with increasing oxygen content...... 38

Fig. 3.11. (Left) X-ray Photoelectron Spectroscopy (XPS) depth profile showing how the tungsten bonding changed as a function of depth in a β film that underwent a FGA and consequently converted to the strained α phase. (Right) The same as above, but of an as-deposited α phase film...... 39

Fig. 3.12. The tungsten EWF after FGA as a function of the oxygen partial pressure during film growth...... 40

Fig. 4.1.Ta-Si-N microstructure as a function of the nitrogen flow rate. (From [3]) ...... 45

Fig. 4.2. Crystallization temperatures for various quaternary alloys.4 ...... 46

Fig. 4.3. Terraced SiO2. These substrates were created by gradually dipping a wafer with a thermal oxide layer into 2% hydrofluoric acid...... 48

Fig. 4.4. Left: High angle x-ray diffraction of the as deposited alloys. Right: High o angle x-ray diffraction of alloys after a 1000 C, 10 second anneal in N2...... 49

Fig. 4.5. The flatband voltage vs. effective oxide thickness after a 1000oC, 10s -13 2 anneal for Ta20W60Si10B10. The magnitude of Qf here is 6.8x10 C/m ...... 49

Fig. 4.6. Comparison plot of the CV curves before and after the 1000oC, 10s RTA. Normal electrical behavior is observed...... 50

Fig. 4.7. Wedding cake SiO2 with a thin layer (2nm) of HfO2 ...... 51

o Fig. 4.8. Ta-W-Si-B on HfO2 after a 10s, 1000 C rapid thermal anneal and 45 minute, 400°C FGA...... 52

Fig. 4.9. Effective work function before and after the 10s, 1000oC rapid thermal anneal...... 53

o Fig. 4.10. Bidirectional CV data of Ta-W-Si-B on HfO2 after a 1000 C, 10s RTA 18 3 in N2. Bulk doping is 2.5x10 /cm ...... 53

Fig. 4.11. XRD showing the remarkable structural stability of Ta-W-Si-B. This anneal sequence was carried out in vacuum...... 54

Fig. 4.12. XRD of varying Ta-W-Si-B compositions as-deposited and after 10 minute 800, 900, and 1000oC anneals in vaccum...... 57

Fig. 4.13. XRD patterns of two Ta-W-Si-B alloys after 10 minute anneals in vacuum at 1000 and 1100oC ...... 59

Fig. 4.14. Metal and oxide were stripped from anneal samples ...... 59

Fig. 4.15. SIMS analysis showing that boron does diffuse out of Ta50W30Si10B10 and into the channel region at temperatures above 900oC...... 60

Fig. 4.16. SIMS analysis comparing boron diffusion out of Ta50W30Si10B10 and o Ta28W57Si10B5 after a 10 minute, 1000 C anneal...... 61

Fig. 5.1. The structure of Ta40W40Si10C10 as a function of anneal temperature. For the “substrate” curve, a piece of the bare substrate was annealed at 1000oC for 15s and then scanned. From [1]...... 64

Fig. 5.2. X-ray reflectivity data for a 7nm film. Even at such thicknesses, these films are continuous. X’Pert Reflectivity was used to model the film. The simulated stack was Ta2O5/TaW/SiO2/Si...... 65

Fig. 5.3. Capacitance vs. Voltage data for Ta40W40Si10C10 before (a) and after (b) the 1000oC rapid thermal anneal in forming gas. These materials exhibit normal electrical behavior. Bulk doping (p-type) was 5.6x1014/cm3...... 66

Fig. 5.4. Effective work function (EWF) extraction from plots of the flatband voltage vs. effective oxide thickness (EOT). (a) after the forming gas anneal, error: ±0.2 eV; (b) after the rapid thermal anneal in forming gas, error: ±0.1 eV. 67

Fig. 5.5. XRD patterns showing the microstructures of the films before and after a 5 minute, 900oC activation anneal in vacuum...... 68

Fig. 5.6. Gate-first transistor process flow. See Section 2.6. for the detailed process flow ...... 69

Fig. 5.7. ID vs. VG for transistors made with the listed gate materials...... 70

Fig. 5.8. Effective electron mobility vs. effective electric field for transistors made with the listed gate materials. The channel length is 55 µm...... 70

Fig. 5.9. Films from the alloy targets after a 1000oC, 30s anneal in forming gas. 73

Fig. 5.10. Data from a Ta-W-Si-C film sputtered at AMAT from a Ta40W40Si10C10 alloy target. The breadth of the XRD feature centered at 40o 2θ indicates that the film is amorphous. Note that the grazing incidence geometry allowed a stronger signal to be obtained from the thin film layer. Also, note the similarity of these spectra to Fig. 2.6...... 73

Fig. 6.1. Various Ru + Ta35W35Si15C15 alloys plus a layered Ru/Ta35W35Si15C15 film...... 77

Fig. 6.2. Various Ru + Ta35W35Si15C15 alloys plus a layered Ru/Ta35W35Si15C15 film after a 30s, 1000oC anneal...... 77

xii

o Fig. 6.3. The 25% and 35% Ru/Ta35W35Si15C15 alloy films after a 30s, 1000 C anneal. The various crystalline phases have been indexed. Note that all of the %25 Ru alloy peaks are uniformly shifted to the left (larger lattice spacing). This may be due to the higher concentration of the Ta and W, as both of these elements have larger atomic radii than Ru...... 78

Fig. 6.4. Left, Case 1; Right, Case 2 ...... 79

Fig. 6.5. A schematic of the dipole layer induced the C is sandwiched between W layers...... 79

Fig. 6.6. From [1]. Tuning the work function with carbon...... 80

Fig. 6.7. Various Ru + Ta35W35Si15C15 alloys plus a layered Ru/Ta35W35Si15C15 film...... 80

Fig. 6.8. A Planar bulk FET. From freescale.com...... 81

Fig. 6.9. A Tri-Gate FET. [5] ...... 82

Fig. 6.10. Conformal deposition of WNxCy. From [7]...... 83

xiii

List of Tables

Table 1.1. Predicted and experimental σVth at the 45 and 22nm nodes. RDF indicates σVth due to random dopant fluctuation; LER indicates σVth due to line edge roughness, and WFV indicates σVth due to work function variability. The highlighted values are S.U. theory estimates based on the Intel and Leading Edge’s experimental values for σVth...... 8

Table 2.1. Grain size and crystalline fractions of the silicon films deposited as different magnetic field. From [3]...... 19

Table 2.2. Example data: EOT and VFB ...... 24

Table 3.1. Semi-quantitative ratio of the A15 (β)/BCC (α) tungsten. These numbers were obtained by calculating the ratio of the integrated area of the β(200) peak to the integrated area of the combined β(200), α(110) peak...... 35

Table 4.1. Crystal structure, resistivity as a function of composition (From [3]) . 45

Table 4.2. EWF, EOT as a function of the nitrogen flow rate (From [3]) ...... 45

Table 4.3. Ta-W-Si-B compositions ...... 48

Table 4.4. Summary of work function values before and after the 1000oC RTA for Ta-W-Si-B alloys on SiO2 ...... 50

Table 4.5. Resistivity and Qf values before and after the 1000oC RTA for Ta-W- -14 Si-B alloys on SiO2. Since the error for these values is on the order of 5x10 C/m2, it can be seen that there is not a significant difference in the interface trap density before or after the RTA or between the various alloys...... 51

Table 4.6. Ta-W-Si-B compositions ...... 51

Table 4.7. Work function of Ta-W-Si-B on HfO2 as a function of anneal...... 53

Table 4.8. Ta-W-Si-B alloys investigated in the high temperature anneal study.. 55

Table 4.9. Ta-W-Si-B alloys investigated in the high temperature anneal study: Ta/W variation...... 57

Table 4.10. Ta-W-Si-B alloys investigated in the high temperature anneal study: Si/B and Si+B variation...... 57

xiv

Table 5.1. FWHM of highest intensity XRD peaks and resistivity of 30 nm vacuum annealed Ta and Ta47.5W47.5Si2.5C2.5 films. Peaks were fitted in X’Pert Highscore Plus...... 69

Table 5.2. Extracted parameters from the long channel transistors...... 69

Table 5.3. Extracted parameters from the long channel transistors ...... 71

Chapter 1

Introduction

Complementary metal oxide semiconductor (CMOS) circuits use a combination of n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) to store and manipulate data in many types of electronic devices. The main function of transistors in these devices is to act as a switch – they need to conduct as much current as possible when on and shut down when turned off. Transistors can be found in microprocessors which are essentially the brains of electronic devices such as laptops and cell phones. In the 1970s, there were only a couple thousand transistors per microprocessor. Now, as can be seen in Fig. 1.1, there are as many as a couple billion transistors per microprocessor.

Fig. 1.1. The number of transistors per microprocessor as a function of time. From: www.intel.com/technology/mooreslaw/

This increased transistor density is due to transistor geometry scaling:

Fig. 1.2. This figure shows the number of transistors/microprocessor as a function of time. From www.intel.com/technology/mooreslaw/

Scaling has led to smaller electronics, decreased cost/transistor, increased electronic processing power and data storage capacity.

1.1. History of Transistor Gates

Until recently, doped poly-silicon on SiO2 was the standard for transistor gate materials and dielectrics. However, as the gate length scaled down and dielectric thickness approached 1nm, this system started to exhibit problems such as boron penetration. In this case, the boron would diffuse from the gate and into the channel region causing unwanted doping. Additionally, high-k materials could not be integrated with poly-silicon due to inferior leakage behavior, yield reduction, and threshold voltage instability.1 Another problem was that the high resistivity of poly-silicon caused the depletion effect. (Fig. 1.3) This occurs when a layer at the gate/dielectric interface is depleted of carriers. This layer adds to the effective oxide thickness and the capacitance, which is proportional to 1/thickness, decreases. Since the switching speed of a transistor is directly proportional to the capacitance (C), for maximum device performance, C should be maximized.

Fig. 1.3. An illustration of the depletion effect. M = the polysilicon gate, O = the oxide, and S = the substrate.2

In 2007, Intel introduced high-k dielectrics and metal gates into their 45nm node devices. In Fig. 1.4, it can be seen that the introduction of these materials has caused the gate leakage to be decreased by more than 10x and that oxide scaling can now continue after stagnating between the 90 and 65 nm nodes.

Fig. 1.4. Gate leakage as a function of oxide thickness at various technology nodes.1

1.2. Ideal Gate Properties

In order for transistor performance to be maximized, the gate electrode material must have the following material and electrical properties: • Thermal stability • High conductivity (to avoid depletion effect) • CMOS process compatibility • Interfacial stability with the dielectric • Appropriate work function (depends on device type)

1.3. Gate Work Function and Transistor Operation

As mentioned in the previous section, specific work functions are required for certain devices. The work function is generally defined as the minimum energy required to remove an electron from a material. In a metal, this is shown as the energy distance from the Fermi level to the vacuum level. (Fig. 1.5)

2 Fig. 1.5. Fermi and vacuum levels for a metal/semiconductor before and after contact. Note that ΦM is the metal work function, ΦS is the semiconductor work function, Efm is the Fermi level of the metal, Efs is the Fermi level of the semiconductor, Ev is the valence band, Ec is the conduction band, and the dotted line is the vacuum level.

In order to switch a transistor “on” a voltage greater than or equal to the threshold voltage (σVth) must be applied. In Fig. 1.6., a positive voltage is applied to the gate and this causes the semiconductor bands to bend so much that an n-type channel region is formed at the dielectric/semiconductor interface. Electrons can then flow from the source (S) to the drain (D).

Fig. 1.6. Schematic of p-type transistor operation2

For CMOS devices, transistors come in pairs. One transistor in the pair is n-type (work function close to the semiconductor band edge) and the other p-type (work function is close to the semiconductor valence band edge). Work functions for various metals with respect to the Si bandgap are shown in Fig. 1.7.

3.0 Y 3.1

Mg 4.0 3.66 Ec Ec Al Mn 4.1 4.1 Pb Ta Ag Ti Zn 4.2 4.254.25 4.33 4.33 W Fe Cr 4.5 4.5 4.5 Mo Cu 4.6

5.0 4.65 Work Function (eV) Function Work Work Function (eV) Function Work Ev Ev Co 5.0 Au Pd Ni 5.1 5.125.15

Pt 5.65 6.0 Fig.1.7. Bulk metal work functions relative to the silicon bandgap.9

Note that an advantage of working with an alloy is that as long as it has two elements with work functions near the Si band edges, it has the potential to be tuned by varying relative ratio of those two elements.

1.4. Gate Integration: Gate-First and Gate-Last Processes

There are currently two predominant ways to integrate gates into the transistor process flow – gate-first and gate-last. Gate-first means that the gate is deposited before the source-drain activation anneal and gate-last means that the gate is deposited afterward. Transistors fabricated by these methods are depicted in Fig. 1.8:

Fig. 1.8. Transistors fabricated by gate-first (left) and gate-last (right) methods.3

There are advantages and disadvantages to both methods:

Gate First:

• (Pro) Conventional Process

• (Pro) Self-aligned Source/Drain (S/D)

• (Con) High temperature required for S/D activation → gates need to be stable at 800-1000oC

• (Con) Dual dielectric capping layers are required in order to set the threshold voltage (VTh) since the metal gate VTh tends not to be stable after the S/D activation anneal.

Gate-Last: • (Con) More Complex Process. A sacrificial gate deposited. The removal of the dummy gate and the deposition of the metal fill in the narrow gate trench opening have presented challenges.

• (Pro) Gate required to be stable at 400oC

It should be noted that hybrid methods have also been developed. Recently, United Microelectronics Corporation successfully used a hybrid approach for high performance devices. C. Lai, et al. used gate-first for nMOS and gate-last for pMOS.4 Gate-last was chosen for the pMOS because it is especially difficult to maintain the high VTh required after the S/D activation anneal. Thus, the hybrid process gets around the gate-first VTh issues and is significantly less complex than the full gate-last process. A downside to this method is that the high-k is deposited before the S/D activation anneal, so the thermal stability of the high-k will likely need to be improved significantly for integration into the sub-32nm nodes to be possible. 1,4

1.5. The Case for Amorphous Metal Gates As mentioned in the previous sections, polycrystalline silicon gates were once widely used in CMOS devices since they are easily tuned by doping; however, as scaling continued, the decreased capacitance caused by the gate depletion layer became a pressing concern for device performance. Polycrystalline metal gates do not have this depletion issue, and consequently they have replaced poly-silicon. However, polycrystalline metal gates are not without problems of their own. Threshold voltage variability (σVth) has become a problem as CMOS devices continue to scale down. This is due, in part, to the polycrystalline nature of the current metal gates.5-8 The threshold voltage variability has components due to LER (line edge roughness), RDF (random dopant fluctuation), and WFV (work function variability). RDF refers to the variability caused by varying numbers of dopant atoms in the channel from transistor to transistor, WFV refers to variability due to crystal structure, and LER refers to variability due to fluctuations about the photolithographically defined edges in a device. These variabilities sum up according to Eqn. 1.1:

(Eqn. 1.1)

Decreasing the WFV is the focus of this research and from Table 1.1, it can be seen that the σVth attributed to WFV is significant:

σ RDF LER WFV Vth 5Intel Exp. 45nm 60mV 60%, 36mV 5mV* (3nm) 48 mV**

6 S.U. Theory 45nm 40mV 30mV 5mV (3nm) 22 mV Intel Predicted 22nm 75mV S.U. Theory 22nm 60mV 38mV 15mV 45mV 7L.E. Exp. 22nm 100mV 38 mV* 15 mV* 91 mV**

In order to understand how work function variability arises, consider the expression for the threshold voltage:

VTh = ΦMS – Qi/Cox + Δφs + Δφs (Eqn. 1.2) where ФMS is the work function difference between the metal and the semiconductor, Qi is the interface state density, Cox is the oxide capacitance, Δφs/ox is the voltage drop across the semiconductor/oxide. From Eqn. 1.2, it can be seen that the threshold voltage depends on the work function of the metal (ΦM). A variation in threshold voltage can result from grains in a polycrystalline metal gate that have different interfacial work functions. How much the work function can vary is well illustrated by work from C.J. Fall, et al.10 which shows that the tungsten work function ranges from 4.44-5.26 eV depending on the hkl plane that the electron is stripped from. (Fig. 1.9)

Fig. 1.9. The dependence of the tungsten work function on crystallographic orientation.10

In [10] the work functions modeled and measured are surface work functions. In transistors, what is measured is the interfacial/effective work function (EWF). These two types of work function can differ mainly because there can be dipoles, traps, etc., at or near the interface of the metal gate/dielectric layers. It should be noted that even work function differences as small as 0.2 eV have been theoretically shown to cause significant threshold voltage variation.6 Results from such simulations are shown in Fig. 1.10.

LER LER 60 60 RDF RDF WFV 50 WFV 50 All All 40 40

(mV)

(mV) ) ) 30 30

Vth

 

20  20 

10 10 20 25 30 35 40 45 20 25 30 35 40 45

Lmin (nm) Lmin (nm) Fig. 1.10. From [6]. The comparison between different sources of variability for NMOS(Left) and PMOS(Right), W=Lmin, LER=3nm. At the 22nm node, the WFV is predicted to become the predominant contribution to the threshold voltage variability.

For these simulations, TiN gated transistors were simulated at various technology nodes. Each transistor’s gate electrode had metal grains with specific work functions

(TiN(200) = 4.6eV and TiN(111) = 4.4eV) and thus their own inversion carrier density in the channel. The numerical solutions for the device behaviors are shown in the figure above.6

The physical reason for the increasing significance of σVth with decreasing technology node is that as the gate length becomes comparable to the grain size, each gate will have a different distribution of grain orientations and because there will be fewer grains in each gate, the work functions will not average out to the same value and the threshold voltage (VTh) will vary from transistor to transistor. (Fig. 1.11)

For example, take a random distribution of n grains in a gate. The average work function of the gate would simply be:

∑ (Eqn 1.3) and the standard deviation (variability) would be:

√ ∑ (Eqn. 1.4)

Thus it can be seen that for a large gate with small grains, the variability will be less than that of a small gate with similar grain sizes and distribution. These formulae are presented to give a general idea of how the variability arises; it should be noted that, as described in Eqn. 1.2., the threshold voltage depends on more than just an average of the work function. The simulations that result in Fig. 1.10 are quantitative because they are based on a more comprehensive physical representation of the threshold voltage variability.

In short, it is becoming increasingly important that new gate electrode materials be developed that minimize the device variability due to a crystalline microstructure. There has been some experimental work in this area. In their 2008 IEDM paper, Ohmori et al compared transistors made with nano-crystalline Ru30Mo70 gates to those made 8 with large-grained Ru50Mo50 gates. TEM images of the two materials are shown in Fig. 1.12:

Fig. 1.12. From [8]. TEM images of nano-crystalline and large-grained Ru-Mo alloys. The material with the smaller average grain size showed less variation, as expected. (Fig. 1.13)

Fig. 1.13. From [8]. σVth comparisons between large-grained and nano-crystalline transistors.

Switching from nano-crystalline to amorphous gates should further reduce the threshold voltage variability, especially in short channel devices.

Amorphous metal gates not only have the potential to decrease σVth, but they also have the potential to increase channel mobility. As seen below in Fig. 1.14, work function variability can be a source of potential fluctuation, which will cause additional Coulomb scattering of channel carriers similar to how the presence of grain boundaries in poly-Si gates causes fluctuations in the potential, as demonstrated by Brown et al.11

- e

Fig. 1.14. Potential fluctuation due to different grain orientations in the gate electrode.

Additionally, the roughness of polycrystalline gates may have similar effects as rough gate dielectrics.11, 12

Fig. 1.15. An illustration of roughness caused by grain boundary grooves.

It is hypothesized that both of these effects will cause scattering. Amorphous materials would not have the potential fluctuation caused by work function variability, and as long as they are smooth, integrating them into MOS devices could reduce mobility degradation.

1.6. Summary In this chapter, amorphous metal gate electrodes have been presented primarily as a means for eliminating the work function contribution to the threshold voltage variability. Their potential to increase channel mobility and have a tunable work function was also addressed.

1.7. Thesis Objectives and Organization The goal of this thesis project was to develop fully amorphous, high-temperature stable metal alloy gates in order to determine if amorphous alloys can improve CMOS device performance at the 22nm node and beyond. Chapter 2 discusses how capacitors and transistors are fabricated and analyzed. This chapter also briefly discusses x-ray diffraction (XRD) theory for amorphous materials as well as some of the problems encountered while trying to obtain quantitative compositional information with x-ray photoelectric spectroscopy (XPS). Chapter 3 details the effect that processing conditions (oxygen) can have on the effective work function of tungsten gates. Changes in processing conditions can give rise to wafer-to-wafer variability even in long channel devices. A hypothesis is given for the trend of increasing work function with increasing oxygen growth pressures. Chapter 4 examines Ta-W-Si-B amorphous metal alloys. Synthesis, structural, thermal and electrical characterization of these alloys is discussed. Boron diffusion into the Si channel was a concern for this material. Based on secondary ion mass spectrometry (SIMS) surface profiling, its ability to be used as a gate-first material was determined. Chapter 5 investigates Ta-W-Si-C amorphous metal alloys. Synthesis, structural, thermal and electrical characterization of these alloys is discussed. Also, single alloy targets are developed for industrial collaborators. Long channel transistors are

13 fabricated to determine if the effective channel mobility is improved with amorphous gates versus polycrystalline ones. Chapter 6 discusses possibilities for future work including work function tunability and thermal stability of Ta-W-Si-C and related alloy and Ta-W-Si-C as a diffusion barrier. Finally, Chapter 7 summarizes the conclusions of this thesis.

References

1. T.Y. Hoffmann. Integrating high-k /metal gates: gate-first or gate-last http://www.electroiq.com/articles/sst/2010/03/integrating-high-k.html. 2010

2. G.M.T. Wong. An investigation of the work function of metal gate electrodes for advanced CMOS applications. Ph.D. dissertation, Dept. Mat. Sci. & Eng., Stanford Univ., Stanford, CA, 2008.

3. H.-C. Wen and J.J. Chambers. Gate contact materials in Si channel devices. MRS Bulletin. Vol. 36. 2011

4. C. Lai et al. A Novel Hybrid High-k/Metal Gate Process for 28nm High Performance CMOSFETs. IEDM Tech. Dig., pp. 655-658, 2009.

5. K. J. Kuhn. Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS. IEEE IEDM 2009

6. X. Zhang, J. Li, M. Grubbs, Michael Deal, Blanka Magyari-Kope, Bruce Clemens, Yoshio Nishi. Physical Model of the Impact of Metal Gate Work Function Variability on emerging Dual Metal Gate MOSFETs and its Implication for SRAM Reliability. IEEE IEDM 2009

7. K. Ishimaru. Solid-State Electronics. 45nm/32nm CMOS –challenge and perspective. Volume 52, pg. 1266-1273. 2008

8. K. Ohmori, T. Matsuki, D. Ishikawa, T. Morooka, T. Aminaka, Y. Sugita, T. Chikyow, K. Shiraishi, Y. Nara, K. Yamada. Impact of Additional Factors in Threshold Voltage Variability of Metal/High-k Gate Stacks and Its Reduction by Controlling Crystalline Structure and Grain Size in the Metal Gates. IEEE IEDM 2008

9. S. Hung, “Exploration of Novel Gate Electrode Material and Structure for MOS Applications”, Stanford Ph.D. Thesis, Chap. 6, 2005.

10. C. J. Fall, N. Binggeli, and A. Baldereschi. Theoretical maps of work-function anisotropies. Physical Review B. Volume 65, pg. 65-70. 2001

11. A.R. Brown, G. Roy, A. Asenov. Poly-Si gate related variability in decananometer MOSFETs with conventional architecture. IEEE Transactions. Volume 54, pg. 3056-3063. 2007

12. F. Gámiz, A. Godoy, F. Jiménez-Molinos, P. Cartujo-Cassinello, and J.B.Roldán. Remote surface roughness scattering in ultrathin-oxide MOSFETs. Proc. ESSDERC '03, pp 403-6

Chapter 2

Experimental Procedures

The purpose of this chapter is to outline the deposition/characterization techniques and photolithography processes required for metal oxide semiconductor (MOS) capacitors and transistors. These structures provide effective oxide thickness (EOT), effective work function data, threshold voltage, and other electrical characteristics crucial to this work. The theory and methods of data analysis for these structures will also be discussed.

2.1. Introduction to Sputter Deposition

All metals films in this thesis were deposited by direct current sputtering. A schematic of this technique is shown in Fig. 2.1:

Fig. 2.1. Direct current sputtering of a Ta target

For DC sputtering, a voltage is applied across the anode and the cathode; this creates an electric field. An ionized gas, or plasma, is produced by releasing argon gas into the electric field. Free electrons bombard and then ionize argon atoms. Ar+ ions are then accelerated towards the cathode where the targets are located. Ion bombardment on the targets ejects atoms, some of which are then deposited on the substrate. A schematic of the sputtering chamber used is depicted below in Fig. 2.2: 16

Fig. 2.2. Schematic of the Kobe sputtering chamber

Base pressures for this chamber range from 10-9 – 10-8 torr. The red, yellow, green, and blue circles represent the positions of the four 2” sputter guns.

2.2. X-ray Diffraction of Amorphous Materials X-ray diffraction (Fig. 2.3) was used to determine atomic structure. When the diffracted x-rays constructively interfere (λ = 2d sinθ) in a crystalline solid, the result is a tall, narrow peak in the diffracted intensity since d, the inter-planar spacing, is well- defined in crystalline structures as there is long range order.

Fig. 2.3. A schematic of x-ray diffraction in an ordered material.

Amorphous materials diffract x-rays as well; however, they have at most short range order. This local order arises from the fact that two atoms must be separated by at least the sum of their radii. Since the atoms in an amorphous material are randomly arranged on a larger scale (no long range order), the inter-atomic spacing (d) is not well-defined and the diffracted x-rays are scattered into a much wider, lower intensity peak. (Fig. 2.4) This peak is often called an “amorphous hump” and it reflects the distribution of inter-atomic distances.1

Fig. 2.4. X-ray diffraction patterns of crystalline and amorphous films of equivalent thicknesses.

It should also be noted that the width of x-ray diffraction peak can also be an indicator of the grain size. From the Scherrer equation, it can be seen that the wider the full width at half maximum (FWHM, Δ) of an XRD peak, the smaller the crystallite size (L):

⁄ (Eqn. 2.2)

In this equation, λ, is the x-ray wavelength.2 Note that the Scherrer equation outputs a lower bound on the crystallite size as peaking broadening can also be due to instrument broadening, anisotropic strain, etc. The presence of these effects would mean that the crystallites are actually larger than indicated by the Scherrer equation. For example, consider nano-crystalline and amorphous silicon. Wei, et al [3] show x-ray diffraction patterns of nano-crystalline silicon (Fig. 2.5):

. Fig. 2.5. XRD spectra of films deposited at different magnetic fields (a) 0G and (b) 100G. From [3] The authors were partially studying the effect of magnetic field on crystallite growth.

Table 2.1. Grain size and crystalline fractions of the silicon films deposited as different magnetic field. From [3].

Grain Size (nm) Magnetic Field (G) Crystalline Fraction (%) (111) (220) 0 22 1.7 3.5 100 72 8.0 5.5

Note that even though the grain sizes are as small as 1.7 and 3.5 nm, the peaks corresponding to the Si (111), 28.5o 2θ; Si (220), 47.5o 2θ; and Si(311), 56o 2θ are clearly visible. Compare these spectra to those from amorphous silicon.4 (Fig. 2.6.)

The main difference between the nano-crystalline and amorphous spectra is that the Bragg peaks are easily distinguished in the nano-crystalline case, but are absent in the amorphous case. Additionally, amorphous humps could be differentiated from nano-crystalline peaks in this work because the broad peaks retained their full width at half maximum 20

(FWHM) even after anneals such as 800oC for 6 hours or 1000oC for 10 minutes. Because of this, since the amorphous phase is not an equilibrium phase, it is extremely unlikely that the alloys grown were nano-crystalline. Furthermore, when the quaternary gate alloys crystallize, they do so in multiple phases and the peaks are not centered on the amorphous hump. (See Fig. 4.13 for reference.)

2.3. XPS Analysis X-ray photoelectron spectroscopy is a technique wherein x-rays are used to eject electrons from the surface/near surface of a given sample. The kinetic energy of the electrons that have been ejected is used to calculate the binding energy via Eqn. 2.3.

BE = hυ – KE – Φspec (Eqn. 2.3) where BE is the binding energy of the detected electron, hυ is the x-ray energy, KE is the electron kinetic energy, and Φspec is the work function of the spectrometer. The various orbitals of the different elements have well-defined binding energies and these are what are calculated from the electrons’ kinetic energies and used to determine the elements present and their relative ratios. XPS analysis was used in this work in an attempt to determine Ta-W-Si-B/C alloy compositions. However, the light elements in the compound, Si, B, and C, have very low relative sensitivities and thus XPS was not 5 able to provide quantitative compositional data for these alloys.

2.4. MOS Capacitor Process Flow As mentioned earlier, capacitors are used to extract the effective work functions (EWFs) from the various amorphous metal alloys. The capacitor process begins with prime Si(100) wafers: 1. The wafers go through a diffusion cleaning to strip away organic/inorganic impurities and the native oxide. The Si surface ends up being hydrogen terminated.

2. The wafers are annealed in oxygen (program Dry1000A in tylan 1 or 2) in order obtain device-quality oxide. Atomic layer deposited (ALD) HfO2 can also be deposited. A graduated dip in hydrofluoric acid will result in stepped HfO2 or SiO2. Oxide thickness is confirmed via ellipsometry.

3. The metal is deposited onto the Si/Oxide stack.

4. The MOS stack goes thru an HMDS prime (Yes oven) for good photoresist adhesion.

5. Photo-resist spin on 1 micron SPR 3612 (5.5k rpm, 30s) and baked at 90oC on a hot plate for 1 minute. Resist thickness should be confirmed. (Nanospec)

6. The resist is exposed for 1.4 s (Karl Suss 1 or 2) and the wafers are developed in MF-26A for 30 seconds and then rinsed under running water for 1 minute. The quality of the exposure is checked under an optical microscope and the samples are baked for 1 minute on a 115oC hot plate.

7. The metal is dry etched (drytek 1) and the quality of the etch is checked under an optical microscope.

8. The photoresist is removed by soaking the samples in 40oC PRX-127 for 5 minutes, rinsing under running water for 5 minutes, and thoroughly drying. (Note that PRX-127 + water can etch metal.)

9. Finally, the finished capacitors are annealed in forming gas (4% H2) for 30 min at 400oC.

A side view of the finished devices can be seen in Fig. 2.7:

Capacitors

Fig. 2.7. Cross-section view of the MOS capacitor structures.

The capacitors fabricated were 50, 75, 100, 150, and 200 μm in diameter. The 100 μm diameter capacitors were measured throughout this work unless otherwise stated.

2.5. MOS Capacitor Analysis For the electrical analysis, the capacitance vs. voltage data is obtained. Example data is shown in Fig. 2.8.

2.0

VFB

1.5

1.0

0.5

(pF) Capacitance

0.0 -1.5 -1.0 -0.5 0.0 0.5

Voltage (V) Fig. 2.8. An example of capacitance vs. voltage data. VFB indicates the flat band voltage. The device area and C-V data is then input into the NSCU simulation software developed by Hauser.6 This program fits the experimental data to a theoretical C-V curve that includes quantum effects. This program outputs the effective oxide thickness (EOT); this is calculated from the capacitance and the capacitor area. The flatband voltage (VFB), substrate doping, model data (to compare the fit to the experimental data), and the error percentage are also calculated. The fit errors in this work were usually between 0.5 and 3%. The work function is obtained from a plot of the flatband voltage vs. EOT:

(Eqn. 2.3)

where VFB is the flatband voltage, ФMS is the work function difference between the semiconductor substrate and the metal, Qi is the concentration of interface charge (the 7 sign of the charge dictates the sign of the slope), and Cox is the oxide capacitance. It should be noted that this equation does not account for charge in the bulk (in fact, it assumes that there is none) and it also assumes that the insulator layer has infinite resistance (meaning a constant Fermi level). If these assumptions don’t hold for the capacitors being measured, then there will be scatter in the data from these effects.

It can be seen that the y-axis intercept of a linear fit to Eqn. 2.3 gives the work function difference between the semiconductor substrate and the metal and that the

slope corresponds to the concentration of interface traps. (Table 2.2 and Fig. 2.9)

Table 2.2. Example data: EOT and VFB

EOT (nm) VFB (V) 3.73 -0.536 3.74 -0.600 4.18 -0.507 4.29 -0.510 4.37 -0.515 5.04 -0.555

5.09 -0.580 5.10 -0.585 5.20 -0.565

-0.475

-0.500

-0.525

-0.550

(V) FB V -0.575

-0.600

-0.625 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4

EOT (nm) Fig. 2.9. A plot of the EOT vs. VFB. The y-intercept is the difference between the metal and semiconductor work functions.

The semiconductor Fermi level (and hence work function) is easily calculated from the semiconductor doping with the following equation:

(Eqn. 2.4)

24 where ϕF is the Fermi level, k is Boltzmann’s constant, T is the temperature, q is the 3 electron charge, NA/D is the number of donor/acceptor atoms/cm , and ni is the intrinsic doping concentration.1 Once the semiconductor work function is obtained, the metal gate work function can be easily calculated.

2.6. Ring Gate Transistor Process Flow

This process begins with low resistivity (10-20 Ohm*cm) prime silicon wafers.

1. The wafers go through a diffusion cleaning to strip away organic/inorganic impurities and the native oxide. The Si surface ends up being hydrogen terminated. (Fig. 2.10)

Fig. 2.10. An H-terminated silicon wafer

2. 7-10 nm of ALD HfO2 is deposited. (Atomicity Systems)

Fig. 2.11. Dielectric layer (HfO2) on Si

3. The metal gate is deposited.

Capacitors

Fig. 2.12. Metal/HfO2/Si stack

4. First mask process (identical to steps 4-7 of the capacitor process): Spin on 1um of 3612 photoresist at 5.5k rpm for 30s, bake on a hot plate at 90oC for 1min, expose (karlsuss 1 or 2; mask = gate metal), develop, and check under an optical microscope. Etch away the metal (drytek 4,

Nitride etch – 100 parts SF6 + 10 parts O2)

H H H H H H

Fig. 2.13. Photoresist/Metal/HfO2/Si stack

5. Ion implantation to form the source/drain regions (n-type, 100keV, 5E15/cm2, done at Innovion Corp.)

6. Remove implantation hardened photoresist with the Matrix. Note that the photoresist takes a while to completely etch away. The samples were examined carefully under an optical microscope to ascertain that the resist was entirely removed.

Fig. 2.14. Metal gate defined

7. Spin rinse/dry or clean in 40oC PRS 1000 for 5 minutes and rinse for 5 minutes under running water.

8. Perform a rapid thermal anneal (RTA) at 900oC for 5 minutes in a forming or inert gas atmosphere.

9. Lift-off (for defining the source/drain contacts):

o Clean in 40oC PRS 1000 for 5 minutes and rinse for 5 minutes under running water

o Bake in the Singe Oven for 30 minutes at 150°C

o Deposit LOL2000 at 3000 rpm for 60 seconds (= 2000Å).

o Bake for 5 minutes on a 170°C hotplate

o Coat with 1um of 3612 photoresist.

o Bake for 60 seconds on a 110°C hotplate.

o Expose with standard exposure times for the photoresist used. (mask = ohmic)

o Align and expose (on the karlsuss 1 or 2)

o Develop for 40-50 seconds in MF-26A. Check the development under an optical microscope. A bit of over-development is recommended to facilitate the lift-off procedure.

Fig. 2.15. SPR 3612 + LOL 2000 Photoresist/Metal/HfO2/Si stack. Prep for lift-off.

o Bake 60 seconds on a 110°C hotplate

o Bake for 30min at 110°C

10. Remove the HfO2 with concentrated hydrofluoric acid (HF). The etch rate is approximately 5nm/minute. However the oxide must first be damaged with argon ion bombardment (MRC), otherwise the oxide is impermeable to even concentrated HF.

Fig. 2.16. Deposition of the source/drain contacts

11. Deposit the source/drain contact layer - Ti (100Å) under Al (900 Å). Perform the lift-off with an acetone bath and rinse the finished devices with isopropyl alcohol.

12. Remove LOL resist with 10 minute dip in PG remover.

13. Clean in 40oC PRS 1000 for 5 minutes and rinse for 5 minutes under running water.

14. Perform forming gas anneal at 400oC for 30 minutes

A cross-section of the finished device can be seen in Fig. 2.17:

C B A B C

Fig. 2.17. Finished device. A,5 B, and C sections correspond to Fig. 2.18.

A plan view of the finished device can be seen in Fig. 2.18:

A B C

Fig. 2.18. Plan view of a ring gate transistor. A = the source, B = the gate, and C = the drain.

2.7. MOS Transistor Analysis

EOT, drain current (ID), and gate voltage (VG) from the ring gate electrical measurements are used by Mob2D (a 2D mobility modeling program) in order to calculate the effective mobility as a function of effective electric field. Example data is shown in Fig. 2.19:

30.0µ 28 25.0µ

20.0µ

15.0µ

(Amps)

D 10.0µ I

5.0µ

0.0

0.0 0.5 1.0 1.5 2.0 VG (Volts)

Fig. 2.19. An example plot of the drain current vs. the gate voltage.

To extract the mobility values, Mob2D uses the relationship between the drain saturation current (IDS) and the mobility (μn) given by:

(Eqn 2.5)

where IDS is the drain saturation current, Cox is the oxide capacitance, W and L are the 8 transistor gate dimensions, VG is the gate voltage, and VT is the threshold voltage. Note that Eqn. 2.5 was derived under the following assumptions: 1) μn is constant, 2) channel inversion and bulk charges are controlled only by the vertical electric field, 3) the threshold voltage is not a function of position y along the channel, and 4) the transistor is operating in the saturation region. Also, the 2D mobility calculated by this equation does not take into account any carrier trapping at/near the channel-insulator interface which would immobilize induced carriers.

References

1. H. P. Klug and L. E. Alexander. X-ray Diffraction Procedures for Polycrystalline and Amorphous Materials. 2nd ed. New York, Wiley. 1974

2. B.D. Cullity & S.R. Stock. Elements of X-Ray Diffraction. 3rd Ed. Prentice-Hall Inc. 2001 p 167-171

3. L. C. Feldman and J. W. Mayer. Fundamentals of Surface and Thin Film Analysis. North Holland, New York. 1986

4. Y.U. Wei, et al. Growth of Nanocrystalline Silicon Films by Helicon Wave Plasma Chemical Vapor Deposition. Chinese Phy. Lett. 21, No. 7 (2004) pg. 1320

5. S. Guha, et al. Structural, defect, and device behavior of hydrogenated amorphous Si near and above the onset of microcrystallinity. App. Phys. Lett. Vol. 74, No. 13 (1999) pg. 1860

7. R. F. Pierret. Semiconductor Device Fundamentals. Addison-Wesley Publishing Company, Inc. 1996.

8. R. S. Muller and T. I. Kamins. Device Electronics for Integrated Circuits. 3rd ed. John Wiley & Sons, Inc. 2003

Chapter 3

The Effect of O2 on the Tungsten Work Function

The effect of oxygen on the work function of tungsten electrodes is discussed in this chapter. It was found that the presence of the meta-stable A15 (β) phase is correlated with oxygen concentration. Tungsten films with minimal oxygen content contain only the stable bcc (α) phase. However, after a forming gas anneal (FGA) was performed on MOS capacitors made from these films, it was found that the β phase converts completely to a strained α phase. Despite this uniform transformation, it was found that the work function of the tungsten gate electrodes varies from 4.5–4.9 eV depending on the partial pressure of oxygen that the tungsten films were grown in. It is hypothesized that the observed variation after the forming gas anneal is due solely to the incorporation of oxygen from the growth environment into the W layer at the SiO 2/W interface. This study highlights the effect of growth atmosphere on the effective work function (EWF).

3.1. Introduction

Tungsten is used extensively in CMOS processing, and because of this it is vital to understand how differences in processing can affect its characteristics. The effect of oxygen on the work function of metal gate structures is commonly reported, and it is often assumed to be related to oxygen at the metal/dielectric interface.1,2 However, in the case of tungsten metal gates, other factors may be important, such as the structure of the tungsten or strain effects, which could be affected by the presence of oxygen throughout the film. It has been demonstrated that increasing the concentration of oxygen in the deposition environment causes the tungsten to go from the bcc phase (α), to the A15 phase (β), and finally to the amorphous phase.1 (Fig. 3.1 and 3.2) The β phase which is consistent with higher oxygen content has been shown by [3-5] to be metastable. That is, it is converted irreversibly to the bcc phase upon annealing.

Fig. 3.1. The top crystal structure (a) is body-centered cubic (BCC) and the bottom one (b) is A15.

Fig. 3.2. From [1]. Tungsten phase as a function of the oxygen partial pressure during film growth.

In [3] it was observed that the β phase was present in an as-deposited evaporated tungsten film and that only the α phase was observed in an as-deposited sputtered film

(Fig. 3.3); it was hypothesized that this could be due to the cleaner environment for the sputter deposition in that study.

Si (200) 1200 BCC-W (110) 1000

800

Sputtered 600 Tungsten

400 A15-W A15-W Intensity (a.u.) Intensity (200) (210) A15-W (211) Evaporated 200 Tungsten

0 30 40 50 2 Theta (degrees)

Fig. 3.3. XRD comparison of sputtered and evaporated tungsten.

After the forming gas anneal (FGA), these same films had effective work functions (EWFs) of 4.60 eV and 4.84 eV respectively. (Fig. 3.4.)

-0.1

-0.2 FGA -0.3 Evaporated

V_fb (V) -0.4

-0.5

Sputtered -0.6 As-dep. -0.7 0.00 50.00 100.00 150.00 200.00 250.00

EOT (A) 33

Fig. 3.4. From [3]. The work function of evaporated vs. sputtered tungsten films. Before the FGA, the sputtered W work function is 4.44eV and the evaporated W work function is 4.81eV. After the FGA, the sputtered W work function is 4.64eV and the evaporated W work function is 4.88eV. This observation motivated this study to explicitly determine whether the work function difference in tungsten thin films could be attributed to the phase difference or only to the oxygen concentration. We also wished to determine to what extent the oxygen content or β phase fraction affected the work function and if the work function could be

tuned by adjusting the oxygen content or β phase fraction.

3.2. Experimental Procedure Fifty nm thick tungsten thin films were grown by reactive dc magnetron sputtering at room temperature in oxygen on terraced SiO2/Si(100) substrates at a rate of 0.55 Å/s. The oxygen partial pressures used were 6.0x10-7, 1.7x10-6, and 8.0x10-6 torr. The oxygen that was leaked into the sputtering chamber was 99.999% pure and its partial pressure was regulated with the ion gauge. After the partial pressures were set, 3 mtorr of Ar was introduced into the chamber for sputtering. One tungsten film was grown without any oxygen being leaked into the chamber, which had a background pressure of < 10-8 torr. The resultant films were made into MOS capacitors so that the

EWF could be obtained with plots of the flat band voltage (VFB) versus effective oxide thickness (EOT). High angle x-ray diffraction (XRD) was performed on the capacitors before and after the FGA in order to determine whether the α and/or β phases were present. The FGA was performed at 400°C for 30 minutes in 4%H2 in N2. Finally, x-ray photoelectron spectroscopy (XPS) depth profiling was done in order to determine the atomic percent of oxygen that was present in the bulk before and after the forming gas anneal. XPS was also used to determine how the tungsten was bonded in the bulk; that is, whether there were W—O bonds in the bulk or whether the added oxygen occupied interstitial sites.

3.3. Results As seen in Fig. 3.5, the as-deposited films contain varying amounts of the β and α phases. Table 3.1 gives the ratio of β/α found by comparing the integrated areas of the β(200) and the β(210)/α(110) peaks.

12    -6 8x10 torr O2 10

1.7x10-6 torr O 8 2

-7 6x10 torr O 6 2 

Log(Intensity(a.u.)) 4 Clean BCC W

35 40 45 50 55

2 Theta (Degrees) Fig. 3.5. Out-of-plane XRD of as-deposited tungsten films. Peaks due to the A15 phase are denoted by β; peaks due to the BCC phase are denoted by α

Sample β/α ratio No added O2 0 -7 6.0x10 torr O2 0.67 -6 1.7x10 torr O2 0.84 -6 8.0x10 torr O2 1.36

This reported β/α ratio is only semi- quantitative since the only visible peak in the bcc tungsten XRD pattern is the (110) and this peak directly overlaps with the β(210) peak which makes a quantitative ratio impossible to determine. (Fig. 3.6)

-- A15 W 100 -- BCC W

40 Intensity (a.u.) Intensity

40 60 80 2 Theta (degrees)

Fig. 3.6. PDF card data for the BCC and A15 W. Note that the BCC(110) and the A15(210) peak positions overlap.

In-plane x-ray diffraction patterns were obtained in order to see if the signal from more sample planes would allow the BCC(110) and A15(200) peaks to be resolved. For in- plane x-ray diffraction, the scattering vector lies in the plane of the film. This allows in- plane grain orientation to be characterized. Unfortunately, as seen in Fig. 3.7, the BCC(110) and A15(200) peaks were not resolved

1200

(110) BCC 900

(210), A15

600

(a.u.) Intensity A15 (200) A15

300 (211) A15

A15 (321) A15 (211) BCC (400) A15

(320) A15 BCC (200) BCC

30 40 50 60 70 80 2 Theta (Degrees) Fig. 3.7. In-plane XRD of as-deposited tungsten film. No oxygen was added to the growth atmosphere for this sample. Peaks due to the A15 phase are denoted by β; peaks due to the BCC phase are denoted by α.

Furthermore, when the powder pattern (Fig. 3.6) is compared to Fig 3.7, it seems possible that there is preferred orientation for at least the A15 phase. Note that this also prevents quantitative phase analysis. Additionally, as shown in Fig. 3.8, the A15 β phase is converted to the BCC α phase during the FGA. The (110) BCC peak is shifted relative to that for the film grown with no added oxygen, indicating a lattice contraction in the out-of-plane direction, possibly due to a tensile elastic strain in the film. This tensile strain may be due to the oxygen loss and the relatively low temperature FGA (400oC, 30 minutes). From the PDF patterns in Fig. 3.6, the cubic lattice parameter for the tungsten A15 phase is 5.05Å and the lattice parameter for the bcc phase is 3.16Å. Following the oxygen loss, the in- plane W lattice parameter would want to contract; however, the substrate and low thermal budget may prevent it from doing so. This tensile distortion could have an effect on the out-of-plane lattice parameter.

10  (110) -6 8x10 torr O2 8 -6 1.7x10 torr O2 6

6x10-7 torr O 4 2

Log(Intensity(a.u.))

Clean BCC W 2

35 40 45 50 55

2 Theta (Degrees) Fig. 3.8. XRD of the tungsten films after the 400oC, 30 minute FGA. Note that only the α phase remains and that the films that were grown in an oxygen ambient exhibit strain (manifested by a shift of the (110) peak).

The extracted work functions are summarized in Fig. 3.9. Note that the work functions after FGA increases from 4.54 eV to 4.91 eV as the partial pressure of O2 in the growth environment increases from background (<10-8 torr) to 8.0 x 10-6 torr.

-0.4 -0.4

-0.6 -0.6

V V -7 -0.8 No O -0.8 6.7x10 torr O 2 2 WF = 4.5 eV WF = 4.6 eV -1.0 -1.0 16 18 20 18 20 22

EOT (nm) EOT (nm)

0.0

-0.4 -0.2

-0.6 V V 1.7x10-6 torr O -0.4 8x10-6 torr O 2 2 -0.8 WF = 4.8 eV WF = 4.9 eV -0.6 12 14 16 8 10 12 14 16 EOT (nm) EOT (nm)

XPS depth profiles were performed for an as-deposited film grown without added oxygen, and for a film grown with an oxygen partial pressure of 8.0 x 10-6 torr, both as-deposited and after the FGA. These measurements were performed in order to determine the bulk oxygen content and tungsten bonding before and after the FGA. As shown in Fig. 3.10, the oxygen content drops dramatically as the surface region is sputtered away, and, for both the film deposited with no additional oxygen and for the FGA annealed, oxygen-deposited film, there is no detectable oxygen (< 1 atomic %) in the bulk of the films.

60 Growth Oxy gen Pressure -6 8 x 10 Torr 50 -6 8 x 10 Torr + FGA 40 No added oxgen 30

Oxygen Content (at 10%)

0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Sputter Time (min)

Fig. 3.10. Oxygen concentration (as determined by the O1s and W4f XPS intensities) as a function of sputter time for blanket W films grown with either no added oxygen or with an oxygen pressure of 8x10-6 torr. Results for before and after FGA are shown. The error in the XPS readings is generally on the order of a couple percent. Further information on the oxygen bonding in these films can be obtained from the position of W4f peaks.6 Fig. 3.11 shows representative XPS data for the both the film deposited with no additional oxygen and for the FGA annealed, oxygen-deposited film.

In both, the W4f5/2 and W4f7/2 peaks from the surface region of the film are clearly shifted to higher binding energies due to the effect of bonding with oxygen. However, in the bulk of both films, the peak positions are representative of metallic W—W bonding.

Film surface

Film surface 3/2 3/2 - - 30s of sputtering - - 30s of sputtering

300 _ W5p 60s of sputtering W5p 200

7/2

counts/sec)

counts/sec) 3 200 3

7/2

5/2

W4fMetallic -

5/2

W4fMetallic - 100

W4fMetallic - W4fMetallic -

100 7/2

5/2 7/2

5/2

W4fOxide -

W4fOxide - W4fOxide - W4fOxide -

0 0 XPS Intensity (10 Intensity XPS (10 Intensity XPS 44 40 36 32 28 44 40 36 32 28 Binding Energy (eV) Binding Energy (eV) Fig. 3.11. (Left) X-ray Photoelectron Spectroscopy (XPS) depth profile showing how the tungsten bonding changed as a function of depth in a β film that underwent a FGA and consequently converted to the strained α phase. (Right) The same as above, but of an as -deposited α phase film.

3.4. Discussion As shown in Fig. 3.12, the EWF of forming gas annealed W films is a strong function of the oxygen partial pressure in which they are grown, increasing from 4.54. eV to 4.91 eV as the growth oxygen pressure increases from the background (< 10-8 torr) to 8.0 x 10-6 torr. This dramatic effect is somewhat surprising in view of lack of structural and chemical differences between films grown with different oxygen pressures. As grown, the films deposited with oxygen added to the growth environment exhibit the metastable A15  phase, but after the FGA the films grown in oxygen exhibit the same BCC structure as the film grown with no added oxygen.

5.0

4.9

4.8

4.7

4.6 WorkFunction (eV) 4.5

0.0 2.0x10-6 4.0x10-6 6.0x10-6 8.0x10-6 O Partial Pressure (Torr) 2 Fig. 3.12. The tungsten EWF after FGA as a function of the oxygen partial pressure during film growth.

While there is some strain evident in the converted BCC films, it is the same for all oxygen-grown films, even though the EWF changes substantially. Furthermore, after FGA, the oxygen content in the bulk of the film is not detectable with XPS and the nature of the W bonding is the same, independent of the presence of oxygen during growth. This indicates that during growth, the oxygen is incorporated as an interstitial and diffuses readily during the anneal.1 Given that the first few metal layers near the metal-oxide interface are sufficient to control the work function7, and given the similarity in the bulk structure and chemistry among the W films deposited with various oxygen pressures, it is reasonable

40 to expect that a difference in the structure and/or chemistry of the interface region is responsible for the observed changes in EWF. Note that in bcc materials, the 110 planes are the closest packed and hence have the lowest energy. As a result, it is common for this plane to be parallel to the substrate surface.8 From Fig. 3.8 it can be seen that this is the case here, and thus it is expected that the unpinned work function of these films will be closer to 5 eV instead of the 4.55 eV value for bulk tungsten measured by contact potential difference.9,10 One hypothesis for the observed work function differences is that during growth with no added oxygen, clean W is deposited directly on the SiO 2 surface, resulting in a large gradient in oxygen chemical potential. This can result in oxygen being pulled out of the SiO2 into the growing W film, forming dangling bonds that can pin the EWF in the mid-gap region.11 When growing in the oxygen ambient, oxygen from the growth environment will be incorporated into the initial W layers, reducing the gradient in oxygen chemical potential at the SiO2/W interface. Since the reduction in chemical potential gradient will depend on the oxygen pressure, the density of dangling bonds formed by oxygen from the SiO2 reacting with W will depend on the oxygen content. In other words, the relative amount of oxygen at the interface would explain the work function variation across the films. Note that characterization methods such as SIMS would not prove the mechanism if indeed the oxygen in the dielectric and tungsten interface is acting only as a chemical potential/diffusion barrier. If there is any oxygen going from the tungsten to the SiO2, then that would be the result of simple mixing since there does not seem to be any driving force that would pull the oxygen out

of the tungsten and deeper into the dielectric layer.

3.5. Conclusions In this chapter, the effect of growth atmosphere on the tungsten work function is determined. It is shown that the work function of tungsten thin films can be varied by approximately 0.45 eV simply by introducing small amounts of oxygen during the growth process. It is also shown that the change in work function cannot be attributed to the change in structure, or the presence of strain after the FGA, or to any residual oxygen in the bulk. It is thought to be caused by the incorporation of oxygen from the growth environment into the W layer at the SiO2/W interface. It is hypothesized that this oxygen rich layer reduces the chemical gradient that would tend to pull the oxygen

41 out of the oxide. These factors could reasonably lead to a higher effective work function for the tungsten.

References

1. Y.G. Shen and Y.W. Mai. Influences of oxygen on the formation and stability of A15 β-W thin films. Mat. Sci, & Eng, A284, pp. 176-183, Jan. 2000.

2. Y.G. Shen and Y.W. Mai. Structure and properties of stacking faulted A15 tungsten thin films. Journal of Materials Science, Vol. 36, pp. 93-98, April 2000

3. G.M.T. Wong. An investigation of the work function of metal gate electrodes for advanced CMOS applications. Ph.D. dissertation, Dept. Mat. Sci. & Eng., Stanford Univ., Stanford, CA, 2008.

4. M. J. O’Keefe and J.T. Grant. Phase transformation of sputter deposited tungsten thin films with A15 structure. J. Appl. Phys. Vol. 79, No. 12, pp. 9134- 9141, March 1996.

5. I.A. Weerasekera, S.I. Shah, D.V. Baxter, and K.M. Unruh. Structure and stability of sputter deposited beta-tungsten thin films. Appl. Phys. Lett., Vol. 64, No. 24, pp. 3231-3233, March 1994

6. J.F. Moulder, W.F. Stickle, P.E. Sobol, and K.D. Bomben. Handbook of X-ray Photoelectron Spectroscopy. Chanhassen, MN: Physical Electronics, Inc, 1995.

7. Blanka Magyari-Kope, Seongjun Park, Luigi Colombo, Yoshio Nishi, and Kyeongjae Cho. First principles study of Al-Ni bilayers on SiO2: implications to effective work function modulation in gate stacks. J. Appl. Phys. 247333-0, November 2008.

8. C. V. Thompson. Grain growth in thin films. Annu. Rev. Mater. Sci. 1990. 20: 245-68

9. C. J. Fall, N. Binggeli, et al. Theoretical maps of work-function anisotropies. Phys. Rev. B, Vol. 65. pp. 045401. 2001

10. H.B.Michaelson. The work function of the elements and its periodicity. J. Appl. Phys. 48, 4729 (1977)

11. E. P. O'Reilly and J. Robertson. Theory of defects in vitreous silicon dioxide. Physical Review B Volume 27, No. 6. March 1983

Chapter 4

Amorphous Metal Alloy Gates: Initial Synthesis and Characterization of Ta-W-Si-B on SiO2 and HfO2

A rising concern with polycrystalline metal gates is that device variability becomes a problem as the gate dimensions become comparable to the grain size. A contributing factor to this problem is that work function varies with varying crystal orientation and when the gate dimensions become comparable to the average grain size, the average work function begins to vary from device to device. In this chapter, amorphous Ta-W-

Si-B alloys are introduced as a potential remedy for this problem.

4.1. Previous Work on Amorphous Metal Gates Previous materials studied were mainly transition metal silicon nitrides.1-3 Wen et al investigated Ta/Ti/Mo-Si-N on HfSiOx for work function tunability. From the x- ray diffraction data provided in the paper, none of these materials appear to be amorphous. The authors also noted that amorphous gate metals were attractive “since they exhibit less dependence of the effective work function on device processing conditions”.1 Harris et al doped TaN with Er, Yb, and Gd in order to tune TaN gates on HfSiON without using a dielectric capping layer. It was claimed that Er-doped TaN was amorphous after a 1070oC spike anneal; however, this conclusion could not be confirmed from the provided HRTEM.2 Suh et al most thoroughly investigated the materials properties of Ta-Si-N alloys on SiO2. Different compositions were grown via reactive sputtering with a TaSi2 target in a N2 atmosphere. In Table 4.1, the resistivity and crystal structure are summarized for each of the alloys. Note that the XRD patterns associated with these alloys do not display any amorphous humps as discussed in section 2.2.

Fig. 4.1.Ta-Si-N microstructure as a function of the nitrogen flow rate. (From [3])

Table 4.1. Crystal structure, resistivity as a function of composition (From [3])

Table 4.2. EWF, EOT as a function of the nitrogen flow rate (From [3])

From Fig. 4.1, it can be seen that the microstructure of the Ta-Si-N on SiO2 after the 900oC anneal is unknown. Additionally, from Table 4.1, these films are not conductive since tantalum silicides form readily and thus large amounts of N2 are required to suppress crystallization. The authors also hypothesize that all of the EWFs after the o 900 C anneal are the same (Table 4.2) because of the formation of a thin TaSi2 layer

(ФTaSi2 ~ 4.7 eV) at the interface. In short, Ta-Si-N alloys are not suitable gate materials. It should also be noted that none of these authors investigated amorphous metal gates in order to reduce threshold voltage variability in CMOS devices.

4.2. Initial Material Choice As devices scale down to the 22nm node, metal gate electrodes in conjunction with high-k dielectrics are required for high performance devices. Potential metal gate materials must a) exhibit band-edge work functions, b) exhibit stable Vth as a function of temperature, and c), for gate-first processing, they must maintain chemical stability with the underlying dielectric during the high thermal budget for dopant activation. As can be seen in Fig. 4.2, of all the refractory transition metal-metalloid alloys studied by Yoshitake et al, the Ta-W-Si-B ones are the only ones with crystallization temperatures, o 4 Tc, above 1000 C. In order to be used in gate first processing, these alloys must be able to undergo source-drain activation anneals without crystallizing, phase separating, or boron diffusion.

Fig. 4.2. Crystallization temperatures for various quaternary alloys.4

There are a couple of contributing factors to the high temperature stability of the Ta-W-Si-B amorphous alloys – the atomic size difference (presence of the metalloids) and the refractory nature of tantalum and tungsten.5-7 According to Polk, “the composition range where the amorphous structure can be obtained is in the vicinity of 80 atomic % metal”.6 This is because for metal-metalloid glasses, theory states that the glass matrix is a random hard packing of (mostly) metallic spheres.8 The smaller metalloid atoms then occupy the larger holes in the matrix and this is a main factor that leads to the stability of the amorphous structure of Ta-W-Si-B. (Note that the compositions range from (Ta0.8W0.2)80B10Si10 to (Ta0.2W0.8)80B10Si10.) Furthermore, compact structures like these (80% metal, 20% metalloid) have been shown in [9, 10] to be more viscous and have lower diffusivity; this also enhances glass forming ability. Finally, as the melting points of tungsten and tantalum are high - 3410oC and 2996oC, respectively – this means that these atoms require more energy to diffuse. This also stabilizes the amorphous phase.

4.3. Ta-W-Si-B Synthesis The alloy films were grown by 4-target, dc magnetron co-sputtering in the Kobe chamber. The targets used were Ta, W, Si, and W2B. Before alloy deposition, each target’s atomic flux at the substrate surface was calibrated and the Mathematica code in Appendix 1 was used to determine what rates each of the targets should be sputtered at in order to get a specific composition. The inputs to the Mathematica code are the molecular weights, atomic masses, densities, and tooling factors of all of the targets. The tooling factor is the ratio of the rate as measured by the chamber’s quartz crystal monitor and the actual rate as confirmed by the use of x-ray reflectivity.

4.4. Ta-W-Si-B Alloy Characterization on SiO2 The desired Ta-W-Si-B compositions are given in Table 4.3:

Table 4.3. Ta-W-Si-B compositions

Desired Composition W

W80Si10B10

Ta20W60Si10B10

Ta30W50Si10B10

Ta40W40Si10B10

Ta60W20Si10B10

These films were grown on stepped SiO2. (Fig. 4.3)

Fig. 4.3. Terraced SiO2. These substrates were created by gradually dipping a wafer with a thermal oxide layer into 2% hydrofluoric acid. 4.4.1. XRD and RTA Analysis High angle XRD was performed on the as-deposited films and they were then made into capacitors as discussed in section 2.3. The capacitors then underwent a 10 second, 1000oC rapid thermal anneal (RTA) and underwent XRD again to check for microstructural stability. As can be seen in Fig. 4.4.2, all alloys were amorphous as deposited and all Ta+W containing alloys remained amorphous after the high temperature anneal.

7500 5000 4500 W (110)

4000 6000 W (110) 3500 W

4500 W 3000 W (110) W Si B W Si B 80 10 10 2500 80 10 10 Ta W Si B

3000 20 60 10 10 2000 Ta W Si B Intensity(a.u.) Intensity(a.u.) 20 60 10 10 Ta W Si B 30 50 10 10 1500 Ta W Si B 30 50 10 10 1500 Ta W Si B 1000 40 40 10 10 Ta W Si B 40 40 10 10 500 Ta W Si B Ta W Si B 60 20 10 10 60 20 10 10 0 0 30 35 40 45 50 55 60 65 70 75 30 35 40 45 50 55 60 65 70 75 2 Theta (degrees) 2 Theta (degrees) Fig. 4.4. Left: High angle x-ray diffraction of the as deposited alloys. Right: High angle x-ray diffraction o of alloys after a 1000 C, 10 second anneal in N2. 4.4.2. Work Function Analysis

Effective work functions were extracted from plots of flatband voltage (VFB) vs. the effective oxide thickness (EOT). (Fig. 4.5) Capacitance vs. voltage plots taken before and after the forming gas anneal were also compared to ensure that these alloys exhibit normal electrical behavior.

o Fig. 4.5. The flatband voltage vs. effective oxide thickness after a 1000 C, 10s anneal for Ta20W60Si10B10. -13 2 The magnitude of Qf here is 6.8x10 C/m .

After FGA, EOT 13.1 nm After RTA, EOT 13.3 nm -7 2.5x10

)

2 2.0x10-7

F/cm -7 ( 1.5x10

1.0x10-7

-8 5.0x10

Capacitance Ta20W60Si10B10 0.0 -2.0 -1.5 -1.0 -0.5 0.0 0.5

Gate Voltage (V)

Fig. 4.6. Comparison plot of the CV curves before and after the 1000oC, 10s RTA. Normal electrical behavior is observed.

A summary of all of the work function values are given in Table 4.4. Note that these alloys have n-MOS compatible EWFs. Also, the shift in the flatband voltage may be due to the out-diffusion of hydrogen (during the 1000oC anneal) and the resulting dangling bonds.

Table 4.4. Summary of work function values before and after the 1000oC RTA for Ta-W-Si-B alloys on SiO2

Desired Composition FGA EWF (eV) RTA EWF (eV) Amorphous after RTA W 4.76 4.81 No

W80Si10B10 4.64 4.75 No

Ta 20W60Si10B10 4.30 4.32 Yes

Ta 30W50Si10B10 4.17 4.30 Yes

Ta40W40Si10B10 4.15 4.22 Yes

Ta 60W20Si10B10 4.29 3.95 Yes

o Table 4.5. Resistivity and Qf values before and after the 1000 C RTA for Ta-W-Si-B alloys on SiO2. Since the error for these values is on the order of 5x10-14 C/m2, it can be seen that there is not a significant difference in the interface trap density before or after the RTA or between the various alloys.

2 2 Desired Composition FGA Qf (C/m ) RTA Qf (C/m ) Resistivity after RTA (μΩ/cm) W 1.3x10-13 1.2x10-13 93 ± 5 -13 -13 W80Si10B10 2.9x10 5.9 x10 204 ± 7 -13 -13 Ta 20W60Si10B10 4.2x10 6.8x10 477 ± 8 -13 -13 Ta 30W50Si10B10 5.9x10 3.2x10 482 ± 9 -13 -13 Ta40W40Si10B10 3.1x10 4.9x10 496 ± 5

-13 -13 Ta 60W20Si10B10 3.1x10 2.5x10 354 ± 7

4.5. Ta-W-Si-B Alloy Characterization on HfO2 Substrate Preparation:

Two p-type wedding cake SiO2/Si wafers were obtained from SEMATECH. Two nm of ALD HfO2 were deposited on both wafers by Cambridge Nanotech. (Fig. 4.7)

Fig. 4.7. Wedding cake SiO2 with a thin layer (2nm) of HfO2

The following Ta-W-Si-B films were grown on the wedding cake structures:

Table 4.6. Ta-W-Si-B compositions

Desired Compositions

Ta30W50Si10B10

Ta50W30Si10B10

Ta60W20Si10B10

The films were then made into capacitors as described in section 2.4.

4.5.1. XRD and RTA Analysis The Ta-W-Si-B capacitors were analyzed by x-ray diffraction after a 10s, o 1000 C anneal in nitrogen to check for microstructural stability on HfO2.

7 Ta-W-Si-B Alloys After RTA

Ta W Si B

5 Si (200) 30 50 10 10

Ta W Si B 50 30 10 10 4 Ta W Si B 60 20 10 10

3 HfO2 (322) Log(Intensity(a.u.))

Bare Substrate 2 30 35 40 45 50 55 60 65

2 Theta (degrees)

o Fig. 4.8. Ta-W-Si-B on HfO2 after a 10s, 1000 C rapid thermal anneal and 45 minute, 400°C FGA. As can be seen in Fig. 4.5.2, the only crystalline peaks come from the substrate, so Ta-

W-Si-B is indeed structurally stable on HfO2.

4.5.2. Work Function Analysis The work function of these alloys was extracted as described in section 2.5. The results can be seen in Fig. 4.9 and Table 4.7.

-0.2 0.0 Before RTA: Ta W Si B After RTA: Ta W Si B 30 50 10 10 30 50 10 10 -0.3 -0.1

-0.4 -0.2

-0.5 -0.3

-0.6 -0.4

-0.7 -0.5 Flatband Voltage (V) Voltage Flatband

Flatband Voltage (V) Voltage Flatband W F = 4.10 eV W F = 3.98 eV -0.8 -0.6 4 5 6 7 8 6 7 8 9 Effective Oxide Thickness (nm) Effective Oxide Thickness (nm)

i Fig. 4.9. Effective work function before and after the 10s, 1000oC rapid thermal anneal.

Table 4.7. Work function of Ta-W-Si-B on HfO2 as a function of anneal.

Composition FGA WF (eV) RTA + 15 min FGA WF (eV)

Ta30W50Si10B10 4.10 3.98

Ta40W40Si10B10 4.16 4.19

Ta60W20Si10B10 4.26 4.27

Ta-W-Si-B alloys also exhibited normal electrical behavior on HfO2. (Fig. 4.10)

4.5x10-7 10 kHz

100 kHz )

2 1 MHz

4.0x10-7

F/cm ( 3.5x10-7

3.0x10-7

Capacitance Capacitance -7 2.5x10 EOT = 7.56 nm Fitting Error = 1.2% 2.0x10-7 -2 -1 0 1 2 Gate Voltage (V)

o Fig. 4.10. Bidirectional CV data of Ta-W-Si-B on HfO2 after a 1000 C, 10s RTA in N2. Bulk doping is 2.5x1018/cm3

4.6 Composition vs. Thermal Stability The purpose of the following study was to test the maximum thermal budget that these alloys can experience prior to crystallization. Ta-W-Si-B films were annealed at temperatures between 800 oC and 1000oC for at least 10 minutes in an attempt to get them to crystallize. From the data in Fig. 4.11, it can be seen that at least

Ta30W50Si10B10 is remarkably robust as this alloy did not crystallize even after 6 hours in vacuum at 800oC.

Fig. 4.11. XRD showing the remarkable structural stability of Ta-W-Si-B. This anneal sequence was carried out in vacuum. The shift of the amorphous hump to smaller 2θ values (from 38.50o – 38.10o 2θ) indicates that the average distance between atoms increases after high temperature anneals. This could be due to the creation of excess volume (associated with the high anneal temperature) that is stabilized by the quick cooling rate. The anneal study was then moved to a tool capable of attaining and sustaining temperatures well over 1000oC. The list of alloys examined in this study is shown below in Table 4.8:

Table 4.8. Ta-W-Si-B alloys investigated in the high temperature anneal study.

Anneal Study Alloys

Ta/W (Si+B)% Si/B

Ta20W60Si10B10 Ta32W63Si2.5B2.5 Ta28W57Si10B5

Ta30W50Si10B10 Ta30W60Si5B5 Ta28W57Si5B10

Ta40W40Si10B10 Ta25W50Si12.5B12.5

Ta50W30Si10B10

Ta60W20Si10B10

The Ta/W ratio, the total percentage of Si+B, and the Si/B content were varied in order to determine how these factors affect the crystallization temperature. Also, since boron diffusion was a concern, another goal of this study was to see if the boron concentration could be minimized while maintaining gate-first compatibility. The anneals were all done under vacuum conditions at SLAC facilities where the maximum furnace temperature was 1200oC. Each alloy was held at 800oC, 900oC, 1000oC, and 1100oC for 10 minutes in order to gauge the crystallization temperature. The results are summarized in the XRD patterns below and in Tables 4.9 and 10:

8000 8000 Ta W Si B Ta20W60Si10B10 30 50 10 10

6000 6000

)

1000oC a.u. ( o 4000 900 C 4000 800oC 1000oC o

2000 2000 900 C

Intensity (a.u.) Intensity Intensity Intensity o As deposited 800 C As deposited 0 0 35 40 45 50 55 60 35 40 45 50 55 60 2 Theta (degrees) 2 Theta (degrees)

8000 8000 Ta W Si B Ta40W40Si10B10 50 30 10 10

6000 6000

o 4000 1000 C 4000 1000oC 900oC 900oC 2000 o 2000

800 C (a.u.) Intensity Intensity (a.u.) Intensity 800oC As deposited As deposited 0 0 35 40 45 50 55 60 35 40 45 50 55 60 2 Theta (degrees) 2 Theta (degrees)

8000 15000 Ta W Si B Ta60W20Si10B10 32 63 2.5 2.5

6000 10000

o 4000 1000 C 900oC 5000 o

Intensity (a.u.) Intensity 2000

800 C (a.u.) Intensity o 800 C

As deposited As deposited 0 0 35 40 45 50 55 60 35 40 45 50 55 60 2 Theta (degrees) 2 Theta (degrees)

8000 8000 Ta30W60Si5B5 Ta25W50Si12.5B12.5

6000 6000

o 4000 4000 1000 C 1000oC

900oC 900oC

Intensity (a.u.) Intensity 2000 o 2000 800 C (a.u.) Intensity 800oC As deposited As deposited 0 0 35 40 45 50 55 60 35 40 45 50 55 60 2 Theta (degrees) 2 Theta (degrees)

8000 8000 Ta W Si B Ta28W57Si10B5 28 57 10 5

6000 6000

1000oC o 4000 4000 1000 C

o o

900 C 900 C Intensity (a.u.) Intensity 2000 (a.u.) Intensity 2000 800oC 800oC

As deposited As deposited 0 0 35 40 45 50 55 60 35 40 45 50 55 60 2 Theta (degrees) 2 Theta (degrees)

Fig. 4.12. XRD of varying Ta-W-Si-B compositions as-deposited and after 10 minute 800, 900, and 1000oC anneals in vacuum.

Table 4.9. Ta-W-Si-B alloys investigated in the high temperature anneal study: Ta/W variation.

Amorphous or As 800oC, 900oC, 1000oC, 1100oC, Crystalline? Dep. 10min 10min 10min 10min

Ta20W60Si10B10 A A A A + C C

Ta30W50Si10B10 A A A A + C C

Ta40W40Si10B10 A A A A + C C

Ta50W30Si10B10 A A A A C

Ta60W20Si10B10 A A A C C

Table 4.10. Ta-W-Si-B alloys investigated in the high temperature anneal study: Si/B and Si+B variation.

Amorphous or As 800oC, 900oC, 1000oC, 1100oC, Crystalline? Dep. 10min 10min 10min 10min Si/B

Ta28W57Si10B5 A A A A C

Ta28W57Si5B10 A A A + C C C (Si+B)%

Ta32W63Si2.5B2.5 A C C C C

Ta30W60Si5B5 A A A + C A + C C

Ta25W50Si12.5B12.5 A A A C C

From Table 4.9, it can be seen that the Ta/W ratio does not have a big effect on the alloy crystallization temperature. However, when the Si/B ratio is varied, the alloy with half as much Si crystallizes much earlier. We hypothesize that this is the case because

Si is more effective at preventing Ta and W atoms from phase separating due to either bonding or size effects. From the (Si+B)% variation, it can be seen that we are in the “sweet spot” using 10% each of Si and B. This is because one of the general design rules for metallic glasses is to pick elements with large differences in size, which leads to a complex structure that crystallizes less easily. Generally, for this design guideline, compositions with 80 atomic % of the metal(s) and 20 atomic % of the metalloid(s) 5-7 have been successful.

4.7. SIMS Analysis of select Ta-W-Si-B alloys: Boron Penetration Because boron is such a small species, it has the potential to be mobile in the amorphous alloy. Additionally, because the Ta-W-Si-B alloys also go through such high temperature anneals, B diffusion into the channel region was a strong concern as it would cause uncontrolled channel doping. In order to determine if this was occurring, front-side secondary ion mass spectrometry (SIMS) was performed on select Ta-W-Si- B alloys.

4.7.1. Sample Selection and Prep o The 800-1000 C Ta50W30Si10B10 samples were selected for SIMS analyses because o Ta50W30Si10B10 remained amorphous even after the 10 minute, 1000 C anneal. The 10 o minute, 1000 C Ta38W57Si10B5 sample was also selected because it, too, remained mostly amorphous. (Fig 4.13)

10000 Ta W Si B 50 30 10 10

8000

6000 o 1100 C

4000

Intensity (a.u.) Intensity 2000 1000oC

0 35 40 45 50 55 60

2 Theta (degrees)

20000 Ta W Si B 28 57 10 5

15000

10000

o 5000 1100 C

Intensity (a.u.) Intensity

o 1000 C 0 35 40 45 50 55 60 2 Theta (degrees) Fig. 4.13. XRD patterns of two Ta-W-Si-B alloys after 10 minute anneals in vacuum at 1000 and 1100oC

Additionally, if boron diffusion occurred, Ta38W57Si10B5 might be a better gate-first material candidate. The films had been grown on an n-type substrate and the SIMS samples were prepared by etching off the selected alloy films using an SF6+O2 plasma etch. The dielectric layer (15Å of SiO2) was then wet etched with 2% HF. (Fig. 4.14)

Fig. 4.14. Metal and oxide were stripped from anneal samples

4.7.2. SIMS Analysis SIMS measurements were done by the Evans Analytical Group (EAG) in Sunnyvale, CA. The primary ion beam was O2+ with oxygen flooding. The primary ion energy was 3.0keV and the raster size was 250x250 µm. Additionally, the secondary ions detected were 11B. From Fig. 4.15, it appears as if the plasma etching mentioned in the previous section drove some of the boron into the substrate because the concentrations of boron is high at the surface of the as-deposited sample and then rapidly drops off. Since the SIMS curves for the as-deposited and 800oC samples are similar, it can be concluded that no significant boron diffusion takes place at 800oC. However, from the curves for 900oC and 1000oC, it is very clear that significant boron diffusion took place during the anneal. (Fig. 4.15)

1019 % (As Dep.)

% (800oC) )

3 o 1018 % (900 C) % (1000oC)

1017

1016

1015 Ta W Si B

(atoms/cm Concentration B 50 30 10 10 1014 0 500 1000 1500 2000 Depth (Angstroms)

Fig. 4.15. SIMS analysis showing that boron does diffuse out of Ta 50W30Si10B10 and into the channel region at temperatures above 900oC.

Due to its lower boron concentration, Ta28W57Si10B5 showed a marked improvement, as seen in Fig. 4.16; however, this material is still not desirable for gate-first processing. The boron diffusion results in uncontrolled doping of the channel region and this would add to the RDF contribution to the threshold voltage variability.

19 Effect of Decreasing the B at.%

10 ) 3

18 10

17 10 Ta W Si B , 1000oC 50 30 10 10

16 10 Ta W Si B , 1000oC 28 57 10 5

1015

B Concentration (atoms/cm Concentration B Ta W Si B , As Dep. 50 30 10 10

0 500 1000 1500 2000

Depth (Angstroms) Fig. 4.16. SIMS analysis comparing boron diffusion out of Ta50W30Si10B10 and Ta28W57Si10B5 after a 10 minute, 1000oC anneal.

4.8 Conclusions

Ta-W-Si-B alloys were characterized on both SiO2 and HfO2 gate insulators. The alloys remained amorphous after a 10s, 1000oC anneal and exhibited normal electrical behavior and n-MOS compatible work functions on both dielectrics. In an extensive anneal study, all alloys remained mostly or completely amorphous for at least 10 minutes at 900°C except for Ta32W63Si2.5B2.5. From this study it was also found that for high temperature stability in Ta-W-Si-B alloys, Si is more important than B. The SIMS study showed that at 800°C and below, boron diffusion from the gate alloy into the substrate channel region is insignificant; however, for alloys that are 10-5 at.% B, significant boron diffusion occurred during the 900°C and 1000°C 10 minute anneals. The Ta28W57Si10B5 sample annealed for 10 minutes at 1000°C did show less B diffusion; however a significant amount of diffusion still occurred. Overall, these results indicate that Ta-W-Si-B alloys are compatible with, at most, gate-last processing.

References

1. H. C. Wen, H. N. Alshareef, H. Luan, K. Choi, P. Lysaght, H. R. Harris, C. Huffman, G. A. Brown, G. Bersuker, P. Zeitzoff, H. Huff, P. Majhi, B. H. Lee. Systematic Investigation of Amorphous Transition-Metal-Silicon-Nitride Electrodes for Metal Gate CMOS Applications. 2005 Symposium on VLSI Technology Digest of Technical Papers 46-47

2. H. R.Harris, H. Alshareef, H.C. Wen, S. Krishnan, K. Choi, H. Luan, D. Heh, C.S. Park, H.B. Park, M. Hussain, B.S. Ju, P.D. Kirsch, S.C. Song, P. Majhi, B.H. Lee, R. Jammy. Simplified manufacturable band edge metal gate solution for NMOS without a capping Layer. IEDM 2006, December, San Francisco

3. You-Seok Suh, Greg Heuss, and Veena Misra. Characteristics of TaSixNy thin films as gate electrodes for dual gate Si-complementary metal-oxide- semiconductor devices. Journal of Vacuum Science Technology B 22.1, ©2004 American Vacuum Society 175-179

4. T. Yoshitake, Y. Kubo and H. Igarashi. Preparation of Refractory Transition Metal-Metalloid Amorphous Alloys and their Thermal Stability. Materials Science and Engineering, 97 (1988) 269-271

5. T. Egmai and Y. Waseda. Atomic Size Effect on the Formability of Metallic Glasses. Journal of Non-Crystalline Solids. 64 (1984) pgs. 113-134

6. D. E. Polk. Structural Model for Amorphous Metallic Alloys. Scripta Metallurgica. Vol. 4, Issue 2 (1970) pgs. 117-122

7. O. N. Senkov and D. B. Miracle. Effect of the Atomic Size Distribution on Glass Forming Ability of Amorphous Alloys. Materials Science Research Bulletin Vol. 36 (2001) pgs. 2183 – 2198

8. J. D. Bernal. The Bakerian Lecture, 1962: The Structure of Liquids. Proceedings of the Royal Society of London. Series A, Mathematical and Physical Sciences. pgs. 299-322

9. A.R. Yavari, A. Inoue, in: W.L. Johnson, A. Inoue, C.T. Liu (Eds.), Bulk Metallic Glasses, MRS Symposium Proceedings, Vol. 554, Materials Research Society, Warrendale, PA, 1999, p. 21.

10. R. Busch. The Thermophysical Properties of Bulk Metallic Glass-Forming Liquids. Journal of the Minerals, Metals and Materials Society. Vol. 52, No. 7 (2000) pgs. 39-42

Chapter 5

Amorphous Metal Alloy Gates: Synthesis and Characterization of Ta- W-Si-C

In this chapter, a Ta-W-Si-C alloys were developed and characterized. As discussed in the previous chapter, it was found that (TaxW1-x)80Si10B10 alloys were structurally stable and remained amorphous above 1000oC; however, at anneal temperatures above 800oC, boron diffused out of the alloy and into the silicon substrate, making (TaxW1-x)80Si10B10 unsuitable for gate first processing integration and led to our development of Ta40W40Si10C10. Deposition of Ta-W-Si-C from a single target was also developed for industry collaboration and these materials were integrated into long channel transistors in order to see if amorphous gates improved the channel mobility with respect to crystalline ones. As mentioned in Chapter 1, work function variability can be a source of potential fluctuation, which would cause additional Coulomb scattering of channel carriers.

5.1. Growth and Structural Characterization of Ta-W-Si-C

Forty nm thick Ta40W40Si10C10 thin films were deposited by 3 target dc- magnetron co-sputtering on HfO2/SiO2/Si(100), with 2 nm HfO2 and varying thicknesses of SiO2. The targets used were Ta, W, and SiC. The microstructure of these films was determined using high angle x-ray diffraction (XRD), and x-ray reflectivity (XRR) was used to confirm film thickness and quantify smoothness.

In order to gauge the structural stability of the amorphous alloy on HfO2, thin films of Ta40W40Si10C10 underwent rapid thermal anneals (RTA) in a 10% H2 forming gas environment at 800, 900, 1000, and 1120oC. (Fig. 5.1)

6 Si(200)

5 HfO (322) 2

1120oC, 15s o 4 1000 C, 30s 900oC, 30s 800oC, 30s

3 Log(Intensity (a.u.)) Log(Intensity Substrate 2 35 40 45 50 55 o 2 Theta ( ) Fig. 5.1. The structure of Ta40W40Si10C10 as a function of anneal temperature. For the “substrate” curve, a piece of the bare substrate was annealed at 1000oC for 15s and then scanned. From [1].

From the high angle XRD, it was found that even at temperatures as high as o 1120 C, Ta40W40Si10C10 remains amorphous. It was found that amorphous o Ta40W40Si10C10 films are structurally stable at temperatures above 1100 C; this indicates that this alloy is compatible with gate first processing conditions. It should be noted that even if the carbon does diffuse through the dielectric and into the semiconductor substrate, this is not a problem like boron diffusion was with the (TaxW1-x)80Si10B10 amorphous alloys because C does not dope silicon. Carbon could still scatter charge; however, it should be noted that carbides have been used as gate-first materials without 2 incident. Additionally, all the components of Ta40W40Si10C10 are compatible with CMOS processing. From modeling the x-ray reflectivity data (Fig. 5.2), we found that

Ta40W40Si10C10 also forms a continuous layer at thicknesses less than 7 nm with an RMS surface roughness of approximately 0.3 nm.

2 Log(Intensity(a.u.))

0 2 4 6 8 10 12 o 2 Theta ( )

Fig. 5.2. X-ray reflectivity data for a 7nm film. Even at such thicknesses, these films are continuous . X’Pert Reflectivity was used to model the film. The simulated stack was Ta2O5/TaW/SiO2/Si.

5.2. Electrical Characterization of Ta-W-Si-C

Ta40W40Si10C10 thin films were made into 100 μm capacitors for EWF extraction. As seen in Fig. 5.3, Ta40W40Si10C10 exhibits normal electrical behavior on

HfO2.

4.5x10-7 10 kHz

4.0x10-7 100 kHz )

2 -7 1 MHz 3.5x10

-7

F/cm 3.0x10 ( 2.5x10-7 2.0x10-7 1.5x10-7

-7 Capacitance Capacitance 1.0x10 (a) 5.0x10-8 EOT = 7.7 nm 0.0 -3 -2 -1 0 1 2 Gate Voltage (V)

-7 4.0x10 10 kHz

100 kHz

) 2 -7 1 MHz

3.0x10

F/cm (

2.0x10-7

1.0x10-7

Capacitance Capacitance (b) 0.0 EOT = 8.1 nm

-2 -1 0 1 2 Gate Voltage (V)

o Fig. 5.3. Capacitance vs. Voltage data for Ta40W40Si10C10 before (a) and after (b) the 1000 C rapid thermal anneal in forming gas. These materials exhibit normal electrical behavior. Bulk doping (p-type) was 5.6x1014/cm3.

Note that for these samples, the RTA was carried out in forming gas and another 30 minute 400oC forming gas anneal was done after the RTA to passivate interface traps. This may account for both the shift and reduced stretch-out of the RTA CV with respect to the FGA CV.

From plots of the flatband voltage (Vfb) vs. effective oxide thickness (EOT), we found that this alloy has an NMOS compatible work function (i.e. near the conduction band) before and after the rapid thermal anneal. (Fig. 5.4)

-1.2 FGA EWF = 4.07 eV -1.0

-0.8

-0.6

-0.4

FlatBand Voltage (V) Voltage FlatBand (a) -0.2 5.5 6.0 6.5 7.0 7.5 8.0 8.5 EOT (nm)

-0.6 RTA EWF = 4.10 eV

-0.4

-0.2

FlatBand Voltage (V) Voltage FlatBand (b) 0.0 6.5 7.0 7.5 8.0 8.5 EOT (nm)

5.3. Long Channel Transistors with Ta-W-Si-C Gates

As mentioned in the introduction, mobility may be improved by using amorphous metal gates. This is because work function variability can be a source of potential fluctuation, similar to how the presence of grain boundaries in poly-Si gates causes fluctuations in the potential, as demonstrated by Brown et al.3 Additionally, the roughness of polycrystalline gates may have similar effects as rough gate dielectrics.3,4 It is hypothesized that both of these effects will cause scattering, and since Ta-W-Si-C films are amorphous (Fig. 5.1) and smooth (Fig. 5.2), integrating these alloys into MOS 67 devices could reduce mobility degradation. It should be noted that at this time, the work function contribution to the mobility has not yet been explored; however, it could affect both the low and high field mobility.

Amorphous Ta40W40Si10C10 films were again grown by three target dc- magnetron co-sputtering. The targets used were tungsten, tantalum, and silicon carbide.

Crystalline tantalum and Ta47.5W47.5Si 2.5C2.5 films were also grown for mobility comparison. Please note that these materials’ work functions were not previously optimized for either nMOS or pMOS devices. Also, all films were 30 nm thick and deposited onto 7 nm of ALD HfO2. The films’ microstructure was characterized by high-angle 2θ-ω x-ray diffraction (XRD). Fig. 5.5 shows that Ta40W40Si10C10 remains amorphous even after 5 minutes at 900oC.

18 Tantalum Ta(110) o After 5 min at 900 C As deposited 12 TaSi (201) Ta W Si C 0.4 47.5 47.5 2.5 2.5 TaWC (111) 2 o

After 5 min at 900 C Ta Si (110) 3.28 0.72 As deposited 6 Ta40W40Si10C10 o Log(Intensity(a.u.)) After 5 min at 900 C Si (200) As deposited 0 30 40 50 60 70 80 90

2 Theta (degrees) Fig. 5.5. XRD patterns showing the microstructures of the films before and after a 5 minute, 900oC activation anneal in vacuum.

Since the average grain size is inversely proportional to the full width at half maximum (FWHM) of the the XRD peak, it can be seen that the Ta has larger grains (on average) than Ta47.5W47.5Si 2.5C2.5. (Table 5.1) 68

Table 5.1. FWHM of highest intensity XRD peaks and resistivity of 30 nm vacuum annealed Ta and Ta47.5W47.5Si2.5C2.5 films. Peaks were fitted in X’Pert Highscore Plus.

FWHM [2θ(o)]: 900oC, 5min Anneal ρ (μΩ·cm) Tantalum 0.603 37.3

Ta47.5W47.5Si 2.5C2.5 0.644 127.1

Ta40W40Si10C10 4.52 138.5

The resistivity of the 30 nm films was measured using a four point probe; it was found that the resistivity of amorphous Ta40W40Si10C10 was nearly 4 times that of the pure Ta film. (Table 5.1) It should be noted that Ta40W40Si10C10’s resistivity is still much lower than the resistivity of highly doped poly-Si.

The Ta40W40Si10C10, Ta47.5W47.5Si 2.5C2.5, and Ta films were made into long channel ring-gate nMOSFETs using a gate-first process. (Fig. 5.6)

Fig. 5.6. Gate-first transistor process flow. See Section 2.6. for the detailed process flow

The threshold voltages, work functions, and effective oxide thicknesses (EOTs) are shown in Table 5.2 The IV characteristics are shown in Fig. 5.6.

Table 5.2. Extracted parameters from the long channel transistors.

Vth (V) EWF (eV) EOT (nm) Tantalum 0.61± .01 4.6 eV 2.60 ± 0.15

Ta47.5W47.5Si 2.5C2.5 0.85± .01 4.9 eV 2.98 ± 0.05

Ta40W40Si10C10 0.36± .01 4.4 eV 2.50 ± 0.17

10µ

1µ ) 100n

10n Amps

( 1n

D I 100p Ta W Si C (Amorphous) 40 40 10 10 10p Ta Ta W Si C (Crystalline) 47.5 47.5 2.5 2.5 1p 0.0 0.5 1.0 1.5 2.0 V (Volts) G Fig. 5.7. ID vs. VG for transistors made with the listed gate materials.

The subthreshold swing (SS) values from Fig. 5.7 are: Ta40W40Si10C10 SS = (70 ± 2) mV/dec, Ta SS = (70 ± 2) mV/dec, and Ta47.5W47.5Si2.5C2.5 = (100 ± 3) mv/dec. A low

SS value is required to maintain a high Ion/Ioff ratio; however, even in the ideal case of inﬁnite gate capacitance, the SS value for MOSFETs cannot be lower than 60 mV/dec at room temperature.5

Fig. 5.8 shows the relative effective electron mobility (μEff) of the transistors made with Ta40W40Si10C10, Ta47.5W47.5Si 2.5C2.5, and Ta.

600 Ta W Si C (Amorphous) 40 40 10 10 500 Ta Ta W Si C (Crystalline) 400 47.5 47.5 2.5 2.5

300

m/(v*s)

(

Eff 200



100

1.0 2.0 3.0 4.0 5.0 5 Electric Field (10 *V/m)

Fig. 5.8. Effective electron mobility vs. effective electric field for transistors made with the listed gate materials. The channel length is 55µm. 70

4 The mobility for the Ta gates are comparable to other results on HfO2. Differences in EOT have been shown to affect mobility with mobilities increasing as the EOT becomes thicker.6,7 As seen in Table 5.3, the amorphous gate has the lowest EOT, so the mobility enhancement is not due to thickening of the oxide layer. Note that this should be expected since amorphous materials have been widely used as corrosion-resistant layers as their lack of grain boundaries/channels inhibit chemical reactions.

Table 5.3. Extracted parameters from the long channel transistors

Vth (V) EWF (eV) EOT (nm) Tantalum 0.61± .01 4.6 eV 2.60 ± 0.15

Ta47.5W47.5Si 2.5C2.5 0.85± .01 4.9 eV 2.98 ± 0.05

Ta40W40Si10C10 0.36± .01 4.4 eV 2.50 ± 0.17

It should be noted that the amorphous gate has the lowest threshold voltage of the three materials used. This is interesting since tantalum has a bulk work function of 4.25 eV (Fig. 1.7) and should have a threshold voltage comparable to the amorphous gate. As the transistors underwent identical processing, this result suggests that the work function of the amorphous gate metal is less susceptible to Fermi-level pinning. Also, as expected, the transistors with amorphous gates appear to have the highest relative μEff. Once again, this overall enhancement is reasonable because this amorphous material lacks sites that generate potential fluctuations such as grain boundaries and grains with differing work functions. However, there was some capacitor hysteresis in this experiment, so it should be repeated for confirmation of this effect. It is also interesting to note that the mobility of the Ta gate relative to the Ta47.5W47.5Si 2.5C2.5 gate is much higher. As noted earlier, the annealed Ta gates have larger grains than the Ta47.5W47.5Si

2.5C2.5 ones. Thus, it is possible that the μEff of Ta47.5W47.5Si 2.5C2.5 is relatively low because it has the highest grain boundary density of the three gate materials characterized in this work. Furthermore, it is reasonable to conclude that although the use of nano-crystalline gates (4-5 nm average grain size) decreases the σVTh, their integration in MOS devices would lead to significantly degraded mobilities with respect to their larger-crystalline counterparts. Amorphous metal gates are ideal for possibly enhancing the mobility and have the potential to reduce σVTh at the same time. 71

5.4. Collaboration with AMAT and IMEC: Development of Ta-W-Si-C Alloy Single Targets

The main goal of this project is to compare amorphous gate transistors to conventional polycrystalline metal gate transistors in order to see if there is indeed a reduction in the threshold voltage variability. Since fabrication of short channel devices is not currently possible at Stanford, an industrial collaboration is necessary. The collaborating companies on this research are Applied Materials (AMAT) and IMEC. AMAT is a process equipment producer serving the semiconductor, LCD, and other industries, and IMEC is a research center that performs advanced nanoelectronics research in Leuven, Belgium. AMAT can deposit on 12” wafers, so it was decided that AMAT would deposit and IMEC would fabricate the transistors using a gate-first process. In order to integrate Ta-W-Si-C easily into AMAT processing, it must be possible to sputter this gate metal from a single target. Ta40W40Si10C10 and

Ta35W35Si15C15 custom targets were ordered from Plasmaterials, Inc. Different compositions were chosen in case there were differences in sputter yield between the four elements. However, it should be noted that alloy sputter targets are expected to equilibrate to the target stoichiometry. This is because in this case, the surface region becomes enriched in the lower sputtering yield material(s) so the sputtered flux eventually approaches the same composition as the target.8 The new alloy targets were sputtered at high power for 30 minutes in order to bring the sputter flux into equilibrium. Thirty nm thin films were then deposited from both of the targets. These were amorphous as deposited. The films then underwent a 30s, 1000oC rapid thermal anneal in forming gas. From Fig. 5.9, it can be seen that the films remained amorphous after this processing.

Fig. 5.9. Films from the alloy targets after a 1000oC, 30s anneal in forming gas.

Thus, it can be seen that the deposition of gate-first compatible Ta-W-Si-C alloys from a single target is possible. AMAT has since purchased their own alloy target, and the Fig. 5.10 shows some of the characterization that was performed.

As the collaboration stands at present, AMAT has deposited 12” wafers with varying thicknesses of the amorphous alloy for etch testing at IMEC. Once etch testing is complete, short channel device fabrication should be able to commence.

References

1. Melody Grubbs, et al. Development and Characterization of High Temperature Stable Ta-W-Si-C Amorphous Metal Gates. APL. Vol. 97, Issue 21. 2010

2. K. Tatsumura, et al. Clarification of Additional Mobility Components associated with TaC and TiN Metal Gates in scaled HfSiON MOSFETs down to sub-1.0nm EOT. IEDM pg. 349-352 2007

3. A.R. Brown, G. Roy, A. Asenov. Poly-Si gate related variability in decananometer MOSFETs with conventional architecture. IEEE Transactions. Vol. 54, pg. 3056-3063. 2007

4. F. Gámiz, A. Godoy, F. Jiménez-Molinos, P. Cartujo-Cassinello, and J.B.Roldán. Remote surface roughness scattering in ultrathin-oxide MOSFETs. Proc. ESSDERC '03, pp 403-6

5. W. Y. Choi, et al. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE EDL, Vol. 28, N0. 8 (2007) pg. 743-745

6. Wenjuan Zhu and Jin-Ping Han. Mobility Measurement and Degradation Mechanisms of MOSFETs Made With Ultrathin High-k Dielectrics. IEEE Trans, Vol. 51, No. 1, Jan. 2004

7. T Ando, MM Frank, K Choi, et al. Understanding mobility mechanisms in extremely scaled HfO (EOT 0.42nm) using remote interfacial layer scavenging technique and V -tuning dipoles with gate-first process. IEDM 2009

8. B.M. Clemens. Course Notes for MSE 312: Thin Film Deposition. Stanford University. 2000

Chapter 6

Amorphous Metal Alloy Gates - Future work

In this chapter, several future research paths are suggested. Work function tunability is necessary for CMOS fabrication, and so the development of amorphous pMOS compatible alloys will be discussed. The development of atomic layer deposition (ALD) methods for amorphous metals will also be discussed as a means to bring the potential benefits of these materials into high aspect ratio 3D architectures such as replacement gate structures and multi-gate FETs.

6.1. Development of pMOS Compatible Amorphous Metals As mentioned in previous chapters, Ta-W-Si-C is nMOS compatible with an EWF of approximately 4.1 eV. In order to integrate amorphous materials into CMOS devices, a pMOS composition (5.1 eV) must be developed as well. From Fig. 1.7, it can be seen that Ta has a bulk work function of 4.25 eV and that W has a bulk work function of 4.5 eV. Thus, it is not likely that materials with pMOS compatible work functions will be made just by adjusting the relative ratios of Ta/W. (Also, see Table 4.4. Adjusting the Ta/W ratio did not work for the Ta-W-Si-B alloys.) Adding a higher work function material to the alloy or having a thin layer of it at the interface could raise the work function. Ruthenium was chosen as the initial candidate as it has a bulk work function of 4.7 eV and has been used extensively in metallic glasses. Ruthenium was co-sputtered with the Ta35W35Si15C15 target in order to produce films that contained 5-35 atomic% Ru. The as-deposited XRD patterns are shown in Fig. 6.1:

76 0.5 nm Ru/24nm Ta W Si C (Layered Structure) 6000 35 35 15 15 (Ta35W35Si15C15)95 Ru5 (Ta35W35Si15C15)85 Ru15 5000 (Ta35W35Si15C15)75 Ru25 (Ta35W35Si15C15)65 Ru35 4000

3000

2000

Intensity (a.u.) Intensity 1000

0 35 40 45 50 55 2 Theta (degrees)

Fig. 6.1. Various Ru + Ta35W35Si15C15 alloys plus a layered Ru/Ta35W35Si15C15 film.

Although the all of the compositions were amorphous as-deposited, only the layered structure remained fully amorphous after a 1000oC, 30s rapid thermal anneal in forming gas. (Fig. 6.2)

1 nm Ru/24nm Ta35W35Si15C15 12000 Ta35W35Si15C15 w/ %5 Ru Si (200) Ta35W35Si15C15 w/ %15 Ru Ta W Si C w/ %25 Ru 10000 35 35 15 15 Ta35W35Si15C15 w/ %35 Ru 8000

6000

4000 Intensity (a.u.) Intensity

2000

0 34 36 38 40 42 44 46 48 50 2 Theta (degrees)

o Fig. 6.2. Various Ru + Ta35W35Si15C15 alloys plus a layered Ru/Ta35W35Si15C15 film after a 30s, 1000 C anneal.

Ta35W35Si15C15 w/ %25 Ru Ta35W35Si15C15 w/ %35 Ru

20000

(111) (111)

45 Ta

16000 (220)

2 2

55 (200)

12000 (200) Si

(111)

(110), Ru (110),

3 3

(200), RuSi (200),

3 3 Ru

8000 Ru

RuC (100) RuC

W TaRuC TaRuC

Intensity (a.u.) Intensity 4000

34 36 38 40 42 44 46 48 2 Theta (degrees)

From the XRD patterns taken after the high temperature anneal, it can be seen that the layered structure is the only option among these alloys for a gate-first application. The remaining alloys are, at best, only gate-last compatible. In addition to crystallization under gate-first processing temperatures, it was also found that Ru-containing alloys do not etch with SF6 + O2 as the Ta-W-Si-B and Ta-W- Si-C alloys did. Thus a way to etch the Ru-containing alloys must still be developed. Finally, Ru-W-Si-C alloys should also be deposited and characterized. A potential advantage of these alloys is that low work function Ta is completely eliminated from the alloy. Another way to tune the work function was demonstrated by C.M.Lin, et al.1 In their paper, carbon was alloyed and layered with tungsten to tune the work function. Their structures are shown in Fig. 6.4:

Fig. 6.4. Left, Case 1; Right, Case 2

For Case 1, tungsten was alloyed with carbon. The authors hypothesized that this method could tune the work function because the more electro-negative C attracts electrons from W and the remaining W electrons are more strongly bonded. This increases the effective work function. For Case 2, a carbon layer is sandwiched between two tungsten layers. The authors hypothesized that this method could tune the work function because of the dipole that is created by doing this. (Fig 6.5) This dipole increases the Φms and thus the EWF decreases. The strength of this dipole layer can be increased or decreased by decreasing or increasing the distance of the carbon layer to the channel.

Fig. 6.5. A schematic of the dipole layer induced the C is sandwiched between W layers.

Note that if Case 2 does occur, the low diffusion coefficient of amorphous materials would give us a greater ability to maximize this effect.2

As seen in Fig. 6.6, by using these two methods, the authors were able to tune the work function by 0.5 eV.

Fig. 6.6. From [1]. Tuning the work function with carbon.

In order to see if Ta-W-Si-C could accommodate more C without crystallizing, the Ta35W35Si15C15 target was co-sputtered with a SiC target to produce Ta30W30Si20C20.

From the XRD patterns in Fig 6.7, it can be seen that Ta30W30Si30C20 remains amorphous after an 800oC anneal in forming gas. This indicates that the addition of carbon is a viable option for increasing the work function.

Fig. 6.7. Various Ru + Ta35W35Si15C15 alloys plus a layered Ru/Ta35W35Si15C15 film.

For future work, the C concentration alone should be increased. This could be done by using a carbon target (instead of the SiC one) in conjunction with rf sputtering. The layering method could also be used to bring the already nMOS compatible

Ta40W40Si10C10 closer to the conduction band edge. Finally, amorphous materials have been used extensively as diffusion barriers.2 Furthermore, work by G. Wong3 and C.-H. Liu4 suggest that work function change in bilayer metal gates is due to the diffusion of the top metal through the bottom metal to the gate/dielectric interface. Thus, the Ta-W- Si-C amorphous alloy can also be used to study the bilayer effect. For this, several nanometers of Ta-W-Si-C would be deposited on gate dielectric/substrate and then a pMOS metal layer would be deposited on top of that. If this is done and the work function does not change, then this would suggest that the diffusion model proposed by [3,4] is correct.

6.2. Atomic Layer Deposition (ALD) of Amorphous Alloys As mentioned in the introduction, replacement gates require ALD to deposit conformal high-k and metal gate layers after the sacrificial gate is stripped away. As developed in this work, the amorphous materials can only be used in a gate-first process as sputter deposition is not a conformal method. Furthermore, planar bulk FETs are currently widely in use. (Fig. 6.8)

Fig. 6.8. A Planar bulk FET. From freescale.com.

There are several concerns with this type of structure as transistors continue to scale down and one of the big ones is the “off-state" leakage current. This leakage

81 current increases the standby power required by the mobile device and thus reduces the performance. Because of this issue, 3D FETs are being investigated. (Fig. 6.9)

Fig. 6.9. A Tri-Gate FET. [5]

A major advantage of 3D FETs is that the channel is surrounded by several gates on multiple surfaces and this allows for more effective suppression of the "off-state" leakage current. This leads to lower power consumption and enhanced device performance. 3D FETs can also be more compact. This could lead to higher transistor density thus to smaller overall electronics. In fact, Intel has already announced that the company plans to use 3D transistors for their 22nm node.6 However, the complex geometries and/or high aspect ratios of gate-last and 3D architectures require ALD in order to deposit the metal gate. Thus, a way to deposit amorphous metals by ALD must be found in order to bring their advantages to 3D/ gate-last structures.

S.-H. Kim, et al., used ALD to deposit nano-crystalline WNxCy thin films for use a diffusion barrier layer.

Fig. 6.10. Conformal deposition of WNxCy. From [7].

This experiment demonstrates deposition of alloys similar to amorphous alloys, giving an indication that deposition of amorphous alloys by ALD might be possible. Additionally, Ta can also be deposited by ALD.8 However, since gate-last materials only have to be stable under gate-last processing conditions (400oC), new, less complex amorphous materials could also be developed. Quaternary alloys with refractory metals were used in this work since gate-first compatibility was desired. The recent shift towards gate-last processing methods would ease up these material restrictions. Thus, for future work, ALD deposition of gate-last (nMOS and pMOS) and gate-first (nMOS and pMOS) amorphous alloys should be developed. Note that gate first and gate last both have appropriate applications. Low power applications can tolerate higher EOT and VTh, so gate first might be the most appropriate choice. High performance applications, however; require gate last processing.9

References

1. C.M.Lin, et al. Work Function Tailoring of Carbon-Added Tungsten Gate Electrodes. J. Electrochem. Soc., Volume 158, Issue 2, pp. H146-H149 (2011)

2. J.P.Chu, et al. Ultrathin Diffusion Barrier for Copper Metallization: A Thermally Stable Amorphous Rare-Earth Scandate. J. Electrochem. Soc., Volume 157, Issue 3, pp. H384-H388 (2010)

3. G.M.T. Wong. An investigation of the work function of metal gate electrodes for advanced CMOS applications. Ph.D. dissertation, Dept. Mat. Sci. & Eng., Stanford Univ., Stanford, CA, 2008.

4. C.H. Liu. Bilayer metal gate electrodes with tunable work function: behavior, mechanism, and device characteristics. Ph.D. dissertation, Dept. Electrical Eng., Stanford Univ., Stanford, CA, 2007.

5. F. Shearer. Power management in mobile devices--A view of energy conservation--Part IV. eetimes.com. 2008

6. http://newsroom.intel.com/docs/DOC-2032

7. S.-H. Kim, et al. Characterization of Atomic Layer Deposited WNxCy Thin Film as a Diffusion Barrier for Copper Metallization. J. Electrochem. Soc., Vol. 151 (4) C272-C282 (2004)

8. S. M. Rossnagel, et al., Plasma-enhanced atomic layer deposition of Ta and Ti for interconnect diffusion barriers. J. Vac. Sci. Technol. B. Vol 18, pg. 2016 (2000)

9. T.Y. Hoffmann. Integrating high-k /metal gates: gate-first or gate-last http://www.electroiq.com/articles/sst/2010/03/integrating-high-k.html. 2010

Chapter 7

Conclusions

At the beginning of this thesis, it was shown, experimentally and theoretically, that threshold voltage variability is a problem. In Chapter 3, varying levels of oxygen in the gate deposition process were shown to cause work function variability that was measureable even in long channel devices. For gate films grown in carefully controlled conditions, a portion of the threshold variability measured has been attributed to the work function variability caused by the polycrystalline nature of current metal gates (like TiN). In order to confirm/remedy this problem, Ta-W-Si-B amorphous gate alloys were initially o developed. These materials are structurally stable on HfO2 at 1000 C; however, B diffusion above 800oC makes these materials at most gate-last compatible Ta-W-Si-C alloys were developed next. These materials are also structurally o stable above 1100 C on HfO2. Additionally, C is not a dopant in Si, so these materials appear to be gate-first compatible. They also have nMOS compatible work function and can be integrated into MOS devices. Because Ta-W-Si-C is smooth and lacks the potential roughness caused by grain boundaries and work function variation, it was hypothesized that amorphous materials may also decrease mobility degradation with respect to polycrystalline gates. Ta-W-Si-

C was successfully integrated into ring gate transistors via gate-first processing on HfO2 and initial mobility measurements suggest that Ta-W-Si-C enhances the electron μeff with respect to crystalline gates. Further testing should be done to confirm this effect. Making short channel devices to compare the threshold voltage variability of amorphous metal gates with respect to conventional polycrystalline ones has necessitated industry collaboration. In order to integrate Ta-W-Si-C at Applied

Materials, single target alloy deposition had to be developed. Ta40W40Si10C10 and

Ta35W35Si15C15 custom alloy targets both provided films with crystallization

85 temperatures above 1000oC. IMEC will do the short channel, gate-first device fabrication; this collaboration is ongoing. As far as future work is concerned, pMOS compatible amorphous alloys should be developed. Alloy possibilities are Ta35W35Si15Cx, (Ta35W35Si15C15)xRu(1-x) and Ru- W-Si-C. Layering Ta-W-Si-C with a high work function metal has shown gate-first stability; however, new etching procedures need to be developed. ALD development of amorphous metals should also be investigated for 3D architectures such as replacement gate structures and multi-gate FETs.

All in all, amorphous gate metals have the potential to reduce σVth, improve the mobility, and to be integrated into gate-first and gate-late processing.

Appendix 1

Growth Rate Calculations for Alloy Films

This appendix provides the code and the documentation that was used in order to calculate the required target fluxes for the alloy deposition. Note that these rates are still only approximately correct: the densities for the perfect crystal structures were used in the calculations; however, the density can vary in sputter films depending on the sputtering conditions (such as the argon pressure). Denser films are generally deposited at lower sputtering pressure, so 3mtorr of argon (or less) was used throughout these experiments in an attempt to minimize error due to varying density.

[Mathematica Code]: Si Rate set at .5A/s

//////////////////////////////////////Target Densities//////////////////////////////////////////////

ρW := 19.30

ρTa := 16.60

ρWB := 12.79

ρSi := 2.33 //////////////////////////////////////Target Molecular Weight/////////////////////////////////

MW := 183.84

MTa := 180.95

MWB := 205.46

MSi := 28.09 ///////////////////////////////////////////Tooling factors///////////////////////////////////////////

tW := 0.65 tTa := 0.41 tWB := 0.73 tSi := 0.67

////////////////////////////////Desired Alloy Atomic Fractions//////////////////////////////

xW := 0.5 xTa := 0.3 xB := 0.1 xSi := 0.1 /////////////////////////////////////////////Constants/////////////////////////////////////////////////

z := 2/3 y := 1/3 Area := 2.262 1017 Na := 6.022 1023 ///////////////////////////////////////////Silicon Sputter Rate////////////////////////////////////

RSi := 0.05 ////////////////////////////////////////////Silicon Flux /////////////////////////////////////////////

///////////Given the silicon atomic flux, this is the total atomic flux /////////////

////////////////////////Necessary Ta, W2B, and W atomic fluxes////////////////////////

//////////////////////////////////////Target Rates Returned/////////////////////////////////////

{Rw, Rwb, RSi, RTa }

//////////////////////////////////////////////End Code////////////////////////////////////////////////