Chrontelchrontelchrontel Digital PC to TV Encoder Features
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CH7006C CHRONTELCHRONTELChrontel Digital PC to TV Encoder Features 1. F EATURES 2. G ENERAL D ESCRIPTION • Function compatible with CH7004 Chrontel’s CH7006 digital PC to TV encoder is a stand- • Universal digital interface accepts YCrCb (CCIR601 alone integrated circuit which provides a PC 99 compliant or 656) or RGB (15, 16 or 24-bit) video data in both solution for TV output. It provides a universal digital non-interlaced and interlaced formats input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly • True scale rendering engine supports underscan into NTSC or PAL TV format. operations for various graphic resolutions † ¥ This circuit integrates a digital NTSC/PAL encoder with • Enhanced text sharpness and adaptive flicker removal 9-bit DAC interface, and new adaptive flicker filter, and with up to 5-lines of filtering † high accuracy low-jitter phase locked loop to create • Enhanced dot crawl control and area reduction outstanding quality video. Through its true scale scaling • Fully programmable through serial port and deflickering engine, the CH7006 supports full vertical and horizontal underscan capability and operates in 5 • Supports NTSC, NTSC-EIA (Japan), and PAL (B, D, different resolutions including 640x480 and 800x600. G, H, I, M and N) TV formats A new universal digital interface along with full • Provides Composite, S-Video and SCART outputs programmability make the CH7006 ideal for system-level • Auto-detection of TV presence PC solutions. All features are software programmable • Supports VBI pass-through through a standard serial port, to enable a complete PC solution using a TV as the primary display. • Programmable power management • 9-bit video DAC outputs • Complete Windows and DOS driver software • Offered in 44-pin LQFP † Patent number 5,781,241 ¥ Patent number 5,914,753 LINE YUV-RGB CONVERTER MEMORY RGB-YUV CONVERTER TRUE SCALE DIGITAL Y/R SCALING & NTSC/PAL D[15:0] INPUT DEFLICKERING TRIPLE ENCODER DAC INTERFACE ENGINE C/G PIXEL DATA & FILTERS CVBS/B RSET SYSTEM CLOCK SERIAL PORT TIMING & SYNC CONTROLLER PLL GENERATOR SC SD RESET* XCLK HV XI XO/FIN CSYNC P-OUT DS/BCO Figure 1: Functional Block Diagram 201-0000-026 Rev. 2.9, 1/7/2014 1 CHRONTEL CH7006C 3. P IN D ESCRIPTIONS 3.1 Package Diagram H V DVDD P-OUT DGND DS/BCO AGND D[0] D[2] D[1] XCLK 44 43 42 41 40 39 38 37 36 35 34 D[3] 1 33 XO/FIN D[4] 2 32 XI D[5] 3 31 AVDD D[6] 4 30 DVDD DVDD 5 CHRONTEL 29 ADDRRESET* D[7] 6 CH7006 28 DGND D[8] 7 27 SC DGND 8 26 SD D[9] 9 25 VDD D[10] 10 24 RSET D[11] 11 23 GND 12 13 14 15 16 17 18 19 20 21 22 Y/R C/G GND D[12] D[13] D[14] D[15] DVDD DGND CSYNC CVBS/B Figure 2: 44-Pin LQFP 2 201-0000-026 Rev. 2.9, 1/7/2014 CHRONTEL CH7006C 3.2 Pin Descriptions Table 1. Pin Descriptions 44Pin Type Symbol Description LQFP 1,2, In D15-D0 Digital Pixel Inputs 3,4, These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or 6,7,9, 16-bit non-multiplexed formats, determined by the input mode setting (see Registers 10,11, and Programming section). Inputs D0 - D7 are used when operating in 8-bit 12,13, multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs 14,15, D0 - D15 are used when operating in 16-bit mode. The data structure and timing sequence for each mode is described in the section on Digital Input Port. 42,43, 44 37 Out P-OUT Pixel Clock Output The CH7006, operating in master mode, provides a pixel data clocking signal to the VGA controller. This clock will only be provided in master clock modes and will be tri- stated otherwise. This pin provides the pixel clock output signal (adjustable as 1X,2X or 3x) to the VGA controller (see the section on Digital Video Interface, Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. 39 In XCLK Pixel Clock Input To operate in a pure master mode, the P-OUT signal should be connected to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P- OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7006 accepts an external pixel clock input at this pin. The capacitive loading on this pin should be kept to a minimum. 41 In/Out V Vertical Sync Input/Output This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical sync to the VGA controller. The capacitive loading on this pin should kept to a minimum. 40 In/Out H Horizontal Sync Input/Output This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal sync to the VGA controller. The capacitive loading on this pin should be kept to a minimum. 35 In/Out DS/BCO Data/Start (input) / Buffered Clock (output) When configured as an input, the rising edge of this signal identifies the first active pixel of data for each active line. When configured as an output this pin provides a buffered clock output. The output clock can be selected using the BCO register (17h) (see Registers and Programming). 32 In XI Crystal Input A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. 33 In XO/FIN Crystal Output or External Fref A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. 24 In RSET Reference Resistor A 360 Ω resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. 22 Out Y/R Luminance Output A 75 Ω termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating modes other than SCART and RGB bypass, this pin outputs the composite video signal. In SCART and RGB Bypass modes, this pin outputs the red signal. 201-0000-026 Rev. 2.9, 1/7/2014 3 CHRONTEL CH7006C Table 1. Pin Descriptions 44Pin Type Symbol Description LQFP 21 Out C/G Chrominance Output A 75 Ω termination resistor with short traces should be attached between C and ground for optimum performance. In normal operating modes other than SCART and RGB bypass, this pin outputs the composite video signal. In SCART and RGB Bypass modes, this pin outputs the green signal. 20 Out CVBS/B Composite Video Outpu t A 75 Ω termination resistor with short traces should be attached between CVBS and ground for optimum performance. In normal operating modes other than SCART and RGB bypass, this pin outputs the composite video signal. In SCART and RGB Bypass modes, this pin outputs the blue signal. 17 Out CSYNC Composite Sync Output A 75 Ω termination resistor with short traces should be attached between CSYNC and ground for optimum performance. In SCART mode, this pin outputs the composite sync signal. 26 In/Out SD Serial Data (External pull-up required) This pin functions as the serial data pin of the serial port, and uses the DVDD supply and is not 5V tolerant. 27 In SC Serial Clock (Internal pull-up) This pin functions as the serial clock pin of the serial port, and uses the DVDD supply and is not 5V tolerant. 29 In Reset* Reset Input When this pin is low, the CH7006 is held in the power-on reset condition. When this pin is high, the device operates normally and reset is controlled through the serial port register. 34 Power AGND Analog ground This pin provides the ground reference for the analog section of the CH7006, and MUST be connected to the system ground, to prevent latchup. Refer to the Application Information section for information on proper supply decoupling. 31 Power AVDD Analog Supply Voltage This pins supplies the 5V power to the analog section of the CH7006. 25 Power VDD DAC Power Supply This pins supplies the 5V power to CH7006’s internal DAC’s. 19,23 Power GND DAC Ground These pins provide the ground reference for CH7006’s internal DACs. For information on proper supply decoupling, please refer to the Application Information section. 5,16, Power DVDD Digital Supply Voltage 30,38 These pins supply the 3.3V power to the digital section of CH7006. 8,18, Power DGND Digital Ground 28,36 These pins provide the ground reference for the digital section of CH7006, and MUST be connected to the system ground to prevent latchup. 4 201-0000-026 Rev. 2.9, 1/7/2014 CHRONTEL CH7006C 4. D IGITAL V IDEO I NTERFACE The CH7006 digital video interface provides a flexible digital interface between a computer graphics controller and the TV encoder IC, forming the ideal quality/cost configuration for performing the TV-output function. This digital interface consists of up to 16 data signals and 4 control signals, all of which are subject to programmable control through the CH7006 register set.