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An Efficient Hardware Implementation of LDPC Decoder Monazzahalsadat Yasoubi a Thesis in the Department of Electrical and Comput

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An Efficient Hardware Implementation of LDPC Decoder Monazzahalsadat Yasoubi a Thesis in the Department of Electrical and Comput An Efficient Hardware Implementation of LDPC Decoder Monazzahalsadat Yasoubi A Thesis In the Department of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements for the Degree of Master of Applied Science (Electrical and Computer Engineering) at Concordia University Montreal, Quebec, Canada February 2020 © Monazzahalsadat Yasoubi, 2020 CONCORDIA UNIVERSITY SCHOOL OF GRADUATE STUDIES This is to certify that the thesis prepared By: Monazzahalsadat Yasoubi Entitled: An Efficient Hardware Implementation of LDPS Decoder and submitted in partial fulfillment of the requirements for the degree of Master of Applied Science Complies with the regulations of this University and meets the accepted standards with respect to originality and quality. Signed by the final examining committee: ________________________________________________ Chair Dr. M. Medraj (MIAE) ________________________________________________ Examiner, External Dr. M. Medraj (MIAE) To the Program ________________________________________________ Examiner Dr. Y. R. Shayan ________________________________________________ Supervisor Dr. M. R. Soleymani ________________________________________________ Co-Supervisor Dr. Approved by: ___________________________________________ Dr. Yousef R. Shayan, Chair Department of Electrical and Computer Engineering _______13/02/2020____ ___________________________________ Dr. Amir Asif, Dean Gina Cody School of Engineering and Computer Science Abstract An Efficient Hardware Implementation of LDPC Decoder Monazzahalsadat Yasoubi Reliable communication over noisy channel is an old but still challenging issues for communication engineers. Low density parity check codes (LDPC) are linear block codes proposed by Robert G. Gallager in 1960. LDPC codes have lesser complexity compared to Turbo-codes. In most recent wireless communication standard, LDPC is used as one of the most popular forward error correction (FEC) codes due to their excellent error-correcting capability. In this thesis we focus on hardware implementation of the LDPC used in Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) standard ratified in 2005. In architecture design of LDPC decoder, because of the structure of DVB-S2, a memory mapping scheme is used that allows 360 functional units implement simultaneously. The functional units are optimized to reduce hardware resource utilization on an FPGA. A novel design of Range addressable look up table (RALUT) for hyperbolic tangent function is proposed that simplifies the LDPC decoding algorithm while the performance remains the same. Commonly, RALUTs are uniformly distributed on input, however, in our proposed method, instead of representing the LUT input uniformly, we use a non-uniform scale assigning more values to those near zero. Zynq XC7Z030, a family of FPGA’s, is used for Evaluation of the complexity of the proposed design. Synthesizes result show the speed increase due to use of LUT method, however, LUT demand more memory. Thus, we decrease the usage of resource by applying RALUT method. Keyword: LDPC code, DVBS2 standard, Hardware implementation, Vivado HLS. iii Acknowledgments I would like to thank my advisors Prof. M. R Soleymani. I value our discussions on different research challenges as well as their insightful guidance. He has been extremely supportive mentors, both professionally and personally. I could not have come this far without the love of my family. I am always grateful to my parents, my sisters, and my wonderful husband, Ali Mazaheri, for their endless love and support. iv Table of Contents List of Figures .......................................................................................................................... vi List of Tables .......................................................................................................................... vii List of Symbols ........................................................................................................................ ix List of Acronyms ...................................................................................................................... x Chapter 1 .................................................................................................................................. 1 Introduction .............................................................................................................................. 1 1.1. Motivation ........................................................................................................................................... 1 1.2. Related work ........................................................................................................................................ 2 1.2.A. LDPC code and data compression .................................................................................. 4 1.2.B. Reason for using high level synthesizing ........................................................................ 6 1.2.C. Caching method .............................................................................................................. 8 1.3. Thesis contributions ........................................................................................................................... 10 1.4. Thesis outline ..................................................................................................................................... 10 Chapter 2 ................................................................................................................................ 12 Background information ....................................................................................................... 12 Summary ................................................................................................................................. 12 2.1. Low Density Parity Check (LDPC) code .................................................................................................. 12 v 2.2. LDPC code Representation ....................................................................................................................... 15 2.2. A. Bipartite graph representation .......................................................................................... 15 2.2.B. Matrix representation ......................................................................................................... 16 2.2. C. Degree distribution polynomial representation of LDPC 퐻 matrix ................................... 18 2.3. Decoding Algorithm of LDPC code .......................................................................................................... 20 2.3. A. Bit-Flip decoding algorithm (Hard Decoding) .................................................................. 20 2.3. B. Belief propagation decoding algorithm based on Log-likelihood ..................................... 21 2.4. Slepian Wolf coding theorem .................................................................................................................... 24 2.5. Wyner Ziv Coding ..................................................................................................................................... 26 2.6. What is an FPGA? .................................................................................................................................... 26 2.7. Xilinx FPGA Architecture ......................................................................................................................... 28 2.8. Three main methods for designing Lookup table ...................................................................................... 34 2.8. A . Piecewise Linear (PWL) Approximation .......................................................................... 35 2.8.B. Lookup Table (LUT) Approximation .................................................................................. 35 2.8.c. Hybrid Methods ................................................................................................................... 35 Chapter 3 ................................................................................................................................ 37 Decoder Hardware Implementation and Slepian-Wolf compression using DVB-s2 LDPC code .............................................................................................................................. 37 Summary ................................................................................................................................. 37 3.1. LDPC Codes in DVB-S2 Standard ............................................................................................................ 38 3.2. The architecture of the hardware implementation of DVB-S2 LDPC ....................................................... 42 3.3. Hyperbolic Tangent Function Implementation ......................................................................................... 44 3.4 Implementation of the Hyperbolic Tangent Function by Range Addressable Lookup Table ..................... 47 vi 3.4 A. Applying Range addressable Lookup Table Approximation to update variable nodes in the LDPC decoder .............................................................................................................................. 49 3.4. B. Applying the Proposed Range addressable Lookup Table Approximation to update variable node of eLDPC decoder .................................................................................................. 50 3.5. Data
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