DOCSLIB.ORG

Andre Heidekrueger

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Andre Heidekrueger AMD Heterogenous Computing X86 in development AMD new CPU and Accelerator Designs Building blocks for Heterogenous computing with the GPU Accelerators and the Latest x86 Platform Innovations 1 | Hot Chips | August, 2010 Server Industry Trends China has Seismic The performance of the 265m datasets online gamers fastest supercomputer typically exceed a terabyte grew 500x in the last decade The top 8 systems Accelerator-based on the Green 500 list use accelerators 800 servers on the Green 500 images list are 3x as energy are uploaded to Facebook efficient as those without every second 2 | Hot Chips | August,accelerators 2010 2 Top500.org Performance Projections: Can the Current Trajectory Achieve Exascale? 1 EFlops Might get there on current trajectory, but… • Too late for major government programs leading to 2018 • System power in traditional x86 architecture would be unmanageable Source for chart: Top500.org; annotations by AMD 3 | Hot Chips | August, 2010 Three Eras of Processor Performance Multi-Core Heterogeneous Single-Core Systems Era Era Era Enabled by: Enabled by: Enabled by: Moore’s Law Moore’s Law Moore’s Law Voltage Scaling Desire for Throughput Abundant data parallelism Micro-Architecture 20 years of SMP arch Power efficient GPUs Constrained by: Constrained by: Temporarily constrained by: Power Power Programming models Complexity Parallel SW availability Communication overheads Scalability o o ? we are we are here o here we are Performance here thread Performance - Time Time Application Targeted Time Throughput Throughput Performance (# of Processors) (Data-parallel exploitation) Single 4 | Driving HPC Performance Efficiency Fusion Architecture The Benefits of Heterogeneous Computing x86 CPU owns GPU Optimized for the Software World Modern Workloads . Windows®, MacOS FUSION . Enormous parallel and Linux® franchises computing capacity ARCHITECTURE . Thousands of apps . Outstanding performance-per - . Established programming watt-per-dollar and memory model . Very efficient . Mature tool chain hardware threading . Extensive backward . SIMD architecture well compatibility for matched to modern applications and OSs workloads: video, audio, . High barrier to entry graphics 5 | Driving HPC Performance Efficiency A New Era of HPC Performance Microprocessor Advancement Single-Core Multi-Core Heterogeneous FUSION Era Era Systems Era ARCHITECTURE Heterogeneous System-level Computing programmable OpenCL™/DirectX® Homogeneous driver-based programs Computing nt Graphics GPU Programmability driver-based programs Advanceme Throughput Performance GPU 6 | Driving HPC Performance Efficiency Current AMD HPC Product Portfolio Energy efficient CPU and discrete GPU processors focused on addressing the most demanding HPC workloads Multi-core x86 Processors • Outstanding Performance • Superior Scalability • Enhanced Power Efficiency ATI FirePro™ Professional Graphics • 3D Accelerators For Visualization • Full support for GPU computation with OpenCL AMD FireStream™ GPU Accelerators • Optimized for server integration • Single-slot and dual-slot form factors • Industry standard OpenCL SDK 7 | Driving HPC Performance Efficiency Progression to AMD Server Fusion Current Future (Socket G34) NG Interlagos Terramar CPU/FMAC Server Fusion SR56x0 Accelerator 3 PCI PCI BUS Accelerator 2 GPU Acc. 1 8 | Driving HPC Performance Efficiency Ongoing Memory System and GPU Architecture Improvements . Significant and ongoing bandwidth improvements CPU Cores throughout the / MC UNB System Memory memory system Future UVD APU Chip . Continue incredible pace of GPU improvements in Substantial GPU increases performance/watt planned . Increase sophistication of the GPU so that Substantial increases Substantial it becomes a first-class citizen of the overall planned increases system architecture planned . Single unified virtual address space Discrete GPU Discrete GPU . Virtual memory support via IOMMU Card/Chip MC GDDR (optional) GPU Memory . Participation in system-level coherency UVD . Support for context switching 2X increase planned (PCIe Gen3) 9 | Driving HPC Performance Efficiency AMD SERVER PLATFORM 2003-2011 AMD Opteron™ processor, world’s first x86 World’s first native quad-core processor with 64- and 32-bit capability, x86 processor with HW-based integrated memory controller, HyperTransport™ virtualization features technology high-speed serial system bus and glueless 1-to-8P scalability AMD Opteron™ processor HE/EE, World’s first 6-core x86 first low-power x86 processors processor for 1P to 8P “Bulldozer” World’s first dual-core x86 processor World’s first 12-core x86 processor and direct connect architecture 2.0 AMD socket F (1207) platform: four generations of upgradeability World’s only sub-6 watt per core server Processor 2003 2004 2005 2006 2007 2008 2009 2010 2011 Anticipating needs and delivering innovation at the right time for the market 10 | Presentation Title | February, 2011 | Public BUILDING A “BULLDOZER” PROCESSOR Each processor die is composed of multiple “Bulldozer” modules Module divisions are transparent to Shared L3 CacheL3Shared shared hardware, operating system or application Memory Controller NB/HT Links The modular architecture speeds chip development and increases product flexibility Server: “Interlagos” –16 cores (2 dies) “Valencia” –8 cores (1 die) Client: “Zambezi” –8 cores (1 die) 12 | Presentation Title | March, 2011 | Public NEW “BULLDOZER” INSTRUCTIONS Instruction Description Applications SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3) is a SIMD instruction Video encoding and transcoding. set. It contains 16 discrete instructions; because each can act on 64-bit MMX or 128-bit XMM registers it represents a total of 32 instructions. SSE 4.1 A set of 47 instructions that execute operations which are not specific to Covers a range of applications with several new packed data operations multimedia applications. It features a number of instructions whose action is including various specialized data movement instructions; dot product, determined by a constant field and a set of instructions that take XMM0 as min/max, compare and rounding operations for numeric processing, and an implicit third operand. further video encoding support. SSE 4.2 An additional 7 instructions that are incremental to SSE 4.1, including 4 POPCNT (Population Count) instruction is applicable to bioinformatics very powerful and generic string compare operations. algorithms; CRC32 is for accelerating CRC-based integrity checking of network or disk data transfers; string instructions are applicable to any text- intensive applications such as XML and HTML parsing. Advanced Encryption Standard (AES) Instruction Set is an extension to the Any application that uses AES encryption, key uses being secure network AES (AESNI), x86 instruction set architecture. It helps improve the speed of applications transactions (internet and LANs), disk encryption such as Microsoft’s PCLMULQDQ performing encryption and decryption using the Advanced Encryption BitLocker, and database encryption. Standard (AES). AVX The size of the SIMD vector registers is increased from 128-bits XMM Provides a significant performance boost for vector floating point registers to 256-bits registers called YMM0 - YMM15. Existing 128-bit applications , and a lesser boost for multimedia apps and non-vector FP- instructions use the lower half of the YMM registers. The AVX instruction intensive apps. set allows all two-operand XMM instructions to be modified into non- destructive three-operand forms where the destination register is different from both source registers. FMA4 The FMA instruction set is a extension to the 128-bit and 256-bit SIMD A further boost for numeric applications, particularly HPC-type applications, instructions in the X86 microprocessor instruction set to perform fused providing up to a 2x increase beyond AVX on AMD processors. multiply-add operations. XOP XOP makes the binary coding of new instructions more compatible with A variety of numeric and multimedia applications, including DSP signal Intel's AVX instruction extensions, while the functionality of the instructions processing algorithms for audio and radio. is unchanged. 13 | Presentation Title | March, 2011 | Public Unprecedented Server Performance Gains 45 Floating Point Integer 40 35 30 25 20 15 10 5 0 2003 2004 2005 2006 2007 2008 2009 2010 2011 AMD Opteron™ AMD Opteron™ AMD Opteron™ AMD Opteron™ AMD Opteron™ AMD Opteron™ AMD Opteron™ AMD Opteron™ “Interlagos”* 244 250 x75 285 2356 2384 2435 6176 SE (dual-core) AMD expects “Bulldozer”-based Interlagos to deliver up to 50% more performance than current 12-core AMD Opteron™ processors in standard server workloads * “Interlagos” data is based on AMD projections 14 | Hot Chips | August, 2010 Ongoing Memory System and GPU Architecture Improvements . Significant and ongoing bandwidth CPU improvements throughout the Cores UNB / MC UNB System Memory memory system Future UVD APU Chip . Continue incredible pace of GPU Substantial GPU increases improvements in performance/watt planned Substantial . Increase sophistication of the GPU so that increases Substantial planned it becomes a first-class citizen of the overall increases system architecture planned . Single unified virtual address space Discrete GPU Discrete GPU Card/Chip MC GDDR . Virtual memory support via IOMMU (optional) GPU Memory UVD . Participation in system-level coherency 2X increase planned . Support for context switching (PCIe Gen3) 15 | Hot Chips | August, 2010 .
Load more

Recommended publications
  • Elementary Functions: Towards Automatically Generated, Efficient
    Elementary functions : towards automatically generated, efficient, and vectorizable implementations Hugues De Lassus Saint-Genies To cite this version: Hugues De Lassus Saint-Genies. Elementary functions : towards automatically generated, efficient, and vectorizable implementations. Other [cs.OH]. Université de Perpignan, 2018. English. NNT : 2018PERP0010. tel-01841424 HAL Id: tel-01841424 https://tel.archives-ouvertes.fr/tel-01841424 Submitted on 17 Jul 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Délivré par l’Université de Perpignan Via Domitia Préparée au sein de l’école doctorale 305 – Énergie et Environnement Et de l’unité de recherche DALI – LIRMM – CNRS UMR 5506 Spécialité: Informatique Présentée par Hugues de Lassus Saint-Geniès [email protected] Elementary functions: towards automatically generated, efficient, and vectorizable implementations Version soumise aux rapporteurs. Jury composé de : M. Florent de Dinechin Pr. INSA Lyon Rapporteur Mme Fabienne Jézéquel MC, HDR UParis 2 Rapporteur M. Marc Daumas Pr. UPVD Examinateur M. Lionel Lacassagne Pr. UParis 6 Examinateur M. Daniel Menard Pr. INSA Rennes Examinateur M. Éric Petit Ph.D. Intel Examinateur M. David Defour MC, HDR UPVD Directeur M. Guillaume Revy MC UPVD Codirecteur À la mémoire de ma grand-mère Françoise Lapergue et de Jos Perrot, marin-pêcheur bigouden.
    [Show full text]
  • Hierarchical Roofline Analysis for Gpus: Accelerating Performance
    Hierarchical Roofline Analysis for GPUs: Accelerating Performance Optimization for the NERSC-9 Perlmutter System Charlene Yang, Thorsten Kurth Samuel Williams National Energy Research Scientific Computing Center Computational Research Division Lawrence Berkeley National Laboratory Lawrence Berkeley National Laboratory Berkeley, CA 94720, USA Berkeley, CA 94720, USA fcjyang, [email protected] [email protected] Abstract—The Roofline performance model provides an Performance (GFLOP/s) is bound by: intuitive and insightful approach to identifying performance bottlenecks and guiding performance optimization. In prepa- Peak GFLOP/s GFLOP/s ≤ min (1) ration for the next-generation supercomputer Perlmutter at Peak GB/s × Arithmetic Intensity NERSC, this paper presents a methodology to construct a hi- erarchical Roofline on NVIDIA GPUs and extend it to support which produces the traditional Roofline formulation when reduced precision and Tensor Cores. The hierarchical Roofline incorporates L1, L2, device memory and system memory plotted on a log-log plot. bandwidths into one single figure, and it offers more profound Previously, the Roofline model was expanded to support insights into performance analysis than the traditional DRAM- the full memory hierarchy [2], [3] by adding additional band- only Roofline. We use our Roofline methodology to analyze width “ceilings”. Similarly, additional ceilings beneath the three proxy applications: GPP from BerkeleyGW, HPGMG Roofline can be added to represent performance bottlenecks from AMReX, and conv2d from TensorFlow. In so doing, we demonstrate the ability of our methodology to readily arising from lack of vectorization or the failure to exploit understand various aspects of performance and performance fused multiply-add (FMA) instructions. bottlenecks on NVIDIA GPUs and motivate code optimizations.
    [Show full text]
  • Theoretical Peak FLOPS Per Instruction Set on Modern Intel Cpus
    Theoretical Peak FLOPS per instruction set on modern Intel CPUs Romain Dolbeau Bull – Center for Excellence in Parallel Programming Email: [email protected] Abstract—It used to be that evaluating the theoretical and potentially multiple threads per core. Vector of peak performance of a CPU in FLOPS (floating point varying sizes. And more sophisticated instructions. operations per seconds) was merely a matter of multiplying Equation2 describes a more realistic view, that we the frequency by the number of floating-point instructions will explain in details in the rest of the paper, first per cycles. Today however, CPUs have features such as vectorization, fused multiply-add, hyper-threading or in general in sectionII and then for the specific “turbo” mode. In this paper, we look into this theoretical cases of Intel CPUs: first a simple one from the peak for recent full-featured Intel CPUs., taking into Nehalem/Westmere era in section III and then the account not only the simple absolute peak, but also the full complexity of the Haswell family in sectionIV. relevant instruction sets and encoding and the frequency A complement to this paper titled “Theoretical Peak scaling behavior of current Intel CPUs. FLOPS per instruction set on less conventional Revision 1.41, 2016/10/04 08:49:16 Index Terms—FLOPS hardware” [1] covers other computing devices. flop 9 I. INTRODUCTION > operation> High performance computing thrives on fast com- > > putations and high memory bandwidth. But before > operations => any code or even benchmark is run, the very first × micro − architecture instruction number to evaluate a system is the theoretical peak > > - how many floating-point operations the system > can theoretically execute in a given time.
    [Show full text]
  • Introduction to Intel Scalable Architectures
    Introduction to Intel scalable architectures Fabio Affinito (SCAI - Cineca) Available options... Right here, right now… two kind of solutions are available on the market: ● IBM+ nVIDIA (Coral-like) ● Intel-based (Xeon/Xeon Phi) IBM+NVIDIA Each node will be based on a Power CPU + 4/6/8 nVIDIA TESLA GPUs connected using an nVIDIA NVlink interconnect Intel Xeon and Xeon Phi Intel will keep on with the production of server processors on the Xeon line, together with the introduction of the Xeon Phi many-core chips Intel Xeon Phi will not be a co-processor anymore, but a self-standing CPU with a very high number of cores Such systems are integrated by several vendors in many different configurations (Cray, HP, Lenovo, E4..) MARCONI FERMI, the IBM BlueGene/Q deployed in Cineca ended its lifecycle in 2016 We needed a new HPC machine that could - increase the computational power - respect the agreements with PRACE - satisfy the needs of the italian computing community MARCONI MARCONI NeXtScale architecture nx360M5 nodes: Supporting Intel HSW & BDW Able to host both IB network Mellanox EDR & Intel Omni-Path Twelve nodes are grouped into a Chassis (6 chassis per rack) The compute node is made of: 2 x Intel Broadwell (Xeon processor E5-2697 v4) 18 cores, 2,3 HGz 8 x 16GB DIMM memory (RAM DDR4 2400 MHz), 128 GB total 1 x 129 GB SATA MLC S3500 Enterprise Value SSD Further details 1 x link OPA 100GBs 2*18*2,3*16 = 1.325 GFs peak 24 rack in total: 21 rack compute 1 rack service nodes 2 racks core switch MARCONI - Network MARCONI - Network MARCONI - Storage
    [Show full text]
  • Intel® Architecture Instruction Set Extensions and Future Features
    Intel® Architecture Instruction Set Extensions and Future Features Programming Reference May 2021 319433-044 Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All product plans and roadmaps are subject to change without notice. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not “commercial” names and not intended to function as trademarks. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be ob- tained by calling 1-800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Copyright © 2021, Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
    [Show full text]
  • Intel(R) Advanced Vector Extensions Programming Reference
    Intel® Advanced Vector Extensions Programming Reference 319433-011 JUNE 2011 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT- ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Developers must not rely on the absence or characteristics of any features or instructions marked “re- served” or “undefined.” Improper use of reserved or undefined features or instructions may cause unpre- dictable behavior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use. The Intel® 64 architecture processors may contain design defects or errors known as errata. Current char- acterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel® processor supporting Hyper- Threading Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information, see http://www.in- tel.com/technology/hyperthread/index.htm; including details on which processors support HT Technology.
    [Show full text]
  • Effective Vectorization with Openmp 4.5
    ORNL/TM-2016/391 Effective Vectorization with OpenMP 4.5 Joseph Huber Oscar Hernandez Graham Lopez Approved for public release. Distribution is unlimited. March 2017 DOCUMENT AVAILABILITY Reports produced after January 1, 1996, are generally available free via US Department of Energy (DOE) SciTech Connect. Website: http://www.osti.gov/scitech/ Reports produced before January 1, 1996, may be purchased by members of the public from the following source: National Technical Information Service 5285 Port Royal Road Springfield, VA 22161 Telephone: 703-605-6000 (1-800-553-6847) TDD: 703-487-4639 Fax: 703-605-6900 E-mail: [email protected] Website: http://classic.ntis.gov/ Reports are available to DOE employees, DOE contractors, Energy Technology Data Ex- change representatives, and International Nuclear Information System representatives from the following source: Office of Scientific and Technical Information PO Box 62 Oak Ridge, TN 37831 Telephone: 865-576-8401 Fax: 865-576-5728 E-mail: [email protected] Website: http://www.osti.gov/contact.html This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any in- formation, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial prod- uct, process, or service by trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof.
    [Show full text]
  • Asianux Server 4 ==
    Asianux Server 4 == MIRACLE LINUX V6 SP3 リリースノート Asianux Server 4 == MIRACLE LINUX V6 SP3 リリースノート (C)2014 MIRACLE LINUX CORPORATION. All rights reserved. Copyright/Trademarks Linux は、Linus Torvalds 氏の米国およびその他の国における、登録商標または商標です。 Asianux は、ミラクル・リナックス株式会社の日本における登録商標です。 ミラクル・リナックス、MIRACLE LINUX は、ミラクル・リナックス株式会社の登録商標です。 RedHat、RPM の名称は、Red Hat, Inc. の米国およびその他の国における商標です。 Intel、Pentium は、Intel Corporation の登録商標または商標です。 Microsoft、Windows は、米国 Microsoft Corporation の米国およびその他の国における登録商標です。 Oracle、Java は、Oracle およびその関連会社の登録商標です。 その他記載された会社名およびロゴ、製品名などは該当する各社の登録商標または商標です。 目次 第 1 章 製品の概要..................................................................................................................5 1.1 本製品の特徴......................................................................................................................................5 1.1.1 スケーラビリティの重視................................................................................................................... 5 1.1.2 ビルトインの仮想化技術................................................................................................................... 5 1.1.3 RAS 機能の充実.............................................................................................................................. 5 1.1.4 Oracle Database との親和性........................................................................................................... 5 1.1.5 他の Linux との互換性・差別化......................................................................................................... 6 1.1.6 充実の有償追加サービス..................................................................................................................
    [Show full text]
  • VCL C++ Vector Class Library Manual
    VCL C++ vector class library manual Agner Fog ○c 2019-10-31. Apache license 2.0 Contents 1 Introduction 3 1.1 How it works . .4 1.2 Features of VCL . .4 1.3 Instruction sets supported . .4 1.4 Platforms supported . .5 1.5 Compilers supported . .5 1.6 Intended use . .5 1.7 How VCL uses metaprogramming . .5 1.8 Availability . .6 1.9 License . .6 2 The basics 7 2.1 How to compile . .7 2.2 Overview of vector classes . .8 2.3 Constructing vectors and loading data into vectors . .9 2.4 Getting data from vectors . 11 2.5 Arrays of vectors . 13 2.6 Using a namespace . 14 3 Operators 15 3.1 Arithmetic operators . 15 3.2 Logic operators . 16 3.3 Integer division . 19 4 Functions 21 4.1 Integer functions . 21 4.2 Floating point simple functions . 23 5 Boolean operations and per-element branches 28 5.1 Internal representation of boolean vectors . 29 5.2 Functions for use with booleans . 30 6 Conversion between vector types 32 6.1 Conversion between data vector types . 32 6.2 Conversion between boolean vector types . 38 7 Permute, blend, lookup, gather and scatter functions 40 7.1 Permute functions . 40 7.2 Blend functions . 41 7.3 Lookup functions . 42 7.4 Gather functions . 45 7.5 Scatter functions . 46 1 8 Mathematical functions 48 8.1 Floating point categorization functions . 49 8.2 Floating point control word manipulation functions . 50 8.3 Floating point mathematical functions . 52 8.4 Inline mathematical functions .
    [Show full text]
  • Speeding up Energy System Models - a Best Practice Guide
    Speeding up Energy System Models - a Best Practice Guide Yvonne Scholz1, Benjamin Fuchs1, Frieder Borggrefe1, Karl-Kien Cao1, Manuel Wetzel1, Kai von Krbek1, Felix Cebulla1, Hans Christian Gils1, Frederik Fiand2, Michael Bussieck2, Thorsten Koch3, Daniel Rehfeldt4, Ambros Gleixner4, Dmitry Khabi5, Thomas Breuer6, Daniel Rohe6, Hannes Hobbie7, David Sch¨onheit7, Hasan Umitcan¨ Yilmaz8, Evangelos Panos9, Samir Jeddi10, and Stefanie Buchholz11 1German Aerospace Center 2GAMS Software GmbH 3Technische Universit¨atBerlin 4Zuse Institute Berlin 5High Performance Computing Center Stuttgart 6Juelich Research Centre 7Technische Universit¨atDresden 8Karlsruhe Institute of Technology 9Paul Scherrer Institute 10University of Cologne 11Technical University of Denmark June 30, 2020 2 Contents 1 Introduction 13 1.1 Energy system optimization models: characteristics and dimensions............... 14 1.1.1 Specific characteristics of different energy system model types.............. 15 1.1.2 The Optimization Environment GAMS.......................... 17 1.2 Solution algorithms.......................................... 17 1.3 High performance computing.................................... 18 1.3.1 High performance computing in Germany......................... 19 1.4 The model experiment in BEAM-ME................................ 20 1.4.1 Participating models and partner institutions....................... 20 1.4.2 Aim of the model experiment................................ 20 1.4.3 Structure of the model experiment............................. 20 I Modeling
    [Show full text]
  • Intel® Architecture Instruction Set Extensions Programming Reference
    Intel® Architecture Instruction Set Extensions Programming Reference 319433-014 AUGUST 2012 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTIC- ULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "MISSION CRITICAL APPLICATION" IS ANY APPLICATION IN WHICH FAILURE OF THE INTEL PRODUCT COULD RESULT, DIRECTLY OR INDIRECT- LY, IN PERSONAL INJURY OR DEATH. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EM- PLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRIT- ICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or char- acteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no respon- sibility whatsoever for conflicts or incompatibilities arising from future changes to them.
    [Show full text]
  • Creating a Compiler Optimized Inlineable Implementation of Intel
    International Journal of Academic Engineering Research (IJAER) ISSN: 2000-001X Vol. 2 Issue 7, July – 2018, Pages: 6-13 Creating a Compiler Optimized Inlineable Implementation of Intel Svml Simd Intrinsics Promyk Zamojski1, Raafat Elfouly2 Mathematics and Computer Science Department/ Rhode Island College, RI Email: [email protected], [email protected] Abstract: Single Input Multiple Data (SIMD) provides data parallelism execution via implemented SIMD instructions and registers. Most mainstream computers architectures have been enhanced to provide data parallelism though SIMD extensions. These advances in parallel hardware have not been accompanied by the necessary software libraries granting programmers a set of functions that could work across all major compilers adding a 4x, 8x or 16x performance increase compared to standard SISD. Intel’s SVML library offers SIMD implementation of Math and Scientific functions that have never been ported to work outside of Intel's own compiler. An Open Source inlineable implementation would increase performance and portability. This paper illustrates the development of an alternative compiler neutral implementation of Intel's SVML library. Keywords: Data Parallelism, SIMD Intrinsics, SVML, C++ Math Library, Computer Simulation, Scientific Math Library. 1. INTRODUCTION Compiler[4]. SVML functions can be broken down into 5 main category, Distribution, Division, Exponentiation, Data parallelism occurs when one or more operations Round, Trigonometry and subcategories of __m128, are applied repeatedly
    [Show full text]