AN ABSTRACT OF THE THESIS OF
Alan Winthrop Ede for the Ph.D. in Electrical and
Electronics Engineering presented on August 9, 1968.
Title: Space -Charge -Limited Currents in Silicon Using
Gold Contacts Redacted for privacy Abstract approved: James C. Looney - 1 Major professor
The theoretical characteristics of space- charge- of limited currents in solids are reviewed, and a survey
suitable dielectric materials and experimental space -
charge- limited devices is presented.
The properties of the gold -silicon contact as used in- in space- charge -limited devices were experimentally
vestigated. It was found that the observed characteris- dif- tics could be explained on the basis that the gold
fuses far enough into the silicon under fabrication reduces temperatures to set up a region of traps, which tc a very the space -charge- limited component of current
low value. -limited An attempt to fabricate planar space- charge as the triodes using silicon as the dielectric and gold
source and drain contacts was unsuccessful. Space- Charge- Limited Currents in Silicon Using Gold Contacts
by
Alan Winthrop Ede
A THESIS
submitted to
Oregon State University
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
June 1969 APPROVED: Redacted for privacy
Associate Professor of Electrical and Electronics Engineering in charge of major
Redacted for privacy
and Eiead of Departmént tof Electrical Electronics V Engineering
Redacted for privacy
Dean of Graduate School
Date thesis is presented August 9, 1968
Typed by Erma McClanathan ACKNOWLEDGMENT
It is a pleasure for the author to express his gratitude to the many people whose assistance and advice were invaluable in this investigation. Particular thanks go to Professor James C. Looney of the Department of
Electrical and Electronics Engineering for his overall guiding hand; to Professor Louis N. Stone, Head of the
Department of Electrical and Electronics Engineering, and the Collins Radio Company for financial assistance which indirectly made this investigation possible; and who to Mr. T. N. Tucker, of the Dow Corning Corporation,
so kindly supplied the all- important silicon. TABLE OF CONTENTS
1 I. INTRODUCTION
II. SPACE- CHARGE -LIMITED CURRENTS IN SOLIDS 5 Analogy to a Vacuum Tube 5 The Perfect Insulator 8 The Semi- Insulator with Traps 14 Semiconductors 20 Warm and Hot Electrons 22 Double Injection 27 Transient Space- Charge- Limited Currents 30 Space- Charge Suppression of Noise 34 Temperature Effects 38 Capacitance of Conducting Dielectric 39 Transit -Time Effects 42 43 III. MATERIALS FOR SPACE -CHARGE -LIMITED DIODES Properties of Suitable Materials 43 Cadmium Sulfide 44 Silicon 46 Other Materials 48 51 IV. SPACE -CHARGE- LIMITED TRIODES The Gate 51 History of Early Solid -State Triodes 51 The Gate -Controlled Analog Triode 53 Thin -Film Dielectric Triodes 61 The Heterojunction Triode 67 Metal -Gate Dielectric Triodes 69 The Surface -Channel Dielectric Triode 70 Two- Carrier Dielectric Triodes 73 Noise in Space- Charge- Limited Triodes 74 Frequency Response of Dielectric Triodes 76 77 V. THE PLANAR SURFACE -CHANNEL DIELECTRIC TRIODE Choice of Geometry 77 Choice of Dielectric 78 Type of Contact 79 Metal Contacts to Silicon 80 81 Gate Insulator Gate Material 82 Drain Electrode 82 Design Procedure 82 TABLE OF CONTENTS (Continued)
Experimental Procedure 86 Photoresist Procedure 86 Step -by -Step Fabrication Procedure 88 Testing Procedure 92 Expected Results 92 Discussion of Results 96 106 VI. NATURE OF THE GOLD -SILICON CONTACT Purpose of the Study 106 Design of One- Dimensional Devices 106 Step -by -Step Fabrication Procedure 107 Theoretical Considerations 114 Testing Procedure 117 Discussion of Results 117 Conclusions 126
BIBLIOGRAPHY 128
APPENDIX 152 LIST OF FIGURES
1. The Vacuum Diode 6
2. Potential in a Vacuum Diode 6
3. Mathematical Model for Perfect Insulator Diode 10
4. V -J Characteristic for Semi -Insulator with Deep Traps 10
5. Trap -Free Current for Step Voltage 33
6. Non -Trap -Free Current for Step Voltage 33
7. Lilienfeld's Earliest Triode 52
8. Hilsch and Pohl's Device 52
9. Lilienfeld's Later Device 52
10. Shockley's Early Triode 54
11. Shockley's Analog Triode 54
12. Wright's Mathematical Model 56 56 13. Triode of Ruppel and Smith 60 14. Zuleeg's Analog Triode
15. Weimer's Thin -Film Triode ...... 60 63 16. Geurst's Mathematical Model
17. Typical Silicon TFT 63
18. Heterojunction Triode of Brojdo et al 68 68 19. Band Diagram of Heterojunction Triode 71 20. Surface -Channel Dielectric Triode
21. Mathematical Model for Surface -Channel Dielectric Triode 71 85 22. Source -Drain Geometry 85 23. Gate Geometry LIST OF FIGURES (Continued)
24. Cross -Sectional Geometry 85
25. Mathematical Model for Silicon Surface -Channel Dielectric Triode 93
26. Expected Drain Characteristics 93
27. Response of Triode 1 AuB to a 25 [1-sec. Pulse 103
28. Method of Handling Small Devices 113
29. Diffused Gold Contacts...... 123 LIST OF PLATES
I. High -Voltage Operation of Triode 1 AuB 101
II. High- Temperature Operation of Triode 1 AuB 101
III. Depletion Mode Characteristics of Triode 1 AuB 102
IV. Characteristics of Platelet No. 5 at 25 °C and 220 °C 102
LIST OF GRAPHS
I. Drain Characteristics of Triodes of Chip No. 1. 97
II. Drain Characteristics of Triodes of Chip No. 2. 98
III. Characteristics of Platelet No. 1 118
IV. Characteristics of Platelet No. 2 119
V. Characteristics of Platelet No. 3 120 SPACE -CHARGE- LIMITED CURRENTS IN SILICON USING GOLD CONTACTS
INTRODUCTION
his environ- As man strives to reach ever further from long ment, he finds that communication over increasingly difficult. distances becomes both more important and more beam, high In order to concentrate energy into a narrow faint frequencies must be used, and in order to detect the
signal, stable low -noise equipment is necessary. the Technological progress has brought into being and the junction transistor, the field -effect transistor, solid - space- charge -limited dielectric triode among active the state devices. Of these, the junction transistor has
most well -developed technology, and has been extremely to successful. Although great strides have been made of increase the frequency response and decrease the noise fact that it the junction transistor, it suffers from the which is in- operates by means of a diffusion mechanism, factor herently a slow process, and which is the limiting bipolar in the frequency response. In addition, it is a present device, and carrier regeneration and combination is that it is to generate noise. A third disadvantage is variations. relatively unstable with respect to temperature being At the present time, a great deal of effort is transistor, expended in the development of the field- effect 2 particularly the metal -oxide- semiconductor (MOS) type. done, opera- Although a tremendous amount of work has been They tion of these devices is not yet fully understood. and as are known as one of the group of unipolar devices, noise. such, they do not suffer from carrier recombination the dimen- Current is by drift in a conducting region, and sions and /or conductivity of the conducting region is modulated by means of a transverse electric field. The pres- diffusion mechanism of the junction transistor is not this process. ent, and frequency response is not limited by of the The MOS transistor has only recently come out ap- research stage into development. Continued progress and the fact pears assured in light of the effort involved, an that development of this device appears to be as much
art as a science.
Space- charge- limited currents in solids, on the other
hand, can often be handled theoretically in,a rigorous currents can manner. Such work has shown that substantial mobil- be drawn through an insulator having a high carrier since ity. These currents show very low noise figures, smoothed out by the random variations of drift current are con- the presence of a space- charge cloud at the emitting supply tact. This space- charge region acts as a virtual currents do of carriers, or source, and as such, diffusion an increase not limit the frequency response. In addition, the in temperature decreases the current by decreasing 3 carrier mobility, which makes for thermally stable devices.
Yet, space -charge -limited devices have remained a laboratory curiosity. Although simple in theory, diffi- culties arise in practice.
It is the purpose of this thesis to examine some of the technological problems encountered in the fabrication will of dielectric devices. An experimental planar triode the be described, and its characteristics examined, and characteristics of the gold -silicon contacts used will be experimentally investigated.
The second chapter discusses the mathematical models and theoretical determinations of space -charge- limited currents in insulators, impure insulators, semi -insulators, dis- and semi -conductors. Transient effects are briefly cussed, as is space- charge suppression of noise, capaci- tance of a conducting dielectric, and transit -time effects.
The third chapter describes the materials which have compares been used in experimental two -contact devices and
them from a technological standpoint.
The fourth chapter is a history of the space- charge- and theo- limited triode. A summary of the experimental
retical work up to the present time is presented.
The fifth chapter describes the experimental three - charac- electrode devices, and compares the experimental
teristics with the theoretical ones. the The sixth chapter discusses the properties of 4 gold- silicon contacts, and describes some experimental one -dimensional devices. 5
SPACE -CHARGE -LIMITED CURRENTS IN SOLIDS
Analogy to a Vacuum Tube
cur- The solid -state analog of a space -charge -limited current rent in a vacuum diode is a space- charge -limited of solids in an insulator. It is shown in the band theory carriers, and that a perfect insulator contains no free follows since a vacuum contains none either, the analogy
(158). an anode The vacuum diode consists of a cathode and an electrode in an evacuated enclosure. The cathode is low enough work with a sufficiently high melting point and from function to allow electrons to be thermally emitted above the cathode a solid surface. The cloud of electrons potential surface forms a space charge which depresses the to repel in this region to a point which is sufficient -state additional emitted electrons; thus a stable steady
condition is obtained. See Fig. 1. the anode, a If a positive potential is applied to and posi- conducting electrode insulated from the cathode from tioned some distance from it, electrons are drawn anode. The the space- charge cloud and collected by the cathode surface potential depression immediately above the electrons to weakens enough to allow an equal number of interval of time. enter the space -charge cloud in a given of At all times, however, the rate of emission 6
Cathode Anode (Heated)
Applied potential
Figure 1. The vacuum diode.
V (Potential)
Cathode Anode
(distance)
k- Virtual Cathode
diode. Figure 2. Potential in a vacuum 7
exceed the rate at electrons from the cathode surface must Under which electrons are drawn from the electron cloud. charge -limited, these conditions operation is termed space- rate of emis- and the diode current is independent of the sion of electrons from the cathode (185). appear to be One finds, therefore, that the electrons position of produced at a surface which coincides with the termed the the potential minimum, and this surface is potential virtual cathode (16). It is evident that the for a gradient at the potential minimum must be zero; by: planar geometry (see Fig. 2), this is expressed
dV (Eq. 1) = 0 dx to the In order to obtain the solid -state analog carriers into thermonic vacuum diode, one must inject free at the "cathode" an insulator. Either electrons injected electrode, or electrode, or holes injected at the "anode"
both, are possible. into an insulator it In order to inject free carriers to the insulator is necessary to make intimate contact in work func- with a conducting material. The difference must be low tions between the conductor and the insulator into the insula- enough so that free carriers can diffuse of current in tor. Such a contact will allow passage "injecting "; either direction, and is termed "ohmic" or the "source." in solid -state terminology, it becomes 8
is high enough to If the difference in work functions into the insulator, elec- prevent carriers from diffusing from the dielectric trons can pass only in the direction contact is termed "block- to the conductor. This type of if unidirectional current ing," and it becomes the "drain" can be used as the drain if is desired. An ohmic contact
rectification properties are not wanted. between metals Since the difference in work functions than the work func- and insulators is considerably lower into insulators tions of metals alone, carrier injection by a suitable can be accomplished at room temperature As in the thermionic choice of the conducting material. into the insulator vacuum diode, the diffusion of carriers to prevent additional depresses the potential sufficiently minimum becomes the virtual diffusion (86). The potential with the application of source, and a current can be drawn drain. a suitable potential at the
The Perfect Insulator
of space- charge- The current -voltage relationship of interest here. A limited currents in insulators is was presented by rigorous treatment of the problem simplified treatment, how- Borgnis (19) in 1935. A much
ever, suffices. material, and Consider a flat plate of insulating essentially sufficiently extensive to be considered 9
injecting con- infinite in its lateral dimensions. Let an source, and a second tact be made to one face to form the blocking, be made contact, which may be either injecting or the distance from to the other face to form the drain. Let contact to the drain the potential minimum at the injecting contact be L'. See Fig. 3, p. 10. low voltage, Under the application of even a rather to the source con- the potential minimum is extremely close contact. The actual tact for a copiously injecting metal in work distance depends primarily upon the difference and the functions between the metal and the insulator, applied voltages applied voltage (158, p. 169 -171). For is of the order of in excess of a volt or so the distance magnitude of 10 -6 m (259). the application Let a current density, J, flow under of the potential of an applied voltage, V. The magnitude is Vo. minimum below the reference (source) potential magnitude of .1 volt This is typically of the order of difference, V', is (158, p. 171). The inner potential to drain and is, the voltage drop from virtual source
therefore, (Eq. 2) V = V + Vo. are not accel- Unlike a vacuum diode, the electrons drain, but because of erated continuously from source to a drift velocity, scattering by the crystal lattice attain is proportional to the v, which, at low field strengths, lo
V (potential)
Drain Source
x (distance)
Virtual source L
model for perfect Figure 3. Mathematical insulator diode.
J (log scale) law Child's Traps -filled limit for solids (JosV2)
Ohm's law (JxV)
V (log scale) VTFL VSZ-c
for semi - J characteristic Figure 4. V- traps. insulator with deep 11 electric field, and opposite in direction to it:
v = -4E. (Eq. 3)
The constant of proportionality, 4, is called the
mobility.
From elementary considerations, the current density
due to the electric field, JE, is related to the drift
velocity by 4) JE _ -Nev, (Eq. and N where e is the magnitude of the electronic charge
2 into the electron concentration. Substitution of Eq.
Eq. 4 yields 5) JE = NepE. (Eq. the If the concentration is not constant through to dielectric there will be a component of current due
diffusion. This component is
6) Jo = Dedx (Eq. '
where the proportionality constant, D, is called the
diffusion constant.
The total current density, then, is (Eq. 7) J = JE +JD = Nep,E +DecI .
by The electric field is related to the charge one Poisson's equation; using mks units this is, for
dimension,
dE Ne (Eq. 8) ) dx = E Solving where E is the permittivity of the dielectric. 12 this equation for N, and substituting in Eq. 7 yields 2 E (Eq. 9) J = d + DE . EllEdx dx One obtains by integration
1 Jx +co = µ,E2 +DEdx (Eq. 10) ,
and pl where co is the constant of integration. Since D are related by the Einstein relation,
kT), (Eq. 11) D = , e absolute where k is Boltzmann's constant and T is the
is of the order of magnitude of temperature, and since dx E/L one finds: kT..,EE DEdE ti (Eq. 12) dx eLi
This term can be neglected if it is small with respect to .1,E22 E. . If
keTLeE 1 < E2, then
« 2EL. e applied Since EL' is of the order of magnitude of the
= .025 volts, it is voltage, and, at room temperature eT justified observed that dropping the diffusion term is or so. Thus, for applied voltages in excess of a volt
ti (Eq. 13) Jx + co 2 E2 . field Since the potential minimum is at x = 0, the integration vanishes E = 0 at this point; the constant of 13 and one gets
..> 1 2 (Eq. 14) µE Jx - 2 or, solving for E,
(2Jx) ' (Eq. 15) E _ J . µ A subsequent integration, L z ti f(2jx) (Eq. 16) V dx , o yields:
N ( 3/2 (Eq. 17) ) L ' V' 3 l Eµ which, when solved for J, becomes
9 . I2 (Eq. 18) J - V 8 L'3
above a volt or so, If the applied voltage is from source to virtual source V' = V; and if the distance insulator thickness, L, is small with respect to the N the following approximate L L'. Under these conditions
relation holds:
, 2 2 (Eq. 19) -E4 V . J = S
law for solids, by This is commonly known as Child's for a vacuum diode, analogy to the well -known Child's law power law instead of which, however, is a three -halves
the square law derived here (30). more amenable to experi- It is evident that Eq. 19 is varies in a mental verification than is Eq. 18. L' 14 complicated fashion with V, and the height of the potential and minimum does also. Both variations are slow, however, at usual operating voltage the differences in J obtained by using Eq. 18 and Eq. 19 would be very small. A more rigorous analysis, taking diffusion into account, essen- tially verifies these results (259).
Meltzner (153) has shown that a square -law is ex- pected for cylindrical and spherical geometries as well.
The Semi -Insulator with Traps
Child's law for solids predicts that for a typical insulator, 10 -5 m in thickness, current densities of the order of tens of amperes per square centimeter should be obtained with an applied potential of several volts.
Experimentally, however, currents are found to be gener- ally much lower than those predicted by the theory
(188, 227) and follow the square law only for relatively high values of applied voltage (197).
In a real crystal, there apparently exist vacant called energy levels below the conduction band, commonly by the traps. Electrons from the source are immobilized
insulator in these traps, where they form a space- charge and barrier which repels additional electrons. Mott the trap Gurney (158, p. 173) have determined that if
concentration were as low as 1016 /cm3, a layer 10 -5 cm any thick would be sufficient to prevent the passage of 15 current at room temperature.
Traps are arbitrarily divided into two classifica- tions.
"Shallow" traps have an energy level only slightly below the bottom of the conduction band such that under thermal equilibrium only a relatively small number are filled at any one time.
"Deep" traps have an energy level sufficiently far below the bottom of the conduction band so that the traps are normally nearly completely filled under the condi- tions of operation.
Space- charge -limited currents in an insulator having shallow traps have been discussed by Rose (191). He
assumes that the current is reduced by the ratio of free
to total number of electrons to get
9 BEu. 2 J - V (Eq. 20) 8 L3
where 8 is the above ratio, and is given by the approxi-
mate relation ET (Eq. 21) e kT . t
Here, N is the electron concentration in the insula-
tor, Nt the trap concentration, and ET is the trap depth
below the bottom of the conduction band.
Trap depths have been experimentally determined
using these relations (80). 16
A more rigorous treatment of space- charge -limited made currents in an insulator with deep traps has been by Lampert (116). in- Let us assume that we have ohmic contact to an concen- sulator with relatively deep traps, of sufficient at low tration to prevent current flow from the metal voltages. can Then, at low voltages, the only current that the insula- flow is that due to the bulk conductivity of law. tor itself, and the current will follow Ohm's
As the anode potential is increased, electrons and keep penetrate into the insulator and fill the traps, the depth of the potential minimum nearly constant. filled- Eventually a point is reached, called the "traps- to be filled limit," when there are no additional traps this point, the in the bulk of the semi -insulator. At very potential barrier drops rapidly, with a resulting further steep rise in current. As the applied voltage is negligible with increased, the effect of trapping becomes takes over. respect to the free charge, and the square law
See Fig. 4, p. 10. should It is expected, then, that a semi -insulator region show a low- voltage region where JV, a second two, and a third where JecV, where ac..is greater than
region, where J0cV2 the solutions The theoretical J -V curves follow from 17 of the following three equations, subject to the appropri-
ate boundary conditions.
These are, respectively, the current -flow equation,
Poisson's equation, and the Fermi -Dirac occupation func-
tion for the traps.
If the diffusion current is neglected, the current -
flow equation is as before, (Eq. 22) J = NeµE.
Poisson's equation becomes
dE [(n-z) + (nt- nt) (Eq. 23) dx E and trapped where n and nt are the concentrations of free
electrons, respectively, and ñ and Et are the concentra- the tions of free and trapped electrons, respectively, in
bulk material with no applied voltage. These must be con- subtracted out because although some bulk electrons the tribute to the current, they do not contribute to posi- field, since they are neutralized by corresponding
tive charges in the electrically neutral bulk material.
N is the total number of free electrons.
The equation of state, from Fermi -Dirac statistics, is Nt (Eq. 24) nt (x) Et (x) -F (x) 1 + e kT energy Nt is the trap concentration, Et(x) the trap -insulator. level, and F(x) the Fermi level of the semi 18 x, as before, is distance into the semi -insulator.
Two boundary conditions are necessary. If the dielectric is considered to be semi -infinite in extent, then n --k ñ as x --* co. The second boundary condition must be applied at the interface. By taking the inter- face to be at the potential minimum an approximate boundary condition of E --* 0 as x -9 0 is obtained.
Even with these simplifications an exact solution in a general closed form has not, to the writer's knowledge, been obtained, and is probably impossible (261, 262). A large amount of work has been done on the problem, how- ever, and approximate solutions have been determined for many cases having restricted ranges of interest (1, 37,
55, 116, 121, 130, 139, 187, 222, 224, 225, 235, 259).
Of interest are the points of intersection, VQ and occurs when VTFL. V2-c
Jo = Jc. (Eq. 25)
JQ is the Ohm's -law current density, and Jc is the
Child's law current density. Since J = aE (Eq. 26) and for the bulk material Q=ñeµ, (Eq. 27) we have
(Eq. 28) J = neµE . Since the current density is normally very low at
this point, 19
(Eq. 29) .v V
L ' and - V (Eq. 30) JQ N neµL .
Child's law current density Equating this to the yields 2 V 31) V52 -c 9 Q -c (Eq. ne µ - rtµ L L3 ' so that v 8eL2ñ (Eq. 32) VS2-c - 9E of free carriers in a From this the concentration has been calculated (80). given semi -insulator since is of greater interest The traps -filled limit If the trap concentration of traps. it depends upon the equilibrium greater than the thermal concentration is much the traps - in the bulk material, concentration of carriers the current very well defined, since filled limit will be to once the repulsion due will increase very rapidly overcome. filled traps has been are assumed to be If all traps in the dielectric becomes equation in one dimension filled, then Poisson's 33) dE Nte (Eq. dx E that Nt is constant Under the further assumptions 0, and that E -; 0 at x --'- throughout the insulator,
integration yields: dV Ntex (Eq. 34) E . - dx - E 20
A subsequent integration yields: NteL2 (Eq. 35) VTFI, 26 ' this being the voltage necessary to overcome the repulsion due to the trapped charge.
From this, measurement of the traps -filled limit has been used, with variable success, to determine trap con- centrations (5, 27, 120, 123, 225, 243, 275). Recent work by Nicolet (164) indicates that the traps outside the immediate vicinity of the source have little effect on the
J -V characteristics, and that since trap concentrations likely vary in the material, particularly near the surface, the traps -filled limit may not be a reliable tool for get- ting trap concentrations.
Further theoretical work on traps has been carried out by English and Drews, as cited by Lampert (118, p. 341); they presented an analysis for two trap levels.
It is evident that the effect of traps can be com- pensated by a similar concentration of donor impurity atoms; work on trap concentrations and depths in crystals having a significant degree of compensation has been carried out by Marlor and Woods (149).
Semiconductors
Space- charge -limited currents in semiconductors show
characteristics very similar to those for semi -insulators. 21
In an n + -i -n+ structure, the n+ source forms an injecting contact, and if hole current is neglected, the resulting J -V curves are the same as those for an insula- tor. An analogous result occurs for hole current in a p + -i -p + structure. + - + + - + -p In an n -p -n structure (or its analog, the p -n configuration) the characteristics are quite similar to those for a semi -insulator with traps. The source injects majority carriers into the relatively lightly doped base there region where they combine with the majority carriers in a to form a space- charge region depleted of carriers, manner entirely analogous to that for an insulator with
traps.
Evidently, the low- voltage characteristic is that of voltage is a floating -base transistor. As the applied base increased the space- charge region extends across the
region until the base is entirely depleted of carriers. carriers At this point, the repulsion due to the trapped semiconductor is overcome, and current rises rapidly. In the terminology, the traps- filled limit voltage is called the current "punch- through" voltage. Beyond this point mobility approaches the square -law characteristic, if the
of the carriers remains constant. before, The punch- through voltage is obtained, as get: by integrating Po ?son's equation twice to L P (Eq. 36) - - , Vp 2E 22
charge where Vp is the punch- through voltage and p the P impurity density in the base, which is essentially the concentration at room temperature. semicon- The difference between semi -insulators and traps, these ductors evidently lies in the mobility of the and highly being essentially immobile in a semi -insulator, called holes. mobile in a semiconductor, where they are the inter- For a more rigorous theoretical analysis Shockley and ested reader is referred to the work done by
Prim (217).
Warm and Hot Electrons
sections are The results obtained in the previous most important of subject to several approximations. The of dif- these are the following: First, the contribution Second, the approxi- fusion current has been neglected.
0 has been mate boundary condition E --b- 0 as x -- assumed to applied. Third, the mobility, p, has been
remain constant with the electric field. these In general, solution of the problem without the results that assumptions is extremely difficult, and these assump- have been obtained have generally justified (259). An tions for insulators and for semi -insulators work done excellent summary of much of the theoretical (242). through 1965 has been compiled by Tredgold applied, the If sufficiently high voltages are 23 mobility for such high -mobility materials as silicon, germanium, gallium arsenide and indium antimonide is not constant, but falls with increasing electric field strengths (198). Deviations from the square -law, then, are to be expected. Shockley (212) predicted that above a certain critical electric field strength given by
3 ç (Eq. 37) Ecl = 2 , µo
crystal, and 110 where c is the velocity of sound in the 0
the low -field mobility, non -elastic scattering with
acoustical phonons begins to occur, and the resulting
carrier drift velocity is given by
(Eq. 38) v = 2 cµoE .
For germanium and silicon the velocity of sound is the such (18, 142) that the critical field Ecl is near
lower end of the range of practical interest. Similar
values are expected for other high- mobility materials,
with the result that some semiconductors do not generally temperatures obey the square law (115), especially at low
(49, 68, 70) .
By defining the mobility by (Eq. 39) v = [1E ,
and substituting Eq. 38 for v,
3 ' 40) 2 coo (Eq. 1-1 = 11 E
Then, substituting for c from Eq. 37, the dependence 24
for values of E above of µ on the field is obtained Ec1:
Ecl I (Eq. 41) µ = LIS E
From Eq. 9, if one neglects the contribution due to diffusion,
(Eq. 42) J = E dx .
Then, substituting for µ,
1 dE J = (Eq. 43) EµoEclE dx -
Integration, subject to the approximate boundary condition E -. 0 as x --> 0 yields
3 Jx E3/2 2 (Eq. 44) E µo Ecl
From this, Jx 2/3 dV / E _ _ 3 (Eq. 45) dx 11 YET Eµo cl and a subsequent integration yields 2/33 5/3 (2J) 5x V - (Eq. 46) ' (Eµo cl)3/2 or, (5)á/2L5/2 V3/2 2 (Eq. 47)
E µo'EC l
Solving for J yields 3/2 2 5 3(3) EµoYEcl V3/2 (Eq. 48) J = L5/2
Currents obeying this law are said to be composed 25 of "warm" or "tepid" electrons; the average energy of the electrons is appreciably, but not greatly, above that of a field -free crystal.
Experimentally, the onset of the 3/2 -power law does not occur until the field is several times the predicted critical field; however, experimental values of the crit- ical field are not high, ranging from about 900 v /cm for n -type germanium to 7500 v /cm for p -type silicon at room temperature (198).
If breakdown effects can be avoided, one would ex- pect the drift velocity to approach a constant limit viim above a second critical field Ec2 because of non -elastic scattering by lattice phonons (68, 109).
Under these conditions, the current -flow equation is
J = Nevlim (Eq. 49) ' and Poisson's equation is
dE _ Ne (Eq. 50) dx E Elimination of the carrier concentration N between
these equations yields
dE (Eq. 51) J = Evlim dx .
Integration, subject to the boundary condition
E -} 0 as x -4- 0 yields
dV Jx 52) E - = (Eq. dx Evlim
and a second integration yields 26
1JL 2 2 53) V = , (Eq. -Evlim so 2Evlim J - V (Eq. 54) L2
Currents obeying this law are said to be composed of
"hot" electrons, since their energy is much above that of the carriers in a field -free crystal. Experimental observation of hot -electron behavior has been reported by several investigators (49, 68, 69).
Early work on warm and hot electrons has been re- viewed by Koenig (109). Lee and Nicolet have shown that the functional dependence of J on V for field- dependent mobility is the same for planar, spherical and cylindrical geometries (125). Solid -state active devices making use of hot electrons have been reviewed by Moll (155).
Emission -limited currents (analogous to temperature - limited currents in a vacuum diode) can be expected to occur at sufficiently high voltages, if the source contact is marginally ohmic. Under these conditions the potential barrier betwen the source and the insulator is relatively high so that the emission rate is low, which limits the current at higher voltages. Emission -limited currents, commonly called "Schottky" currents, have been investi- gated by a number of workers (54, 58, 96, 126, 169, 230,
231, 239). Operation beyond space- charge- limited 27 conditions is beyond the scope of this study, however, and further details will not be included here.
Double Injection
The p -i -n configuration, which yields two- carrier injection, has been the subject of a great deal of theo- retical and experimental work. The problem is complicated by instabilities due to the fact that carrier recombina- tion can occur (124).
Theoretical analyses have been presented by Lampert
(112, 113, 117, 119) and others (12, 13, 106, 175) on the problem of two -carrier space- charge -limited currents in insulators. Lampert (113, 119), Ashley and Milnes (8), and many others (50, 78, 88, 189, 202) have published
theoretical work on the more difficult problem of double
injection into doped semiconductors.
Lampert's theory predicts a region of ohmic behavior
at low currents caused by thermally released carriers.
At higher voltages, the current becomes space- charge-
limited, and follows the square law. If the voltage is
increased to the point where carrier lifetime becomes
comparable to the transit time, the carriers begin to
cancel the space charges; current increases rapidly, with
the possibility of an unstable, or negative- resistance
region, and in this region follows a cube law.
Some experimental results on intrinsic germanium 28 and silicon have tended to verify Lampert's work to some extent (2, 14, 50, 77, 150, 152); however, these investi- gators reported neither a breakdown region nor a cube -law region for intrinsic or compensated material. It seems likely that the breakdown region was not attained in these cases, for most other investigators have reported a nega- tive- resistance or breakdown condition under double injec- tion, using lower- resistance material. It has been ob- served in doped germanium (93, 95, 232), doped silicon
(2, 50, 93, 95, 100, 218, 250), gallium arsenide (93, 95,
99), gallium phosphide (134), a compound of gallium arsenide and gallium phosphide (63) and cadmium sulfide
(131). Instabilities and oscillations have been reported in doped silicon p -i -n diodes (94, 156, 157) and in gallium arsenide (110).
A number of attempts have been made to account for the negative- resistance effects (8, 53, 112, 113, 114,
232, 233, 271). According to Ashley and Milnes (8), who used a p -type model, holes injected by the p- contact become readily trapped by the occupied acceptor levels, and a space charge builds up. Electrons injected by the n- contact are trapped by empty acceptor levels, but since the material is p -type, recombination occurs, and electron injection can take place, resulting in single- carrier space- charge -limited current. When the hole transit time 29 becomes comparable to the hole lifetime, two- carrier cur- rent commences, with space- charge compensation and negative resistance.
Recent experimental work strongly indicates that upon breakdown the current switches from bulk conduction to a filamentary conduction, analogous to the breakdown from glow discharge to an arc in a gas tube, and that the
Ashley and Milnes theory applies only prior to breakdown, and possibly after the filamentary conducting region has increased to fill the bulk of the material (11, 62, 193,
250) .
The recombination of carriers can result in the emission of electromagnetic radiation, generally in the infrared or visible parts of the spectrum, and has re- sulted in the development of the light- emitting diode
(118).
A mixture of positive and negative carriers is gen- erally known as a plasma, and a detailed study is out of place here. Motz (159) has written an excellent summary of the work done through 1965 on gaseous plasmas, and a good source of references on plasma effects in solids is contained in the Proceedings of the Seventh International
Conference on the Physics of Semiconductors (207). 30
Transient Space -Charge- Limited Currents
When a voltage greater than V -c is suddenly applied to an insulator with traps, the initial current is that due to the flow of carriers into the conduction band, and obeys Child's law for solids. As the carriers fall into the traps, however, the current decays to the steady - state value for an insulator with traps.
The decay time is generally extremely long compared to the transit time, and experimentally may be of the order of minutes or more (116). The time required is a direct measure of the capture cross section of the traps for free carriers (145).
If the voltage is suddenly decreased from its steady - state value, an undershoot in the current may be observed
(191). This comes about because the trapped space charge forms an insurmountable barrier for electrons with the lower applied voltage, cutting off the current until suf- ficient numbers of traps have been thermally emptied.
Consider as a mathematical model the configuration shown in Fig. 3. The conduction equation must include the displacement current, since steady -state conditions do not exist; if diffusion is neglected, and the mobility is assumed constant, we get
J(t) = N(x,t)eµE(x,t) + EaE t't (Eq. 55) 31
If we assume infinite resistance, Poisson's equation becomes
aE X,t ¡'n(x,t) + (Eq. 56) nt(x,t)1 , x E and the continuity equation becomes x an ant(x't)] aJ t _ -e[ xt) (Eq. 57) -- dt + at If we assume that the trapping rate is much greater than the release rate, as will be the case over at least the initial part of the decay range, then the relation between free and trapped carriers can be expressed by
ant(x,t) n(x,t) at (Eq. 58) where r is the trapping time, and is the time for the
free- electron concentration to drop to 1/E of its initial value.
This is seen easily by writing, for an exponential
decay, -t/ n = Ne r, so that
an N n _ - e - t/ _ -?, . Since n +nt = N, a constant,
an ant cwt- at '
from which we get Eq. 58.
We assume, as before, that the virtual cathode is at
x = 0; the boundary conditions, then, are 59) E(0,t) = 0 for t > 0, (Eq. 32 and L E(x,t)dx = V for t ? 0. (Eq. 60)
The initial conditions are
= for x >0, (Eq. 61) E(x,0) L 62) n(x,0) = no for x> 0, (Eq.
and (Eq. 63) nt (x, 0) = nto for x > 0.
out by Solution of these equations has been carried
03) Many and Rakavy (144) for the trap -free case (I, obtained an approx- and the fast -trap case (?'--,* 0); they
imate solution for the more general case. indicates an In the absence of traps the analysis about half its final instantaneous rise in the current to above its final value; it increases to a maximum somewhat transit time, and value in a time somewhat less than the its steady -state value decays in an oscillatory fashion to 5. in about two transit times. See Fig. traps the above In the presence of all but very fast number of transient will die out before an appreciable subsequently decay traps are filled; the current would level at a relatively exponentially to its trap- inhibited
slow rate. See Fig. 6. and Independent analyses by Baron et al. (15), confirm these Schilling and Schachter (204) essentially has been reported results, and experimental verification 33
8JL3 9cpV
t/tr
Figure 5. Trap -free current for step voltage.
3 - 9EWI 5
, t (msec)
Figure 6. Non -trap -free current for step voltage. 34
(15, 145, 146, 220).
Additional analyses have been carried out for a num- ber of special cases. Papadakis (174) has investigated the case where the carriers are suddenly created, as by a light source; Schilling and Schachter (203, 205) have justified the assumption that the diffusion current can be neglected for signals large compared to kT /e; the oscil-
latory decay has been investigated by several workers have (15, 144, 204); double- injection transient currents been analyzed (13), as well as the response to a saw -tooth
voltage (273).
Switch -off characteristics have apparently not been
rigorously investigated (15). Experimentally, when the
voltage is suddenly removed from a conducting space -
charge- limited diode, a marked undershoot in current is
observed, due to the emptying traps (261, 265). The
duration and magnitude of the reverse current generally
depends upon the release rate and concentration of trapped
electrons (227).
Helfrich and Mark (83), by suddenly applying a
reverse bias on a previously forward -biased dielectric in diode measured the magnitude of the hole space charge
anthracene.
Space- Charge Suppression of Noise
Noise properties of space- charge- limited devices 35 have been extensively investigated theoretically by Webb and Wright (250), Sergiescu (206), and Van der Ziel (245,
246, 247, 248). Although there is considerable variation in the predicted results, they all agree that the "shot noise," or random variations in carrier density and veloc- ity, would be suppressed by the space- charge cloud at the virtual source, as in vacuum tubes (167). Early measure- ments on cadmium sulfide (6) had indicated that this would be the case.
At frequencies low enough so that capacitative effects
can be neglected, the arrival of each carrier at the col-
lector can be regarded as an impulse of current density
(Eq. 64) J = pv ;
current density fluctuations are then given by
(Eq. 65) dJ = pdv +vd p .
The velocity fluctuations of emitted carriers are
destroyed by collisions with the crystal lattice, and the
charge density fluctuations of the emitted carriers are
reduced by the repelling nature of the space- charge cloud.
The electrons reaching the drain, then, possess a thermal
motion superimposed upon a drift velocity, which is essen-
tially independent of carrier density and velocity at the
source. In the absence of other sources of noise, such
as hole -electron pair generation, and traps, the limiting
noise of the device is expected to be thermal noise, which
is due to the thermal motion of the carriers. 36
Nyquist (168), in 1928, deduced that the thermal noise of a conductor is given by:
_2 (Eq. 66) en = 4kTRnAf , n n where en is the effective (rms) noise voltage, Rn is the incremental resistance of the conductor, and Of is the frequency range of the noise.
By assuming the carriers to be in thermal equilibrium with the crystal lattice, the thermal noise of a dielectric diode, then, is given by Eq. 66. This can be expressed in terms of the noise current, using Ohm's law, to get (179)
2 (Eq. 67) 1n = 4kTgLf , n where 1 is the effective noise current and g is the in-
cremental conductance.
Determination of the incremental conductance for the
case of thermal equilibrium involves differentiating
Child's law for solids (Eq. 19) to yield
dI 9 E41AV (Eq. 68) g dV 4 L3 '
Van der Ziel (246), however, obtains twice the value
of noise current given by Eq. 67. He considers the noise
to be the sum of that from all sections of the diode:
_2 (Eq. 69) en = 4kTRnAf = Z4kTARAf .
If diffusion is neglected,
V (Eq. 70) Rn = ZAR = ZAI = ; 37 then, from Child's law for solids, Eq. 19,
I 9 tE..I.AV = = 2 g. (Eq. 71) V 8 L3
This means that the square of the noise current
_2 (Eq. 72) ln = 8kTg.Lf , which is twice Webb and Wright's value. He subsequently obtains this result for high frequencies as well (247).
In a later paper (244) he calculates the suppressed shot noise, and shows that it is an order of magnitude below the thermal noise; thus, the limiting noise appears to be the thermal noise.
More recently Klaassen (107) has taken issue with both Webb and Wright and Van der Ziel. He claims that it
is not permissible to compute the short -circuited noise current by means of a linear summation of open- circuit
voltages. By making use of a generalization of Nyquist's
formula he obtains
2 = Tg (Eq. 73) lnn 3
which is two -thirds Webb and Wright's value. Whatever the exact result, it is evident that the
noise is greatly reduced by the space- charge cloud.
In a device following the 3/2 -power law, it is
expected that the noise would be somewhat greater, for than the effective temperature of the carriers is greater
the temperature of the crystal itself. 38
Experimental measurements show large amounts of low - frequency "excess" noise, from undetermined sources. At higher frequencies, the equivalent noise resistance has been found to be essentially the bulk resistance of the device for CdS (132), and GaAs (98) which agrees with the above results.
Noise in double- injection diodes has been experi- mentally studied by Jordan and Knepper (100) and Nicolet et al. (165) in the pre- breakdown region, and they found it to be space- charge suppressed. Large amounts of low - frequency excess noise were encountered, both in silicon and cadmium sulfide.
Tentative sources of excess noise here are fluctua- tions in occupancy of recombination centers or fluctua- tions in the occupancy of shallow traps (100, 274).
Temperature Effects
The temperature affects the space- charge- limited shallow current in that as the temperature is decreased, car- traps retain more carriers, and the mobility of the
riers is increased. shallow In a material having a high concentration of tem- traps, the current can be expected to increase with of the perature (191) in spite of the decreasing mobility
carriers.
Theoretical work by Long (135, 136) and Shockley 39
(211) indicate that the mobility of the carriers in the
3/2 -power region should be proportional to T -1`5. It appears, however, that the mathematical model is not yet sufficiently developed, since attempts at experimental verification have generally yielded a greater magnitude of the exponent (49, 136, 138, 170, 197). However, the experimental results have been quite variable, for both germanium and silicon, with temperature dependencies as high as T -2.7, and as low as T -1.5.
Capacitance of Conducting Dielectric
The capacitance of a dielectric space- charge- limited diode is much lower than that of a junction diode of the same dimensions (51), and is essentially independent of the applied voltage. The stored charge of an operating dielectric diode is present throughout the bulk of the material, and the effective incremental capacitance is actually less than the geometric capacitance.
Let us consider the charge per unit area in an operating space- charge -limited diode. This is given by L 9 (Eq. 74) = of Ndx , Á o where is the charge, A the cross -sectional area of the 9 diode, and N the carrier concentration.
By means of Eq. 8, one gets
E dE (Eq. 75) N = -e- . e dx 40
For a square -law variation, the electric field has been shown to be
z E - (Eq. 15) ( Cµx)
Child's law for solids is
J = V2 ; (Eq. 19) 8 L these two equations can be combined to yield
3 V i E = x . (Eq. 76) 2 L3/23/2
From this,
3 V dE x -2 (Eq. 77) dx 4 L3/2 ' so 3 E V -z N = (Eq. 78) 4 e L3/2 x and L 3 x-zdx . (Eq. 79) A E 4 V3/2 - o L
Integration yields
3 EA V (Eq. 80) 9 - 2 L so the capacitance of the diode
dg 3 EA 3 (Eq. 81) Cd dV 2 L 2C g ' where C, is the capacitance of a parallel -plate capacitor idential to the diode. Cg is called the geometric capaci- tance, and is the capacitance of the diode when it is not conducting (210). 41
It might appear, then, that the equivalent circuit of
a dielectric diode consists of the conductance g in paral-
lel with the capacitance 2Cg.
However, under normal operation, transit -time effects must be taken into account. Wright (264) shows that the
effect of the lagging current is to introduce an effective
negative capacitance equal to three -fourths the geometrical
capacitance; the equivalent circuit, then, under A.C. con-
ditions, consists of the conductance g in parallel with
the capacitance Cg.
At frequencies sufficiently high so that the transit
time is an appreciable fraction of a cycle, the incremen-
tal capacitance increases toward a limit of Cg, and the
conductance falls to two -thirds of its low- frequency
value (42, 210).
Experimental measurements of the input admittance have verified these values of incremental capacitance; however, the incremental conductance increased with fre- quency, due, presumably, to dielectric losses (25).
Although no negative- resistance effects have been
predicted for single- carrier current in a perfect insula-
tor, Dascalu (45) has predicted it to occur at high fre- quencies in an insulator having a high density of fast
shallow traps, and has investigated the effect of traps
on frequency response (43, 44). 42
Transit -Time Effects
The carrier transit time is dependent upon the mobil- ity, diode thickness, and applied voltage.
Since
(Eq. 82) dx = vdt , where v is the carrier drift velocity, the transit time L dx t = . (Eq. 83) r f v o
Since v = 4E, by Eq. 3,
1 (L dx (Eq. 84) tr = . 4J o Substituting for E from Eq. 76 yields
L 3 "2 2 2 4 tr = 3 y x dx = . (Eq. 85) µJ 4V o
Evidently, the only parameter that can be varied to decrease the transit time without increasing the capaci- tance is the mobility. Thus, for high- frequency operation, high- mobility crystals such as germanium or silicon, or such compounds as gallium arsenide, are to be preferred.
These high -mobility materials do not generally obey the square law. This has been found to have very little effect on the incremental capacitance (219). However,
Eq. 85 no longer applies, and the transit time will be
somewhat greater than that which would be obtained by the
use of it. 43
MATERIALS FOR SPACE -CHARGE- LIMITED DIODES
Properties of Suitable Materials
Inspection of the J -V relations, Eq. 19 and Eq. 48, show that the only physical properties of the insulator which affect the current are the permittivity and the carrier mobility. The permittivity of most insulating the materials is of the same order of magnitude, and so mobility of the carriers may be considered to be the the primary figure of merit. Since the transit time is
limiting factor for high- frequency operation (25, 267),
a high mobility is desirable. the It is also necessary that the conductivity of car- material be low enough so that thermally generated
riers and traps do not interfere with the space- charge-
limited current. Materials having both a high carrier
mobility and sufficiently high resistivity are intrinsic gallium silicon, some of the 3 -5 compounds, such as cadmium arsenide, and some of the 2 -6 compounds, such as
sulfide.
Single -crystal materials generally possess higher crystals mobilities than amorphous ones; however, single experi- are more difficult to manufacture. Some promising using mental results have been obtained in some instances
polycrystalline layers (82, 275). 44
Cadmium Sulfide
The greater portion of the early experimental work on dielectric diodes made use of cadmium sulfide as the insu- lator, largely because it was available at a relatively early date in the form of high- resistivity single- crystal platelets with a fairly high carrier (electron) mobility.
Indium is one of the few metals which form an in- jecting contact to cadmium sulfide (226), and it is quite generally used as the cathode. Any one of a large number of metals will form a blocking contact for the anode.
Silver (227), gold (275), tellurium (197), and aluminum
(147) have all been used successfully. Junctions can be formed by means of physical pressure (195), or by solder- ing (234).
Most experimental cadmium sulfide diodes drew much less current than Child's law would predict (149). Since pulsed currents were often much higher than D.C. currents, a relatively high concentration of deep traps was indi- cated, and experimental J -V curves generally approximated those predicted for a semi -insulator with deep traps.
(See Fig. 4, p. 10) Some indications of more than one discrete trapping level were observed (243).
Copper is thought to be an inevitable impurity in cadmium sulfide, where it can substitute for cadmium in
the crystal lattice. It acts as an acceptor impurity and 45
by forms the deep traps. If these traps are compensated is an equal concentration of shallow donors, their effect essentially nullified (171), with the result that compen- sated cadmium sulfide should effectively simulate material without traps.
Compensation can be accomplished by the introduction growth. of a suitable shallow donor impurity during crystal in the crystal Chlorine is thought to substitute for sulfur Since structure and act as a source of donor electrons. less favorable the incorporation of donors is energetically of when the traps are all filled, an accurate compensation deep traps is achieved (137). current has The square -law dependence of voltage with sulfide. The been demonstrated using compensated cadmium magnitude of the current is, however, still considerably Currents less than Child's law would predict (161, 172). been in excess of the theoretical predictions have were attrib- observed in at least one instance (274), and
uted to the onset of double injection (17). with tempera- The current has been found to increase to the ture for uncompensated material due, presumably, slowly with emptying of traps (197), and to decrease of the de- temperature for compensated material because
creasing carrier mobility (172). on cadmium High- frequency and transient measurements
sulfide dielectric diodes has shown that operation 46 in the kMhz range is feasible (31, 210).
Space -charge -limited cadmium sulfide diodes have also been used as photodiodes (190, 192).
It is evident that the properties of cadmium sulfide are highly dependent upon the degree and type of imperfec- tions (28, 51). It appears to be extremely difficult to avoid impurities in the manufacture of this material, and as a result the properties are not easily reproducible.
Therefore cadmium sulfide does not appear to be a satis- factory engineering material for the manufacture of space - charge- limited devices at the present time.
Silicon
Silicon is chemically and physically stable; it is available in pure single- crystal form, with a high resis- tivity and a high carrier mobility. It has a well- devel- oped technology, and is therefore well suited for the study of space- charge -limited currents in solids.
Silicon as nearly intrinsic as possible is used for space- charge -limited devices, and resistivities are typically greater than 1000 ohm -cm. Such pure silicon
can be obtained either p or n--type at the present time,
but early samples were invariably p -type because of the
presence of boron. A process has been developed for the
deposition of high- resistivity single- crystal silicon
films on sapphire (143), and such films are also p- -type. 47
High -resistivity n -type material is labeled n or v
to distinguish it from the usual lower -resistivity n -type,
or the degenerate highly- conducting n+ -type. Similarly,
p -type material, if nearly intrinsic, is labeled p or v.
Space- charge -limited hole currents in silicon were
extensively studied by Gregory and Jordan (68, 69, 70).
Using thin wafers, p + -p --p+ devices were made by means of
a low- temperature boron diffusion on opposite sides of the
wafer and subsequently breaking the wafer into small
pieces.
By using a phosphorus diffusion in place of boron on
otherwise similarly prepared crystals, Denda and Nicolet - (49) fabricated n + -p -n+ devices in which the current was
composed of electrons.
Aluminum or gold is generally used to make contact
to the chips, depending upon whether contact is to a p+ or n surface.
Experimental characteristics of these devices were + - + similar, except at low voltages, where the n -p -n devices showed a sub -linear characteristic typical of an + - + open -base transistor, and the p -p -p devices were ohmic.
Beyond the abrupt increase in current at punchthrough, the device characteristics approached a 3/2 -power law at higher voltages.
Additional experimental work has been generally in agreement with these results (29, 166, 170). 48
Silicon space- charge- limited diodes are obtained by source using a single diffusion and ohmic contact for the and a blocking contact for the drain. Such diodes are expected to retain their rectification and detection characteristics at centimeter and even millimeter wave- lengths (29, 42, 267).
Results using silicon have generally been reproduc- ible, and it appears to be a suitable engineering material addition for solid -state space- charge -limited devices. In
to diodes, it can be used to fabricate analog triodes as (which will be discussed presently), and has been used
the dielectric in such devices as the "space- charge
varactor" (97), which has different constant capacitances oscillator in the two directions, and a proposed microwave
(183), consisting of an n + -p -i -p diode in a resonant
cavity.
Other Materials
as A large number of other materials have been used
the dielectric in space- charge -limited devices. to Gallium arsenide shows characteristics similar of traps those of cadmium sulfide (4, 46, 270). Evidence and in at at various depths has been reported (5, 178), oxygen least one case, an accurate compensation using also shows has been accomplished (4). Gallium arsenide sulfide the low- frequency "excess" noise that cadmium 49 does (98), and, in common with cadmium sulfide, has properties that are very difficult to reproduce from sample to sample.
Zinc sulfide also shows characteristics similar to those of cadmium sulfide (3, 196). It appears to be quite difficult to make a reliable injecting contact to this material (52), and in addition it has all the disadvan- tages of cadmium sulfide.
Space- charge -limited currents have been observed also in crystalline iodine (145, 146), amorphous selenium
(79, 122, 123), single crystal silicon carbide (176), crystalline barium titanate (22, 23), amorphous arsenic triselenide (21), silica (90), and several organic com- pounds (80, 83, 84, 85, 104, 105, 148, 221, 236, 237) .
Organic materials generally show low trap densities, and obey the square law.
A review of the earlier work on space- charge- limited currents through 1962 has been published by Lampert (118).
A number of the 3 -5 compounds, particularly gallium arsenide and gallium phosphide, have shown an unstable condition under single- carrier injection (46). Oscilla- tions at several GHz. were first observed by Gunn (73,
74, 75), and the effect bears his name. Theoretical work by Copeland (33, 34) indicates that there are two conduc- tion levels in these compounds, and that the mobility of electrons is vastly different in the two levels. 50
He then explains how the electrons in these levels set up stable space- charge waves which travel the length of the crystal.
The Gunn effect, however, has not been observed under space- charge- limited conditions, presumably because of the relatively low current drawn, but can not be theoretically excluded. A thorough treatment of the Gunn effect is given in a special issue of the Institute of Electrical and Electronics Engineers Transactions on Electron Devices, on Semiconductor Bulk -Effect and Transit -Time Devices, published January, 1966. 51
SPACE - CHARGE -LIMITED TRIODES
The Gate
The addition of a modulating electrode, or gate, to
a dielectric diode results in a space- charge -limited
triode. There are a large number of feasible geometries
and suitable materials, and in addition, many solid -state
configurations originally designed for use with drift cur-
rents are amenable to space- charge -limited operation.
Therefore a review of the earlier devices is in order.
History of Early Solid -State Triodes
Attempts to control the current in a solid by means
of an auxiliary electrode date back to 1926, when Lilien-
feld filed the first of three patent applications (127,
128, 129). Fig. 7 shows his earliest device, consisting
simply of a semi -insulating current -carrying plate, with
the gate, or control, electrode being an insulated wire
on the surface between the source and the drain.
Hilsch and Pohl, in 1938, used an embedded uninsu-
lated rod to modulate the current (87), as shown in
Fig. 8.
One of Lilienfeld's later patents (129) indicates
the use of a completely transverse field to accomplish
modulation. See Fig. 9.
Other early devices were patented by Heil, as cited 52
Insulated Gate Wire Drain Source , __
Semi -Insulator
Figure 7. Lilienfeld's earliest triode.
Drain (platinum
I. Potassium Bromide Source -sue plate) (calcium rod) '.I Gate (platinum rod)
Figure 8. Hilsch and Pohl's device.
Drain Source I I .I7//SI -Semi- Insulator Insulator Gate
Figure 9. Lilienfeld's later triode. 53 by Wright (265, p. 1643), and by Glazer, Koch and Voigt
(67). All of these early devices were quite large in ex- ternal dimensions, and performance was inferior to that of the vacuum tube.
All of the earliest solid -state triodes depended upon carriers already present in a semi -insulating material.
It was not until the development of the junction transis- tor that a true analog to the vacuum triode was presented, and, as might be expected, the earliest suggestions came from Shockley. Following an early device (213), shown in
Fig. 10, he proposed the analog triode shown in Fig. 11
(214)
The analog triode of Fig. 11, however, has not been constructed in cylindrical form, and a planar arrangement would not be a true analog. Shockley suggested the name
"unipolar" for his analog triode, but subsequently he applied the term to any device which employed a single type of carrier. His subsequent treatment of the then proposed field -effect transistor, also called " unipolar," is based upon modulating the effective conductance of the channel, rather than the modulation of a space - charge- limited current (215).
The Gate- Controlled Analog Triode
The gate -controlled analog triode is the solid- state equivalent of the vacuum triode. The source takes 54
Source Gate
Insulator.
Drain Gate
Figure 10. Shockley's early triode.
Drain
Gates
Source
Figure 11. Shockley's analog triode. 55 the place of the cathode, the drain replaces the anode, or plate, and the gate substitutes for the grid; in addition the geometry is such that the analogy is essentially pre- served.
Shockley's triode, as far as the author knows, has not been fabricated because of constructional difficulties.
A planar geometry suggested by Kurshan (111), and shown in
Fig. 12, was used by Wright (260) as a more nearly practi- cal substitute, and served him as a model for the theo- retical determination of the characteristics.
For a perfect insulator Child's law (Eq. 19) states that
ID = PVD (Eq. 86) for a dielectric diode, where ID is the drain current,
VD is the drain voltage, and P, called the permeance, is given by
9 . }_l,A P = (Eq. 87) 8 L3
A is the cross -sectional area of the device normal to the direction of current flow. If the insulator has shallow traps, the permeance must be multiplied by 8, the ratio of free to total number of electrons.
In a triode the current depends upon both the drain and gate potentials, and by analogy with the vacuum triode, will be given by 2 D) (Eq. 88) ID = PK(VC+ , 56
Source OWE t\1 Gate _ ""_ """"`\ Drain
Figure 12. Wright's model.
Drain riiiiii iiiiiii (tellurium) Gate Insulator (tellurium) r..) 1011m (cadmium sulfide) imo:irsi Source (indium)
Figure 13. Triode of Ruppel and Smith. 57 where VG is the gate potential with respect to the source, and VD is the drain potential with respect to the source.
The amplification factor, G, is determined by the
relative contributions of the gate and drain potentials
at the source in the usual way:
A G (Eq. 89) aV D G ID = const.
From Eq. 76,
dV 3 VD x z (Eq. 90) dx 2 L3/2 '
of and a subsequent integration shows that the potential to the a diode varies as the distance into the crystal
3 /2- power: x3/2 (Eq. 91) V = . VD -372-2
the If the gate is allowed to float, it acquires arbi- potential of a diode at the gate depth, LG. If,
trarily, VG is taken to be 1V, then, 3/2 L (Eq. 92) VD = G give a This is the drain potential sufficient to
floating gate a potential of one volt.
The diode equation now holds, so V 2 (Eq. 93) ID = PVD2 = PK(VG+ GD
1 and under these conditions. Substituting VG =
Eq. 92 into Eq. 93 yields 58
2 1 3 (Eq. 94) K [1 + ) / 9 G \ L 3/2]J G1 so \ 3/2] -2 / 3 (Eq. 95) K _ [1 4. t G) GJ and VG+ ) \ VD / 2 J 9 e: A G (Eq. 96) =_ ID g \ 3/2] 2 LG + L1 L G )
for G It is necessary that some estimate be made depends before the characteristics can be calculated; this triode is upon how much of the cross -sectional area of the blocked by the gate. The transconductance
(Eq. 97) gm alDaVG A V = const.
and the drain resistance
0 a VD 98) rD = (Eq. aÌD VG = const.
can now be easily determined. Resulting characteristics resemble those of a
vacuum triode (260).
The remotely similar triode of Ruppel and Smith -like (197), shown in Fig. 13, page 56, showed triode
characteristics. field - Recently Zuleeg has developed the multichannel grown heter- effect transistor (277, 279). Using silicon oepitaxially on sapphire, photoresist processes, 59 diffusions and sequential epitaxial growth, he has fabri- of a cated devices having a control electrode in the form in Fig. 14. p+ -type mesh embedded in the material, as shown field - Using high -resistivity material, the multichannel to the effect transistor becomes a nearly perfect analog vacuum triode (278). punch- Space- charge -limited operation commences upon through of the p regions. Experimentally Zuleeg's analogy to triodes operated in the 3/2 -power range. By
the vacuum triode, and using Eq. 48,
2 53/2 3 ( 3 `;kto 117c1A (Eq. 99) P = 5/2 L G can be shown By the procedure outlined previously it
that 5/2 5/31 ® ¡L r L 2 (Eq. 100) K L1 +GL ) J G G
so that V 3/2 1 2 ( A VG+ GD (Eq. 101) _ 3 J `'lo"c I D 5/2 5/3 3/2 [l+ -1G ( 1 DG \ G G G described by Although experimental results could be was increased, punch - Eq. 101, it was apparent that as VD the gate, effec- through occurred over a greater area of however, were tively decreasing G. The characteristics,
very triode -like in form. 60
Source a11 `"`101311111""`m" "MIld p Gate ÿ2i _nowainliat p+ n- awwIN a Im me am Drain m I Substrate
Figure 14. Zuleeg's analog triode.
Insulator (SiO) Drain (Au)
Figure 15. Weimer's thin -film triode. 61
Thin -Film Dielectric Triodes
The first successful space -charge -limited triode to be fabricated by thin -film techniques used polycrystalline cadmium sulfide as the current -carrying insulator (254), and an insulated gate, as shown in Fig. 15, page 60.
With an insulated gate, both enhancement and deple- tion modes of operation are possible, corresponding to positive and negative gate bias respectively.
Considerable interest was generated by this "TFT," and a large number of similar devices, varying somewhat
in geometry, and using other polycrystalline insulators
as the current -carrying dielectric, have been reported.
The characteristics can be either triode -like or
pentode -like. If the source -drain spacing is relatively
small, then the drain field can penetrate through to the
source, and a relatively low G and triode -like character-
istics result.
If on the other hand, the gate is much closer to al- the source than the drain, it controls the current
most completely, and the drain simply serves as a collec-
tor of the current determined by the gate voltage; so G
is high, and pentode -like characteristics result. the If a semi -insulator or semiconductor is used, con- current is not space -charge -limited, but is still
trolled, as above, by the gate. This mode of operation 62 corresponds to that of a field -effect transistor, and as a result the thin -film transistor and thin -film triode can have identical geometries, and are both designated by the same abbreviation: TFT. It is possible for the pentode - like characteristics of the thin -film transistor to change to the triode -like characteristics of the thin -film dielec- tric triode at higher drain voltages, as the ohmic current saturates and space -charge- limited current commences. The transition from field -effect transistor operation to space - charge- limited operation has been analyzed by De Graaff
(48), Neumark and Rittner (163), and Hofstein (89), and has been observed not only in TFT's (56, 81, 193, 275), but also in multichannel devices (240, 276).
Much of the theory of the field -effect transistor
(38, 39, 41, 91, 92, 102, 173, 200, 215, 216, 249) applies to the thin -film transistor as well (20, 64, 65, 66, 76,
162, 186, 199, 277),
Of particular interest is the work by Geurst (65)
and Rittner and Neumark (162, 186). Although Geurst
analyzed only the insulated -gate field- effect transistor, he included space- charge effects, with the result that his results are sufficiently general so that they can be
applied to the thin -film triode as well, which was done
by Rittner and Neumark.
Geurst's mathematical model is shown in Fig. 16.
The source and drain are assumed to be infinitely 63
Y
tate
h Source Drain s X
L L 2 2 Semiconductor Gate
Figure 16. Geurst °s mathematical modelo
N -type Channel Insulator (Si02) Gate (Al) Drain (Au) Source (Au viuii 11.11- ---11.1115.111Li c1
Substrate (sapphire)
/ / i i
Figure 17. Typical. silicon TFT. 64 thin, and infinite in extent. The drift current is asso- ciated with the charges already present, and since their trajectories must be normal to the electric field, the drift current is restricted to a channel very close to and parallel to the x -axis. The space -charge current is produced by the y- component of the electric field.
The channel can be described by a single equation for the current, which is a function of the x- and y- compon- ents of the field, This equation is used as the boundary condition between the source and drain; at the electrodes,
Ex = 0 is assumed.
By means of particularly elegant mathematical tech- niques, Geurst has solved the Laplace equation throughout
the semiconductor medium subject to these boundary con-
ditions.
By making some simplifying assumptions which apply
to a perfect insulator, Rittner and Neumark obtained the
following result for the current per unit length of a
thin -film triode: 2 r 21 -1-2-12- f ) JI ID = - - óGD \VG-Vo 3/l h2 L (Eq. 102)
Where Go is the amplification factor at cut -off, Vo
is the 'pinch -off potential' defined by eN h Vo = - 2L° (Eq. 103)
where No is the electron concentration present with no 65 applied voltages.
Rittner and Neumark checked their results by means of resistance paper, obtained excellent agreement, and found that VG (Eq. 104) G VD zero potential just touches source
One of the results of the work of Rittner and Neumark is that the amplification factor G is proportional to irL e 2h . Thus, to obtain pentode -like characteristics, a
large ratio L/h is required. A large L, however, de-
creases the gain- bandwidth product by increasing the
transit time.
Many experimental TFT's made use of cadmium sulfide 209, 251). (7, 254, 255, 275), or cadmium selenide (208,
Although the characteristics of triodes using these
materials tend to vary unpredictably with time (71, 184),
experiments are continuing (32, 47, 51, 154, 180, 181,
241, 268, 281) .
Experimental TFT's have also been made using gallium
arsenide (40), tellurium (253, 258), lead sulfide (177), has a lead telluride (223), indium antimonide (59), which
particularly high mobility (101), tin oxide (108), and
indium arsenide (24).
Since the development of the heteroepitaxial process on by which single- crystal silicon films can be deposited 66 sapphire (143), the use of silicon in TFT's has rapidly increased. A typical silicon TFT is shown in Fig. 17, page 63.
The silicon is normally high- resistivity p -type as deposited. If oxidation of the silicon is employed to produce the gate insulator, then an .n -type channel is formed, the current of which can be modulated by the gate voltage. Both enhancement and depletion modes of opera- tion are possible (280).
If the n -type inversion channel is not formed by oxidation, it is sometimes induced by a positive gate bias, and the enhancement mode consists of normal MOS
operation. No channel is present for the depletion mode,
and no current flows until punchthrough of the p- region
occurs, beyond which space- charge -limited operation is
evident. In this case the same device can act as either
a thin -film MOS -type transistor, or a thin -film dielectric
triode.
If the gate does not extend entirely across the p
region, the channel will be incomplete, and the device
can be space- charge -limited triode in both the enhancement
and depletion modes (193, 280). In this case the current
is modulated by means of a narrow gate over the source
junction.
Silicon TFT's have been investigated by a number of
workers (81, 160, 193, 200, 201, 280) and poor saturation 67 has sometimes been evident, which has been attributed to the onset of space- charge -limited operation, which in turn is believed caused by the generally high resistivity of the p region (163).
The Heterojunction Triode
One method of completely blocking the drain voltage from the source region would be to make use of a gate consisting of a two -dimensional conducting sheet placed between the source and drain, and transparent to the mobile charges moving through it.
One such device was proposed by Wright (263), and analyzed by him and by Brojdo (25). Subsequently the device shown in Fig. 18 was fabricated (26).
The source region is made of a wide -band -gap insul- ator. The gate and collector are made of relatively narrow -band material having essentially the same work function. This arrangement allows electrons to travel
from the source to the gate, but prevents holes which provide the conductivity of the gate from reaching the source, as shown in the band diagram of Fig. 19.
The device operates at a relatively low positive
gate voltage and relatively high drain voltage, which
results in a high electron concentration in the source -
gate region and a lower concentration in the gate -drain
region; current through the gate is by diffusion, and 68
Source (evaporated indium)
CdS IL I I o AILIM MIMI ft` i I 11»>> (high Gate resistivity) (p+ silicon)
Si ( 1 ohm -cm) IIII `I O tt `IIII t`t t t a a M a aa ILII a` `a a tat "-'Ï4Drain (nickel plate)
Figure 18. Heterojunction triode of Brojdo et al.
Energy A
Conduction Bands Electrons
Valence Bands
Source - Lam/ Gate -vs Z Drain
Figure 19. Band diagram of heterojunction triode. 69 the drain serves only to collect the current which passes through the gate.
The current to the gate is given by the appropriate diode equation, and, at high drain voltages, a high pro- portion diffuses through without recombination with the holes there (90% in Brojdo's device).
Thus, saturation occurs at higher drain voltages.
The characteristics are pentode -like, and spaced accord- ing to the square -law for a cadmium sulfide source region.
Metal -Gate Dielectric Triodes
Conceptually an analogous p +- í- n + -i -p+ device could be fabricated, using a thin metal film in place of the + n region.
Such devices have been constructed (155, 238); how- was ever, transmission of holes through the metal gates
poor, with a maximum transmission of only 30 %.
A theoretical investigation of this problem was made result that sub- by Crowell and Sze (359 36), with the
stantial improvement is unlikely.
Semiconductor- metal -semiconductor transistors are
described by Geppert (60), Atalla and Soshea (10), and a
number of others (9, 60, 72, 103, 229).
Space -charge -limited metal -gate triodes using an
n +- i- M -i -n+ configuration have been briefly considered
by Moll (155) and Atalla and Soshea (10). 70
The Surface -Channel Dielectric Triode
A dielectric triode can theoretically be fabricated on the surface of an insulating material if all three electrodes are located at the surface. Using a low - mobility insulating material to isolate the gate results in a surface -channel dielectric triode, as shown in
Fig. 20.
Under conditions of enhancement operation electrons are drawn toward the drain and, in the source region, are attracted by the gate as well, with the result that the current flows in a thin layer adjacent to the interface with the gate insulator; hence the "surface channel."
At some point between the source and the drain the poten- tial of the crystal is that of the gate. Near this point the field is zero, the channel ends, and the electrons drift into the bulk of the crystal and move to the drain.
Under the perhaps questionable assumptions that the channel is of uniform thickness, and that the electron concentration does not vary across the channel, an approx- imate analysis can be made.
The charge held by the gate potential is obtained by considering the capacitance between the gate and the channel:
C_ 1 d eNlt el _ _ (Eq. 105) A A dV VC-V h ' 71
Gate
Low - Insulator iii i//111111 Source Drain High - µ, Insulator
Figure 20. Surface -channel dielectric triode.
Y
Gate 1 \\O \ Insulator Gate \ \\\\ \ \ \\ \ \ \\ \ h Channel X Source 1 Dielectric d
Figure 21. Mathematical model for surface -channel dielectric triode. 72
Here C is the capacitance, A the cross -sectional area of the device in the plane of the channel, e the charge of thickness, the permit- the electron, h the insulator c1 tivity of the gate insulator, t the channel thickness,
N1 the concentration of electrons held by the gate volt- age, VG, and V is the potential of any point of the chan- nel. See Fig. 21, page 71.
In addition to the charge held by the gate potential,
a charge due to the drain potential is evident, related to
the potential of the channel by Poisson's equation:
d2V - eN2 (Eq. 106) , dx2 2 where c2 is the permittivity of the crystal, and N2 the
charge due to the drain potential.
If we neglect the diffusion current, the current
density is,by Eq. 5,
(Eq. 107) J = eµ(N1 + N2) dx o
Substitution yields
d2V dV (Eq. 108) J = -1! -V) + `2 [ht dx2
This equation can be integrated to yield
) 2 1 ;Ix `1 V 1 1 dV ¡dV21 0 V ) x= ff - 2 - 2 dx + 2\ dx 2µ ``'2 ht V G
(Eq. 109)
If, as is usually the case, the gate is much closer 73 to the source than is the drain, then
dV dV « and dx dy
2 2 (aX) « - v) dx1 ì ht (VG 2 I x = 0 2
With these assumptions,
2Jx ^' - (Eq. 110) htV (2VG - V) .
Then, taking V = VG at x = d,
2 J _ `"JJL (Eq. 111) 2hdt VG
If this is compared to Child's law for solids
(Eq. 19), it is seen that the effect of the gate is to increase the current by several orders of magnitude.
The length of the channel, d, varies with both the drain voltage and the gate voltage. As long as the drain voltage is much greater than the gate voltage, however, it remains nearly constant, and if the channel thickness is assumed to remain constant, pentode -like characteristics result, spaced according to the square law (266).
Two -Carrier Dielectric Triodes
Space- charge -limited triodes making use of double injection have been experimentally investigated by Yu
(272) and MacJuneau (140), and theoretically by Williams
(256, 257).
The devices of Yu were of germanium and of such 74 large physical dimensions that although space- charge-
limited operation was claimed, such operation in the gen-
erally accepted sense does not appear likely, in the
author's opinion.
MacJuneau was able to obtain negative- resistance
effects by placing a resistance in series with the gate.
Noise in Dielectric Triodes
A triode characteristic, in general, can be expressed
by a relation of the form V m (Eq. 112) I = B(VG + G )
The exponent m depends upon the region of operation.
Then V m-1 Bm ( VG + ) (Eq. 113) gm = = GD V G
Substitution of Eq. 113 into Eq. 112 yields V (Eq. 114) I = mgm(VG(VG + GD )
An equivalent drain voltage is found by taking the
gate voltage to be that when it is floating, as before;
this yields m
K ( VG + ) = VDm GD
when VG is the floating grid potential. K is determined can as a function of gate geometry and position. We
write, then, (Eq. 115)
I K gm VD . 75
The thermal noise of the triode drain current is that of a conductance K gm`
12n = 4kT gmAf (Eq. 116) K
The thermal noise of the triode is greater than that
of a similar diode. The additional component of noise,
called the induced gate noise, is caused by induced bi- polar pulses of current which produce pulses of voltage
across the gate -source impedance, which result in a modu-
lation of the drain current. The pulses are evidently of
short duration due to the high velocity of the electrons,
and the resulting noise increases with frequency. Hsu
et al. (98) show that the induced gate noise is expected
to be
_ 2 1nG = 4kTginA (Eq. 117) f ' where the input conductance at the gate, gin, varies as W2.
This analysis essentially parallels that of the
vacuum triode (228).
Experimental measurements of the noise of a silicon
space -charge -limited analog triode indicated an equiva-
lent noise conductance of gm /2, in substantial agreement
with theoretical predictions (262, 269, 272).
It is evident that low -noise devices must have a low
transconductance; some work in this area has been reported
by Zuleeg and Knoll (280).
However, dielectric triodes do offer relatively 76 low -noise performance (252), for they, in common with all unipolar devices, do not suffer from the recombination noise of bipolar transistors.
Frequency Response of Space -Charge -Limited Triodes
The factors which limit the frequency response of a dielectric triode are the electrode capacitances and the
transit time.
The capacitances are very nearly those of the bulk
materials, and Wright (260) has come to the conclusion
that transit -time effects are most important, in spite of
the fact that dielectric triodes can operate at much
greater transit angles, defined by
0 (Eq. 118) et ftr 9
than can vacuum tubes (133).
Operation in the KMHz range has been predicted
(25, 210); however, to the author's knowledge, experi-
mental devices have not yet borne out this prediction. 77
TRIODE THE PLANAR SURFACE -CHANNEL DIELECTRIC
Choice of Gemoetry
approximate analysis In 1962 Wright (263) developed an planar space- charge- for the characteristics of a proposed -channel dielec- limited triode which he called the surface of coplanar source tric triode. Such a geometry makes use gate electrode above and drain contacts, with an insulated is commonly used the source -drain gap. Such a geometry -effect transistor. in the fabrication of the MOS -type field differs from the The surface -channel dielectric triode the current is drawn from MOS transistor, however, in that below the source con- the space -charge cloud of carriers "channel" in the MOS tact, and that since no conducting it can make use of an sense is required for operation, the charges. This insulating material as the carrier of have a high carrier insulating dielectric must, however, to be obtained. mobility if substantial currents are operation Although the onset of space -charge -limited the "soft- breakdown," has been suggested as one source of to triode -like character- or transition from pentode -like seen in MOS transis- istics at high source -drain voltages device of Wright had tors (163), the proposed dielectric been experimentally in- not, to the author's knowledge, addition to having the vestigated prior to this work. In low noise, and advantages of high -speed response, 78
-charge -limited temperature stability common to all space fabrication. devices, this geometry should greatly simplify
Choice of Dielectric
carrier of the The insulating material serving as the substantial ohmic charges must have a high resistivity if carrier mobility, currents are to be avoided, and a high are to be if substantial space- charge- limited currents are not often obtained. Unfortunately, these properties are relatively found together, and satisfactory dielectrics arsenide, gallium few in number, but they include gallium aluminum phosphide, cadmium sulfide, aluminum arsenide,
phosphide, and intrinsic silicon. using many of Much experimental work has been done have been quite the compounds above, and the results of impurities in variable. The presence of small amounts the introduction of these materials apparently results in effectively the deep energy states called traps, which space- charge region. serve to immobilize the charges of a of traps is suf- Since an extremely low concentration very high purity ficient to reduce the current greatly, sufficiently low material is required, and crystals of results are not yet trap densities to yield reproducible
available. feasible Intrinsic silicon is not yet technologically with resistivity either; however, high -purity silicon 79
available, exceeding several thousand ohm -centimeters is based upon and in light of the magnitude of the industry higher resistiv- the use of silicon, it would appear that
ities should be available in the future. number of The introduction of any one of a large of impurities into silicon results in a concentration remain virtually states sufficiently shallow so that they not serve as unfilled at room temperature, and thus do do result in an traps. However, the unfilled states which results increase in the number of mobile carriers, ohmic current. in a decreased resistivity and an increased it would From an engineering standpoint, then, as possible should appear that silicon as nearly intrinsic
be used as the insulator.
Type of Contact
a reservoir of free In a space -charge -limited device, at the carriers must exist in the dielectric material term, space- charge- source, and from the definition of the cloud of carriers limited, the repelling effect of the from diffusing to must act to inhibit additional carriers of the device. the cloud for all conditions of operation high, carriers are drawn If the current is sufficiently as they are emitted, from the region of the source as fast the current is limited no accumulation of charge develops, is known as by diffusion from the source, and operation 80 temperature -limited. -limited opera- Thus, in order to assure space -charge a copious supply of tion, a very abrupt junction between
carriers and the insulator is required. a supply of There are two ways of providing such a suitable carriers in silicon. The first is to introduce reduce the resis- impurity in sufficient concentration to and the tivity of the silicon to that of a conductor, resistivity silicon second is to make contact to the high-
with a suitable metal. generally used, Of these two, the former is quite have been devel- since deposition and diffusion techniques doped region, oped which allow precise control of the the con- both geometrically and electrically. However, a metal, and ductivity can never be as high as that of region and the the junction between the heavily -doped for a doped undoped region is not as abrupt. Thus, occur at a region, temperature -limited operation may than for a much lower current for a given temperature decided to inves- direct metal contact. It was therefore metal -to- silicon tigate the possibility of using a direct
contact, and to omit the doped region.
Metal Contacts to Silicon
ohmic contacts The most common metals used to form lead, silver, and to silicon are gold, aluminum, nickel, 81 chromium. Of these, aluminum is most commonly used.
Aluminum, however, has a relatively high solubility in saturation silicon, where it forms a p -type region. The concentration of aluminum in silicon at low temperatures has apparently not been measured; however, extrapolation indicates a of the concentration -temperature curve (244) sufficient value of approximately 1018 atoms /cm3. This is of suf- to make a p -type region in any sample of silicon carrier of ficiently high resistivity to be useful as a space -charge -limited current. to both n-type Gold is known to make an ohmic contact is and p -type silicon. Its low- temperature solubility
apparently not known either, but extrapolation of its of 1013 curve indicates a value of the order of magnitude lying close atoms /cm3 (244). Gold introduces two states silicon, together very near the middle of the energy gap in at the and as a result does not form an extrinsic layer and can surface. In addition, gold is easily evaporated, has a high be easily etched as well. It is very stable, it conductivity, and adheres well to silicon. Therefore in space - appears to be suitable for use as a source
charge- limited devices.
Gate Insulator
to isolate the A low- mobility insulator is required silicon between gate electrode. Since it must cover the 82
silicon. the source and drain, it must adhere well to of the sili- Silicon dioxide can be grown by the oxidation insulat- con or deposited by evaporation to yield adherent as the gate ing layers free of pinholes, and was chosen
insulator.
Gate Material
be a stable It is necessary that the gate electrode well to the sili- conducting material, and that it adhere well to con dioxide insulator. Gold does not adhere was silicon dioxide, but aluminum does, and so aluminum
chosen as the gate material.
Drain Electrode
the car- The drain electrode serves only to collect to make the riers, and since it facilitates fabrication it was source and drain contacts at the same time,
decided to use gold as the drain elec trode.
Design Procedure
it is As a first step in the design procedure, spacing which necessary to determine the source -drain to predominate will allow space- charge- limited current current is inversely over the ohmic current. Since ohmic path, by Ohm's proportional to the length of the current for silicon is law, and the space- charge -limited current 83 inversely proportional to the length to the five -halves as pos- power, by Eq. 48, as small a source -drain spacing
sible is desirable from this standpoint. by The width of the spacing is limited from below onset breakdown within or across the insulator, or by the
of quantum -mechanical tunneling (57, 61, 182). by Si02, If the surface of the silicon is protected expected avalanche breakdown within the silicon would be minimum to occur at sufficiently high voltages. The used spacing which is feasible with the fly's -eye camera breakdown in this laboratory is about 12 µm. Avalanche electric field; is a function of both the spacing and the for this however, the minimum field required for breakdown this minimum spacing is above 200 kv /cm (141), and, using 240 volts is value, a breakdown voltage of approximately by obtained by taking the electric field to be given
Eq. 29,
The ratio of space- charge -limited current to ohmic and Eq. 48: current was determined by means of Ohm's law
3/2 ^ 2 Eclv JSCL 3( 3) E4o p (Eq. 119) OHM L 5/2E 37), and approximating By writing Ecl = 2 +o , (Eq.
the electric field by
ti V E = E , (Eq. 29)
we get 84
3/2 z 2 z 5 3/2 z ( '21 (' ) `µo ( 2c zpU JSCL '3'0 3) (Eq. 120) jOHM L3/2 -10 For silicon, E = 1.06 x 10 f /m,
c = 9.2 x 103 m /sec (192),
po = .14 m2 /v -sec for electrons. 0
The silicon available had a resistivity of 35.6 Eq. 120 above ohm -m. Substituting these quantities into yields, for L = 12.5 x 10 -6 m,
JSCL ^' (Eq. 121) 5.4 VZ . OHM
It is seen that the space -charge- limited current the gate. should predominate, even without the effect of of the An annular geometry would eliminate open ends straight source -drain space; it is somewhat easier to make was used in- lines on the artwork, so a square geometry were chosen stead. The dimensions of the source and drain should be large rather arbitrarily, taking care that they made by a enough in area so that contact could be easily shown in micromanipulator. The nominal dimensions are
Fig. 22. effects the In an effort to reduce MOS transistor and gate was designed to cover only the source junction with the gate is half the source -drain space; the triode
shown in Fig. 23.
be .1 p,m; The gate oxide thickness was chosen to 85
All .0o dimensions Drain Source N in micrometers
12.7 140 12.7
318
Figure 22. Source -drain geometry.
Source
6.3 I'm
12.7 im
254 p.m
Figure 23. Gate geometry.
Drain (Au) Source (Au) Gate (Al) Si02
Silicon N
Figure 24. Cross- sectional geometry. 86
from experience of others in this laboratory, thinner
oxides increased the incidence of pinholes, and a thicker
oxide layer would decrease the effectiveness of the gate.
The cross -sectional geometry is shown in Fig. 24, page 85.
The thickness of the three electrodes was to be
determined experimentally to yield a sheet resistance of
approximately .5 ohm per square or less. Since a cur-
rent of only a few milliamperes at most was expected, it was not deemed necessary to decrease the sheet resistance
below this value.
Experimental Procedure
Preliminary to the actual fabrication of the devices,
suitable masks had to be made in order to make use of
standard photoresist processes. Three masks were required:
the first for the source and drain regions, the second for
the gate, and the third for removal of the oxide over the
_source and drain contacts.
The artwork was laid out for a 400 times reduction on
Rubylith mylar film, and reduced 400 times directly by
means of a suitable camera and "fly's -eye" lens.
Photoresist Procedure
In order to etch a pattern in a film, some means must
he provided to protect those portions of the film which
are to be retained from being etched. In this case, the 87 chip, after careful cleaning with acetone, was placed upon a Plat Engineering Company photoresist spinner, and enough filtered AZ -1350 positive -working photoresist applied to cover the surface. The chip was spun at approximately
5000 rpm for 15 seconds, visually inspected, and if the coating appeared uniform, dried for 15 to 20 minutes in a
National Appliance Company vacuum oven at 62 °C.
After drying, the chip was exposed through the appropriate mask for an appropriate length of time as specified in the following step -by -step fabrication proc- ess by means of a Sun Gun ultraviolet lamp. Development required 15 seconds in AZ developer for AZ -1350 positive - working photoresist, and the chip was rinsed in running deionized water, inspected under a microscope, and if visually satisfactory, set on a Thermolyne Type 1900 hot plate at 150 °C for 15 to 20 minutes to promote adhesion.
The development process removes all exposed photo- resist, and the subsequent etching operation removes the appropriate exposed film. After etching, the chip is washed carefully in deionized water, dried with dry nitrogen, reinspected, and the remaining photoresist removed by means of a cotton swab and acetone. A sub- sequent careful cleaning with acetone prepares the chip for the next photoresist operation. 88
Step -by -Step Fabrication Procedure
The wafers as obtained from Dow Corning Corporation were dislocation -free, n -type, with a resistivity of 35.6 ohm -meters, and had a bulk carrier lifetime of 500 micro-
seconds. Each wafer was scribed and broken into four
approximately equal pieces.
1. Five of these chips were mounted on brass blocks with a low melting -point wax soluble in acetone, and the
blocks mounted in the block holder for the Beuhler pol-
isher. The exposed surfaces of the chips were lapped with
#600 grit silicon carbide on a brass plate until they were
parallel. The holder and glass plate were carefully
washed with detergent and tap water, and the chips sub-
sequently lapped with five -pm alumina grit. A second
careful washing with detergent and water followed, and the
chips were subsequently polished with one -µm alumina grit
on a glass plate. The holder and chips were again washed carefully with detergent and water, and subsequently the
chips were polished with .3 [1m alumina grit to a mirror
finish on the Beuhler polisher.
2. The brass blocks were removed from the block
holder, and the chips removed by heating the blocks on a
hot plate until the wax melted. The remaining wax was
removed by soaking the chips in acetone; a subsequent
careful cleaning in acetone followed. 89
3. The chips were oxidized at 1100° for 45 minutes in an atmosphere consisting of oxygen which had been passed through deionized water at 95 °C, which resulted in an oxide layer of approximately .5 pm in thickness.
4. The chips were coated with photoresist as outlined above, and exposed for three seconds through the source - drain mask, and developed. The oxide was etched off by
soaking the wafers in buffered Fir etch at room temperature
for 32 minutes° At this point the source -drain spacing was
left protected by oxide, and the oxide removed from the
source and drain regions. The chips were rinsed in flow-
ing deionized water, and dried in dry nitrogen, and
inspected.
5. Two chips were mounted on a wafer holder, and the
holder placed three inches away from an evaporation dish
containing between 40 and 50 milligrams of commercial fine
gold in a Mikros vacuum evaporator. The bell jar was
placed in position and the wafer holder and chips heated
to 200 °C as the evaporator was evacuated to under 10 -4
torr. The gold was brought up to 1500 °C while the wafer
was shielded from it; then the shield was removed and the
temperature maintained at 1500 °C for ten minutes. The
gold was totally evaporated, leaving a film approximately
1.6 x 10 -7 m. thick, which had been determined by weigh-
ing. The chips were allowed to cool to below 100 °C before
being removed from the evaporator. The sheet resistance 90 was then measured to check that it was below 0.5 ohms per square.
6. The chips were coated with photoresist, and again exposed through the source -drain mask, but with an exposure time of ten seconds. The result of a longer exposure time and careful alignment was the removal upon development of all the photoresist on the gold over the oxide, except for an extremely narrow strip at the edges.
7. The gold was removed from the oxide by soaking the chips in Technistrip Au at room temperature until the gold visually disappeared. The chips were subsequently rinsed in deionized water and dried in a jet of dry nitrogen.
8. After the photoresist was removed, the oxide was removed by soaking the chips for five minutes in buffered
HF etch. The additional etching time allowed the oxide under the gold at the extreme edges of the source and drain to be removed, and resulted in a silicon surface
between source and drain uncontaminated by gold. The
chips were rinsed in deionized water and dried in a jet
of dry nitrogen.
9. The chips were placed in a wafer holder, and
approximately 10 -7 m. of silicon dioxide was evaporated
on the chips in the Varian vacuum evaporator at 300`C.
10. The chips were taken directly to the Mikros
evaporator, and aluminum evaporated to a thickness of 91 approximately .15 jm, after heating the chips to 200 °C in vacuum. The chips were allowed to cool to below 100 °C before being removed and the sheet resistance checked.
il. A coating of photoresist was applied to the chips, and they were exposed for ten seconds through the gate mask, and developed.
12, The aluminum was removed by etching in H3PO4
a etch at 40 °C and removing the resulting bubbles with cotton swab until the aluminum disappeared. The wafer was rinsed in deionized water and dried in dry nitrogen, and the gate inspected. wafers 13. After the photoresist was removed and the cleaned in acetone, they were coated with fresh photo - resist and exposed through the contact mask for ten sec-
onds. Subsequent development allowed etching the oxide
from areas of the source and drain so that contact could well be made to these regions. The oxide did not adhere
to the gold, and care had to be taken not to leave the
chips in the buffered etch for over 45 seconds at room
temperature. The photoresist was carefully removed by
gently rubbing with a cotton swab in acetone. The chips
were subsequently carefully cleaned in acetone. The
devices were now completed and ready for testing. 92
Testing Procedure
Contact to the devices was made by means of a Micro - manipulator Model 1600 KGS 100, and the drain characteris- tics displayed on a Fairchild Curve Tracer Model 6200 B.
A sample of five devices on each of three chips was taken, and the characteristics of each photographed at room temperature. Samples with obvious gate -to- source
short circuits were not included.
From the relatively low currents and high gate volt-
ages observed, it was suspected that operation might not
be space- charge -limited; and so the characteristics of one show sample with a high drain voltage was photographed to
the onset of breakdown, and then heated to 175°C, and the
characteristics photographed at this temperature.
The above sample was connected in the common -source
configuration and a 1000 -ohm load connected to the drain.
a four - Using a positive ten -volt drain supply voltage, was volt positive pulse with a rise -time of 50 nanoseconds
applied to the gate, and the output wave -shape displayed
on a storage oscilloscope, and traced.
Expected Results
An approximate analysis of the expected drain charac- See teristics can be made using Wright's method (266).
Fig. 25. 93
Source Gate Gate h Drain Insulator
'J///N////N//, x .. . '...... :.;: d
Carriers
Figure 25. Mathematical model for silicon surface -channel dielectric triode.
Drain Current (mA) 4V 20 VG = 18 16 14 VG = 3V 12 10 8 VG = 2V 6 4 VG = 1V 2 Drain 0 25 30 35 Voltage 5 10 15 20 (volts)
Figure 26. Expected drain characteristics. 94
The charge held by the gate is obtained by consider- ing, as before, the capacitance between the gate and the layer carrying the electrons:
eN1t C _ 1 lg. __ (Eq. 105). A dV VG-V A G t
The charge held by the drain is obtained by Poisson's equation, Eq. 106; if the gate is extremely close to the source compared to the drain, the field due to the drain in the region of the gate will be very small and the charge held by the drain can be neglected. In this case so this the gate is .1 pm away, and the drain 12.8 pm, and approximation appears valid.
If diffusion current is neglected, as usual, we can write the drain current density, from Eq. 5, as
dV (Eq. 122) `ID - (41N1 dx °
Substituting for N1 from Eq. 105 above yields
El dV = -E! (VG-V) ' `TD ht dx
If the field exceeds 2500 v /cm (198), the mobility will not be constant, and will be given by
41.) 1 = No EEel (Eq. and then
dV (Eq. 123) (VG-V) dx ' °7D o ht E so 2 (Eq. 124) (VG-V) 2 . dDdx = E.o2 2 2 Ec1dV h t 95
We now can integrate over the length of the gate, d; taking the voltage at x = 0 (the source) to be 0 volts yields 2 2 1 2 E1 3 (Eq. 125) U ' JDd = µo Eclh2t2 so 1 to 3/2 JD (Eq. 126) 3d ht G
From this, it is expected that the characteristics would be pentode -like, and spaced according to a three - halves power law.
The drain current density
ID 127) JD = p (Eq. where
(Eq. 128) A = tl , this, 1 being the length of the source -drain gap. From --- Ecl El1.1 o1 3/2 (Eq. 129) ID =:\ 3d h UG
For the devices fabricated, h = 10 -7 m, El =
x 10 -11 f /m, µ = .14 m2 /v -sec, 1 = 6.1 x 10 -4 m, 4.07 0 and d = 6.4 x 10 -6 m. We have
c 3 (Eq. 37) 2 ' Ecl o and since c = 9.2 x 103 m /sec,
Ecl = 9.8 x 104 v /m.
Substituting these values into Eq. 129 yields üG3/2 ID = 2.5 mA. 96
The expected characteristics in the saturation region
are shown in Fig. 26, page 93.
Discussion of Results
Only one chip showed sufficient reproducibility to
warrant a statistical evaluation, and of the other two,
only one was suitable for averaging.
An inspection of Graphs I and II shows that although
saturation of the characteristics occurred, the drain cur-
rent was much lower than that predicted above. In addi-
tion, a substantial current was present with zero gate
bias. The spacing of the curves in the saturation region
indicated that the current depended upon the gate voltage
to a considerably higher power than three -halves.
It is evident that the space- charge -limited component
of current was either greatly reduced, or that operation
was not space -charge limited. Recognizing that the ob-
served currents were an order of magnitude below the
theoretical ones, and that the theoretical ratio of
space -charge -limited current to ohmic current, as given by
Eq. 121 for the source -drain diode was only
SCL = 5.4 V2 (Eq. 121) OHM
it is easy to see that the currents observed were probably
ohmic. as If that is the case, the devices were operating 97
o = Arithmetic mean
Drain I = 95% Confidence Interval Current (mA) 1.0 G=4V
.9
.8
.7
.6 ---_ I VG=3V / .5 /
.4 / OM / / o -- .3 VG=2 V 1 /1// =1V .2 /7 . //- - - - %-OÍ_-- -- VG=OV .1
0 9 10 1 2 3 4 5 6 7 8 Drain Voltage (volts)
of Graph I. Drain characteristics of triodes chip No. 1. 98
o = Arithmetic mean Drain Current (mA) 2.0
1.8 VG=5V ,o 106 ---
.. i i 1.4 / 2'7 / .-- VG=4V // 1.2 / / -Er' i - -0-----V =3V - .- 1.0 - / .-- ' o- / /o/ _ --o--- V G =2V / , _ . ---__--= VG=1V - / .8 /j `/í y VG=OV // ii / . 6 - / /i------.---- / .4-
.2 _
t 1 I 1 0 i 1 I 0 1 2 3 4 5 6 7 8 9 10 Drain Voltage (volts)
Graph II. Drain characteristics of triodes of chip No. 2. 99
MOS transistors, and are not dielectric triodes.
The characteristics of the MOS transistor are known VG2 to follow a law (193), and the observed curves more
closely approximate a square law than a three -halves power
law.
MOS transistors have a conducting channel which is
induced by the gate insulator, the gate voltage, or both.
Saturation occurs because at the end of the channel toward
the drain a depletion region exists which terminates the
channel and prevents the drain voltage from appearing at
the source. The point where the depletion region termi-
nates the channel is called the pinch -off point, and a
high electric field is developed here, which results in
avalanche conditions and breakdown at a much lower drain
voltage than is the case under space- charge- limited con-
ditions.
The pinch -off point moves slowly toward the drain
with increasing drain voltages; if it reaches the drain,
operation becomes space- charge -limited. It may thus be
possible to get space -charge -limited operation by extend-
ing the gate only a very small distance beyond the source.
MOS transistors also have the property that the cur-
rent increases with temperature, because of the increased
number of carriers generated and available for conduction.
This is in contrast to the space -charge -limited triode,
in which the decrease in mobility causes a decrease in l00 current with increase in temperature. However, if the space- charge current is significantly reduced by trapping, the current can increase with temperature due to the in- crease in free carriers having a greater effect than the decrease in mobility.
Finally, MOS transistors can operate in the depletion mode as well as the enhancement mode if a channel is pres- ent with no gate bias.
One device was chosen for a series of tests to deter- mine its mode of operation. was 1. While on the curve tracer, the drain voltage turned up until breakdown began to occur, and the charac- teristics photographed. See Plate I. the 2. The device was heated to 175 °C and again characteristics were photographed. See Plate II.
3. After cooling, and seeing that the characteristics returned to their room -temperature values, the gate polar-
ity was reversed and depletion mode characteristics photographed. See Plate III.
4. The device was connected in the common -source
configuration with a 1K ohm load, and the response to a a drain 50 nanosecond rise -time pulse observed, using
supply of ten volts. The wave -shape was observed on a
storage oscilloscope and traced. See Fig. 27. occurred From Plate I, it can be seen that breakdown of at approximately 20 volts. This is of the order 101
T = 25°C D 1 mA G=4V
mA /fj,i111f'F/A,111inumni V G=3V .5 m/%iaiu VG=2V i VG=1V rr1ÌÉ31+ VG=OV .. VD o 10V 20V
Plate I. High-I.. voltage operation of triode 1 AuB.
ID T = 175°C
-r- VG=4V
VG=3V
f . =2V i jj2/- V i } VG=1V iiiiiî. VG=OV ®11111111:::i4111> e11EME111111i I.t VD o OV`
Plate II. High temperature operation of triode I1 AuB. 102
T-25°C .2 mA IMMMMHNMI 11111111PERINiIEN...cs...... VG=OV /Emsmi VG=-1V ,ï rAi*:r 1 mA VG=-2V IffrM s,1. __ r.. -'1111111011111111 /%//ll111111111111 V =-3V r: C ':-17:rii= VG=-4V
r V --- D 0 4í10V 20V Plate III. Depletion mode characteristics of triode 1 AuB.
ID T = 220°C 5 mA f 4 mA 11111., 3 mA .ME,..,. 1111101111111111211111111111111
2 mA .111111111i 1 mA T=25°C ,I.II. 111111 FAININWELIBirm - VD 0 5V 10V
Plate IV. Characteristics of platelet No. 5 at 25 °C and 220 °C. 103
Drain
Current 2 3 (ma.)
2 C r 5 µsec
1.0
N r 5 µ,sec t N50 nsec r
Time 25 50 (p. sec)
-1,0
-1,5
Figure 27. Response of triode 1 AuB to a 25 11--sec pulse. 104
-drain magnitude expected for an MOS device of this source a space - spacing, but is an order of magnitude too low for charge- limited device.
From Plate II, it is seen that the characteristics current in- are extremely temperature- sensitive, and that creases markedly with temperature. Such a temperature -limited opera- variation is not expected for space -charge
tion unless traps are present. would From Plate III, it is seen that the devices
operate in the depletion mode. Space- charge -limited current directly devices, on the other hand, draw only bulk and these from source to drain under depletion conditions, affected greatly by currents would neither saturate nor be
the gate. concluded that the As a result of these tests it was and not in devices operated in the MOS transistor mode,
the space- charge- limited mode. the devices It remains to determine the reasons why 27, it is seen did not operate as predicted. From Fig. value with a that the current approached a steady -state when the time constant of approximately five microseconds this decay was gate voltage was abruptly changed, and Since the independent of the direction of the change. of 500 microsec- silicon as received had a bulk lifetime were present, and were onds, it was concluded that traps 105 the cause of the failure of the devices to operate in the space -charge- limited modem 106
NATURE OF THE COLD- SILICON CONTACT
Purpose of the Study
triodes In the previous chapter it was seen that the in the using gold contacts on silicon failed to operate was shown space- charge -limited mode. Evidence of trapping component and it is thought that the space -charge -limited that ohmic cur- of current was reduced to such an extent
rents predominated. In this chapter an experimental pre- study of the nature of the gold -silicon contact is that sented, and a comparison with theory made indicating in a layer the presence of gold on silicon indeed results
of traps in the silicon.
Desin of One -Dimensional Devices
it was de- In order to eliminate surface effects, study. In cided not to use a planar geometry for this bulk currents addition, the theory of space -charge -limited in the in insulators is well- developed, and is outlined geo- second chapter of this work for a one -dimensional study of the metry. Such a geometry is suitable for the
gold -silicon contact. contacts on A single -crystal silicon platelet, with were to either side was desired. The lateral dimensions and surface be such that the effect of fringing fields negligible; thus leakage currents at the edges would be 107 it was decided that the lateral dimensions would be at least ten times the thickness.
Some experiments indicated that a silicon film as thin as 10 -5 m. could be fabricated by means of lapping and polishing techniques, and the resulting thin layer broken into platelets. In order to facilitate measuring the dimensions of the platelets it was decided to scribe them and break them along the scribe lines. It was not possible to lap the silicon to a uniform given thickness; however, small platelets of a sufficiently uniform thick- ness that the two surfaces were parallel within the limits of measurement error could be obtained by this method, if the lateral dimensions did not exceed approximately ten mils. A rectangular geometry greatly facilitated the thickness measurements, which could be made under a microscope.
To get nearly parallel surfaces, small lateral dimen- sions were required; to reduce fringe effects, as large lateral dimensions as possible are desirable. A compro- mise is necessary, and it was decided to make the platelets ten mils square, and as thin as possible. Gold was used as the contacts on both sides of the platelets.
Step -by ®Step Fabrication Procedure
The wafers, as obtained from Dow Corning Corporation, were dislocation -free n -type, with a resistivity of 35.6 108 ohm -m. Each wafer was scribed and broken into four chips.
1. Five chips were mounted on brass blocks with a low melting -point wax which was soluble in acetone, and the blocks mounted in the block holder for the Beuhler polish- er. The exposed surfaces were lapped with ##600 grit sili- con carbide on a glass plate until parallel. The holder and glass plate were carefully cleaned with detergent and water, and the chips subsequently lapped with 5 -11m alumina grit. A second careful washing with detergent and water
followed, and the chips were subsequently polished with
1 -11m alumina grit on a glass plate. Again the holder was
carefully washed with detergent and water, and subsequently
the chips were polished with .3 m alumina grit to a mir-
ror finish on the Beuhler polisher.
2. The brass blocks were removed from the block
holder, and the chips removed by heating the blocks on a
hot plate until the wax melted. The remaining wax was
removed by soaking the chips in acetone. A careful
cleaning with acetone followed.
3. The chips were oxidized in wet oxygen at 1100°
for 45 minutes, which resulted in a layer of approximately
.5 11m in thickness.
4. The oxide was removed by soaking the chips in
buffered etch for 3 -1/2 minutes, and the chips rinsed in
deionized water, and dried in a jet of dry nitrogen. Up
to this point the preparation of the surface is the same 109 as that for the source and drain regions of the triodes.
5. Two chips were mounted on a wafer holder, and the holder placed three inches away from an evaporation dish containing between 40 and 50 milligrams of commercial fine gold in a Mikros vacuum evaporator. The bell jar was placed in position, and the wafer holder and chips brought up to 200 °C as the pressure was reduced to below 10 -4 torr.
The gold was brought up to 1500 °C while the wafer was shielded from it; then the shield was removed and the temperature maintained at 1500 °C for ten minutes. The gold was totally evaporated, leaving a film approximately
.16 m thick, which was determined by weighing. The chips were allowed to cool to below 100 °C before being removed
from the evaporator. The sheet resistance was checked to
see that it was below .5 ohms per square.
6. The surface of the chips with the gold on it was
scribed at 254 pm intervals in two perpendicular direc-
tions, leaving a grid of 245 pm by 245 µm square islands
of gold on the surface.
7. A brass block and a chip were heated to 200 °C on
a hot plate and the gold surface of the chip and the
surface of the brass block covered with melted wax soluble
in acetone. The chip was placed gold side down on the
brass block, and since it had previously been coated with
wax, air bubbles were avoided. Excess wax was removed by
means of a paper towel and the block allowed to cool, 110
The remaining excess wax was then removed with acetone.
8. Using 000 silicon carbide grit, the chip was lapped down in thickness until the edges of the chip were removed, and the area of the chip reduced to approximately half of that originally. Careful periodic checking by means of a thickness indicator was necessary to make sure that lapping was taking place evenly. At the conclusion of this operation, the silicon wafer was roughly circular, and approximately one -half inch in diameter.
9. The glass plate and brass block were carefully washed in detergent and water, and the chip was lapped with 5 -11m alumina grit until the area of the silicon was reduced to a roughly circular spot about three -eighths in diameter. At this point the scribe marks could be seen at the edges of the silicon film.
10. The block and the glass plate were again washed very carefully in detergent and water, and subsequently the chip was polished with 1 -µm alumina grit until the surface was as highly polished as possible. This opera- tion reduced the area of the chip only slightly.
11. The block was washed very carefully in detergent and water again, and carefully polished to a mirror finish by hand, using the rotating table of the Beuhler polisher and .3 -11m alumina. At the conclusion of this operation, the chip was reduced to a small spot somewhat over a quarter of an inch in diameter. 111
12. The chip on the block was carefully washed in deionized water, using a cotton swab. It was then mounted in the Mikros evaporator, and gold evaporated, following the procedure outlined in step 5.
13. The chip was removed from the block by soaking the block several hours in acetone. The chip was rinsed several times in acetone.
14. The chip was placed on a piece of bibulous paper. At this stage it had a layer of gold on both sides, one side was scribed into 254 -pm squares, and it had a thickness in the central region of between 12 µm and
25 µm.
15. The chip was laid scribed -side down across a
trough made by folding the paper and opening it again.
By aligning the scribe marks with the trough, and pressing with the point of a pin, the chip was broken into several pieces.
16. Each of the pieces was in turn placed on a
brass block, and heated to 200 °C on a hot plate. A second
block was heated at the same time and a small amount of
the wax used for mounting the chips melted on its surface.
The point of a common pin was slightly blunted, to leave
a nearly flat tip approximately 120 µm in diameter, and
it was pushed perpendicularly through a rectangular
plastic eraser. The pin could now be handled by means of
the eraser. The tip of the pin was touched to the melted 112 wax, excess wax removed by wiping the tip of the pin on a bare place on the brass block, and the chip fragment picked up on the point of the pin by touching it with the waxed tip. The thickness of the fragment could now be checked under a microscope, and regions of constant thickness were located this way. See Fig. 28.
17. A region of a fragment having a nearly uniform thickness was obtained by removing the fragment from the pin by dipping it for a few seconds in acetone held in a watch glass, and breaking the fragment on bibulous paper.
18. The region of uniform thickness was broken into individual platelets on the bibulous paper by laying the fragments scribed -side down and applying pressure with the pin.
19. The individual platelets were placed upon a brass block by holding the partly folded bibulous paper at an angle and scratching the paper near the desired device with a pin. The resulting vibrations would cause the device to tumble down the surface of the paper onto the block. The devices were inspected under a microscope,
and broken or odd -shaped ones rejected. Both sides of
acceptable devices were inspected to check on the condi-
tion of the gold films.
20. An acceptable device was picked up on the tip
of the pin as outlined in step 16, and, using a calibrated
eyepiece, the thickness was measured at four widely 113
Chip Fragment
Pin
Wax
Eraser
Fin
Figure 28. Method of handling small devices. 114 separated places. Devices having noticeably non -uniform thickness were rejected.
21. Acceptable devices were mounted by placing them on a brass plate on a very thin film of Viking LS 232 liquid solder; the thin film was obtained by polishing and cleaning the brass plate, wetting the surface with the solder, and then scraping off the excess with the edge of a microscope slide.
22. The mounted devices were heated to 300 °C for five minutes in an evacuated Mikros evaporator, to simulate the 300 °C heating required for the oxide evaporation of the triodes. The devices were now ready for testing.
Theoretical Considerations
As outlined in the second chapter, the theoretical characteristics for space- charge -limited current in a semi- conductor show three regions. The first region, which oc- curs at low voltages, consists of an ohmic characteristic caused by the finite resistivity of the material. When the voltage is high enough, the space -charge -limited component of current predominates and a square -law characteristic is predicted, up to the critical voltage Ecl, beyond which the three -halves power law takes over.
If deep traps are present, the space- charge -limited component of current is suppressed until the traps are filled, resulting in an extended ohmic region, followed 115 by an abrupt rise to the space -charge -limited character- istic. See Fig. 4.
If shallow traps are present, the space- charge- current is simply reduced by the ratio of trapped to total charge contributing to the space- charge -limited current.
Recent work by Nicolet (164) indicates that traps outside the immediate vicinity of the source have little effect, and, if it is assumed that the concentration of traps in the bulk silicon is negligible, then the observed trapping affects can be attributed to diffusion from the source contact.
From the resistivity and the dimensions, the ohmic current is easily calculated. Since
R = (Eq. 130) A ' and for the silicon used p = 35.6 ohm -m and the area of the platelets was 6.0 x 10 -8 m2,
R = 5.9 x 108 L ohms, (Eq. 131) where L is the platelet thickness. For the three plate- lets tested, L1 = 21.9 p,m, L2 = 19.6 pm, and L5 = 16.3 pm.
From this, the resistance of each of the three platelets can be easily determined to be R1 = 12.9 K, R2 = 11.6 K, and R5 = 9.6 K. From these, in turn, the ohmic charac- teristic can be calculated.
The space- charge -limited component of current below
Ecl, which, for silicon is 9.2 x 104 v /m, is obtained 116 from Child's law for solids:
9 E u,A 2 - 8 V . (Eq. 132) ISD L3
-10 Substituting E = 1.06 x 10 f/m for silicon,
in silicon, and A = p. = .14 m2 /v -sec, for electrons
6.0 x 10 -8 m2 for the platelets yields:
ISD = 1.0 x 10-18V2 (Eq. 133) L3
Substituting for L for each of the three platelets yields:
I = 95 V2 pA ; (Eq. 134) ISD1
132 V2 pA ; (Eq. 135) ISD2 ==
230 V2 pA . (Eq. 136) ISD5 ==
The space- charge -limited component of current above
Ec2 is obtained from Eq. 48:
2 5 3/2, 3 EI-Lo Ecl A 3/2 V . (Eq. 137) ISD L5/2
Substituting for E, µo, Ecl, and A, as before, yields:
x -16 3/2 3.9 10 V (Eq. 138) ISD L5/2 °
Substituting for L for each of the platelets yields:
173 V3/2 pA ; (Eq. 139) ISD1 =
V3/2 pA ; (Eq. 140) ISD2 = 230
350 V3/2 pA . (Eq. 141) ISD5 = 117
Testing Procedure
The static characteristics of three platelets, one from each of three different chips, were taken by means of the Micromanipulator Model 1600 KGS 100 and the Fairchild
Curve Tracer Model 6200 B. These were taken point by point and plotted in Graphs III, IV, and V.
In order to test the temperature sensitivity of the devices, the characteristics of platelet No. 5 was photo- graphed twice by double exposure, once at room tempera- ture and once at 220 °C. See Plate IV, page 102.
Discussion of Results
Inspection of Graphs III, IV, and V shows that the observed currents were much less than those predicted on the basis of a trap -free insulator and an injecting con- tact. as It appears that the ohmic current was reduced to much as two orders of magnitude below its calculated value.
The space- charge- limited current, in the Child's -
law- for- solids region, also has been reduced by nearly
two orders of magnitude below its calculated value. the The 3/2 -power region does not appear. Instead,
experimental curve steepens, and approaches a cube law. come It will now be shown how these properties could 118
e / Area = 6.0x10 -8 m2 / q Thickness = 21.9 µm /
f I / Eq. 139 / / c / 0 d 1000 I / 0 Theoretical / C
0 Eq. 134
/ m 100
ß Ohmic, / / / /4"---'-Z__-- Experimental / l0
/ / /
/ / / /
/ / / / (volts) -+ / Source -Drain Voltage I i 1 I a l l i a 1 i i I i 1 I I I m ,1 1 10 Graph III Characteristics of platelet No. 1. 119
-8 (Area = 6.0x10 m2 r 1 -^ Thickness = 19.6 µm d/ I / 4- -) / - Eq. 140- o / / rJ / / 1000 _d (
_- n /- _w / U q/ _ Eq. 135 0 / cn / / Theoretical /
100 b /
Experimental Ohmic
/ 10
/
1 e i
/ Source-Drain Voltage (volts) --
/ 1 1 1 1 1 1 1 1 1 1 I. 1 1 f 1 1 1 1 1 1 I 1 1 .1 1 10
Graph IV. Characteristics of platelet No. 2. 120 ®8 Area = 6.0x10 Thickness = 16.3 µm Eq. 141 =f
o/
/ wC o% 1000 'j in / Theoretical / - C / 6
iS- / _n /
- Ú / N /
_ p Of a Eq. 136 Experimental 100
Ohmic
7,
101 d/
Y/ /
Source -Drain Voltage (volts) ->
10
Graph V. Characteristics of platelet No. 5. 121 about because of the nature of the gold- silicon contact, under the following assumption: namely, that the gold has diffused into the silicon a distance greater than the dis- tance to the space- charge -cloud in a concentration greater than the concentration of n -type impurities in the mater- ial.
The diffusion coefficient of gold at 300 °C is appar- ently not known; however, it is known to diffuse very rapidly by an interstitial process at temperatures above
500 °C, and presumably this process is active at lower temperatures as well. The solubility of gold at this temperature is apparently not known either, as mentioned earlier, but extrapolation of higher temperature data indicates a value of approximately 10 13 atoms /cm3 (244).
The presence of gold introduces two states in the silicon, at levels .54 and .35 electron -volts below the con- duction band. They can also be thought of as being .55 and .74 electron -volts above the valence band as well.
Thus, these states act as traps for both holes and elec-
trons, and the presence of gold serves to increase the
resistivity of either n- or p -type material (194, p. 166).
It is evident, then, that the gold itself, in the low
concentration apparently existing at low temperatures,
does not contribute a significant number of free carriers,
but instead traps the carriers already present. For a
resistivity of 35.6 ohm -m, the impurity concentration 122 is found from the elementary relation
6 = = epN, (Eq. 142) P to be
N = 1.25 x 1012 atoms /cm3 .
It is seen, then, that a reasonable gold solubility is sufficient to trap virtually all the free carriers in the region. The result of the diffusion of gold, then, is a layer of silicon of virtually intrinsic resistivity next to the gold layer.
When a voltage is applied across the platelet, then, the only ohmic current that flows is that through the high- resistivity layers; and since the resistivity of intrinsic silicon is of the order of 2000 ohm -meters, instead of 35.6, it is seen that the current will be re- duced by nearly two orders of magnitude, if the gold has diffused beyond the space- charge cloud.
The current evidently will be composed of both holes and electrons; however, the electron current will predom- inate because of the higher electron mobility.
It is also evident that an n -i junction exists at each gold contact, as shown in rig. 29.
With the application of a positive drain voltage, the drain junction is reverse biased, and only a satura- tion current would theoretically flow until the n region
is depleted of carriers. This voltage is the punchthrough voltage, and is the voltage at which space- charge- limited 123
Drain (Au)
Figure 29. Diffused gold contacts, 124 current commences. It is given by
L2 ® (Eq. 39) VPT 2E which, for L = 20 microns, is .38 volts.
It is expected, then, that at voltages under .38 volts only small leakage currents would be seen, and this is seen to be the case by inspection of the experimental curves of
Graphs III, IV, and V.
In the square -law region, the current is space - charge- limited. The presence of gold introduces traps, and the ratio of free to total number of electrons is given by
N ET (Eq. 21) 0 = Ñt e -
Both the carrier concentration, N, and the trap concentration, Nt, vary quite rapidly near the gold layer,
and in different ways. For low voltages and low currents, however, it is expected that the space- charge -cloud would
change very little, and that therefore 8 would remain
nearly constant, yielding a square -law characteristic for
a range of voltages above .38 V, as given by
9 2 20) 8 8E41 V . (Eq. ISD -
Experimentally 8 is of the order of .02. at the It is evident that holes can be injected under drain contact as well as electrons at the source current these conditions. At low voltages, the electron 125 is expected to predominate, because of the higher electron mobility, and because the traps for holes caused by the presence of gold are deeper than those for electrons.
At the voltages used, however, because of the rela- tively long bulk lifetime of the silicon, 500 microseconds, negligible recombination can occur. The transit time is given by
4 L2 t _ (Eq. 85) r 3 Ea. J ' for a voltage of 2 V and a thickness of 20 microns, the transit time for holes, with mobility of .05 m2 /volt -sec easily determined to be 5.3 nsec; thus it is evident that negligible recombination can occur.
Thus, holes arrive at the source, and electrons at the drain, and these carriers tend to nullify the space charge and the current increases rapidly. According to
Lampert, double injection space- charge- limited current follows a cube law in the region where appreciable space - charge compensation occurs (113, 119). The experimental curves are seen to approach a cube law for higher voltages.
Although both source and drain were gold on the
triodes, it is not expected that double carrier currents would occur, because the gate did not cover the edge of
the drain, and thus could not modulate any hole current
that might be injected.
Inspection of Plate IV, page 102, shows the marked 126 increase of current that took place with an increase in temperature. The space- charge -limited current was seen to increase almost ten -fold, as the temperature was increased from 25° to 220 °C, due, presumably, to the emptying of traps at elevated temperatures. The current at low volt- ages was seen to increase by an even greater amount, as the the resistance of the "intrinsic" regions dropped, and n -i junctions disappeared.
Conclusions
It has been shown that gold contacts on silicon yield space- charge- limited currents which are much lower than simple theory would predict. charac- It has been demonstrated that the observed teristics can be explained on the basis that the gold at diffuses far enough into the silicon in five minutes the region 300 °C to set up a region of traps in and beyond of the injected space- charge -cloud.
Because of the inhibition of the space- charge- limited current by the traps, planar dielectric triodes using gold source and drain contacts failed to operate in the in the space- charge -limited mode, but operated
typical MOS transistor mode instead. dielec- It is evident that for a successful practical the tric triode using the MOS geometry to be fabricated,
ohmic currents will have to be reduced, and the 127 space- charge -limited currents increased.
Since the MOS channel depends only upon existing car- riers in the silicon for its formation, it seems likely be that a higher resistivity material than silicon may required.
In order to increase the space- charge- limited current,
it will be necessary to use an injecting contact which diffuses negligibly into the insulating material, or to
use a very highly doped n+ region in place of the metal.
It appears that the major difficulty in the fabrica-
tion of planar space- charge -limited devices lies in the
nature of silicon. With the magnitude of intrinsic
resistivity this material has, it is very difficult to
eliminate channels of the MOS type; and until a suitable
method of avoiding MOS operation is found, it appears
that space -charge -limited triodes will remain a laboratory
curiosity. 128
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Measured Characteristics Triodes of chip No. 1. x s 95% C. L. VG VD aD (mA) (mA) (mA) (V) (V) (mA) .24 .27 .054 .20, .34 4 2 021, ,33, .32, .24, .62 .59 .074 .50, .68 4 4 .51, .65, .67, .52, .86 .84 .056 .77, .91 4 6 ,84, e86, .90, .75, .96 .068 .88, 1.04 4 8 ,91, 1.00, 1.03, a87, 1,00
.20, .20 .22 .046 .16 .28 3 2 .19, .20, .30, .40, .44 .41 0049 .35 .47 3 4 .40, .34, .47, .519 .57 ,52 .060 .45 .59 3 6 .52, 043, 058, .55, .62 .58 .059 .51 .65 3 8 .60, .49, .63,
016, ,17 .16 .016 .14 .18 2 2 .15, .13, .19, .26, .27 .25 .040 020 .30 2 4 .22, .20, 030, .30, .33 ,30 .051 .24 .36 2 6 .25, .24, 036, .31, .34 .31 .055 .24 .38 2 8 026, .26, .39, .12, .11 012 .015 .10 .14 1 2 012, .10, .14, .17, .17 017 .025 .14 .20 1 4 a18, .14, .21, .18, .20 .19 .023 .16 .22 1 6 .20, ..16, 022, .18, ,21 .20 .022 .17 .23 1 8 .21, .,17, .22, .10, .10 ,10 .012 .09 .11 0 2 .11, ,09, .12, .14 .15 .019 .13 .17 0 4 .15, .12, .17, .15, .17, .16 .17 0019 .15 .19 0 6 .17, .14, 019, .18, .16 .17 .023 014 ,20 0 8 .18, ,14, .20,
s -F 95% confidence limits = x ± 2.7761¡ n
x = sample mean
s = sample standard deviation n = sample size = 5. 153
Measured Characteristics Triodes of chip No. 2. 95% C.L. VG VD 1D x s (mA) (V) (V) (mA) (mA) .60 057 .115 .43 ,71 5 2 .68, .40, .52, ,66, 1,08 1.06 .158 .86 1.26 5 4 126. .84, .96, 1.04, 1.36 .225 1.08 1,64 5 6 1.60, 1,02, 1.22, 1.46, 1.38 1.60 1,58 .200 1.33 1083 5 8 1.84, 1.34, 1.44, 1.70, .60 ,56 .113 .42 .70 4 2 .66, .40, 050, .66, .90 .138 .73 1.07 4 4 1.04, .70, ,82, 1.00, .90 1,10 .164 .90 1.30 4 6 1026, .86, 1.00, 1.20, 1.16 1.24 .165 1.04 1.44 4 8 1,40, 1.00, 1.14, 1.34, 1.32 .64 .56 .110 .42 .70 3 2 ,62, .40, 048, .64, .84 .81 .109 .67 .95 3 4 .88, .64, .74, .90, 1.02 .93 .139 .76 1.10 3 6 1,04, .72, .86, 1.02, 1.12 1.03 .115 .89 1.17 3 8 1.14, .88, .94, 1.08, .64 .54 ,118 .39 .69 2 2 .60, .38, .46, .64, ,80 .73 .095 .61 .85 2 4 .80, .60, .66, .80, .90 .83 .107 .70 .96 2 6 .90, .66, 078, .90, ,94 .87 0105 .74 1,00 2 8 094, .70, .84, .94, .64 ,53 .126 .37 .69 1 2 .58, .36, .44, 064, ,80 .72 ,103 .59 .85 1 4 .78, ,58, .64, .80, .88, .88 .79 0107 .66 ,92 1 6 .84, .64, .72, .90 .82 .100 .69 .95 1 8 .88, .68, .76, ,90, 058 .52 .124 .35 .67 0 2 .56, .36, .42, .62, .78 .71 ,101 .58 .84 0 4 ,76, ..,58, .64, .78, .84 ,78 .107 .65 091 0 6 .84, .64, .72, .84, .88 .81 ,100 .68 ,94 0 8 .88, ,68, .74, .88, 154
Measured Characteristics. One -Dimensional Devices.
Device ##1. Thickness, 21.9 pm.
Area of gold contact on source 6.0 x 10 -8 m2.
Device #2. Thickness, 19.6 ¡Im.
Area of gold contact on source 6.0 x 10 -8 m2.
Device #5. Thickness, 16.3 pm.
Area of gold contact on source 6.0 x 10 -8 m2.
Device #5 Device #2 Device #1 V (U) I 4,1A) V (U) I (µ`) (U) VSD(V) SD SD SD USD 1SD {4`) m10 .1 .10 .2 .10 .2 .20 .3 .50 1.2 .20 .4 .50 1.5 1.0 3.5 .50 1.4 1.0 4.2 1.95 10 1.0 3.7 1.76 10 2.8 20 2.0 10 2.4 20 4.6 50 3.1 20 3.8 50 6.3 100 5.4 50 5.2 100 8.7 200 7.4 100 7.1 200 12.6 500 10.4 200 10,1 500 16.5 1000 15.3 500 13.0 1000 21 2000 19 1000 16,5 2000 28 5000 24 2000 22 5000 34 10000 29 5000 27,5 10000 34 10000
Noticeable thermal effects were evident at high
currents. This effect was essentially a runaway effect, with current increasing rapidly with voltage, and, at
sufficiently high voltages, a negative- resistance region.