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(12) United States Patent (10) Patent No.: US 6,541,400 B1 Tian Et Al

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(12) United States Patent (10) Patent No.: US 6,541,400 B1 Tian Et Al USOO6541400B1 (12) United States Patent (10) Patent No.: US 6,541,400 B1 Tian et al. (45) Date of Patent: Apr. 1, 2003 (54) PROCESS FOR CVD DEPOSITION OF T. Fukuda et al., Highly Reliable SiOF Film Formation by FLUORINATED SILICON GLASS LAYER ON ECR-CVD Using SiFH, Tech. Digest on 1996 Symp. On SEMCONDUCTOR WAFER VLSI Tech., p. 114-115 (1996). (75) Inventors: Jason L. Tian, Milpitas, CA (US); Shapiro et al., “CVD of Fluorosilicate Glass For ULSI Harald Te Nijenhuis, Fremont, CA Applications,” Elsevier Science S.A., 1995, pp. 503-507. (US) Laxman, "Low e Dielectrics: CVD Fluorinated Silicon Dioxides,” Semiconductor International, vol. 18, No. 5, (73) Assignee: Novellus Systems, Inc., San Jose, CA May 1995, pp. 71–74. (US) Singer, “Low K Dielectrics: The Search Continues,” Semi (*) Notice: Subject to any disclaimer, the term of this conductor International, vol. 19, No. 3, May 1996, pp. patent is extended or adjusted under 35 88-96. U.S.C. 154(b) by 0 days. T. Tamura et al., Ext. Abstracts 43th Spring Meeting; The Japan Soc. Appl. Phys. And Related Soc., p. 658 (1996) (21) Appl. No.: 09/501,347 (without English Translation). (22) Filed: Feb. 9, 2000 T. Fukuda et al., Highly Reliable SiOF Film Formation by (51) Int. Cl." ....................... H01L 21/31; H01L 21/469; ECR-CVD. Using SiFH, Tech. Digest 1996 symp. On VLSI H05H 1/02; H05H 1/24 Tech., pp. 114-115 (1996). (52) U.S. Cl. ....................... 438/784; 438/788; 427/574; 427/579 * cited by examiner (58) Field of Search ................................. 438/783, 784, 438/787, 788; 427/574, 578,579 Primary Examiner Olik Chaudhuri ASSistant Examiner Erik Kielin (56) References Cited (74) Attorney, Agent, or Firm-Skjerven Morrill LLP U.S. PATENT DOCUMENTS (57) ABSTRACT 5,563,105 A 10/1996 Dobuzinsky et al. ....... 437/240 An improved process for depositing a robust fluorosilicate 5,571,576 A 11/1996 Qian et al. .................. 427/574 5,827,785 A 10/1998 Bhan et al. ................. 438/784 glass film on a Substrate in a chamber includes maintaining 5,880,018 A * 3/1999 Boeck et al. ..... ... 438/619 a total pressure in the chamber of less than about 1.7 torr, 6,001,728 A * 12/1999 Bhan et al. .......... ... 438/624 introducing vapor phase chemicals Such as N, SiFi, SiH, 6,057.250 A * 5/2000 Kirchhoff et al. ........... 438/784 and N2O into the chamber, and reacting the vapor-phase 6,077,764 A * 6/2000 Sugiarto et al. ..... ... 438/597 chemicals with Sufficiently Supplied energy to deposit a thin 6,165,915 A * 12/2000 Jang ........................... 438/787 film layer of the fluorosilicate glass on the Substrate. Advantageously, the deposited fluorosilicate glass films are FOREIGN PATENT DOCUMENTS chemically, mechanically, and thermally stable without JP 7-2545.92 * 10/1995 additional processing. Also advantageously, the films are deposited uniformly at rates greater than about 5000 Ang OTHER PUBLICATIONS Stroms per minute with dielectric constants of about 3.4 to T. Fukuda et al., Highly Reliable SiOF Film Formation by about 3.9. ECR-CVD Using SiFH, Tech. Digest 1996 symp. On VLSI Tech., p. 114-115 (1996). 22 Claims, 6 Drawing Sheets 28 GAS SOURCE BARRIER LAYER TCHSTOP- oocood LAYER 120 --- 1.5-112 18 r 122 124 PUMP ke Blistering 99 -- %FTIR) 78 59 - 39 18 I is tes 1s 8 2. 2. 2. 2.1 2-4 2.7 Pressure (tort: U.S. Patent Apr. 1, 2003 Sheet 1 of 6 US 6,541,400 B1 128 GAS A1 1 OO BARRIER LAYER OOOOOOOOO ETCH STOP LAYER 12O 1177,777 134 HEATER FIG. U.S. Patent Apr. 1, 2003 Sheet 2 of 6 US 6,541,400 B1 R 1300.00 1250.OO L 1200.00 1.43853 1.4345914459 - 1150.00 11 OO.OO 1.50 1.65 18O 1.95 2. O FIG 2 Pressure Si-F% 13OO.OO 1250.00 - LL 1200.00 - 1150.00 144083 11 OO.OO 1.50 1.65 18O 1.95 2.1 O FIG O 3 PreSSure U.S. Patent Apr. 1, 2003 Sheet 3 of 6 US 6,541,400 B1 Dep. Rate 1300.00 1250.OO 1200.00 5227.58 4967.42 - 1150.00 1 100.00 1.50 1.65 18O 1.95 2.1 O FIG 4 Pressure 900.OO 750.00 600.00 CO 450.00 3OO.OO 1.50 1.65 18O 1.95 2.1 O FI G 5 Pressure U.S. Patent Apr. 1, 2003 Sheet 4 of 6 US 6,541,400 B1 900.00 750.00 600.00 cf) 450.00 300.00 150 1.65 1.80 1.95 2.1 O FI G 6 Pressure Dep. Rate (A/min) 90O.OO 750.00 6OO.OO 5227.58 4967.42 f5 45O.OO 3OO.OO 1.50 1.65 1.80 1.95 2.10 FIG. 7 Pressure U.S. Patent Apr. 1, 2003 Sheet S of 6 US 6,541,400 B1 11.0 1,448 10.0 1446 1.444 9.0 1.442 8.O 1.44 2s 7.O 1.438g CC 1.436 is 6.O s 1.434 5.O () 1.432 At. F 4.O 1.43 3.O 1.428 2OO 4OO 6OO 800 1000 1200 1400 1600 FIG 8 SiF4FLow 1448 3.8 1.446 1.444 3.75 x 1.442 3.7 c2 1.44 : g 1.438 3.658 5 9. is 1.436 5 if 1.434 3.6 O 1.432 3.55 1.43 1428 3.5 2OO 4OO 600 800 OOO 12OO 1400 1600 SiF4FLow (scCm) FIG. 9 U.S. Patent Apr. 1, 2003 Sheet 6 of 6 US 6,541,400 B1 99 Pressure (torr) FIG. O US 6,541,400 B1 1 2 PROCESS FOR CVD DEPOSITION OF structure of some FSG films result in the films having a FLUORINATED SILICON GLASS LAYER ON tendency to absorb water. The absorbed water increases the SEMCONDUCTOR WAFER dielectric constant of the film and reacts with fluorine to form corrosive HF. The HF and absorbed water typically outgas during thermal processes, Such as anneal processes, BACKGROUND and degrade the adhesion properties of the FSG film. For example, outgassing HF and water can cause blister and 1. Field of the Invention bubble formation in Subsequently deposited metal or dielec The present invention is related to methods of forming tric layers. dielectrics of the type used in semiconductor VLSI Some conventionally deposited unstable FSG films can be applications, and more particularly to improved processes Stabilized by annealing or by other post-deposition treat for forming low-dielectric constant fluorinated Silicon glass ments. However, Such methods require additional process layerS having improved characteristics. Steps, equipment, and expense. 2. Description of the Related Art For these reasons, what is needed is an improved process Capacitive coupling between metal features in an inte 15 for depositing a robust FSG film on a substrate such that the grated circuit increases in inverse proportion to the distance FSG film exhibits, for example, improved chemical, between the metal features. AS the typical metal feature size mechanical, and thermal Stability without additional pro in integrated circuits decreases with each new generation of cessing. circuits, the Spacing between metal features in the circuits also decreases. Consequently, as integrated circuits increase SUMMARY in complexity and shrink in size, capacitive coupling An improved proceSS for depositing a robust fluorosilicate between metal features increases in magnitude. The glass film on a Substrate in a chamber includes maintaining resistance-capacitance (RC) signal delays associated with a total pressure in the chamber of less than about 1.7 torr, capacitive coupling Similarly grow in magnitude, and introducing vapor phase chemicals into the chamber, and degrade the performance of the circuits. 25 reacting the vapor-phase chemicals with Sufficiently Sup Since capacitance is directly proportional to the dielectric plied energy to deposit a thin film layer of the fluorosilicate constant (k), RC problems in integrated circuits can be glass on the Substrate. In one embodiment, the total preSSure reduced if low dielectric-constant materials are used as the in the chamber is about 0.5 torr to about 1.7 torr. insulating material. Silicon dioxide (SiO2) has long been In one embodiment, the vapor-phase chemicals are N, used as a dielectric for integrated circuits because of its SiFi, SiH, and N.O introduced into the chamber at flow excellent mechanical and thermal Stability and relatively rates, in Standard cubic centimeters per minute (Scem), with good dielectric properties (k~4.0). However, industry now a ratio of about 1.7:0.5:1:7 to about 17:7:1:70. The energy is requires materials with dielectric constants less than that of supplied as RF energy of frequency about 13.56 MHz at a Silicon dioxide for use as intermetal and interlevel dielectrics power density of about 0.4W/cm to about 5 W/cm, and as in modern integrated circuits. 35 RF energy of frequency of about 250 kHz and power density Fluorosilicate glass (FSG) has been identified as a very about 0.2 W/cm° to about 3 W/cm’. promising low dielectric constant material for use in inte Advantageously, fluorosilicate glass films deposited with grated circuits. Incorporation of fluorine, a very electrone the improved process are chemically, mechanically, and gative atom, into a Silicon oxide layer decreases the polar thermally stable without additional processing. Also izability and hence the dielectric constant of the layer. 40 advantageously, the films are deposited uniformly at rates Further increasing the fluorine content of the Silicon oxide greater than about 5000 Angstroms per minute with dielec layer generally further decreases the dielectric constant.
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