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Understanding IBM RS/6000 Performance and Sizing February 1997

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Understanding IBM RS/6000 Performance and Sizing February 1997 SG24-4810-00 Understanding IBM RS/6000 Performance and Sizing February 1997 IBML International Technical Support Organization SG24-4810-00 Understanding IBM RS/6000 Performance and Sizing February 1997 Take Note! Before using this information and the product it supports, be sure to read the general information in Appendix A, “Special Notices” on page 297. First Edition (February 1997) This edition applies to IBM RS/6000 for use with the AIX Operating System Version 4. Comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JN9B Building 045 Internal Zip 2834 11400 Burnet Road Austin, Texas 78758-3493 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. Copyright International Business Machines Corporation 1997. All rights reserved. Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Contents Figures . ix Tables . xiii Preface . xv How This Redbook Is Organized ........................... xv The Team That Wrote This Redbook ........................ xvi Comments Welcome . xvii Chapter 1. Introduction . 1 1.1 Meaningless Indicators of Performance .................... 2 1.2 Meaningful Indicators of Performance ..................... 4 Chapter 2. Background . 5 2.1 Performance of Processors ............................ 5 2.2 Hardware Architecture ............................... 5 2.2.1 RISC/CISC Concepts . 6 2.2.2 Superscalar Architecture: Pipeline & Parallelism ............ 7 2.2.3 Memory Management . 8 2.2.4 MP Implementation Specifics ........................ 16 2.3 The Kernel . 18 2.3.1 Responsibilities . 18 2.3.2 AIX Characteristics . 18 2.3.3 Context/Thread Switches . 20 2.4 64-bit Architecture . 20 2.4.1 Reasons for the 64-bit Architecture .................... 20 2.4.2 Types of Addresses .............................. 21 2.4.3 Understanding 64-bit Architecture ..................... 21 2.4.4 Understanding 64-bit Machines ....................... 21 2.4.5 Addressability . 21 2.4.6 CPU, System and I/O Bus .......................... 22 2.4.7 Advantages of 64-bit Architecture ..................... 22 2.4.8 Performance of 64-bit Architecture ..................... 24 2.4.9 Software Considerations for 64-bit Architecture ............. 24 2.4.10 AIX and 64-bit Implementations of PowerPCs .............. 25 2.4.11 Conclusion . 26 2.5 References . 26 Chapter 3. IBM RS/6000 Architectures ....................... 29 3.1 POWER . 29 3.1.1 Functional Units . 30 3.1.2 Storage Control . 31 3.1.3 Instruction Set . 33 3.1.4 Performance .................................. 33 3.2 RSC (RISC Single Chip) .............................. 34 3.3 POWER2 Multichip . 34 3.3.1 POWER2 Super Chip ............................. 36 3.4 PowerPC . 37 3.4.1 PowerPC 601 . 38 3.4.2 PowerPC 603 and 603e ............................ 41 3.4.3 PowerPC 604 and 604e ............................ 42 Copyright IBM Corp. 1997 iii 3.4.4 PowerPC 620 . 43 3.5 Conclusion . 46 3.6 References . 46 Chapter 4. Hardware . 47 4.1 Processor . 47 4.1.1 Cycles Per Instruction ............................ 47 4.2 Memory . 48 4.2.1 Memory Hierarchy . 48 4.2.2 Memory Cycles . 49 4.2.3 Scientific, Commercial and System Environment ............ 50 4.2.4 Uniprocessor vs. Symmetric Multiprocessor Memory Cycles ..... 51 4.2.5 Miss Rate Penalty ............................... 52 4.2.6 L1 Cache Size ................................. 54 4.2.7 Effect of L2 Cache ............................... 55 4.2.8 L2 Latency vs. Processor Speed ...................... 56 4.2.9 Effect of Processor Speed .......................... 57 4.2.10 Memory/Cache Effects . 59 4.3 Storage . 60 4.3.1 Performance View . 60 4.3.2 SCSI Technology . 65 4.3.3 Serial Link Storage .............................. 67 4.3.4 Serial Storage Architecture (SSA) ..................... 68 4.3.5 Fiber Channel Arbitrated Loop (FC-AL) .................. 69 4.3.6 RAID Technology . 69 4.3.7 Adapters for Storage Devices ........................ 71 4.3.8 Storage Products for the RS/6000 ..................... 72 4.3.9 AIX Logical Volume Manager Performance and Sizing Concepts .. 78 4.3.10 Considerations When Configuring Storage ............... 81 4.3.11 References . 85 4.4 Asynchronous Communication Adapters .................... 86 4.4.1 Terms Used in Serial Communication ................... 86 4.4.2 Communication Methods ........................... 87 4.4.3 Flow Control . 87 4.4.4 IBM RS/6000 Asynchronous Hardware .................. 88 4.4.5 Asynchronous Adapter Considerations .................. 89 4.4.6 Conclusion . 90 4.4.7 References . 90 4.5 LAN / WAN Adapters ................................ 90 4.5.1 Ethernet . 90 4.5.2 Token Ring . 92 4.5.3 FDDI . 93 4.5.4 ATM . 94 4.5.5 X.25 . 95 4.5.6 ISDN . 96 4.5.7 HIPPI . 97 4.5.8 Fiber Channel . 97 4.5.9 BMPX . 98 4.5.10 ESCON . 98 4.5.11 References . 99 4.6 Graphics Adapters . 99 4.6.1 Entry Graphics Accelerators ........................ 100 4.6.2 2D Graphics Accelerators and Entry 3D (Class I) ........... 101 4.6.3 Mid-Range 3D Graphics Accelerators (Class II) ............ 101 4.6.4 High-End 3D Graphics Accelerators (Class III) ............. 101 iv Understanding IBM RS/6000 Performance and Sizing 4.6.5 Graphics API Enhancement on SMP Systems ............. 102 4.6.6 Understanding Graphics Performance .................. 103 4.6.7 Graphics Accelerator Hardware Sizing ................. 104 4.6.8 Conclusion . 106 4.6.9 References . 106 Chapter 5. IBM RS/6000 Products ......................... 107 5.1 Symmetric Multiprocessor . 107 5.1.1 Hardware . 107 5.1.2 Software . 110 5.1.3 Scaling . 116 5.2 Using an SMP ................................... 120 5.2.1 Parallelizing an Application ........................ 120 5.2.2 Amdahl’s Law . 121 5.2.3 SMP and Database ............................. 121 5.3 Parallel Architecture . 123 5.3.1 IBM Scalable POWERparallel (SP) System ............... 123 5.3.2 SP Switch Performance .......................... 124 5.3.3 Virtual Shared Disk (VSD) ......................... 128 5.3.4 Sizing and Configuring a Control Workstation ............. 128 5.3.5 Sizing and Configuring an SP System .................. 129 5.3.6 Server Consolidation (Serial Applications) ............... 133 5.3.7 Parallel Sizing Factors ........................... 134 5.3.8 Decision Support System (DSS) ..................... 139 5.3.9 On-Line Transaction Processing (OLTP) ................ 140 5.3.10 Scientific Applications . 142 5.3.11 Conclusion . 142 5.3.12 References . 142 5.4 SP and SMP Selection .............................. 143 5.4.1 SMP and SP Considerations ....................... 143 Chapter 6. Benchmarks . 149 6.1 System Performance Evaluation Corporation (SPEC) ........... 149 6.1.1 SPECint92 and SPECfp92 .......................... 150 6.1.2 SPECint95 and SPECfp95 .......................... 151 6.1.3 SPECweb96 . 154 6.1.4 SPEC SFS . 155 6.1.5 The SPEC System Development Multitasking (SDM) Workload ... 158 6.1.6 References . 158 6.2 Graphics Performance Characterization (GPC) Committee ........ 159 6.2.1 PLBwire93 and PLBsurf93 ......................... 159 6.2.2 Viewperf . 161 6.2.3 X11perf and Xmark93 ............................ 163 6.2.4 References . 163 6.3 Transaction-Oriented Benchmarks . 164 6.3.1 TPC-A ..................................... 164 6.3.2 TPC-B ..................................... 164 6.3.3 TPC-C ..................................... 165 6.3.4 TPC-D ..................................... 166 6.3.5 References . 170 6.4 OLTP . 170 6.5 LINPACK . 170 6.5.1 Metrics and How to Read Them ..................... 171 6.5.2 Usage ..................................... 171 6.5.3 Conclusion . 171 Contents v 6.5.4 Reference . 172 6.6 The AIM Benchmark Suites ........................... 172 6.6.1 AIM Multiuser Benchmark Suite-VII ................... 172 6.6.2 AIM Workstation Benchmark Suite-VI .................. 172 6.6.3 References . ..
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