DOCSLIB.ORG

Understanding IBM Pseries Performance and Sizing

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Understanding IBM Pseries Performance and Sizing Understanding IBM pSeries Performance and Sizing Comprehend IBM RS/6000 and IBM ^ pSeries hardware architectures Get an overview of current industry benchmarks Understand how to size your system Nigel Trickett Tatsuhiko Nakagawa Ravi Mani Diana Gfroerer ibm.com/redbooks SG24-4810-01 International Technical Support Organization Understanding IBM ^ pSeries Performance and Sizing February 2001 Take Note! Before using this information and the product it supports, be sure to read the general information in Appendix A, “Special notices” on page 377. Second Edition (February 2001) This edition applies to IBM RS/6000 and IBM ^ pSeries as of December 2000, and Version 4.3.3 of the AIX operating system. Comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JN9B Building 003 Internal Zip 2834 11400 Burnet Road Austin, Texas 78758-3493 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 1997, 2001. All rights reserved. Note to U.S Government Users – Documentation related to restricted rights – Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Contents Preface. .ix The team that wrote this redbook. .ix Comments welcome. .xi Chapter 1. Introduction . 1 Chapter 2. Background . 5 2.1 Performance of processors . 5 2.2 Hardware architectures . 6 2.2.1 RISC/CISC concepts . 6 2.2.2 Superscalar architecture: pipeline and parallelism . 7 2.2.3 Memory management . 11 2.2.4 PCI. 19 2.2.5 MP implementation specifics . 21 2.2.6 NUMA. 24 2.2.7 Logical partitioning (LPAR) . 26 2.3 AIX kernel . 28 2.3.1 Description . 28 2.3.2 Executable file formats . 29 2.3.3 Kernel and user mode . 30 2.3.4 I/O . 30 2.3.5 Context/Thread switches . 31 2.3.6 Virtual address space . 31 2.3.7 Demand paging . 32 2.3.8 Kernel scalability enhancements . 32 2.3.9 References. 32 2.4 64-bit architecture . 33 2.4.1 Concepts . 33 2.4.2 Addressability. 34 2.4.3 Advantages of 64-bit architecture . 35 2.4.4 Performance of 64-bit architecture . 36 2.4.5 Software considerations for 64-bit architecture . 37 2.4.6 64-bit operating system capabilities . 37 Chapter 3. IBM RS/6000 and IBM pSeries architectures . 39 3.1 POWER2 Super Chip . 39 3.2 POWER3 . 41 3.2.1 POWER3 execution core . 43 3.2.2 Memory access section . 44 3.2.3 POWER 3 II chip . 47 3.3 PowerPC . 50 © Copyright IBM Corp. 2001 iii 3.3.1 PowerPC 604 and 604e . 50 3.3.2 Differences between 604 and 604e processors . 51 3.3.3 RS64 II processor. 52 3.3.4 RS64 III processor . 60 3.3.5 POWER4 . 72 Chapter 4. IBM RS/6000 and IBM pSeries products . 77 4.1 Symmetrical Multiprocessor (SMP). 77 4.1.1 Migrating to SMP . 77 4.1.2 Symmetrical Multiprocessor (SMP) concepts and architecture . 78 4.1.3 Software . 86 4.1.4 Scaling . 93 4.1.5 References. 98 4.2 Scalable POWERparallel (SP) . 98 4.2.1 Parallel architecture . 98 4.2.2 IBM SP (Scalable POWERparallel) system. 100 4.2.3 SP switch performance. 104 4.2.4 Shared disk components of Parallel System Support Programs 110 4.2.5 Sizing and configuring a control workstation . 113 4.2.6 Sizing and configuring an SP system . 115 4.2.7 Resources . 131 Chapter 5. Hardware. 133 5.1 Processors . 133 5.2 Memory . 134 5.2.1 Cache memory . 134 5.2.2 Addressing considerations . 135 5.2.3 Memory cycles . 140 5.2.4 Uniprocessor vs. symmetric multiprocessor memory cycles . 141 5.2.5 Miss rate penalty . 143 5.2.6 Effect of L2 cache. 144 5.2.7 Effect of processor speed . 146 5.3 Storage . 148 5.3.1 Performance view. 149 5.3.2 Levels of storage . 150 5.3.3 How an I/O request is processed . 151 5.3.4 How a disk works . 153 5.3.5 SCSI technology. 155 5.3.6 Serial Storage Architecture (SSA) . 160 5.3.7 RAID levels overview and performance considerations. 162 5.3.8 IBM Enterprise Storage Server (ESS). 167 5.3.9 Logical Volume Manager (LVM) concepts. 168 5.3.10 Raw logical volumes versus Journaled File Systems (JFS). 174 iv RS/6000 and IBM ^ pSeries Performance and Sizing 5.4 Asynchronous Communication adapters. 176 5.4.1 Terms used in serial communication. 176 5.4.2 Flow control . 178 5.4.3 Asynchronous adapter overview . 179 5.4.4 Evaluating asynchronous communications options . 179 5.4.5 Product selection considerations . 183 5.4.6 Topology considerations. 187 5.5 LAN/WAN Adapters . 187 5.5.1 Ethernet . 187 5.5.2 Token Ring. 190 5.5.3 Fibre Channel. 191 5.5.4 ATM . 192 5.5.5 General network tuning recommendations . 194 5.6 Graphics accelerators . 196 5.6.1 Currently available RS/6000 graphics accelerators. 199 5.6.2 IBM’s graphics workstations . 204 5.6.3 Graphics APIs - The “softer side.
Load more

Recommended publications
  • IBM Systems Group
    IBM Systems Group IBM ~ p5 520 IBM ~ p5 550 Milan Patel Offering Manager, pSeries Entry Servers v 3.04 IBM Confidential © 2004 IBM Corporation This presentation is intended for the education of IBM and Business Partner sales personnel. It should not be distributed to clients. IBM Systems Group Agenda ❧Learning Objectives ❧Offering Description – p5-520 1.65GHz (2 way) – p5-550 1.65GHz (2-4way) ❧Selling Scenarios ❧Pricing and Positioning – The Value Paks New – Portfolio Positioning – Market Positioning – Retention Positioning ❧Target Sectors and Applications ❧Speeds and Feeds © 2004 IBM Corporation page 2 Template Version 3.04 IBM Systems Group Field Skills & Education IBM Confidential IBM Systems Group Learning Objectives At the conclusion of this material, you should be able to: ❧ Articulate the key messages and value-prop of ~ p5-520, ~ p5-550 ❧ Identify the opportunities and target sectors for the ~ p5-520, ~ p5-550 ❧ Articulate the enhancements and benefits of the ~ p5-520, ~ p5-550 ❧ Explain how Advanced POWER™ virtualization can help to reduce costs and simplify customer environments © 2004 IBM Corporation page 3 Template Version 3.04 IBM Systems Group Field Skills & Education IBM Confidential IBM Systems Group Offerings Overview p5-520 and p5-550 © 2004 IBM Corporation page 4 Template Version 3.04 IBM Systems Group Field Skills & Education IBM Confidential IBM Systems Group IBM ~ p5 520 What is p5-520? ❧ p5-520 is a 2 way entry server that complements the p5-550 in the entry space ❧ p5-520 delivers - – Outstanding performance –
    [Show full text]
  • Understanding IBM RS/6000 Performance and Sizing February 1997
    SG24-4810-00 Understanding IBM RS/6000 Performance and Sizing February 1997 IBML International Technical Support Organization SG24-4810-00 Understanding IBM RS/6000 Performance and Sizing February 1997 Take Note! Before using this information and the product it supports, be sure to read the general information in Appendix A, “Special Notices” on page 297. First Edition (February 1997) This edition applies to IBM RS/6000 for use with the AIX Operating System Version 4. Comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JN9B Building 045 Internal Zip 2834 11400 Burnet Road Austin, Texas 78758-3493 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. Copyright International Business Machines Corporation 1997. All rights reserved. Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Contents Figures . ix Tables . xiii Preface . xv How This Redbook Is Organized ........................... xv The Team That Wrote This Redbook ........................ xvi Comments Welcome . xvii Chapter 1. Introduction . 1 1.1 Meaningless Indicators of Performance .................... 2 1.2 Meaningful Indicators of Performance ..................... 4 Chapter 2. Background . 5 2.1 Performance of Processors ............................ 5 2.2 Hardware Architecture ............................... 5 2.2.1 RISC/CISC Concepts . 6 2.2.2 Superscalar Architecture: Pipeline & Parallelism ............ 7 2.2.3 Memory Management . 8 2.2.4 MP Implementation Specifics ........................ 16 2.3 The Kernel . 18 2.3.1 Responsibilities .
    [Show full text]
  • Eserver P5 Capacity on Demand
    IBM Systems Group eServer p5 Capacity On Demand Dave Nypaver Marketing Manager, On Demand and Software © 2004 IBM Corporation This presentation is intended for the education of IBM and Business Partner sales personnel. It should not be distributed to customers. IBM Systems Group Agenda Topics to be covered are: – Why Capacity on Demand is Value to Clients – Differences in Capacity on Demand between eServer p5 and pSeries – eServer p5 Capacity on Demand offering details © 2004 IBM Corporation page 2 IBM Systems Group Field Skills & Education IBM Systems Group IBM eServer pSeries and p5 Capacity on Demand After completed this topic, you should be able to: ❧ Explain why On Demand features are important to your clients ❧ Highlight eServer p5 Capacity on Demand abilities ❧ Describe differences between pSeries and eServer p5 on demand features page 3 © 2004 IBM Corporation page 3 IBM Systems Group Field Skills & Education IBM Systems Group Why is On Demand Important to you? ❧ Server capacity you need, when you need it ❧ Address your non-disruptive growth needs ❧ Build in flexibility to address spikes in demand ❧ Increased configuration flexibility ❧ Increased reliablity ❧ Deploy new services quickly ❧ Gain additional workload throughput and automated systems performance leveling Customer Capacity Growth Defer 70-80% of Temporary Capacity payment for on Demand inactive capacity… Permanent Capacity Upgrade Planned on Demand (CUoD) Actual *Capacity on Demand Features available on selected models of eServer p5 © 2004 IBM Corporation page 4 IBM
    [Show full text]
  • The Interactive Performance of SLIM: a Stateless, Thin-Client Architecture ✽ ✽ ✝ Brian K
    17th ACM Symposium on Operating Systems Principles (SOSP’99) Published as Operating Systems Review, 34(5):32–47, December 1999 The interactive performance of SLIM: a stateless, thin-client architecture ✽ ✽ ✝ Brian K. Schmidt , Monica S. Lam , J. Duane Northcutt ✽ Computer Science Department, Stanford University {bks, lam}@cs.stanford.edu ✝ Sun Microsystems Laboratories [email protected] Abstract 1 Introduction Taking the concept of thin clients to the limit, this paper Since the mid 1980’s, the computing environments of proposes that desktop machines should just be simple, many institutions have moved from large mainframe, stateless I/O devices (display, keyboard, mouse, etc.) that time-sharing systems to distributed networks of desktop access a shared pool of computational resources over a machines. This trend was motivated by the need to provide dedicated interconnection fabric — much in the same way everyone with a bit-mapped display, and it was made as a building’s telephone services are accessed by a possible by the widespread availability of collection of handset devices. The stateless desktop design high-performance workstations. However, the desktop provides a useful mobility model in which users can computing model is not without its problems, many of transparently resume their work on any desktop console. which were raised by the original UNIX designers[14]: This paper examines the fundamental premise in this “Because each workstation has private data, each system design that modern, off-the-shelf interconnection must be administered separately; maintenance is technology can support the quality-of-service required by difficult to centralize. The machines are replaced today’s graphical and multimedia applications.
    [Show full text]
  • Sun Ultratm 2 Workstation Just the Facts
    Sun UltraTM 2 Workstation Just the Facts Copyrights 1999 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun Logo, Ultra, SunFastEthernet, Sun Enterprise, TurboGX, TurboGXplus, Solaris, VIS, SunATM, SunCD, XIL, XGL, Java, Java 3D, JDK, S24, OpenWindows, Sun StorEdge, SunISDN, SunSwift, SunTRI/S, SunHSI/S, SunFastEthernet, SunFDDI, SunPC, NFS, SunVideo, SunButtons SunDials, UltraServer, IPX, IPC, SLC, ELC, Sun-3, Sun386i, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. OpenGL is a registered trademark of Silicon Graphics, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. Display PostScript and PostScript are trademarks of Adobe Systems, Incorporated. DLT is claimed as a trademark of Quantum Corporation in the United States and other countries. Just the Facts May 1999 Sun Ultra 2 Workstation Figure 1. The Sun UltraTM 2 workstation Sun Ultra 2 Workstation Scalable Computing Power for the Desktop Sun UltraTM 2 workstations are designed for the technical users who require high performance and multiprocessing (MP) capability. The Sun UltraTM 2 desktop series combines the power of multiprocessing with high-bandwidth networking, high-performance graphics, and exceptional application performance in a compact desktop package. Users of MP-ready and multithreaded applications will benefit greatly from the performance of the Sun Ultra 2 dual-processor capability.
    [Show full text]
  • 18-741 Advanced Computer Architecture Lecture 1: Intro And
    18-742 Fall 2012 Parallel Computer Architecture Lecture 10: Multithreading II Prof. Onur Mutlu Carnegie Mellon University 9/28/2012 Reminder: Review Assignments Due: Sunday, September 30, 11:59pm. Mutlu, “Some Ideas and Principles for Achieving Higher System Energy Efficiency,” NSF Position Paper and Presentation 2012. Ebrahimi et al., “Parallel Application Memory Scheduling,” MICRO 2011. Seshadri et al., “The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing,” PACT 2012. Pekhimenko et al., “Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency,” CMU SAFARI Technical Report 2012. 2 Feedback on Project Proposals In your email General feedback points Concrete mechanisms, even if not fully right, is a good place to start testing your ideas 3 Last Lecture Asymmetry in Memory Scheduling Wrap up Asymmetry Multithreading Fine-grained Coarse-grained 4 Today More Multithreading 5 More Multithreading 6 Readings: Multithreading Required Spracklen and Abraham, “Chip Multithreading: Opportunities and Challenges,” HPCA Industrial Session, 2005. Kalla et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 2004. Tullsen et al., “Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor,” ISCA 1996. Eyerman and Eeckhout, “A Memory-Level Parallelism Aware Fetch Policy for SMT Processors,” HPCA 2007. Recommended Hirata et al., “An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads,” ISCA 1992 Smith, “A pipelined, shared resource MIMD computer,” ICPP 1978. Gabor et al., “Fairness and Throughput in Switch on Event Multithreading,” MICRO 2006. Agarwal et al., “APRIL: A Processor Architecture for Multiprocessing,” ISCA 1990. 7 Review: Fine-grained vs.
    [Show full text]
  • Ultra 80 Workstations
    Sun UltraTM 80 Workstation Just the Facts Copyrights 2001 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Ultra, PGX, PGX32, Sun Workstation, Sun Enterprise, Starfire, Solaris, UltraComputing, VIS, Java, Java 3D, SunCD, Sun StorEdge, Solstice, Solstice AdminTools, SunVTS, Solstice Enterprise Agents, ShowMe, ShowMe How, ShowMe TV, iPlanet, SunPCi, StarOffice, Solaris Resource Manager, TurboGX, TurboGXplus, S24, OpenWindows, SunCD 2Plus, Netra, SunButtons, SunDials, Sun Quad FastEthernet, SunFDDI, SunLink, SunATM, SunVideo, SunVideo Plus, SunCamera, SunMicrophone, SunForum, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunStart, SunSolve, SunSolve EarlyNotifier, and SunClient are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and in other countries, exclusively licensed through X/Open Company, Ltd. OpenGL is a trademark of Silicon Graphics, Inc., which may be registered in certain jurisdictions. Netscape is a trademark of Netscape Communications Corporation. PostScript and Display PostScript are trademarks of Adobe Systems, Inc., which may be registered in certain jurisdictions. Last
    [Show full text]
  • Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux
    Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2008, Article ID 582648, 16 pages doi:10.1155/2008/582648 Research Article Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux Emiliano Betti,1 Daniel Pierre Bovet,1 Marco Cesati,1 and Roberto Gioiosa1, 2 1 System Programming Research Group, Department of Computer Science, Systems, and Production, University of Rome “Tor Vergata”, Via del Politecnico 1, 00133 Rome, Italy 2 Computer Architecture Group, Computer Science Division, Barcelona Supercomputing Center (BSC), c/ Jordi Girona 31, 08034 Barcelona, Spain Correspondence should be addressed to Roberto Gioiosa, [email protected] Received 30 March 2007; Accepted 15 August 2007 Recommended by Ismael Ripoll Multiprocessor systems, especially those based on multicore or multithreaded processors, and new operating system architectures can satisfy the ever increasing computational requirements of embedded systems. ASMP-LINUX is a modified, high responsive- ness, open-source hard real-time operating system for multiprocessor systems capable of providing high real-time performance while maintaining the code simple and not impacting on the performances of the rest of the system. Moreover, ASMP-LINUX does not require code changing or application recompiling/relinking. In order to assess the performances of ASMP-LINUX, benchmarks have been performed on several hardware platforms and configurations. Copyright © 2008 Emiliano Betti et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1. INTRODUCTION nificantly higher than that of single-core processors, we can expect that in a near future many embedded systems will This article describes a modified Linux kernel called ASMP- make use of multicore processors.
    [Show full text]
  • Sun Blade 1000 and 2000 Workstations
    Sun BladeTM 1000 and 2000 Workstations Just the Facts Copyrights 2002 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Blade, PGX, Solaris, Ultra, Sun Enterprise, Starfire, SunPCi, Forte, VIS, XGL, XIL, Java, Java 3D, SunVideo, SunVideo Plus, Sun StorEdge, SunMicrophone, SunVTS, Solstice, Solstice AdminTools, Solstice Enterprise Agents, ShowMe, ShowMe How, ShowMe TV, Sun Workstation, StarOffice, iPlanet, Solaris Resource Manager, Java 2D, OpenWindows, SunCD, Sun Quad FastEthernet, SunFDDI, SunATM, SunCamera, SunForum, PGX32, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunSolve, SunSolve EarlyNotifier, and SunClient are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and in other countries, exclusively licensed through X/Open Company, Ltd. FireWire is a registered trademark of Apple Computer, Inc., used under license. OpenGL is a trademark of Silicon Graphics, Inc., which may be registered in certain jurisdictions. Netscape is a trademark of Netscape Communications Corporation. PostScript and Display PostScript are trademarks of Adobe Systems, Inc., which may be registered in
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • SPEC SFS Performance on Eserver Pseries Systems Page 1 IBM ~ Performance Technical Report
    IBM ~ Performance Technical Report SPEC SFS Performance on eServer pSeries ™ Systems Agustin Mena III February 5, 2002 ©2002 International Business Machines Corporation, all rights reserved SPEC SFS Performance on eServer pSeries Systems Page 1 IBM ~ Performance Technical Report Abstract A common use of UNIX® servers is in fileserving environments, specifically those using the Network File System (NFS) protocol [1, 2]. SPEC SFS 3.0 is an industry standard benchmark for measuring and comparing NFS server performance across a variety of file server vendors’ systems. Based on recently published SPEC SFS 3.0 results, the IBM® eServer pSeries™ 690 running AIX® 5L Version 5.1 proves to be an excellent choice for customers interested in a general-purpose UNIX server with outstanding performance in a large-scale NFS environment. The p690 results published in December 2001 are the highest of any SMP system in the industry. Also, the recently published (January 2002) IBM eServer pSeries 660 6M1 8-way results showcase this system as an excellent midrange NFS server. This white paper discusses the benchmark, the system configurations used, and details of the results and how they stack up against the competition. The SPEC SFS 3.0 Benchmark SPEC (Standard Performance Evaluation Corporation) SFS (System File Server) 3.0 is the most recent version of the industry standard SPEC benchmark which provides a means of comparing NFS server throughput and response time performance across different vendor platforms [3]. The benchmark is client-independent and vendor neutral. The results must conform to a set of run and disclosure rules. It is this set of rules that ensure that customers have a reasonable standard to compare and contrast the results across different vendor systems.
    [Show full text]
  • Understanding IBM Pseries Performance and Sizing
    Understanding IBM pSeries Performance and Sizing Comprehend IBM RS/6000 and IBM ^ pSeries hardware architectures Get an overview of current industry benchmarks Understand how to size your system Nigel Trickett Tatsuhiko Nakagawa Ravi Mani Diana Gfroerer ibm.com/redbooks SG24-4810-01 International Technical Support Organization Understanding IBM ^ pSeries Performance and Sizing February 2001 Take Note! Before using this information and the product it supports, be sure to read the general information in Appendix A, “Special notices” on page 377. Second Edition (February 2001) This edition applies to IBM RS/6000 and IBM ^ pSeries as of December 2000, and Version 4.3.3 of the AIX operating system. This document was updated on January 24, 2003. Comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JN9B Building 003 Internal Zip 2834 11400 Burnet Road Austin, Texas 78758-3493 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 1997, 2001. All rights reserved. Note to U.S Government Users – Documentation related to restricted rights – Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Contents Preface. 9 The team that wrote this redbook. 9 Comments welcome. 11 Chapter 1. Introduction . 1 Chapter 2. Background . 5 2.1 Performance of processors . 5 2.2 Hardware architectures . 6 2.2.1 RISC/CISC concepts . 6 2.2.2 Superscalar architecture: pipeline and parallelism . 7 2.2.3 Memory management .
    [Show full text]