FIRST BIN (Volume – 9, Issue – 01, Jan – 2021)
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Volume – 9 | Issue – 01 Jan 2021 FIRSTFIRST BINBIN A Newsletter for the Semiconductor Engineering Community Contents Dear Customer, I wish all A Very Happy and Healthy New Year! From the CEO’s Desk As you are all aware, it has been a challenging 2020! Tessolve team was able to quickly adapt to the new norm ensured continuity and best of Tessolve Showcase support to you all. 1. Effective Thermal Management Using Heat Pipe I would like to thank you for your support in a challenging year. I would also like to especially thank ADI for awarding us the Best Supplier award in the Ajay Kumar Balakrishna – Design Engineer, Mechanical Design, engineering services category! V J Nitheesh Shenoy – Sr. Design Engineer, Mechanical Design. This is a testament to the commitment and customer focus of Team 2. Low Cost PMIC Testing via conventional Digital cum Tessolve and we will continue to give our best to meet your engineering Mixed Signal ATE needs. Pravenakumara. D – Test Engineer 2, We continue to invest in engineering talent and our team has grown to over Manoj Manimaran Selvaraj – Test Engineer 2 2000 engineers worldwide. We have also invested in acquiring new testers (ETS364B, Advantest T2k Air) and also invested in a full suite of Cadence tools to address our growing project demand. Tessolve Engineering Challenge Contest We also launched the Centre of Excellence initiative to ensure we have dedicated teams working on initiatives to work on the latest technologies 1. DDR IO Calibration Debug Challenges In Multichannel Design and special projects. Some of the projects COE is taking up are 112GBPS PAM4, mmWave, High-Performance Compute qualifications, Analog Suneetha Thentu – Sr. Test Engineer 1, power management IP building blocks, RISCV verification IP, Automotive Anirudh Mathur – Sr. Test Lead design/productization flows, etc. 2. Innovative Test Solution to implement dynamic Latch-Up I am also proud to say that we recently completed an end-to-end PMIC on conventional static Latch-Up Test Equipment productization project involving complete circuit design, layout, packaging and test development and characterization. Madhu Babu Gangavarapu – Sr. Test Engineer 1 Tessolve also introduced an ultra-low-power System on Module based on the Mediatek i500 family of chips to address the AIOT ecosystem. It is nice to be selected as an AIOT partner for Mediatek and I congratulate the team for it! Editorial Team We have exciting plans ahead for 2021. We are looking at further enhanc- ADVISORY COMMITTEE EDITORIAL SUPPORT ing our Physical Design capabilities and also setup test labs in the U.S. We Srinivas Chinamilli Anuradha Noone are also enhancing our ASIC architecture and supply chain management Rajakumar D Srinivasa Rao Peram capabilities and we are moving towards providing complete ASIC solutions to you. TECHNICAL COMMITTEE OPERATIONS SUPPORT I would like to congratulate our employees for winning awards at the Vidyut Yagnik Thirumalesh Babu Murthy Mentor 2020 Technology Leadership Awards competition. Srinivasprasad B V Arunraj R and Team won a team award under Consumer Electronics & Prashanth Kudva MARKETING Handheld category for Mentor Xpedition Enterprise. Sudarshan Sarma HS Tanusree Mathad Srinivasan C Vinayaka L.G SathishKumar Kalaiselvan, Manikandan Ravi, Karthick Sathiyaseelan and Kishore Subramani won Honorable Mentions under the Mentor PADS™ software category. Printed and Published on behalf of Looking forward to working with you all to make your endeavors in 2021 a Tessolve Semiconductor Pvt. Ltd. big success! Plot # 31, Electronic City, Phase 2, Bangalore 560 100, Karnataka, India. Best Regards, Tel: +91 80 4181 2626 www.tessolve.com Srinivas Chinamilli Your kind enquiries / feedback solicited at, Co-Founder & CEO [email protected] / [email protected] 01 Tessolve Showcase 1. EFFECTIVE THERMAL MANAGEMENT USING HEAT PIPE Ajay Kumar Balakrishna – Design Engineer, Mechanical Design. V J Nitheesh Shenoy – Sr. Design Engineer, Mechanical Design. Introduction First time in TESSOLVE, a heat pipe is used for thermal management. In the Present world, Size reduction &Weight reduction at optimum cost is the main requirement in the Electronic industry. The miniaturizing of the electronic system combined with IP rating (require proper sealing) has thrown a challenge in front of mechanical engineers for effective thermal management of the electronic system. Using Heat pipe is one such technique that helps in miniaturizing and effective cooling. This case study gives an insight into the use of heat pipe to satisfy the requirement of miniaturizing the system combined with IP rating, reduced noise and effective cooling. Heat Pipe Figure 2: Heat pipes A heat pipe is a two-phase heat transfer device with a very high effective thermal conductivity. It is a vacuum-tight device consisting of an envelope, a working fluid, and a wick structure. Working: The heat input vaporizes the liquid working fluid inside the wick in the evaporator section. The saturated vapor, carrying the latent heat of vaporization, flows towards the colder condenser section. In the condenser, the vapor condenses and gives up its latent heat. The condensed liquid returns to the evaporator through the wick structure by capillary action. The phase change processes and two-phase flow circulation continues as long as the temperature gradient between the evaporator and condenser are maintained. The benefits of using heat pipes are: High thermal Conductivity (10,000 to 100,000 W/m-K) Isothermal | Passive | Low cost | Shock/Vibration tolerant Figure 1: Heat pipe in smartphone Freeze/thaw tolerant | Miniaturizing electronic system Case Study For the Auto radar designed for one of our Customers, They had a requirement of IP rating, which required proper sealing of enclosure. This sealing prevents the entry of air into the enclosure thus reducing the effect of cooling due to air circulation. The major heat dissipating component in the system was FPGA which dissipates 12 W of heat and If the junction temperature of the FPGA goes over 100°C, the system shutdowns. Two designs were considered for thermal simulation. Existing design Heat tower on the enclosure was made to touch FPGA using TIM. The heat thus conducted was then dissipated using 15 mm rear fins and 8 CFM fan. Design with heat pipe In this design, a combination of the heat spreader and heat pipe was used to carry heat to the enclosure and then using 3 mm fins heat was dissipated. Figure 3: Heat pipe arrangement 02 Parameters RADAR Enclosure with fan RADAR Enclosure with heat pipe without fan Total Length 151 mm 151 mm Total Width 153 mm 153 mm Total Height 39.85 mm 27.73 mm Fin height 15 mm 3 mm Weight 0.804 kg 0.662 kg The drawback with design 1 is that it is oversized and the presence of a Takeaways fan needs an additional power supply, which imparts slight noise and vibration. • Heat pipe carried heat away from the FPGA, Both the designs were subjected to thermal simulation under identical conditions. It was observed that both the simulation showed a thereby allowing further heat transfer. comparable result (Figure 4). With design 2 giving a good result at low cost and size. • Heat Pipe unlike fan is energy efficient as there is no external energy source required for working of the heat pipe. • The heat pipe is reliable since there is no moving part, unlike the fan. • Using Heat pipe permits the use of sealed enclosure. • The Fabrication cost of the enclosure was reduced. • The weight of the unit was reduced. Figure 4: Temperature contour of FPGA for existing design and design with heat pipe 03 2. LOW COST PMIC TESTING VIA CONVENTIONAL DIGITAL CUM MIXED SIGNAL ATE Pravenakumara. D – Test Engineer 2, Manoj Manimaran Selvaraj – Test Engineer 2 Abstract Testing of Modules within a PMIC in parallel for different Current Loads With ever scaling progress in Semiconductor Design & Manufacturing yielding into miniature IC designs and increased product complexity in Generally, PMIC Modules (DCDC, LDO, Power switches) are tested to turn leading to proportional advancements in ATE Instrumentation, it their required maximum current loads to guarantee the specifications becomes seemingly challenging to maintain the Test Cost well within in datasheet without any compromise in Test Coverage cum HVM the stipulated budget for any given Semicon supplier. On the contrary, it Test-Time that also mandates testing all modules within a PMIC in is to be realized that most semiconductor organizations and relevant parallel cum test sites. subgroups would want to Design, Test & Manufacture a diverse range This case study is performed on a PMIC (DUT), that comprises 16 of products on one common HVM platform. This enables faster LDO’s that are to be tested for conventional parameters like ramp-up from DesignValidationProduction, thereby both entities- Line-cum-Load regulation, Soft Start-time, Current Limit (Icl). To meet product owner & the supplier able to maintain economic supply chain the load current requirement, an optimal programmable current load management throughout the entire product lifespan from early stages was implemented in the ATE load board and the output of the LDO is Si PowerON HVM RampUp EOL. connected to dynamically programmable current load, while the voltage is sensed with a digitizer via an On-chip Analog monitor pin. Introduction Below Figure2 is a conceptual illustration of Programmable current load implemented via Virtual Shunt created by the Op-Amp that sets This article emphasizes a similar objective to utilize the widely the voltage across the variable resistor to establish a constant current available Test Systems across OSAT’s for testing a Low Cost PMIC load accompanied by programmable Vsource. (generally used for Power Management of a CPU Core & IO Peripherals) via a non-PMIC standard Digital cum Mixed Signal Tester. Generally dedicated PMIC tester Architecture is designed such a way that any back-end instruments such as VI Source, AWG, Digitizer can be routed internally and be available on any given ATE port; but not the case on a conventional Digital cum Mixed Signal tester were most instruments remain fixed to their allocated ports for usage.