Volume – 9 | Issue – 01 Jan 2021 FIRSTFIRST BINBIN A Newsletter for the Semiconductor Engineering Community

Contents Dear Customer, I wish all A Very Happy and Healthy New Year! From the CEO’s Desk As you are all aware, it has been a challenging 2020! Tessolve team was able to quickly adapt to the new norm ensured continuity and best of Tessolve Showcase support to you all.

1. Effective Thermal Management Using Heat Pipe I would like to thank you for your support in a challenging year. I would also like to especially thank ADI for awarding us the Best Supplier award in the Ajay Kumar Balakrishna – Design Engineer, Mechanical Design, engineering services category! V J Nitheesh Shenoy – Sr. Design Engineer, Mechanical Design. This is a testament to the commitment and customer focus of Team 2. Low Cost PMIC Testing via conventional Digital cum Tessolve and we will continue to give our best to meet your engineering Mixed Signal ATE needs.

Pravenakumara. D – Test Engineer 2, We continue to invest in engineering talent and our team has grown to over Manoj Manimaran Selvaraj – Test Engineer 2 2000 engineers worldwide. We have also invested in acquiring new testers (ETS364B, Advantest T2k Air) and also invested in a full suite of Cadence tools to address our growing project demand.

Tessolve Engineering Challenge Contest We also launched the Centre of Excellence initiative to ensure we have dedicated teams working on initiatives to work on the latest technologies 1. DDR IO Calibration Debug Challenges In Multichannel Design and special projects. Some of the projects COE is taking up are 112GBPS PAM4, mmWave, High-Performance Compute qualifications, Analog Suneetha Thentu – Sr. Test Engineer 1, power management IP building blocks, RISCV verification IP, Automotive Anirudh Mathur – Sr. Test Lead design/productization flows, etc.

2. Innovative Test Solution to implement dynamic Latch-Up I am also proud to say that we recently completed an end-to-end PMIC on conventional static Latch-Up Test Equipment productization project involving complete circuit design, layout, packaging and test development and characterization. Madhu Babu Gangavarapu – Sr. Test Engineer 1 Tessolve also introduced an ultra-low-power System on Module based on the Mediatek i500 family of chips to address the AIOT ecosystem. It is nice to be selected as an AIOT partner for Mediatek and I congratulate the team for it! Editorial Team We have exciting plans ahead for 2021. We are looking at further enhanc- ADVISORY COMMITTEE EDITORIAL SUPPORT ing our Physical Design capabilities and also setup test labs in the U.S. We Srinivas Chinamilli Anuradha Noone are also enhancing our ASIC architecture and supply chain management Rajakumar D Srinivasa Rao Peram capabilities and we are moving towards providing complete ASIC solutions to you.

TECHNICAL COMMITTEE OPERATIONS SUPPORT I would like to congratulate our employees for winning awards at the Vidyut Yagnik Thirumalesh Babu Murthy Mentor 2020 Technology Leadership Awards competition. Srinivasprasad B V Arunraj R and Team won a team award under Consumer Electronics & Prashanth Kudva MARKETING Handheld category for Mentor Xpedition Enterprise. Sudarshan Sarma HS Tanusree Mathad Srinivasan C Vinayaka L.G SathishKumar Kalaiselvan, Manikandan Ravi, Karthick Sathiyaseelan and Kishore Subramani won Honorable Mentions under the Mentor PADS™ software category.

Printed and Published on behalf of Looking forward to working with you all to make your endeavors in 2021 a Tessolve Semiconductor Pvt. Ltd. big success! Plot # 31, Electronic City, Phase 2, 560 100, Karnataka, India. Best Regards, Tel: +91 80 4181 2626 www.tessolve.com Srinivas Chinamilli Your kind enquiries / feedback solicited at, Co-Founder & CEO [email protected] / [email protected]

01 Tessolve Showcase

1. EFFECTIVE THERMAL MANAGEMENT USING HEAT PIPE Ajay Kumar Balakrishna – Design Engineer, Mechanical Design. V J Nitheesh Shenoy – Sr. Design Engineer, Mechanical Design.

Introduction

First time in TESSOLVE, a heat pipe is used for thermal management. In the Present world, Size reduction &Weight reduction at optimum cost is the main requirement in the Electronic industry. The miniaturizing of the electronic system combined with IP rating (require proper sealing) has thrown a challenge in front of mechanical engineers for effective thermal management of the electronic system. Using Heat pipe is one such technique that helps in miniaturizing and effective cooling. This case study gives an insight into the use of heat pipe to satisfy the requirement of miniaturizing the system combined with IP rating, reduced noise and effective cooling.

Heat Pipe Figure 2: Heat pipes

A heat pipe is a two-phase heat transfer device with a very high effective thermal conductivity. It is a vacuum-tight device consisting of an envelope, a working fluid, and a wick structure. Working: The heat input vaporizes the liquid working fluid inside the wick in the evaporator section. The saturated vapor, carrying the latent heat of vaporization, flows towards the colder condenser section. In the condenser, the vapor condenses and gives up its latent heat. The condensed liquid returns to the evaporator through the wick structure by capillary action. The phase change processes and two-phase flow circulation continues as long as the temperature gradient between the evaporator and condenser are maintained. The benefits of using heat pipes are:

High thermal Conductivity (10,000 to 100,000 W/m-K)

Isothermal | Passive | Low cost | Shock/Vibration tolerant Figure 1: Heat pipe in smartphone Freeze/thaw tolerant | Miniaturizing electronic system

Case Study

For the Auto radar designed for one of our Customers, They had a requirement of IP rating, which required proper sealing of enclosure. This sealing prevents the entry of air into the enclosure thus reducing the effect of cooling due to air circulation. The major heat dissipating component in the system was FPGA which dissipates 12 W of heat and If the junction temperature of the FPGA goes over 100°C, the system shutdowns. Two designs were considered for thermal simulation.

Existing design Heat tower on the enclosure was made to touch FPGA using TIM. The heat thus conducted was then dissipated using 15 mm rear fins and 8 CFM fan.

Design with heat pipe In this design, a combination of the heat spreader and heat pipe was used to carry heat to the enclosure and then using 3 mm fins heat was dissipated.

Figure 3: Heat pipe arrangement

02 Parameters RADAR Enclosure with fan RADAR Enclosure with heat pipe without fan

Total Length 151 mm 151 mm

Total Width 153 mm 153 mm

Total Height 39.85 mm 27.73 mm

Fin height 15 mm 3 mm

Weight 0.804 kg 0.662 kg

The drawback with design 1 is that it is oversized and the presence of a Takeaways fan needs an additional power supply, which imparts slight noise and vibration. • Heat pipe carried heat away from the FPGA, Both the designs were subjected to thermal simulation under identical conditions. It was observed that both the simulation showed a thereby allowing further heat transfer. comparable result (Figure 4). With design 2 giving a good result at low cost and size. • Heat Pipe unlike fan is energy efficient as there is no external energy source required for working of the heat pipe.

• The heat pipe is reliable since there is no moving part, unlike the fan.

• Using Heat pipe permits the use of sealed enclosure.

• The Fabrication cost of the enclosure was reduced.

• The weight of the unit was reduced.

Figure 4: Temperature contour of FPGA for existing design and design with heat pipe

03 2. LOW COST PMIC TESTING VIA CONVENTIONAL DIGITAL CUM MIXED SIGNAL ATE Pravenakumara. D – Test Engineer 2, Manoj Manimaran Selvaraj – Test Engineer 2

Abstract Testing of Modules within a PMIC in parallel for different Current Loads With ever scaling progress in Semiconductor Design & Manufacturing yielding into miniature IC designs and increased product complexity in Generally, PMIC Modules (DCDC, LDO, Power switches) are tested to turn leading to proportional advancements in ATE Instrumentation, it their required maximum current loads to guarantee the specifications becomes seemingly challenging to maintain the Test Cost well within in datasheet without any compromise in Test Coverage cum HVM the stipulated budget for any given Semicon supplier. On the contrary, it Test-Time that also mandates testing all modules within a PMIC in is to be realized that most semiconductor organizations and relevant parallel cum test sites. subgroups would want to Design, Test & Manufacture a diverse range This case study is performed on a PMIC (DUT), that comprises 16 of products on one common HVM platform. This enables faster LDO’s that are to be tested for conventional parameters like ramp-up from DesignValidationProduction, thereby both entities- Line-cum-Load regulation, Soft Start-time, Current Limit (Icl). To meet product owner & the supplier able to maintain economic supply chain the load current requirement, an optimal programmable current load management throughout the entire product lifespan from early stages was implemented in the ATE load board and the output of the LDO is Si PowerON HVM RampUp EOL. connected to dynamically programmable current load, while the voltage is sensed with a digitizer via an On-chip Analog monitor pin.

Introduction Below Figure2 is a conceptual illustration of Programmable current load implemented via Virtual Shunt created by the Op-Amp that sets This article emphasizes a similar objective to utilize the widely the voltage across the variable resistor to establish a constant current available Test Systems across OSAT’s for testing a Low Cost PMIC load accompanied by programmable Vsource. (generally used for Power Management of a CPU Core & IO Peripherals) via a non-PMIC standard Digital cum Mixed Signal Tester. Generally dedicated PMIC tester Architecture is designed such a way that any back-end instruments such as VI Source, AWG, Digitizer can be routed internally and be available on any given ATE port; but not the case on a conventional Digital cum Mixed Signal tester were most instruments remain fixed to their allocated ports for usage. To overcome this limitation, resource sharing circuitry is designed onboard to share available resources like digitizer, accurate DC measurement instrument, Device power supply, and on-board Programmable current load.

Below Figure1 shows the concept diagram:

Figure2: Programmable Current load

By adopting the Programmable current load and as well design feature of remote Voltage sense via Analog Monitor pins, The LDO test is performed by applying different current load and supply voltage conditions sequentially to the LDO. This is required to test dynamic characteristics of the LDO like line/load regulation followed by transient parameters like Ton & T-off Below Figure3 shows the sequence of voltage measured via the Digitizer for the current load of 0mA(No Load),600mA(Full Load),900mA(Over Current) using the on-board programmable current load. Figure1

For this case study, we have used the Advantest 93000 PinScale Test System as a reference to describe the key techniques adopted for realization & conclusion

Figure3

04 With this approach of testing, the effective test time for 16 LDO’s was Introduction 380ms It is also important to notice that in the absence of such On-board The purpose of IO Calibration is to provide constant output impedance programmable current load, the same Test -Time would be ~1.6s as it across Process, Voltage & Temperatures (PVT) by calibrating to an involves a sequence of events-like Power Up the LDO, apply Load external resistor. current via a PMU / VI Source and then perform the Voltage measure- The driver is calibrated against an external resistor on the board which ment via a Digitizer/PMU in discrete steps that involves Setup Time calibrates the pad drive strengths across PVT. This resistance is typical Overheads. of the same value as the characteristic impedance of the line. IO Cal test consists of NFET/PFET calibration in functional mode followed by NFET Count and PFET Count read-out. The calibration block interfaces Test Time with the calibration pad and sweeps the PFET/NFET Count value to determine the optimal setting for the current PVT conditions. These in Sec optimal values are then propagated to the IO calibration slave blocks which then propagates the final values onto the pads. 16 LDO’s tested with static current load 1.6

Effective test time for 16 LDO’s per PMIC 0.38 Approach Step 1: Initial Results Profit in test time per 16 PMIC 1.22 IO Calibration is showing default/saturated value (16) for the odd channels (CH1,3,5,7), while for even channels (CH0,2,4,6) the PFET/NFET Count values are as expected. The impact of this problem Conclusion is also observed in Eye monitoring performance parameters in both ATE and design simulations. With very marginal investment in BOM and Engineering; we can provide a cost-effective solution without any deviation/change in the widely available conventional Digital/Mixed Signal based Test Systems. "Default Data Thereby such techniques are not just innovative & low cost but with Condition (in Steps)" Zero compromise on Test Quality & still able to guarantee the desired DPPM target; in-turn benefitting the entire community of the Semicon supply chain. PFET NFET Channels Count Count

CH 0/2/4/6 2 10

Tessolve Engineering CH 1/3/5/7 16 16

Challenge Contest Table1: IO CAL – Initial Values

Eye Shmoo for CH0 Eye Shmoo for CH1 1. DDR IO CALIBRATION DEBUG CHALLENGES IN MULTICHANNEL DESIGN

Suneetha Thentu – Sr. Test Engineer 1, - Anirudh Mathur – Sr. Test Lead

Abstract

IO Calibration issue observed for the odd channels (CH 1,3,5,7) on an 8-channel product. DDR PHY Req signal OR gate to Micro-controller getting hooked-up to the Master channel instead of the expected Slave channel resulted in Calibrated values not getting propagated from master to slave. SW (software) workaround is discovered to qualify the silicon before next the Metal tapeout.

Fig2: Write Path Calibrated delay vs Reference Voltage Eye Shmoo for CH0 & CH1 at default condition

05 Step 2: Hardware connections Analysis Data with Software Condition EVEN Channels Workaround (in steps) Master (of CH0) is calibrated through the resistor & the calibrated values are sent to slave PHY (of CH2). From the slave PHY, the PFET NFET Channels calibrated values are sent to CH2 Microcontroller. Once CH0 & CH2 Count Count Microcontrollers receive the calibrated values, ACK is sent to the master and slave PHY respectively. The same process follows for CH4 CH 0/2/4/6 2 10 & CH6.

CH 1/3/5/7 2 10

Table2: IO CAL data with SW workaround

Eye Shmoo for CH0 Eye Shmoo for CH1

Fig3: Even Channels Connection Diagram

ODD Channels

ODD Channels: Master (of CH1) is calibrated through the resistor, but here the connection is from slave PHY (of CH3) to master PHY (of CH1) as shown in Fig4. The default values override the master calibrated values and send them to CH1 and CH3 Microcontrollers resulting in default/saturated values on CH1 & CH3. The same process follows for CH5 and CH7. Fig5: Write Path Calibrated delay vs Reference Voltage Eye Shmoo for CH0 & CH1 with SW Workaround

Conclusion With no impact on the application, this approach saved cost and efforts to go for immediate Metal fix facilitating the team to achieve the target of releasing early samples within project timelines.

2. INNOVATIVE TEST SOLUTION TO IMPLEMENT DYNAMIC LATCH-UP ON CONVENTIONAL STATIC LATCH-UP TEST EQUIPMENT Madhu Babu Gangavarapu – Sr. Test Engineer 1

Fig4: Odd Channels Connection Diagram Latch-Up being one of the key product Q & R requirements, for generations very seldom in the industry it has been performed in the orthodox static mode with static Biasing. However, as there is Step 3: Workaround continuous advancement in the VLSI segment, Chip Designers, Product & Quality engineers often envy to perform the LU Test with appropriate Workaround identified before Metal Fix is to update test case algorithm pre-conditioning of the Devices in-order to not have any false by IO Cal register shadowing technique wherein saving the IO interpretation of the LU Test results. Thus, maintaining the device in low Calibration values in a register for Master channels (CH1 & CH5) during current consumption, stable/ quiescent is a key to perform successful initial calibration & copy those values into Status Registers of CH1 & LU test as well as to configure the DUT IO’s to High-Z state before CH5 & respective Slave channels (CH3 & CH7). With this workaround, Latch-Up test. For both such requirements, it mandates the LU Test IO Calibration values are as expected & a good improvement is System to advance itself further to execute basic DUT observed in the EYE height for the odd channels with the response functions/commands/protocols like Reset, Boot & also able to comparable with even channels. program few DUT Specific registers like an ATE. Though there are surplus Latch-Up Test systems across the globe with such dynamic pattern drive capabilities, this Article orchestrates a technique used to enhance the capability of the conventional static Latch-Up Tester to a dynamic one & with very marginal cost implication but far more economical compared to using the Dynamic LU Tester.

06 Approach and Solution

In this article, the example DUT described subject to Latch-Up can only support I2C communication to precondition High-Z & Quiescent state. As the in-house LU tester is limited by pattern drive/register write capability, the only option was to use a Dynamic LU Tester that can drive patterns to the DUT but it would inflate the Project Expenses.

Thus we introduced a Single Board Computer (SBC) solution to program the I2C effectively alongside static LU TestSytem

Fig3: LU Stress Pulse Timing Diagram

Thus, to avoid latch-up stress on actual test pins before the precondition, dummy pins are added to test in LU tester pin configuration.

Pause the LU test: After a few seconds (~5s) from the LU test starts, the tester is paused for the stress with stress applied on dummy pins. The DUT power supplies are still PowerOn state during the paused Fig1: Block diagram- Dynamic LU setup condition. Now trigger the SBC interface control to write the I2C registers to DUT.

The SBC (for ex: raspberry pi, Tinker board, etc.) represents a miniature computer built on a single circuit board. It has a GPIO type header Drive I2C patterns with SBC: The SBC operating system is incorporated catered to various interface protocols like I2C, JTAG, SPI, UART etc. with built-in software tools to control GPIO header test interfaces. I2C These interfaces can be controlled with a minimum set of code. SBC register writes data validated with register read data. will be stationed/ plugged very close to the actual LU tester with a very small form factor and user-friendly UI based I2C programming. Resume the LU test: If the received data matches with write data, in turn, confines to DUT pre-conditioned appropriately in the right state. The LU test to resume to apply Stress on actual Test pins.

Conclusion

Usage of such simplified & cost-effective technique for DUT pre-conditioning before Latch-Up sequence does not just nullify reliance on high end dynamic Latch-Up testers but also advantageous in terms of faster cum user-friendly programming & very limited space occupancy thereby able to gain ~50% cost reduction with conventional dynamic LU tester. Also based on the DUT complexity, the SBC introduction provides additional flexibility/freedom to develop customized/scalable solutions for pre-conditioning requirements to the DUT with various industry-specific interfacing protocols like I2C, I2S, JTAG, SPI, QSPI, UART etc.

Fig2: SBC and LU Test board connection

Start LU test: Before DUT in High-Z mode, the DUT supplies need to be sourced with voltage as per the LU test plan. However, as soon as the Power Supply ramps up to the programmed voltage levels, the stress pulse appears on the test pins automatically. ( This is one such limitation of all static LU tester)

07 Silicon Valley: San Diego: Richardson, TX:

TessolveDTS Inc., 226 Airport Parkway, TessolveDTS Inc., TessolveDTS Inc., Suite 300, San Jose, CA 95110 12348 High Bluff Drive, 1702 N. Collins Boulevard, Suite 161, Tel : +1 408-865-0873 Suite 100, San Diego, CA 92130. Richardson, TX 75080 Fax : +1 408-865-0896 Email : [email protected] Tel : +1 972-290-0172 Email : [email protected] Fax: +1 972-437-9348 Email : [email protected]

Bengaluru: Bengaluru: Bengaluru:

Tessolve Semiconductor Pvt. Ltd., Tessolve Semiconductor Private Limited Tessolve Semiconductor Pvt. Ltd. Plot No: 31 (P2), Electronic City Phase II, Indiqube South Island Building Name: Smart Works (6th Floor) Bangalore – 560 100, Karnataka, India. Sy.No.32, Marenahalli 2nd Phase Global Technology Park, Block “C” Tel : +91 80 4181 2626, JP Nagar, 24th Main, Ward No.177 Marathahalli Outer Ring Road, +91 80 6816 2626 Bangalore 560 078 Devarabeesanahalli Village, Bellandur, Email : [email protected] Tel : + 91 80 66995800 Bengaluru- 560103 Fax : +91 80 2668 6460 Email – [email protected] Email : [email protected]

Visakhapatnam: : Tessolve Engineering Services Pte Ltd.,

Tessolve Semiconductor Pvt. Ltd., Tessolve Semiconductor Pvt. Ltd., Blk 20, Woodlands Link, #06/20 MVR’s Vinayagar Trade center, Excellence – 5th Floor, Singapore 738733 5th Floor, A-wing, VIP Rd, Asilmetta, 104, Race course road, Tel : +65 6297-9613 , Andhra Pradesh 530003. Coimbatore – 641018, Email : [email protected] Tel : 0891- 4805222, 0891- 4805333 Tamilnadu, India. Email : [email protected] Tel : +91 422 2221188, +91 422 2221199 Email : [email protected]

Tessolve Semiconductor Sdn. Bhd. (1143041-M) Tessolve Semiconductor GmbH., Tessolve () Engineering Services Pte. Ltd. Koridor Utara Malaysia, Wöhlerstraße 29 Plot 36, Hilir Sungai Keluang 2, 30163 Hannover, Germany. 667 Ziwei Road, Pudong New Area, Kawasan Perusahaan Bayan Lepas Fasa 4, Email : [email protected] BLDG 172, RM 102 11900 Bayan Lepas, Pulau Pinang, [email protected] Shanghai, China 201210 Office: +604 637 0672 Tel: +86-13127643713 Mobile: +6012 528 9996

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