Delivering Excellence in Semiconductor Engineering [email protected] 9980190859 A HERO ELECTRONIX VENTURE Delivering Excellence in Semiconductor Engineering Volume - 6 Issue - 1 A newsletter for the semiconductor engineering community Jan - 2018 Contents FROM THE PRESIDENT’S DESK From the President's Desk Srinivas Chinamilli Tessolve Showcase 1. Improving the product quality using robust Dear Customer, outlier screening technique I hope the New Year is going good so far for you! capabilies for SOC tesng. 2. Server Product – Test Binning Techniques Tessolve Engineering Challenge Contest Thanks for your support. We are well on our way to We have started Tessolve China office in Shanghai. 1. 1ps Jitter Clock Generation for 93K LB concluding our fiscal year with record revenues and This will enable us to provide beer support to 2. Turret Contactor - A Challenging Library Part achieving 30% growth this year. companies with operaons in China. 3. Sine wave generation for Phase measurement test on 93K To further strengthen our Analog design offerings, Let me take this opportunity to congratulate our Editorial Team we acquired Analog Semi, a company specializing employees who have received recognions and Advisory Committee Technical Committee Analog circuit design and layout. Analog Semi is a accolades. Srinivas Chinamilli Shanthanu V Prabhu team of 50+ engineers led by a very capable Firstly, let me congratulate Raja Manickam, our Sundararajan TNK Nataraju CN management team who are veterans in the industry. Rajakumar D Vidyut Yagnik Founder and CEO for receiving the IESA Sarabhai We are happy to have them as part of Tessolve Vinayaka LG Award for outstanding contribuons by an individual Editorial Support family! to Indian Semiconductor Industry. A well-deserved Aravind N Operations Support Indrasena Reddy M Thirumalesh Babu Murthy We are seeing good tracon in our ESD/Latchup and award for furthering the semiconductor ecosystem Srinivasa Rao Peram Chandra Mohan Putcha Burnin reliability services. Being the only in India! Tanusree Mathad independent Reliability lab in India, we are happy to Let me also congratulate Gowri Shankar, C enable semiconductor companies to extend the S r i n i v a s a n , S i v a Pa v a n , J a ga d i s h k u m a r produczaon capabilies beyond electrical test Printed and Published on behalf of Chandrasekaran on their papers “Adapve RF-DIB and characterizaon to product reliability for ATE and Bench Reducing NRE-cost and Cycle Tessolve Semiconductor Pvt. Ltd. qualificaon. Plot # 31, Electronic City, Time” and “Novel DIB Layout Soluon to Minimize Phase 2, Bangalore 560 100, In our connuing efforts to parcipate in developing Load Capacitance in pico-Amps Measurement”, and Karnataka, India. cung edge technologies, we signed a partnership N Vijay on his paper “Choosing the right PCB Stackup Tel: +91 80 4181 2626 agreement with Instute of Microelectronics, technology for your Teradyne Ultraflex Test Boards”, www.tessolve.com Your kind enquiries / feedback solicited at, Singapore. Our inial collaboraon will involve which were selected at TUG (Teradyne Users Group) [email protected] / [email protected] developing improved test methodologies for conference. advanced packages such as 3D IC packages. We look forward to connuing to provide value add engineering soluons to you and further enhancing I am happy to announce that we have been added as the Naonal Instruments Gold Alliance our partnership with you. partner. This is a good recognion of our outstanding soluons in LabVIEW, TestStand PXI and STS tester based iniaves. This further boosts our capability to offer fully integrated and turnkey PXI Best Regards, based soluons seamlessly. Srinivas Chinamilli We have also invested in Advantest Smartscale Mixed Signal tester which further boosts our Co-Founder & President TESSOLVE SHOWCASE 1. Improving the product quality using robust outlier screening technique Arun Goud Poshala - Sr. Test Engineer Introducon limit(LSL) and upper spec limit(USL). In this technique, we use the To deliver zero defect product quality there are numerous tests to calculated rao on given parametric test results. For e.g. acve leakage screen out the defecve failure parts in both wafer and package level measured by off leakage measured. On known good part, this rao is tesng. In this arcle, we discuss on one such screening technique uniformly distributed. On few specific outlier devices, the rao might which intended to improve the product quality. not remain same. The device might have higher off leakage currents The Effecve Outlier screening technique uses the parametric test and lower acve currents or same on and off leakage currents. Such results such as IDDQ (quiescent currents), CPR (Ring Oscillator devices considered to be failures/Outlier. These devices are not caught recommendaon) etc. on convenonal standard leakage tests because these devices are well within the limits. With the outlier screening technique, we could Descripon potenally catch these failures during the producon screening On a convenonal Leakage measurement tests or any parametric test, eventually improve the product quality. the test pass/fail result is judged by the defined limits say Lower spec 1 Delivering Excellence in Semiconductor Engineering [email protected] 9980190859 Mathemacs involved in outlier screening technique On a given volume parametric test data derive the rao of the tests of interest. Now the equaon of a straight line is derived through two given points. When we do know two points on the line, and so we can use them to work out the gradient. We just use the formula m = (y2 − y1)/(x2 − x1) and drive the equaon of the straight line i.e. y=mx+c. Draw the straight-line equaons on both lower and upper corners- Please refe r F i g u re 3 . Ea c h d ev i c e ' s parametric test result is checked if it lies within this limits or no. If the results failed it is considered as outlier. Figure 1 : Standard Leakage test with defined spec limits Figure 3 : Parametric test outlier screening technique Advantages t This screening technique proved to catch the customer returns. t Cost effecve test screening technique, this test doesn't any DFT Figure 2 : Convenon method of detecng outlying IDDQ Limits test paern. 2. Server Product – Test Binning Techniques P.R. Sudhakar - Staff Engineer and R. Rajmohan - Sr. Test Engineer 2 Cloud compung is growing at a torrid pace. Cloud compung is dynamically in the test program – test-me can be saved on the fly. expected to account for more than 50% of the datacenter server Paral Good (PG) technique is a soluon to the above problem revenue by 2020. This growth is driving profound shis in datacenter statement. This works by reading pass/fail data for cores under test, infrastructure. Data center operators like Google, Microso and Use data from Paral Good Test Array to disable failing cores (from the Facebook have been seeking a compeve alternave that would give informaon of previous tests) -> execute the current test -> Update the them servers with opmized performance for new class of cloud Paral Good Test Array with the results based on the current test - datacenter infrastructure while driving prices lower and boosng >datalog the test results per core -> down-bin based on the number of innovaon. With the increasing demand in processing, the number of passing cores and memory. processor-cores in server chips keeps increasing with high memory. Since the amount of vector memory is more and for containing the FT With Mul cores CPU and more memory inside Server products, (Final Test) yield loss at WS (Wafer Sort), different inserons are used. devices failing for few/single core or few MB of memory need not be Test-me can be saved a lot if Informaon of failing/passing cores is branded as a completely bad device. These chips can sll be salvaged passed to the next level of inseron (ex. WS1 to WS2 or WS to FT and down-binned as a good part with a slightly limited feature-set. A tesng). Data Feed Forward helps in uploading the Pass/Fail core test-me queson comes up here – if a core or a memory bank fail, informaon of the first inseron to tools like Opmal+ (O+) and in the further down the program there might be tests which exercise these subsequent inseron it can be downloaded. Every Paral Good Test failing cores/memories again - why should we test this failed hardware Flow works by downloading Paral Good Array data from previous as the test program proceeds? Can this be avoided? The amount of test- inserons (Data Feed Forward), convert Opmal+ Feed Forward data me involved in tesng thisunit (which has a bad core or failed to local Paral Good Test Array, execute the tests in the flow (excluding memory) for subsequent tests needs to be reduced, thereby overall the failed cores). Each PG test-suite will execute the test and update the tesme (hence the test cost) of the server chip can be reduced. A test test array in real me. At the end of the flow execuon, devices are challenge arises here to record and pass the informaon of failing binned out based on test results and Upload Paral Good Test Array to cores/memories to subsequent tests, so that these failed O+ for future inserons cores/memories (reported by the earlier tests) can be weeded out 2 Delivering Excellence in Semiconductor Engineering [email protected] 9980190859 Tessolve Engineering Challenges Contest (TECC) 1. 1ps Jier Clock Generaon for 93K LB Vinayaka L G – Test Manager Abstract By taking reference from the Layout file of the EVB, we designed This arcle will describe the generaon of High Speed clock frequency Daughter Card. with jier as low as 1ps.