Digital Visual Interface Revision 1. 0 Digital Display Working Group
Digital Visual Interface DVI
Revision 1.0
02 April 1999
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HTC EXHIBIT 1013 Digital Visual Interface Revision 1. 0 Digital Display Working Group
The Digital Display Working Group Promoters (''DDWG Promoters") are Intel Corporation, Silicon Jmage, lnc., Compaq Computer Corporation, Fujitsu Limited, Hewlett-Packard Company, lntemational Business Macbines Corporation, and NEC Corporation
TffiS SPECIFICATION IS PROVIDED "AS lS" WJTH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTAB[LITY, NONlNFRlNGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECWICATION OR SAMPLE.
The DDWG Promoters disclaim all liability, including liability for infringement ofany proprietary rights, relating to usc of information in this sprxilil:ation. No license. express or implied, by estoppel or othetwise, to any intellectual property rights is granted herein.
The DDWG Promoters may have patents and/or patent applications related to the Digital Visua//nteJfaoe Specification. The DDWG Promoters intend to make avai lable to the industry
Copyright © DDWG Promoters l999.
*Third-party br:ands and nan1es are the propeny of their respective owners.
Acknowledgement
The DDWG acknowledges the concerted efforts of employees of Silicon lmage, Inc. and Molex Inc., who authored major portions ofthis specification. Both companies have made a signjficant contribution by developing and licensing to the industry the core technologies upon which this i11dustry specification is based; transition minimized differential signaling (T.M.D.S.) technology from Silicon Image, and connector teclmology from Molex.
REVISION HISTORY
02 Apr 99- 1.0 Initial Specification Release
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Acknowledgement...... 2 REVISION HISTORY ...... 2 1. Introduction...... 5 1.1. Scope and Motivation ...... 5 1.2. Performance Scalability ...... 6 1.2.1. Bandwidth Estimation ...... 7 1.2.2. Conversion to Selective Refresh ...... 8 1.3. Related Documents ...... 8 1.3.1. VESA Display Data Channel (DOC) Specification ...... 8 1.3.2. VESA Extended Display Identification Data (ED/D) Specification ...... 8 1.3.3. VESA Video Signal Standard (VSIS) Specification ...... 8 1.3.4. VESA Monitor Timing Specifications (DMT) ...... 9 1.3.5. VESA Generalized Timing Formula Specification (GTF) ...... 9 1.3.6. VESA Timing Definition for LCD Monitors Specification ...... 9 1.3.7. Compatibility with Other T.M.D.S. Based Implementations ...... 9 2. Architectural Requirements...... 1 0 2.1 . T.M.D.S. Overview ...... 10 2.2. Plug and Play Specification ...... 1 0 2.2.1. Overview...... 10 2.2.2. T.M. O.S. Link Usage Model ...... 11 2.2.3. High Color Depth Support ...... 13 2.2.4. Low Pixel Format Support ...... 14 2.2.5. ED/D ...... 14 2.2.6. DOC ...... 15 2.2.7. Gamma ...... 15 2.2.8. Scaling ...... 15 2.2.9. Hot Plugging ...... 16 2.2.10. HSync, VSync and Data Enable Required ...... 17 2.2.11. Data Formats ...... 18 2.2.12. fnteroperability with Other T.M.D.S. Based Specifications ...... 18 2.3. Bandwidth ...... 18 2.3.1. Minimum Frequency Supported ...... 18 2.3.2. Alternate Media ...... 19 2.4. Digital Monitor Power Management...... 19 2.4.1. Link Inactivity Definition ...... 21 2.4.2. System Power Management Requirements ...... 21 2.4.3. Monitor Power Management Requirements ...... 21 2.5. Analog ...... 22 2.5.1. Analog Signal Quality ...... 22 2.5.2. HSync and VSync Required ...... 22 2.5.3. Analog Timings ...... 22 2.5.4. Analog Power Management ...... 23 2.6. Signal List...... 23 3. T.M.D .. S. Protocol Specification...... 24 3.1 Overview ...... 24 3.1.1 Link Architecture ...... 24 3.1.2 Clocking ...... 24 3.1.3 Synchronization ...... 25 3. 1.4 Encoding ...... 25 3.1.5 Dual-Link Archit.ecture ...... 25 3.2 Encoder Specification ...... 26 3.2.1 Channel Mapping ...... 26
Page 3 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 3.2.2 Encode Algorithm ...... 28 3.2.3 Serialization ...... 30 3.3 Decoder Specification ...... 30 3.3.1 Clock Recovery...... 3D 3.3.2 Data Synchronization ...... 30 3.3.3 Decode Algorithm ...... 31 3.3.4 Channel Mapping...... 31 3.3.5 Error Handling ...... 31 3.4 Link Timing Requirements ...... 32 4. T.M.D.S. Electrical Specification ...... 33 4.1. Overview...... 33 4.2. System Ratings and Operating Conditions ...... 35 4.3. Transmitter Electrical Specifications ...... 35 4 .4 . Receiver Electrical Specifications ...... 38 4.5. Cable Assembly Specifications ...... 39 4.6. Jitter Specifications ...... 39 4 .7. Electrical Measurement Procedures ...... 40 4.7.1. Test Patterns ...... 40 4.7.2. Normalized Amplitudes ...... 40 4.7.3. Clock Recovery ...... 40 4.7.4. Transmitter Rise/Fall Time...... 41 4.7.5. Transmitter Skew Measurement...... 41 4.7.6. Transmitter Eye ...... 41 4.7.7. Jitter Measurement ...... 42 4.7.8. Receiver Eye ...... 42 4.7.9. Receiver Skew Measurement ...... 42 4.7.10. Differential TOR Measurement Procedure ...... 42 5. Physical Interconnect Specification ...... 43 5.1. Overview...... 43 5.2. Mechanical Characteristics ...... 43 5.2.1. Signal Pin Assignments ...... 43 5.2.2. Contact Sequence ...... 44 5.2.3. Digital-Only Receptacle Connectors ...... 45 5.2.4. Combined Analog and Digital Receptacle Connectors ...... 46 5.2.5. Digital Plug Connectors ...... 47 5.2.6. Analog Plug Connectors ...... 47 5.2.7. Recommended Panel Cutout ...... 48 5.2.8. Mechanical Performance ...... 49 5.3. Electrical Characteristics ...... 50 5.3.1. Connector Electrical Performance ...... 50 5.3.2. Cable Electrical Performance ...... 52 5.4. Environmental Characteristics ...... 53 5.5. Test Sequences ...... 54 5.5.1. Group 1: Mated Environmental...... 54 5.5.2. Group II: Mated Mechanical ...... 55 5.5.3. Group Ill: Mechanical Mate/Unmate Forces ...... 56 5.5.4. Group IV: Insulator Integrity...... 57 5.5.5. Group V: Cable Flexing ...... 58 5.5.6. Group VI: Electrostatic Discharge ...... 58 Appendix A. Glossary of Terms ...... ,...... 59 Appendix B. Contact Geometry ...... 61 Appendix C. Digital Monitor Power State- State Diagram ...... 76
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1. Introduction
The Digital Visual Interface (hereinafter DYT) specification provides a high-speed digital connection for visual data types that is display technology independent. The interface is primarily focused at providing a connection between a computer and its display device. The DVl specification meets the needs of all segments of the PC industry (workstation, desktop, laptop, etc) and will enable these different segments to unite arowud one monitor interface specification.
The DVl interface enables: I. Content to remain in the lossless digital domain from creation to consumption 2. Display technology independence 3. Plug and play through hot plug detection, EDlD and DDC28 4. Djgital and Analog support in a single connector
This interface specification is organized as follows: + Chapter 1 provides motivation, scope, and direction of the specificatjon. • Chapter 2 provides a technical overview and the specific system and display architectural and programming requirements that must be met in order to create a11 inter-operable context for the DVI i11terface. + Chapter 3 provides a detailed description of the transition minimized differential signaling (hereinafter T.M.D.S.) protocol and encoding algorithm. + Chapter 4 provides a detailed description of the electrical requirements ofT.M.D.S .. • Chapter 5 contains the connector mechanical description and the electrical characteristics of the connector, including signal placement. + A[ppendix A is a glossary. • Appendix 8 details the connector contact geometry • A[ppendix C enlarged digital monitor power state diagram
1.1. Scope and Motivation
The purpose of this interface specification is to provide an industry specification for a digital interface between a personal computing device and a display device. This specification provides for a simple low-cost implementation on both the host and monitor while allowing for monitor manufacturers and syste m providers to add feature rich values as appropriate for their specific application.
The DDWG has worked to address the various business models and requirements of the iodusu·y by delivering a transition methodology that addresses the needs of those various requirements. This is accomplished by specifying two connectors with identical mechanical characteristics: one that is digital only and one that is digital and analog. The combined digital and analog connector is designed to meet the needs of systems with special form factor or perfom1ance requirements. Having support for the analog and digital interfaces for the computer to monitor interconnect wj[[ allow the end user to simply plug the display into the DVI connector regardless of the display technology.
The digital only DVI connector is designed to coexist with the standard VGA connector. With the combined connector or the digital only connector the opportunity exists for the removal of the legacy YGA collllector. The removal of the legacy YGA connector is anticipated to be driven strictly by bllsiness demands.
A digital interface for the computer to monitor interconnect has several benefits over the standard VGA connector. A digital interface ensures all content transferred over this interface
Page 5 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group remains in the lossless digital domain 1iom creation to consumption. The digital interface is developed with no assumption made as to the attached display technology.
This specification completely describes the interface so that one could implement a complete transmission and interconnect solution or any portion of the interface. The T.M.D.S. protocol and associated electrical signaling as developed by Silicon !mage is described in detail. The mechanical specification of the connector and the signal placement within the connector are described. .
A device that is compliant with this specification is should be interoperable with other compliant devices tlu·ough the plug and play configuration and implementation provided for in this specification. The plug and play ioterface provides for hot plug detection and monitor feature detection. Additionally, this specification describes the number ofT.M.D.S. links available to the display device and the method for configuring the T.M.D.S. links.
The bandwidth and pixel formats that are anticipated and supported by this specification are described. This specification describes the signal quality characteristics required by the cable to support the l1igh data rates required by large pixel format displays. Additionally the DVI specification provides for alternate media implementations. Power management and plug and play configuration management are both fully described. To ensure baseline functionality, low-pixel format requirements are included.
As appropriate, this interface makes use of existing VESA specifications to allow for simple low-cost implementations. Specifically VESA Extended Display Identification Data (EDID) and Display Data Channel (DOC) specifications are referenced for monitor identification and the VESA Monitor Timing Specification (DMT) is referenced for the monitor timings.
1.2. Performance Scalability
The amount of raw bandwidth that is required to support a display type is technology specific. For example a typical CRT allocates a blanking interval time. This blanking interval requirement is technology specific and forces the data transfer to occw· in a limited time slot. This limited time slot increases the bandwidth requirement of the data active window while mandating long data inactive time periods to allow for the blanking to complete. A blanking period is display technology specific and should not be forced on all display types. Reduced blanking periods provide more ofthe actual interconnect bandwidth to the display device. It is anticipated that display technology will continue to advance such that blanking period overheads wi ll be decreased and will eventually be elimi.nated thus providing the maximum bandwidth of the interface to the display device. As displays advance even beyond the capabilities of the copper physical layer it is anticipated display interfaces will migrate toward providing only changed data to the display. This limited update architectltre is an expectation only, not a requiJement.
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'iii'3 .0 ~ .c :0 Copper Barrier .3 2 "0 c: ::::::::::::::4:::::: Selective Refresh ::::::::::::::::::::. co ...... Ill Legend: ~1c: .cco - Proposed Spec () (I) --- Future Architecture c;, .c: i:i) 0 Ul ...... r.J r.J w w • VGA (640x480) 0 0 Ul 0 Ul 0 c.n 0 0 0 0 0 0 • SVGA (800x600) Pixel Bandwidth [MPix/sec) XGA (1024x768) 60Hz LCD --... x- SXGA (1280x1024) 5% blanking .. •+ • UXGA (1600x1200) 60Hz CRT -x-- I GTF blanking .....-- + HDTV (1920x1080) ·-· • QXGA (2048x1536) 75Hz CRT GTF blanking • • X +-- ·• 85Hz CRT GTF blanking • • .. e--+-
Figure 1-1. Available Link Bandwidth
Figure 1-L Available Link Bandwidth. represents the raw bandwidth available from each T.M.D.S. link. The three horizontal axes across the bottom of the figw·e represent the different overhead requirements of the various display technologies. To detem1ine the number of links required for a specific application simply use the legend on the right to select tbe pixel format, then find the pixel format on the horizontal axis that represents the display technology of interest. Once the pixel format has been identified draw a vertical line to intersect the T.M.D .S. bandwidth curve, this is the bandwidth required for the pixel format and djsplay technology selected.
1.2. 1. Bandwidth Estimation
The bandwidth that is requjred over a physical medium is easy to estimate. Data reqLtired as input are Horizontal Pixels, Vertical Pixels, Refresh Frequency (Hz), Bandwidth Overhead (loosely defined as blanking). An equation to quickly estimate the bandwidd1 required is:
[ # Horizonta/Pixelsx# Vertica/Pixels x Rate x ( J + %~~~ead)] = Pixeo/secand
Equation 1-1. Pixels per Secoml. Where overhead is defined as
Blanking 0 verh ea d = ____..;:;;._ 1- Blanking Eqntllionl-2. 01·erhead.
Page 7 of 76 Digital Visual Interface Revision 1.0 Digital Display Working Group To measure the link bandwidth i.n pixels per second assumes each of the three charmels is transmitting an R-pel, G-pel, and B-pel data in unison.
A pel is a pixel element, i.e. the singLLiar red value or green value or blue value of an RGB pixel. Pixels per second can be converted to bits per second by multiplying the pixels per second value by the number of bits per pixel. Using E quation 1-1 and the T.M.D.S. signaling protocol, pixels per second equals tbe T.M.D.S. clock link frequency.
1.2.2. Conversion to Selective Refresh
It is anticipated that in the future the refreshing of the screen will become a function of the monitor. Only when data has changed will the data be sent to the monitor. A monitor would bave to employ an addressable memory space to enable this feature. With a selective refresh interface, the high refresh rates required to keep a monitor ergonomically pleasing can be maintained while not requiring an artificially high data rate between the graphics controller and tbe monitor. The DVI specification does nothing to preclude this potential migration.
1.3. Related Documents
The DVI specificadon references other VESA specifications to enable low cost implementations. Additionally, the DVJ specification references the VESA specifications to help enable plug and play interoperability.
1.3.1. VESA Display Data Channel (DOC) Specification
This specification incorporates a subset of the Display Data Channel for operation between a DDC compliant host and DDC compliant monitor. The DDC level support required in this specification is DDC2B. Compatibility with earlier DDC versions is not supported. lt is anticipated that the DVI specification will require support for the Enhanced-DOC specification within 12 months of VESA adoption. Refer to VESA DOC Specifica.tion Version 3.0 for more information.
1.3.2. VESA Extended Display Identification Data (EDID) Specification
Both DVl compliant systems and monitors must support the EDID data shlJCture. EDID 1.2 and 2.0 are recommended for interim support for systems. Complete requirements are detailed in section 2.2.5. The system is required to read the EDID data structure to determine the capabilities supported by the monitor. It is anticipated that the DVl specification will require support for the EDID J .3 data structw·e support within 12 months ofVESA adoption. Refer to VESA EDID Specification Version 3.0 for more information.
1.3.3. VESA Video Signal Standard (VSIS) Specification
Systems implementing the analog portion of the DVI specification must be in compliance with the VESA VSJS specification within 12 months ofVESA adoption. Refer to VESA VSIS Specification Version 1.6p for more information.
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1.3.4. VESA Monitor Timing Specifications (DMT)
Systems implementing the analog portion of tbe DVl specification should be in compliance with the VESA and Industry Standards and Guidelines for Computer Display Monitor Timings specification. Refer to VESA and lndustry Standards and Guidelines for Computer Display Monitor Timings Version 1.0 Revision 0.8 for more infom1ation
1.3.5. VESA Generalized Timing Formula Specification (GTF)
Systems implementing the analog portion of the DVI specification should be in compliance with the VESA Generabzcd Timing Fommla Specification. Refer to VESA Generalized Timing Formula Specification Version l.O Revision 1.0 for more information.
1.3.6. VESA Timing Definition for LCD Monitors Specification
LCD monitors should be in compliance with the VESA Timing Definition for LCD Monitor Specification. Refer to VESA Timing Definition for LCD Monitor Specification Version I Draft 8 for more information.
1.3.7. Compatibility with Other T.M.D.S. Based Implementations.
The DVI specification is based on a T.M.O.S. electrical layer. Every effo1t has been made to ensure interoperability with existing products that support similarT.M.D.S. signaling. [mplementations ofVESA DFP or VESA P&D specification should connect to the DVI specified coru1ector through a simple adapter.
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2. Architectural Requirements
2.1. T.M.D.S. Overview
The Digital Visual Interface uses transition minimized differential signaling for the base electrical interconnection. The T.M .D.S. link is used to send grapllics data to the monitor. The transition minimization is achieved by implementing an advanced encoding algoritlun that conve-tts 8 bits of data into a 1O-bit transition minimized, DC balanced character.
This interface specification allows for two T.M.D.S. links enabling large pixel format digital display devices, see Figure 2-1. One or two T.M.D.S. links are available depending on the pixel format and timings desired. The two T.M.D.S. links share the same clock allowing the bandwidth to be evenly divided between the two links. As the capabilities of the monitor are determined the system will choose to enable one or both T.M.D.S. links. T.M.D.S. Links _____A ___ ~ ( )
Data Channel 1
Data Channel 2 Pixel Data Pixel Data Graphics Display Controller Controller Control Control ~Qat~~h_gnnel_3__
~.-Data Channel 4 _
Data Channel 5
Figure 2-1. T.M.D.S. l,ogical Links
The transmitter incorporates an advanced coding algorithm to enable T.M.D.S. signaling for reduced EMI across copper cables and DC-balancing for data transmission over fiber optic cables. ln addition, d1e advanced coding algorithm enables robust clock recovery at the receiver to achieve high-skew tolerance for driving longer cable lengths as well as shorter low cost cables.
2.2. Plug and Play Specification 2.2.1. Overview
On initial system boot a YGA compliant device might be assumed by the graphics controller. To accommodate system boot modes and debug modes, the DVI compliant monitor must support the low pixel format mode defined in section 2.2.4.2. Both BIOS POST and the operating system are likely to query the monitor using the DDC2B protocol to determine what pixel formats and interface is supported. DVl makes use of the EDID data structure for tbe identification of the monitor type and capabilities. The combination of pixel formats supported by the monitor, pixel fon11ats supported by the graphics subsystem, and user input will detennine what pixel format to display.
Page 10 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group DVI provides for single or dual T.M.D.S. link implementations. The single Link can supp011 greater than high definition television (HDTV) pixel formats at a reduced blanking interval. The dual Link configuration is intended to provide support for the higher bandwidth demands of displays that do not support reduced blanking. The dual link configuration will enable support for large pixel format digital CRTs; the dual link is not limited to large pixel format digital CRT support. Digital CRTs are envisioned to be similar to classical CRTs except the graphi·cal data received by the display transducer is in the digital domain with the final digital to analog conversion occurring in the monitor. Digital CRTs require time to be allocated to horizontal and vertical retrace intervals. For a CRT to display the same pixel fonnat as a reduced blanking Flat Panel monitor, the retrace time allocation places a high peak bandwidth requirement on the graphics subsystem. The higher bandwidth requirement of the digital CRTs is achieved by using two T.M .D.S. links. With the use oftbe second link and today's technology transmitter, a digital CRT that is compliant with VESA 's Generalized Timing Formula (GTF) can support pixel formats of greater than 2.75 million pixels at an 85Hz refresh rate. A display device that slllpports reduced blankings and refi·esh rates can easily support more than 5 million pixels with two T.M.D.S. links.
On initial system boot, if a digital monitor is detected, only the primary T.M.D.S. link can be activated. The secondary T.M.D.S. link can become active after the graphics controller driver has determiJ1ed the capability for the second link e!lists in the monitor. The two T.M.O.S. links share the same clock allowing the bandwidth to be evenly divided between the two links. lf an analog DVI compliant monitor is attached to the system, the system should treat the analog DVI compliant monitor as it would a analog monitor connected ro the 15 pin VGA connector.
If the DV1 compliant monitor was not present during the boot process, the Hot Plug Detection mechanism exists to allow the system to determine when a DVI compliant monitor has been plugged in. After the Hot Plug-IJ1 event the system will query the monitor using the DDC2B interface and enable the T.M.D.S. link if required.
After the pixel format and timings have been detenuined there are two more parameters that effect the user perception of the picture quality, gamma and scaling.
The gamma characteristic of a monitor is display teclmology dependent. ln the past a CRT has been assumed as the primary display technology to be used. To ensure display independence, no assumption is made of display technology. The DVI requires a gamma characteristic of the data at the interface allowing monitors of varying display technologies to compensate for their specific display transfer characteristic.
If the monitor is identified in the EDID data structure as a fixed pixel format device that supports more than a single pixel format, then a monitor scalar is assumed to exist. A monitor scalar allows monitor vendors the ability to ensure the quality of the displayed image. For complete details on Scaling and EDID reqlLirelllent please see their respective sections later in this specification.
2.2.2. T.M.D.S. Link Usage Model
To maintain compatibility with EDID data structure the DV1 must be able to select between one or two Links based solely on the pixel format and timing information. The compatibility of a monitor and system must be easily identified by the system and reported to the user. To ensure identical pixel formats are supported in an identical fashion by the host and the monitor, the T.M. D.S. link #0 must be used to support all pixel formats and timings reqttiring up to and including 165MHz. Any pixel format ru1d blanking interval requiring more than a 165MHz-clock frequency must be supported using two T.M.D.S. links. If a pixel format and timing requiring greater than 165MHz-clock is supported, each T.M.D.S. link must operate at
Page 11 of 76 Digital Visual Interface Revision 1.0 Digital Display Working Group half the frequency required to suppo1t the pixel format and tinting. For example, if a pixel format and timing requiring a 200M Hz pixel clock is supp01ted, then both links must operate at lOOMHz. One link at l 65MHz and the sec,ond link at 30MHz is not allowed. As such, the second links minimum operating frequency is 82.5MHz.
Note: Lt is perfectly acceptable for a single link to have a maximum operating frequency of less than 165 MHz. For example a system desiring to support a maximum pixel format of 800x600 at 60Hz refTesh using VESA's defined timings would only need to implement a link speed of 40 MHz. If a monitor that supported multiple higher pixel formats were attached then pixel formats up to greatest common dominator {800x600) could be used.
The system is required to manage the Limitations of the graphics controller, transmitter, and monitor. The user should not be able to select a pixel fommt greater than can be supported by the least capable component in the graphics subsystem.
Crossover Frequency Architectural Note:
The goal of the cross over frequency is to ensure both the system and the monitor s upport any specific pixel format using the same number of links. For example, if no si.ngle crossover frequency existed and a monitor suppo1ted 1600xl200 at 60Hz refresh using VESA's defined timings the monitor might choose to implement the required 162 MHz link as two 81 MHz links. If a system supported the same pixel format and timings but using only one 162 MHz link then an incompatibility has been created. The system and monitor would both support the same exact pixel format and timing but the combi.nation would not be able to support the pixel format. Prior to booting the system (at purchase time), no indication would be available to a user to determtne if the monitor and system could interoperate. With no defined crossover frequency, it would take individuals \vith intimate knowledge of the design of both the grapbjcs solution and the monitor to determine if a specific pi.xel f01111at could be suppmied.
Monitor Single Link Dual Link Note # l System Single Link OK OK; Monitor at Note#! l.ow pixel format Note #2 Dual Link OK; System OK pixel fom1at limited by monitor l'uh/e 2-1. Single ami Dual Link Operation.
Table 2-1 identifies the potential T.M.D.S. link combinations of monitors and system. The monitor T.M.D.S. link possibilities are represented across the top row. The system T.M.D.S. link possibilities are represented down the left-hand column.
During the boot process, when the graphics subsystem is initialized only T.M.D.S. link {link #0) wi II be active. T.M.D.S. link # I can become active only after the graphics subsystem determines a pixel format and timing requiring more than 165M Hz T.M.D.S. clock is supported by the system and monitor and the pixel fonnat has been requested by the user.
Note # !. In single link implementations the link must be limited to 165MHz T.M.D.S clock or less operation. Additionally, the first link of a duan Link implementation must support
Page 12 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 165MHz T.M-D.S. clock operation. The single link only mode must be used for 25MHz to 165MHz T.M.D.S clock operation and the first link can operate at above l65MHz T.M.D.S clock only in the case of the total bandwidth requirement surpassing 330MHz T.M.D.S clock.
Note #2. The two-link monitor plugged into the one link system still boots and displays images. The images are pixel format limited by the graphics driver to the maximum system single link frequency of up to 165MHz T.M.D.S clock operation. A configuration illtility may optionally report to the user the nature of the system limitations. A message only stating there is a system limitation is OK, ideally a message should be displayed by the operating system or a display utility to inform the user specifically the issue is the graphics sub-system does not support the larger pixel format.
2.2.2.1. T.M.D.S. Link System Requirements
A DVl compliant system must implement a minimurm of a single T.M.D.S. link, link #0. The minjmum low pixel format mode must be supported. The maximum pixel format supported is implementation specific. If the system supp01ts pixel formats and timings that require greater than a 165MHz T.M.D.S. clock then implementation ofthe second T.M.D.S. link is required. There is no specified maximum for the dual link implementations.
A system supporting dual T.M.D.S. links must be able to dynamically switch between supported pixel formats including switchjng between pixel formats that require single and dual link configurations. When a dual T.M.D.S. link capable system is driving only a single link, the secondary link must be inactive.
2.2.2.2:. T.M.D.S. Link Monitor Requirements
A DVl compliant monitor must implement a minimum of a single T.M.D.S. link, li.nk #0. The minimum low pixel format mode must be supported. The maximum pixel format supported .is implementation specific . lfthe monitor supports pixel formats and timings that require greater than a I 65MHz T.M.D.S. clock then implementation of the second T.M.D.S. link is required.
A dual link T.M.D.S. monitor must be able to detect the activity of each link and dynamically switch between supported pixel formats including switching between pixel fonnats. that requi.re single and dual link configurations.
2.2.3. High Color Depth Support
Color depths requiring greater than 24-bit per pixel are allowed to be supported via the second link. Future versions of this specification reserve the right to require different implementations of high color depth support that are not backwards compatible with thjs version of the speci fication.
The colors per pel are logically concatenated with the most significant bits p rovided over the primary T.M.D.S. Link (link #0) and the least signjficant bits provided over the secondary T.M.D.S. link (link #1). If implemented, the data format on the secondary T.M.D.S. links must the same 24-bit MSB aligned RGB TFT data format as defined for the primary link.
The system must identify the capabili ty exists in the monitor before the high color depth is enabled. lfthe monitor does not support the high colo r depth, the system must be able to operate in the required 24-bit format.
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Low-pixel format modes are supported to allow a default operation mode. This default operation mode enables the user to view a legible display of BIOS messages and progress as well as Operating System initial loading messages. A legible picture does not require the image to be scaled to fulJ screen or centered.
Once the Operating System loads the graphics controller driver the driver may switch into a different pixel format and timing mode. The video BIOS is required to respond to all legacy VESA BIOS calls and INT tO BIOS (IBM PS/2 Legacy BIOS) calls, however it is acceptable for the hardware to emulate the legacy mode.
2.2.4.1 . System Low Pixel Format Support Requirement
Industry Standard T imings for 640x480 pixel format at 60 Hz Refresh with a pixel clock of 25. L75 MJlz and Horizontal Frequency of 31.5 kHz.
To insure compatibility the system must re-map int 10 mode 3 BIOS calls to required low pixel format support mode.
2.2.4.2. Monitor Low Pixel Format Support Requirement
Industry Staudard T imings for 640x480 pixel format at 60 Hz Refresh with a pixel clock of 25. 175 MHz and Horizontal Frequency of3l.5 kHz.
2.2.5. EDID
At the time of the creation of the DVl specification there is a development effort underway by VESA, the standards body responsible for the creation of monitor identification standards. The EDTD 1.3 data structure specification that is under development purportedly addresses several ofthe display technology independent issues germane to the DVI specification. It is anticipated that the DVI specification will require support for the ED!D 1.3 data structure support within 12 months ofVESA adoption.
2.2.5.1 . EDID System Requirements
A DVI compliant system must support the EDID data structure. EDID 1.2 and 2.0 are recommended for interim support for systems. No assumption above the low pixel fonnat requirement (640x480) pixel format can be made about monitor support. The system is required to read the EDID data structure to determine the capabilities supported by the monitor.
Current digital monitors based on the T.M.D.S. electrical specification use both the ED!D 1.2 data structure and the EDID 2.0 data structure. Any system desiring to support both groups of existing monitors must support both EDID data strucrures.
2.2.5.2:. EDlD Monitor Requirements
A DVI compliant monitor must support the EDID data structure. EDID 1.2 and 2.0 are recommended for interim support for systems. The DVI Iow-pixel format requirement does not have to be listed in the EDID data structure but the monitor must present a legible image. If the monitor is a fixed pixel format monjtor then the EDLD "PrefetTed Timing Mode" bit
Page 14 of 76 Digital Visual Interface Revision 1.0
must be set (EDID 1.2 data stmctme offset 18h bit I: EDlD 2.0 data stmcture offset 7Eh bit 6) and the native pixel format of the monitor must be reported in the first detailed tiiming field.
2.2.6. DOC
2.2.6.1 . System DOC Requirements
DDC2B support is required. The DDC +5 volt signal is required in a DVI compliant system.
Note: The power pin must be able to supply a minimum of 55 mA and the monitor may not draw more than 50 mA.
2.2.6.2. Monitor DOC Requirements
DDC2 B support is required. A DVI compliant monitor is not a!Jowed to issue DOC I transactions. Within 250 mS of the application of the DOC required +5 volt, the monitor must be able to respond to transactions to the EDID data structure by DDC2B.
Note: The DDC required +5 volt power pin must be able to supply a minimum of 55 mA. If the monitor is powered off, the monitor may not draw more than 50 mA. If the monitor is powered on, the monitor may not draw more than I 0 mA.
2.2.7. Gamma
Tbe tenu "gamma" is frequently misused; for an excelJent desciiption oftbe te1m and its usage please refer to the sRGB specification which can be found at http://wwvv.srgb.com/. By way of summary, CRT monitors (and TV displays) bave an inherently non-linear color transfer function, requiring pre-compensation of input data in order to generate a normalized image. However, computer generated graphical data (spreadsheets, word processor documents, etc) are generated in a mathematically linear color space. Since this data is typically displayed on a CRT device, the graphics controller applies a display transfer function known as gamma conection, to pre-compensate the data as it leaves the graphics controller. The typical CRT display tJansfer functions areJepresented by an exponential 1 ti.mction of the form Y=x , where xis tbe input signal, Y the output signal andy (gamma) is the display transfer characteristic, which is approximately 2.2 for CRT's.
Generating accw·ate color renditions between different types of output devices is an ongoing research and development topic in the industry. Standards bodies, including the l ntemational Color Consortium, are working to standardize approaches. lt is, therefore, beyond the intent and scope of this specification to define standards in this area.
However, pending further definitive requirements, it is recommended as a default position, that digital monitors of all types suppmt a color transfer function similar to analog CRT monitors (y = 2.2) which make up tbe majority of the computer display maJket. This will avoid, to a great extent, poor color representations on digital monitors, and the necessity of graphics controllers supporting alternate transfer functions.
2.2.8. Scaling
Fixed pixel fonnat {i.e. spatially sampled) monitors have two basic modes of operation, 1 .display of native pixel format data and 2. display of data scaled to the native pixel format of the monitor. Scaling to the native pixel format is the responsibility of the monitor. It is presumed a quality scalar is a value-added feature for the monitor. Fixed pixel format digital
Page 15 of 76 Digital Visual Interface Revision 1. 0
monitors should make eve1y effort to provide a quality scalar thus allowing tbe end-user experience to match that oftbe typical analog nmlti-sync monitor!<.
2.2.8.1 . System Scaling Requirements
The host may assume that the monitor can display the required low pixel format mode even if it is not listed in the EDlD data structure. lf the monitor does not suppmt a requested pixel format, then the graphics controiJer may I. scale the image to the monitor's native pixel format, 2. center the image or 3. report the pixel format as w1available. The system may provide a utility to allow the end user to select between the monitor scalar, if it exists. and the system scalar. The default mode of operation is to use the monitor's scalar when available.
Note: To eliminate the potential for cascaded scalars, if the system scales the image then the system must scale the image to the monitor's defined prefeiTed mode timing (native pixel fonnat in a fLXed pixel format panel).
2.2.82. Monitor Scaling Requirements
If the monitor is identified as a fixed pixel fonnat device that supports more than a single pixel fonnat, a monitor scalar is required to exist for those supp011ed pixel formats, and should always be used. The monitor should scale to all standard pixel formats between its maximum pixel format and the low pixel format requirement. The monitor must only claim support, in the EDTD data structure, for a pixel format that can be ,displayed full screen in at least one dimension.
Lf the monitor does not have a scalar, the monitor must only reporl its single fixed pixel format in the EDl D data, but the monitor must still present a legible picture when presented with the required low-pixel format mode.
Note: Jf a DVl compliant monitor only supports (i.e. full screen in at least one direction) its native. fixed pixel format and if the required low pixel format mode is a legible but not full screen display, then the mon.itor must only List support for its native, fixed pixel format in the EDID data structure. If the required low pixel format mode is d.isplayed full screen in at least one dimension. it can be listed in EDID.
Note: Jfthe monitoT is a ftxed pixel format monitor then the EDID "Preferred Timing Mode" bit must be set and the native pixel format of the monitor must be reported in the ·first detailed timing field. (EDTD "Preferred Timing Mode" bit is located in EDlD 1.2 data stn1cture at offset 18h bit l and in EDJD 2.0 data structure offset 7Eh bit 6d) This prefened mode timing identification requirement is designed to allow the system to determine the native pixel fonnat of a flat panel display (by design, a fLXed pixel format device).
2.2.9. Hot Plugging
Hot Plug Detection (HPD) is a system level function requiring industry specifications at both hardware and software levels. lt is beyond the scope of this specification to define a complete system solution. This section is therefore limited to tbe specification of the bot plug signal tbat provides the hardware underpinning for a complete system solution. The operation of the hot plug pin, as described below, is required by this specifi cation. Any specific system response to the hot plug pin is optional.
Future software specifications are anticipated, which should provide the complete system solution. Ln the interim, the graphics driver is free to generate its own application based on the hot plug signal.
Page 16 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group
Hot Plug Events Monitor Attachment: When a "Monitor Attach" Hot Plug event is detected the graphics subsystem must generate a system level event (OS dependent) to allow the operating system to read the monitor's EDID data. If the graphics subsystem and monitor support compatible pixel formats the operating system s hould enable the monitor and the T.M.D.S. link if required.
Monitor Removal: When a "Monitor Removal" Hot Plug event is detected the graphics subsystem must generate a system level event (OS dependent) to notify the operating system of the event. Additionally, if the DVI complaint monitor is a digital monitor, when "Monitor Removal" is detected the graphics subsystem must disable the T .M.D.S. transmitter within I second.
2.2.9.1. System Hot Plugging Requirements
Any specific system response to Hot Plug Detection is fun1re OS dependent. It is anticipated this ftmctionality will be required in the future, as Operating System API's become available to take advantage of this feature.
When the host detects a transition above +2.0 volts or below +0.8 volts the graphics subsystem must generate a system level event (OS dependent) to inform the Operating System ofthe ·event. Additionally, if the DVl complaint monitor is a digital monitor, when ''Monitor Removal" is detected the graphics subsystem must disable the T.M.D.S. transmitter within 1 second.
Note: The VESA Plug and Display specification aLlows for up to +20 volts to be applied to its Charge/Hot Plug Detect Pin, although no such implementations are kno\¥11 to exist. To ensure the safety of the transmitter and to enable compatibility with a P&D monitor, it is r 2.2.9.2:. Monitor Hot Plugging Requirements The monitor must provide a voltage of greater than +2.4 volts on the Hot Plug Detect (HPD) pin of the connectOT only when the EDID data structure is available to be read by the host. When the EDTD data structure can not be read then voltage on the HPD pin must be below +0.4 volts. Implementation Note: As an exampDe for bot plug support, a simple monitor implementation of HPD support coll.lld be a pull up resistor to the EDID power supply. 2.2.10. HSync, VSync and Data Enable Required It is expected that digital CRT morutors will become available to connect to tbe DVl interface. To ensure display independence, tbe digital bost is required to separately encode HSync and VSync in tbe T.M.D.S. channel. The digital host is required to encode Data Enable (hereinafter DE) in the T.M.D.S. channel. DE must be an active high signal. Note: The bit mapping within the T.M.D.S. is specified in section 3.2. Page 17 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 2.2.11. Data Formats 2.2.11.1. System Data Format Support The system must support the 24-bit MSB aligned RGB TFT data fonnat as a minimum. The 24-bit MSB aligned RGB TFT data f01mat is defined in the VESA EDID specification version 3.0. Note that lower color depths are also defined there. If the monitor implements the EDID 1.2 data structure the system must assume the monitor supports the 24-bit MSB aligned RGB TFT data format. 2.2.11.2. Monitor Data Format Support lftbe monitor chooses to implement the EDJD 1.2 data structure tben the monitor must accept the 24-bit MSB aligned ROB TFT data fonnat as defined in the VESA EDID specification version 3.0. lfthe mon.itor implements the EDID 2.0, 1.3 or newer data structure the monitor may specify any data format that is definable within the EDJD data structure used. In all cases the monitor must support the 24-bit MSB aligned RGB TFT data format as a minimum. 2.2.12. lnteroperability with Other T.M.D.S. Based Specifications The DVL specitication is based on a T.M.D.S. electrical layer. Every effort has been made to ensure interoperability witb existing products tbat support sirnilarT.M.D.S. signali ng. DC coupled implementations ofVESA DFP or VESA P&D specification should connect to the DVl specification through a cable adapter. While every effort is being made to ensure the interoperability of the T.M.D.S. link, the access·ory functions available in other specifications wi ll not function. For example the IEEE J 394 iJHerface potentially in the P&D connector will not have a connection point in the DVl interface and as such will not function. Likewise, USB does not have a connection in the DVI connector. Any interface with USB on the monitor side will have to use an alternative means of cormecting USB to the system. The DVl compliant system may have two T.M.D.S. links. Any non-DVI compliant monitor that was based on T.M.D.S. electrical would not be able to take advantage of the bandwidth available from the second link. To ensure the safety of the transmitter and to enable compatibility witb a P&D monitor, it is required that any adapter connecting a P&D monitor to a DVl compliant system complies with requirements in section 2.2.9. 2.3. Bandwidth 2.3.1. Minimum Frequency Supported The minimum frequency supported js specified to allow the link to differentiate between an active low-pixel format link and a power managed state (inactive link). The lowest pixel format required by the DVl specification is 640x480@60 Hz (clock timing of25.175 MHz). The DVl link can be considered inactive if the T. M. D.S. clock transitions at less than 22.5 MHz for more than one second. Page 18 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 2.3.2. AUernate Media The T.M.D.S. transmjssion protocol is DC balanced and capable of being transmitted over fiber optic cable. Specific details of a fiber optic implementation are not covered in this specification, but left to the designer. Fiber optic implementations can be DVI compliant as long as the plug and play abi Iity of the interconnect is stiJJ supported. For example, the system must be able to read EDlD data and detect a bot plug event. For alternative media to be DV1 compliant it is envisioned that the alternate media will serve as a connector to connector adapter. 2.4. Digital Monitor Power Management The following digital monitor power management (hereinafter DMPM) definition is for power management as applied over the T.M.D.S. link for any monitor type. Power management applied over the analog link is defined in section 2.5.4. Six monitor power states are defined to provide programmatic control of monitor power and ensure the availability of the monitor identification data. For completeness, the monitor power states include states entered via the power switch. Monitor On Power State. T.M.D.S. link is active. T ransmitter powered and active. Receiver powered and active. This power state is equivalent to the DPMS "On" power state. EDI D data is guaranteed to be available. DOC +5 volt signal is present, monitor drawing less than J 0 rnA current from DDC + 5 volt pin. The monitor can leave this state if I. The Link becomes inactive as defmed in 2.4. L, 2. The DDC +5 volt sigual is removed, or 3. The monitor power switch is toggled. Intermediate Power State. T.M.D.S. link is inactive. Transmitter should be powered down. Receiver remains powered with receiver outputs optionall y disabled. The receiver must be able to detect the activation of the link and return the monitor to the "On" Power State. A timer controls the duration of the Intermediate Power State. This power state is similar to the DPMS "Suspend" power state allowing for the controller circuitry in the monitor to be powered as necessary to enable a quick recovery while dissipating less power than the "On" Power State. EDlD data is guaranteed to be available. DOC +5 volt signal is present, monitor drawing less than J 0 mA current from DOC + 5 volt pin. The morutor can leave this state jf l. The link becomes active, 2. The DDC +5 volt signal is remov,ed 3. The monitor power switch is toggled or 4. Monitor timer expires. Active-Off Power State. T.M.D.S. link is inactive. Transmitter should be powered down. Receiver remains powered with receiver outputs optionall y disabled. The receiver must be able to detect the activation of the link and return the monitor to the "On" Power State. This power state is equivalent to the DPMS "OfC' state ("Active Off'' in EDlD 2.0 data structure). EDLD data is guaranteed to be available. DOC +5 volt signal is present, monitor drawing less than 50 mA current from DOC + 5 volt pin. The morutor can leave this state if I. The llnk becomes active, 2. The DOC +5 volt signal is removed, or 3. The monitor power switch is toggled Non-Link Recoverable Off Power State. T.M.D.S. link is inactive. Transmitter should be powered off. Receiver should be powered off. The Non-Link Recoverable Off Power State is entered when the DOC +5 volt signal has been removed from the monitor. EDl D data is NOT Page 19 of 76 Digital Visual Interface Revision 1.0 Digital Display Working Group guaranteed to be available. The "Non-Link Recoverable Off' Power State is not recoverable via activity on the T.M.D.S. liok. This power state is equi valent to the DPMS "Off(with No DPMS recove•y)" power state identified in the EDID 2.0 data structure. The monitor can leave this state if L TheDDC +5 volt signal is reapplied or 2. The monitor power switch is toggled Monitor Power Switch Off Power State. This state is entered only when the power switch on the monitor is toggled to its off position. This power state has two sub-states, with DDC +5 volt signal present and without DDC +5 volt signal present. If the DDC +5 volt signal is present then EDID data is guaranteed to be available and the monitor must draw less than 50 mA current from the DDC +5 volt pin. lfthe DDC +5 volt signal is not present then EDID data is NOT guaranteed to be available. The monitor may toggle between the two sub states as appropriate depending on the state of the DOC +5 volt line. The monitor may exit this power state only when the monitor power switch is toggled to the ON position. Power Management Architectural Note: Table 2-2 is provided as a reference only to help clarify the relationship between tbe VESA DPMS specification and the DV I. DMPM. DMPM is similar to DPMS power management in that no requirement is placed on the power saving that must be achieved, and no requirement on the recovery time that must be met. These areas are left to the implementer to innovate. Tbe Intermediate Power State and the Active-Off power state can be combined by setting the timer value to zero. The power switch state is simply for completeness and tJ1e Non-link recoverable Off power state is itself an innovation allowing monitors tbat wisb to take advantage of this potentially substantial power savings state to do so. Also the Non-Link Recoverable Off and the Monitor Power Switch Off power states can be combined by not putting a user-accessible power switch on the monitor. The timer can be either hard wired at manufacture time, set to zero, or it could be progranunable. A dual input monitor could support only DPMS power management and as such would be in complete compliance with the DVI specification. The caveat would be that you would never directly enter DPMS suspend (or stand-by) on the DVI interface. Although DPMS does not list monitor power switch power states, these stales still exist and must be correctly dealL with in a DPMS implementation. Page 20 of 76 Digital Visual Interface Revision 1.0 DPMS STATE DPMS SPEC OYf- OMPM DVl-DMPM Monitor Power Mandatory Monitor Power on Mandatory Stand-By Optional Not D efined by DMPM Suspehd Mandato1y Intermediate Optional Power State (I) Off Mandatoty Active-Off Mandatory Non-DPMS Not Defined by Non-Link Optional Recoverable Off DPMS Recoverable Off (Listed in EDID 2.0) Not Defined by Not Defined by Monitor Power Optional DPMS DPMS Switch Off table 2-2. DPMS and DMPM comparison. ( I) The DMPM intem1ediate power state is a logical mapping to the DPMS suspend power state, not a direct mapping. 2.4.1. Link Inactivity Definition An inactive T.M.D.S. link is defined as a link on which no logical transitions have occurred on the T.M.D.S. Data Enable (DE) for more than one second . or the T.M.D.S. clock line frequency falls below 22.5MI-lz for more than one second. Note: lt is acceptable for a monitor to consider a link inactive if the link is operating at an invalid frequency. (I.e. one that is below the minimum required frequency as defillled in section 2.3.1 Minimum Frequency Supp01ted or a frequency not supp01ted by the monitor). 2.4.2. System Power Management Requirements A DVJ compliant system must disable the T.M.D.S. link to transition the digital monitor into a low power mode. 2.4.3. Monitor Power Management Requirements Two power states are required by any DVT compliant digital monitor: I) Monitor On Power State, and 2) Active-Off Power State. Additional power states may be optionally supported. Figure 2-2 is a monitor power state state-diagram. A larger, p1intable version of Figure 2-2 in included in Appendix C for clarity. If a monitor only suppo1ts the minimum requirement of two power states, then the monitor must only report active-off in the EDID data structure. If a monitor supports the Intermediate Power State, then the monitor must indicate Suspend suppo1~t in the EDID data struchu·e. If the monitor supports the Non-Link recoverable Off State, then the monitor must indicate Off with no DPMS recove1y in the EDID data stTucture. The monitor should enter a defined Power Management mode if the T.M.D.S. inte1face becomes inactive for greater than five seconds. Page 21 of 76 Digital Visual Interface Revision 1.0 Note: [tis anticipated that the monitor timer register will be defined in the EDID I .3 data structure as an optionaLly writeable byte with 30-second resolution. Zero seconds is an acceptable timer value. link / Active ®i '·... - +~V· :00-TRUE J'o~rS.f.;1>:h! Off ~------~ AHD +5V- FA!SE I +5v ~FALSE +5v = .FAlsE / ' ,. ~· Note: Transitions on the +5 volts signal take precedence over Link Active/Inactive and timer ilransitions Figure 2-2. Sratc! Diagrctm, Monitor Power States 2.5. Analog 2.5.1. Analog Signal Quality Systems implementing the analog portion of the DVl specificatiom must be in compJjance witb the VSJS 3pecification. Refer to VESA VSIS Specification Version I .6p for more information. 2.5.2. HSync and VSync Required Both the system and the analog monitor are required to support separate HSync and VSync. 2.5.3. Analog Timings Systems implementing the analog portion of the DVI specification should be in compliance with the VESA lndust1y Standards and Guidelines for Computer Display Monitor Timings speciflication, or the VESA Generalized Timing Formula Standard. Page 22 of 76 Digital Visual Int erface Revision 1. 0 Digital Display Working Group 2.5.4. Analog Power Manageme11t Systems implementing the analog portion oftbe OVI specification should be in compliance with the VESA OPMS Specification. Refer to VESA OPMS Specification Version 1.0 for more information. 2 6 s·1g na I L.IS t Signal Name Signal Description T.M.D.S, Signals T.M.D.S. Clock+ & - T.M.D.S. clock differential pair T.M.D.S. Clock Shield Shield for T.M.D.S. clock differential pair T.M.D.S. DataO + & - T.M.D.S. link #0 channel #0 differential pair T.M.D.S. Data0/5 Shield Shared shield forT.M.D.S. link #0 channel #0 and link # I channel #2 T.M.D.S. Datal + & - T.M.D.S. link #0 channel #I differential pair T.M.D.S. Data2/4 Shield Shared shield for T.M.D.S. link #0 channel #2 and link #I channel # I T.M.D.S. Data2 + & - T.M.D.S. link #0 channel #2 differential pair T.M.D.S. Data l/3 Shield Shared shield for T.M.D.S. link #0 channel #I and link #I channel #0 T.M.D.S. Data3 + & - T.M.D.S. link # l channel #0 differential pair T.M.D.S. Data4 + & - T.M .D.S. li.nk # I channel #I differential pair T.M.D.S. Data5 + & - T.M.D.S. Link #I channel #2 differential pair Control Signals Hot Plug Detect (HPD) Signal is driven by monitor to enable the system to identi fy the presence of a monitor. DOC Data The data line for the DOC interface. DOC Clock The clock line for the DDC interface. +SV Power + 5 volt signal provided by the system to enable the monitor to provide EDID data when the monitor circuitry is not powered. Ground (for +5V) Ground refereDce for +5 volt power pill. Used as return by HSync and VSync Signals Analog Signals Analog Red Analog Red signal. Analog Green Analog Green signal. Analog Blue Analog Blue signal. Analog Horizontal Sync Horizontal synchronization signal for the analog interface. Analog Vertical Sync Vertical synchronizati on signal for the analog iDterface. Analog Ground Common ground for analog signals. Used as a return for analog red, green and blue signals only. Page 23 of 76 Digital Visual I nt erface Revision 1.0 3. T.M.D.S. Protocol Specification 3.1 Overview 3.1.1 Link Architecture A T.M.D.S. transmjtter encodes and serially transrllits an input data stream over a T.M.D.S. link to a T.M.D.S. receiver (Figure 3-1). The T.M.D.S. encoding specification defines encoder and decoder functional requirements for transmissioa ofthe T.M.D.S. input stream over the link. Although the input stream to each link is represented as 24-bits wide within this specification, this is not intended to limit i11 any way the interface formats to the T.M.D.S. transmitter or receiver components. Transmitters and receivers are not req11ired to present a 24-bit parallel interface to be compliant with this specification. The functionality of additional input and output layers also is not specified. Recovered Input Streams T.M.D.S. Link A A SlA ms ( \ ( \ ( \ r- DE DE (jj. >. ~ ~ j -~ Pixel Data (24 bits) J ~ Output ~ _ Channe l 2~ ~ ~ (fj Format ci Control Data (6 bits) 1~ CLK r '5 Channel C ~ ~ a. ~ '5 0 \ '------T.M.D.S. Frequency Single T.M.D.S. Data Link Reference Figure 3-1. TM.D.S. Link Architecwre The input stream contains pixel and control data. The n·ansmitter encodes either pixel data or conn·ol data on any given input cloclk cycle. depending on the state ofthe data enable signal (DE). The active data enable signal indicates that pixel data is to be transmitted. Note that control (pixel) data is ignored when pixel (control) data is being tmnsmitted. At the T.M.D.S. receiver, the recovered pixel (contTOI) data may transition only when DE is active (inactive). The transmitter contains tlu·ee identical encoders, each driving one serial T.M.D.S. data channel. The input to each encoder is two conn·ol signals and eight bits of pixel data. Depending on the state of DE, the encoder will produce I O-bit T.M.D.S. characters from either the two control signals or from the eight bits of pixel data. The output of each decoder is a c011tinuous stream of serialized T.M.D.S. characters. 3.1.2 Clocking The T.M.D.S. clock channel carries a character-rate frequency reference from which the receiver produces a bit-rate sample clock for the incoming serial streams. Due to the high pair-to-pair skew tbat must be tolerated, the phase of the derived sample clock must be adjusted individually for each data channel. The methods of clock generation for data recovery are implementation specific and beyond the scope of this document. Page 24 of 76 Digital Visual I nt erface Revision 1.0 Digital D isplay Working Group 3.1.3 Synchronization The T .M.D.S. receiver must detennrne the location of character boundaries in the serial data streams. Once character boundaries are established on all data channels, the receiver is defined to be synchronized to the serial streams, and may recover T.M.O.S. characters from the data channels for decode. The T.M.D.S. data stream provides periodic cues for decoder synchronization. The T.M.D.S. characters selected to represent pixel data contain five or fewer transitions, while the T.M.D.S. characters selected to represent the control data contain seven or more transitions. The high-transition content of the characters transmitted during the blanking period form the basis for character boundary synchronization at the decoder. While these characters are not in dividually unique in the serial data stream, they are sufficiently alike that tbe decoder may uniquely detect the presence of a succession of them during transmitted blanking intervals. Tbe exact algorithm for this detection is an implementation detail beyond the scope of this document, but minimum conctitions for receiver synchronization are defined. 3.1.4 Encoding The T.M.D.S. data channel is driven with a continuous stream of 1O-bit T.M.D.S. characters. During the blanking period there are four distinct characters that are transmitted, which map ctirectly to the four possible states of the two input control signals input to the encoder. During active data, when eac.h I O-bit character contains eight bits of pixel data, the encoded characters provide an approximate DC balance as well as a reduction in the number of transitions in the data stream. The encode process for the active data period can be viewed in two stages. The first stage produces a transitjon-minimized nine-bit code word from the input eight bits. The second stage produces a I O-bit code word, the finished T.M.D.S. character, which will manage the overall DC balance of the transmitted stream of characters. The nine-bit code word produced by the first stage ofthe encoder is made up of an eight-bit representation ofthe transitions found in the i11put eight bits, plus a one-bit flag to i.ndicate wl1ich of two methods was used to describe the transitions. In both cases the least s.ignificant bit oftrhe output matches the least significant bit of the input. W itb a starting value established, the remaining seven bits of the output word is derived from sequential exclusive OR (XOR) or exclusive NOR (XNOR) functions of each bit of the input with the pTeviously derived bit. The choice between XOR and XNOR logic is made such that the encoded values contain the fewest possible transitions, and the ninth bit of the code word is used to indicate whether XOR or XNOR functions were used to derive the output code word. The decode of this nine-bit code word is simply a matter of applying either XOR or XNOR gates to the adjacent bits of the code, with the least significant bit passing from decoder input to decoder output unchanged. The second stage of the encoder during active data periods on the interface perfom1s an approximate DC balance on the transmitted stTeam by selectively inverting the eight data bits of the nine-bit code words produced by the first stage. A tenth bit is added to the code word, to indicate when the inversion has been made. The encoder determines when to invert the next T.M .D.S. character based on the running disparity between ones and zeros that it tracks in the transmitted stream, and the number of ones and zeros found in the cwTent code word. If too ma11y ones have been transmitted and the input contains more ones than zeros, the code word is inve1ted. This dynamic encoding decision at the transmitter is simply decoded at the receiver by the conditional inversion of the input code word based on the tenth bit of the I.M.D.S. character. 3.1.5 Dual-Link Architecture The number of data channels in the T.M.D.S. link architecture was originally chosen based on the combination of bandwidth required for video data and the logical simplicity of using one data channel each for red, green and blue pixel data. The dual T.M.D.S. link identified by this Page 25 of 76 Digital Visual Interface Revision 1.0 Digital Display Working Group specification uses six data channels sharing a single clock channel to double the bandwidth of the inte1face. For this configuration, the first data link transmits odd pixels while the second data li nk transmits even pixels. The first pixel of each line is pixel number one, an odd pixel. 3.2 Encoder Specification 3.2.1 Channel Mapping Tbe single-link T.M.D.S. transmitter consists of three identical encoders to which tbe input stream signals are mapped (Figure 3-2). Two control signals and eight bits of pixel data are mapped to each encoder. A dual-link transmitter incorporates an additional three data cbaUDels (Figure 3-3) . The dual link configuration transmits the odd pixels of each horizontal line on the first link and the even pixels of eacb line on tbe second link. The first pixel of each line is pixel number one, an odd pixel. Recovered lrnput Streams T.M.D.S. Link Streams T.M.D.S. transmitter T.M.D.S. receiver r ~ llLLH7:01 Df7:0J D[7:0f 111UI7ill llLUI7:01 --...... Ql IISn.IC Ql N --~ .... II.SYNC II SYNC co 1J Ql Q) co 0 =Ill VSYNC - 1- ~+ >"O VSYNC - VSYNC" Cl o ·c 0 0 Cl p c Ql u u DE - wen Ql Ql OliO DE cro DE - Channel 0 ...... GRNI7:01 ..._ Vfl:llj liRNI7.tll c: GRNI7:01 D/7:0/ ..._ .... Q) ... Ql ~ .... C JI.O C"J1 () C"ITO Ql N Channel 1 Ql Ql Cll E Cti "C = >"O c: CTLI 0 Ill Cl CILl C"ll" I C/ o ·~ 8 8 .2> c Ql Channell Ql Ql DEl !)£ wen cro DJ:: Iii Qi Channel C REDI H il c: REDI7:0l ..._ V(l:O! c: p RFDr7:0l 0(7:01 ..._ .... ro en., ... Ql ~'- Cll.' J:: Ql Ql co (.) CTl."' Ql N >"0 ("11' co '0= 0 0 ('J 1.!. e-n' u u Q) cru Ci 8 ·~ ~ + Ql Q) DL'1· c Ql - n::o DE c DE wen - DE CLK C"LK r ~ Figure 3-2. Single link J:MD.S. Channel Map The use of all control signals other than horizontal sync (HSync) and vertical sync ( VSync) is reserved. The control signals CTL 1, CTL2, and CTL3. must be held to logic low at the transmitter input. It is recommended that CTLO be also held to logic low, however for legacy reasons, some trans mitter chips may send a control signal over CTLO. If this signal is sent over the CTLO line, the only condition placed on it is that the rising edges oftbis signal occur at either the even edges or the odd edges of the single pixel input clock, it must not switch back forth between even and odd while the link is active. Page 26 of 76 Dig ital Visual Interface Revision 1. 0 Digital Display Working Gr oup Recovered lrnput Streams Dual T.M.D.S. Link Streams T.M.D.S. transmitter T.M.D.S. receiver ~ i ( Rl.l lf7·nl D[7.·11J -. ..._ 0{7:11/ RIJ ll7i ll R l 1117•111 .... Ql -. I ISYNC" Ql N ~ .... Cll fiSYNC" HSYNC: co -o = Ql Ql VSYNC i- >"0 VSYNC VSVNC: Cl 8 -~ - + 0 0 Cl c Ql 0 0 DE lLJC/) DEO DE a:::oQl Ql DE .- Channe/0 CiRNr7>1ll CiRNf7:01 ORNI7·01 -. 0{7:/)j 0{7:11] -. ..._ .... Ql ~ .... CTLO CTLO rfLil Ql N Channel 1 Ql Q) Cll en u = >U CILI I 0 (I) 0 0 CJ C'TLI CTU CJ (.) "\: 0 0 I c Ql Channel 2 Ql Q) DE DEl Of lLJ C/) 0:::0 I R l!DI7~11 REDf7:01 -. 0{7:11} REDf7:01 /)(7:1/f -. ..._ e;. ..._ C'll'' C'"ll?. .... Ql Ql Q) co c Cfl? QJ N Q) >U c.~r•u CTlJ co u:: Cl CTl3 0 l1l 8 8 E Cl 0 ·c: ~ -. Ql Q) DE2 c c Ql i- DE I lLJC/) 0:::0 Yd DF DE ro CLK ChannefC (ij r LK I. c c Ill \12[7·()) .. -. D[l-'fl/ BLU2r7:01 ro BLU?f7:01 D(7:11J -. .... ;::. ..._ Ql ~ .... CTL.I .. u CJI :! CTL4 Ql N Ql Ql co .!.. .. co u= ,_.._ >U I 0 l1l - ... Cl cru Q) CII ~ CTL5 C/ o ·c 0u 0 u ""' c .. I - c:: Ql Ql Ql OB4 - DE - U£! UJC/) 0:::0 -. ))[7:0] r.RN?l 7:0l GRNJf7·0! ... GRN2f7:01 .__ .... Channef3 0[7:11) -~'- C"TL6 rrv' '- Q) Q) Q) co ... CTL6 Ql N >U co -o = C/ CTL"~ CIIZ CTL7 I - Channe/4 8 8 .. CJ 8 ·~ Ql Ql :OE4 I - c Ql 0:::0 DE ot: UJC/) I Channe/5 RflD2l"':OI RfD21Z.OI .. -. 0{7:1/f RED117:01 -. ..._ ~ .... C"fLS C'TI,R D/7:0/ Ql Ql CO L Q) .. CTLS Ql N >U CTI.9 CT( 9 Cf/ u:= 0 0 Cl .. I - 0 l1l 0 0 CTL9 0 ·.::: Ql Ql DH Cl ~ DE ... I - c Q) - ... a:::o DE UJC/) I Figure 3-3 D ual Link T.M.D.S. Channel Map Page 27 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 3.2.2 Encode Algorithm The T.M.D.S. encoding algorithm is specified by Figure 3-5 with the definitions of Table 3-1. The encoder produces four unique I O-bit characters during blanking and one of 460 unique 10-bit characters during active data. Use of all other 10-bit characters over the ]jnk is reserved and must not be generated by the encoder. D, CO, C l , DE The encoder input data set. Dis eight-bit pixel data, C l and CO are the conh"ol data for the channel, and DE is data enable cnt This is a r·egister used to keep track of the data stream disparity. A positive value represents the excess number of"l ''s that have been transmitted. A negative value represents the excess number of"O"s that have been transmitted. The expll'ession cnt {t-1 } indicates the previous value of the disparity for the previous set of input data. The expression cnt(t) indicates the new disparity setting for the current set of input data. q_out These I 0 bits are the encoded output value. N 1 {x} This operator returns the number of" l "sin argwnent ''x" Nu{x1 This operator returns tbe number of"O"s in argument "x" Table 3- 1 Encoding Algorithm Definitions Page 28 of 76 Dig ital Visual Interface Revision 1. 0 Digital Display Working Group I DE, 0[0:7), CO, C1 , cnt(t-1) FALSE TRUE q_m[OJ =D[O] ; q_m[OJ = D[O]; q_m(1) = q_m[O) XOR 0[1); q_m[1) = q_m[O) XNOR 0[1]; q_m[2) =q _m[1) XOR D[2); q_ m[2) = q_m[1) XNOR 0[2); q_m[7] = q_m [6] XOR D[7]; q_m[7] =q_m[6] XNOR 0[7]; q_m[8) =1 ; q_m[8) = 0; Cnt(t) =0; case (C1 , CO) 00: q_out[0:9] =0010101011; ~---FALSE--~ 01: q_out[0:9] = 1101010100; 10: q_out[0:9] = 0010101010; 11: q_out[0:9] =110101010 1; TRUE end case (Cnt(t-1 )==0) OR >------TRUE------~ (N1{q_m[0:7]}==N0{q_m[0:7)}) q_out[9) =-q_m[8); q_out[8) =q_m[8]; I q_out[O:?] = (q_m[8]) ? q_m[0:7]:-q_ m[0:7]); FALSE• (Cnt(t-1 )>0 AND q_m[8]==0 (N1{q_ m[0:7]}>N0{q_m[0:7]}) FALSE OR TRUE (Cnt(t-1 }<0 AND 0{q_m[0 ;71}>N1{q_rn(O;?]} q_ out[9) = 1; q_out[8) = q_m[8]; q_out[O:?] = -q_m[O:?); Cnt(t) = Cnt(t-1 )+ Cnt(t) = Cnt(t-1 ) + 2*q_m[8] + TRUE (N1{q_m[0:7)} - N0{q_m[0:7)}); FALSE (N0{q_m[0:7]}- N1{q_m[0:7]}); q_out(9) = O: q_out[8) = q_m[8]; q_out[0:7) = q_m[0:7]; Cnt(t) =Cnt( t-1)- 2*(-q_m[Bl) Cnt(t) = Cnt(t-1) + (N {q_m[0:7)}- N {q_m[0:7]}); + (N1{q_ m[0:7]}- N0{q_m[0:7)}); 0 1 Figure 3-5. T.M.D.S. Encode Algorithm Page 29 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 3.2.3 Serialization The stream ofT.M.D.S. characters produced by the encoder is serialized for transmission on the T.M.D.S. data channel. The least significant bit of each character (q_out[O]) is ithe first bit to be o·ansmitted. 3.3 Decoder Specification 3.3.1 Clock Recovery A T.M.D.S. receiver must be capabl e of phase lock with a transmit clock from 25 MHz up to the stated maximum ·frequency of the receiver. Phase lock to the input clock must occur within I 00 ms from the time that the input clock meets the electrical specifications of chapter four. 3.3.2 Data Synchronization The receiver is required to establish synchmnization w ith the data streams during any blanking period greater than 128 characters in length. Prior to synchronjzation detection, and during periods of lost synchronization, t be receiver shall not update the signals ofthe recovered stream. Page 30 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 3.3.3 Decode Algorithm The T.M.D.S. decode algorithm is specified by Figm·e 3-6. I 0[9:0) 0[7:0] := -0[7:0]; FALSE FALSE >------TRUE-- FALSE + Q[O) := 0[0); Q[O) := 0[0]; case (0[0:9]) Q[1) := 0[1) XNOR 0[0); Q[1) := 0[1) XOR 0[0]; case 0010101011 : C[1:0) : =00; Q[2) := 0[2) XNOR 0[1); Q[2) := 0[2) XOR 0[1); case 1101010100: C[1 :0) : =01; Q[3) := 0[3] XNOR 0[2]; Q[3] := 0[3] XOR 0[2]; case 0010101010: C[1 :0] : = 10; Q[4] := 0[4] XNOR 0[3]; Q[4) := 0[4] XOR 0[3); case 1101010101: C[1 :0]: = 11 ; Q[S] := 0[5] XNOR 0[4]; Q[5) := 0[5) XOR 0[4]; endcase; Q[6) := 0[6] XNOR 0[5); Q[6] := 0[6) XOR 0[5]; Q[7] := 0[7) XNOR 0[6); Q[7J := 0[7] XOR 0[6); Figure 3-6 T.MD.S. Decode Algorithm 3.3.4 Channel Mapping The T.M.D.S. receiver aligns the data channel streams to a common clock and outputs the recovered T.M.D.S. stream as showo in figure 3-2 and Figure 3-3. 3.3.5 Error Handling There is no requirement for eiTOr handling over the T .M.O.S. link. Page 31 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 3.4 Link Timing Requirements The maximum time for encode and serialization and decode is specified in order to bound latency across the interface. Figure 3-7 with Table 3-2 specifies these parameters. active video region ~ 1 4 inactive/blank region ~~ 4 active video region -- to DE ------if BLU(7:0J J*k~------:-----t ignored BLU(7:0J ignored HSYNC.VSYNC 1,'-- ignored ~----~~~~~----- Input I~ 1 St:reums c: GRN[7:0] - ;!, ignored G~N[7:0J :! Ignored CTI.O,CTLI I, i,gnored REDf7:0] ignored *' RED[7:0] I - J l ignored CTL2.C'I'l3 i(' ignored ~I encoded BLU encoded IISYNC,VSYNC enco<.led BLU T.M.D.S. Channel I encoded GRN encoded CTLO.CfLI encodedGRN Link ____.:.:.:.:..:..;~ ..::..:.=--_ __;,t ~ I I" ... Channc12 ..___ _.;.;.:.;.;;.;;:..;;.;;;..:;:;;;;.;:;_encoded RED _ __; encoded CTL2,CTL3 ~)~C encoded REO j' I rK : 1R I *r-*1 t1 DE \1 ttr nclivc video region ~ I - BLU[7:0) ~k invalid BLUL7:0] constant HSYNC,VSYNC I HSYNC,VSYNC *t cons tant HSYNC,VSYNC ! I Recovered I I Streams C.RN[7:0J Jk invalid ;r GRN[7:0] constant CfLO,CTL I CTLO,CTLI constant CTLO.CTLI RED(7;0J invalid RED[7:0] con~l ant CTL2,CTL3 *i CTL2.CTL3 i constant CTL1,CTL3 I I *i Figure 3-7 T.M.D.S. Link Timing Symbol Description Value Unit ta Mjnimum duration blanking period required to ensure character 128 T pixcl boundary recovery at the receiver. Blanking periods of this duration must occur at least once every 50 mS (20 Hz). Maximwn encoding/seriali zer pipeline delay 64 Tpixel Maximum recovery/de-serializer pipeline delay. Recovery 64 T pixcl timing includes inter-channel skew, and is measured from the earHest DE t1·ansition among the data channels. Table 3-2 T.MD.S. Link Timing Parcuneters Page .32 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 4. T.M.D.S. Electrical Specification Some timing parameter values in this specification are based on the clock rate of the link while others are based on absolute values. For scalable timing parameters based on the clock rate, the 6me period of the clock is denoted as p ixel time, or T pixcl· One tenth ofthe 'pixel time' is called the bit time, or T bit· The bit time is also referred to as one Unit interval, or Ul , in the jitter and eye diagram specifications. Schematic cliagrams contained in this chapter are for illustration only and do not represent the only feasible implementation. 4.1. Overview The conceptual schematic of one T.M.D.S. differential pair is shown in Figure 4-1. T.M.D.S. technology ~uses current drive to develop the low voltage differential signal at the receiver side of the DC-coupled transmission Iine. Tihe Iink reference voltage AV cc sets the high voltage level of the differential s,ignal, while the low voltage level is determ.ined by the current source of the transmitter and the termination resistance at the receiver. The tenuination resistance (RT) and the characteristic impedance of the cable (Zo) must be matched. Transmitter Receiver Flgw·e 4-l Conceptual Schematicfilr one T,M.D.S. di.lferential pair A single-ended differential signal, representing either the positive or negative term.inal of a differential pair, is illustrated in Figure 4-2. The nominal high-level voltage of the signal is AVec and tbe nominal low-level voltage of the signal is (A V cc - YswinJ· Since the swing is differential on the pair, the net signal on the pair has a swing twice that of the sing le-ended signal, or 2*Y•wing· The differential signal, as shown in Figure 4-3, swings between positive Y swin!f and negative Ysw in ~· Page 33 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group AVe +Vswin Figure 4-2 Single-ended Dij}'erential Signal Figure 4-3 DijJ'erential Signal The signal test points for a T.M.D.S. link are shown in Figure 4-4. The first test point (TP I), at the pins of the T.M.D.S. transmitter, is not utilized for testing under this specification. Rather, the transmitter is tested at TP2, which includes the network from the transmitter to tbe connector as well as the connector to the cable assembly. The input to the receiver is simila rly described by signal testing at TP3 rather than at TP4, the pins of the receiver. By imposi11g the signal quality requirements of these networks on transmitter and receiver components, link testing is reduced to measurements at only two test points. Cable assembly requirements are given by the allowable signal degradation between test points TP2 and TP3. Transmitter Receiver Network Network Figure 4-4 T.M.D.S. Link Test Points The test procedures required to detem1ine compljanee with the specifications contained in sections 4.3, 4.4, 4.6, and4.6 are described in section 4.7. Page 34 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 4.2. System Ratings and Operating Conditions The maximum ratings of the T.M.D.S. interface are specified in Table 4-1. Exceeding these limits may damage the system. J!tem Value Te nnination Supply Voltage, A Vee 4.0V Signal Voltage on Any Signal Wire -0.5 to 4.0V Common Mode Signal Voltage on Al1y Pair -0.5 to 4.0V Differential Mode Signal Voltage on Any Pair ±3.3V Termjnation Resistance 0 Ohms to Open Circuit Storage Temperature Range -40 to 150 degrees Centigrade Table 4-1 Maximum Rating~· The required operating conditions of the T.M.D.S. interface are specified in Table 4-2. lltem Value Tennioatioo Supply Voltage, AVec 3.3V, ±5% Tennination Resistance 50 Ohms, ±10% Operating Temperature Range 0 to 70 degrees Centigrade Table 4-2 Requirc>d Operating Conditions 4.3. Transmitter Electrical Specifications The DVI interface requires a DC-coupled T.M.D.S. link. Transmitter electrical testing shall be performed using the test load shown in Figure 4-5. TG+ 1-_._--1 ro- Transmitter 1--<::E------' Network 50 +/-1% Figure 4-5 Balcmced Transmifler Test Load The transmitter shall meet the DC specifications in Table 4-3 for all operating conditions specified in Table 4-2 when driving clock and data signals. Tbe Vswi ng parameter identifies the minimum and maximum single-ended peak-to-peak signal amplitude that may be delivered by the transmitter into the test load). Page 35 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group Item Value Single-ended high level output voltage, V H AYcc ±lOmV Single-ended low level output voltage, VL (AVec - 600mV) s; VL s; (AVec - 400mV) Single-ended output swing voltage, V swing 400mY 5 Vswi ng 5 600mY Single-ended standby (offl out-put voltage, YoFF AYcc ±IOmV Table 4-3 Transmiller DC Characteris.tics at TP2 The transmitter shal l meet the AC specifications in Table 4-4 across all operating conditions specified in Table 4-2. Rise and fall times are defined as the signal transition time between 20% and 80% of the nominal swing voltage (Vswin.J of the device under test. The transmitter intra-pair skew is the maximum allowable time difference (on both low-to-high and higb to-]ow transitions) as measured a t TP2, between the true and complement signals. This time difference is measured at the midpoint on the single-ended sigoal swing of the true and complement signals. The transmitter inter-pair skew is the maximum aUowable time difference (on both low-to-high and high-to-low transitions) as measured at TP2, between any two single-ended data signals that do not constitute a differential pair. Etem Value Risetime/Falltime (20%-80%) 75ps s; Risetime/Falltime 5 0.4 T bit Tn tra-Pair Skew at Transmitter Connector, max 0.15 T bit J nter-PaiJ· Skew at Transmitter Connector, max 0.20 T 1,;~,.1 C lock Jitter, max 0.25 T 11;, Table 4-4 Ttansmilfer AC Characteristics a/ TPl For all channels under all operating conditions specified in Table 4-2, the transmitter shall have output levels at TP2, when terminated as shown in Figure 4-5, which meet the normalized eye diagram requirements of Figure 4-6. This requirement, normalized in botb time and amplitude, specifies the minimum eye opening as well as the max_imum overshoot and undershoot relative to the average differential swing voltage of the ·component under test. The time axis is normalized to the bit time at the testing frequency, while the amplitude axis is normalized to the average differential swing voltage. The average differential swing voltage is defined as the difference between the average differential amplitude when driving a logic one and the average differential amplitude when driving a logic zero. The average logic one appears at positive 0.5 on the vertical axis, while the average logic zero appears at negative 0.5. T he no1malized amplitude limits in Figure 4-6 allow 15% (of the average differential swing voltage) maximum overshoot and 25% maximum undershoot, relative to the amplitudes determined to be: logic one and zero. Page 36 of 76 Digital Visual Interface Revision 1. 0 Q) 0.65 ~====::::::::::::::::::::=::::::::::::=:::..~ 1l ~ 0.50 f------1 c::. ~ 0.25 1------..------.... ] c ~ 0.0 !t : Cl i ~ : .!::1 -0.25 ----:--\------( ct : ~ -0.50 f----!----+------i--+----1 c z -a.G5 Pi=::::"!!!T.i'i:~i!==="'7--~=7'~-:~-.l'!'=:ii:9FI 0.0 0.15 0.32 0.68 0.85 1.0 Normalized Time Figure 4-6 Normalized Eye Diagram Mask at TP2 Combining the single-ended swing voltage (Yswing) specified in Table 4-3 with the overshoot and undershoot requirements of Figure 4-6, it is possible to calculate the minimum and maximum high-level voltage (Ywgb) and low-level voltage (V10w) that is allowable on tbe interface. Vhigh (max) = Yswin~ (max) + 15% * (2*Vswing (max)) = 600 + 180 = 780 mY Ybigh (min)= Yswing (min)- 25% * (2*Ys"ins (min))= 400- 200 = 200 mV Ylow (max) = -Yswing (max)- 15% * (2*Y,wing (max)) = -600- 180 = -780 mV Vlow (min) = -Vswing (min)+ 25% * (2*Yswing (min)) = -400 + 200 = -200 mY Minimum opening at transmitter = Yhigh (min)- Y10w(min) = 400 mY Transmitter eye diagram tes1 procedures are defined in section 4.7.6. The transmitter eye diagram mask of Figure 4-6 is not used for response time and clock jitter specifications, but specifies the clock to data jitter indirectly. Page 37 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 4.4. Receiver Electrical Specifications The receiver shall meet the signal requirements listed in Table 4-5. Table 4-6, and Table 4-7 for all operating conditi ons specified in Table 4-2. J!tem Value Differential Input Voltage, Y ;dm· 150 :5 Y;d;rr:5 1200 m V [nput Common Mode Voltage, Y;em (A Vee-300) 5 V;em :5 (A Vee-37) Behavior when Transmitter Disabled or AVcc ±IO mY Disconnected Table 4-5 Receiver DC Characteristics al TP3 Hem Value Minimum differential sensitivity (peak-to-peak) 150mV Maximum differential input (peak-to-peak) 1560mV Allowable Intra-Pair Skew at Receiver Connector 0.4 T bit Allowable Inter-Pair Skew at Receiver Connector 0.6 Tulxrl Table 4-6 Receiver AC Characteristics at TP3 .litem Value TDR Rise Time 75 ps Exception_ window" 500 ps Through_connectionb 100±20 Q At Tenninalionc 100±10 Q Table 4-7 Receiver Impedance Characterislics at TP3 • Within the Exception_ window no single impedance excursion shall exceed the Through_ connection impedance tolerance for a period of twice the TOR rise time specification. The maximum excursion within the Exception_window at TP3 shall not exceed + 75% and - 25% of the nominal cable impedance. b Tlu·ough_ connection impedance describes the impedance tolerance through a mated connector. Tbjs tolerance is greater than the termination or cable impedance due to limits in the technology of the connectors. c The input impedance at TP3, for the termination, shall be recorded 4.0 ns following the reference location determined by an open connector between TP3 and TP4. Page 38 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group For all channels under all operating conditions specified in Table 4-2, the receiver shall reproduce a test 9 data stream, with pixel error rate I o- , when presented with input amplitude illustrated by the eye diagram off'igure 4-7. 1wr------__, .s> Cll ~ .€ [ 7& ::=::.:::::.::===<: )! .A' -7~ ------J--':-· ------( • X : !I :. !, ! I i ! i : ! ; 4.5. Cable Assembly Specifications When driven by an input wavefonn meeting the eye diagram mask requirements offigure 4-6 a DVl cable assembly must a produce an output waveform that meets the receiver eye diagram mask of Figure 4-7. In addition, the cable assembly must meet the signal skew requirements of Table 4-8. Item Value Maximum Cable Assembly Intra-Pair Skew 0.25 Tbil Maximum Cable Assembly Inter-Pair Skew 0.4 Teixel Table 4-8 Cable Assembly Skew Budget (informative) 4.6. Jitter Specifications The differential clock of the T.M.D.S. link shall meet the total jitter specifications defined in Table 4-9. The clock to data jitter is not specified in the table but the system shall produce tbe eye diagram shown in Figure 4-7 when measured at test point TP3. Normative values are highlighted in bold. All other values are informative. Compliance test points are defined ill Figure 4-4. The Unit Interval (Ul) is equal to one bit titne (Tb il). Compliance Test Point Total Jitter lUll TP2 0.25 TP2 to TP3 0. J65a TP3 0.30 Table 4-9 T.M.D.S. Clock Jitter Budget " The total jitter from TP2 to TP3 is calculated based on the assumption that the distribution ofthe jitter is Gaussian. Page 39 of 76 Dig ital Visual Interface Revision 1. 0 Digital Display Working Gr oup 4.7. Electrical Measurement Procedures Electrical measurements shall be performed as described in this clause. 4.7.1. Test Patterns Two different test patterns are used to evaluate T.M.D.S. interface components. For pixel enor rate measurements. a (223-1) bit pseudo-random data pattern is transmitted. Other measurements specify a "half clock" sequence. Tbe half clock pattern consists of alternating Ox3FF (all ones) and OxOOO (all zeros) T.M.D.S. characters. This pattern is useful for determining average swing voltage, logic one, and logic zero voltage levels. 4.7.2. Normalized Amplitudes Normalized amplitude measurements are necessary for both single-ended and d:iJTerential testing of the T.M.D.S. interface. These measurements are made with transmission of the half clock test pattern, and the time base of the measurement equipment set to a scale that is coarse enough to observe at least two full pixel times. The average high-level and low-level amplitudes are detennined at tbe point where signal ringing has subsided. These averages establish the swing voltage and are used to normalize the eye diagram. 4.7.3. Clock Recovery Eye diagram measurements require a clock which has been recovered from the transmit stream. The clock recovery unit is used to remove low frequency jitter from the measlrrement as shown in Figure 4-8. The clock recovery unit has a low pass fi lter with 20dB/decade roll off with -3dB point of 4 MHz. It is used to approximate the phase locked loop in the receiver. The receiver is able to track a large amount of low frequency jitter (such as drift or wander) below this bandwidth. This low frequency jitter would create a large measurement penalty, but does not affect the operation of the link. Eye Diagram Differential Data Measurement Instrument Recovered clock for use as trigger Clock Recovery Unit Figure 4-8 Clock Recove1y Unit in Eye Diagrllm Measurements The eye diagrams produced with by this method will contain only high frequency jitter components that are ootr tracked by the dock recovery circuit of the receiver. The clock recovery unit may be a T.M.D.S, receiver meeting the filter requirements above. Page 40 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 4.7.4. Transmitter Rise/Fall Time Rise time is a differential measurement across the outputs of a differential pair with a load present (including test equipment) equivalent to that shown in Figure 4-5. Both rising and falling edges are measured. The 100% and 0% levels are the normalized I and 0 levels present when sending half clock characters (4.7.1 ). Once the normalized amplitude is determined, the time base is changed to a finer scale to measure the rise and fall time. The half clock data pattern (4.7.1) is transmitted for the rise and fall time measurements. The rise time specification is the time interval between the normalized 20% and 80% amplitude levels. It is recommended to utilize the averaging feature of the equipment to read more stable values. When the equipment's rise time is not negligible compared to the signal's rise time, the effect ofthe equipment should be removed using the equation: 2 2 Trise, fall = ~ (Trise, fall_ measured) - (Trise, fall_ equipment) In order to keep the measurement error under I 0% when using this equation, it is necessary that the equipment rise time be Jess than one third of the signal rise time. 4.7.5. Transmitter Skew Measurement The transmitter skew is the time difference between the two differential signals measured at the normalized 50% crossover point with a load present (including test equipment) equivalent to that shown in Figure 4-5. This measurement is taken using two single ended probes. Skew in the test set-up must be calibrated and removed from the recorded measurements. All of the signal pairs must be measured and the worst case recorded. Nonnalized amplitudes are detennined using the method described in 4. 7.2. The device under test transmits a continuous half clock character pattern as defined in 4. 7.1. The data is averaged using an averaging scope. An easy method to view and measure the skew between these signals is to invert one of the signals. 4.7.6. Transmitter Eye This test is made as a differential measurement at TP2 of 100,000 acquisitions to achieve 99% confidence within I% error of the mean value assuming nonnal distribution of the waveforms in the eye diagram. Referring to Figure 4-6, there are eight critical locations to collect the data of the means and standard deviations: at six horizontal segments of (0 < x < 0. I 5, y=O), (0.85 < x < l.O, y=O), (0 < x < 0.32., y=0.25), (0.68 < x < 1.0, y=0.25), (0 < x <0.32, y=-0.25), (0.68 < x < 1.0, y=-0.25), and at two vertical segments of (x=0.5, 0.25 < y < 0.65) and (x=0.5. -0.65 < y < -0.25). The mean and standard deviation at each of the eight critical regions around the eye are used for time statistics at the six horizontal locations and for amplitude statistics at the two vertical locations. ln all cases 9 the eye must be degraded by ±6 sigma limit points for the pixel error rate of I 0-' • The scope trigger ITmst be a recovered clock as defined in 4.7.3. The data pattern for this test is the pseudo random data pattern defined in 4.7 .I. Page 41 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 4.7.7. Jitter Measurement Jitter measurement is performed as a differential measurement of the rising edge of the clock signal (elk+ minus elk-) at TP2 a nd TP3. The scope trigger must be a recovered clock as defined in 4.7.3. The scope is used to determine the standard deviation of the 50% crossings in measuring time statistics of the differential clock signal. The random jitter at 10·9 pixel error rate will be ±6 sigma limit points oftbe distribution. When the jitter includes any systematic components, care must be taken in obtaining the sigma value from the scope, otherwise the overestimated sigma value can lead to an excessively large value of the jitter limit. 4.7.8. Receiver Eye This differential measurement is made at TP3, through mated connectors with a load present (including test equipment) equivalent to that shown in Figure 4-5. Tbjs test is made as a differential measurement at TP2 of I 00,000 acquisitions to achieve 99% confidence within 1% error of the mean value assuming normal distribution of tl1e waveforms in the eye diagram. Referring to Figure 4-7, there are eight critical locations to collect tbe data of the means and standard deviations: at six ho rizontal segments of (0 < x < 0.25, y=O), (0. 75 < x < 1.0, y=O), (0 < x < 0.30, y=75mv), (0.70 < x < 1.0, y=7 5mv), (0 < x <0.30, y=-75nw), (0.70 < x < 1.0. y=-75mv), and at two ve1tical segments of(x=0.5. 75mv < y < 780mv) am1d (x=0.5, -780mv < y < -75mv). The mean and standard deviation at each of the eight critical regions around the eye are used for time statistics at the six horizontal locations and for amplitude statistics at the two vertical locations. [n all cases the eye must be degraded by ±6 sigma limit points for the pixel error rate of 1o ·<.l. The scope trigger must be a recovered clock as in 4.7.3 and the transmitted data pattern is pseudo-random as defined in 4. 7 .1. 4.7.9. Receiver Skew Measurement This single ended measurement is made at TP3, through mated connectors with a load present (inc luding test equipment) equivalent to that shown in Figure 4-5. The same method is used as for transmitter skew in 4.7.5. 4. 7.1 0. Differential TOR Measurement Procedure The differential time-domain retlectometry (TDR) test setup measures the reflected waveform returned from a load when driven with a step input. It is obtained by driving the load under test with a step waveform using a driver with a specified source impedance and rise time. The reflected waveform is the difference between (a) the observed waveform at the device under test when driven with the specified test signal, and (b) the waveform tJ1at results when driving a standard test load with the same specified test signal. From this measurement result we can i_nfer the impedance of the device under test. The driving waveform is sourced from a balanced, differential I 00-ohrn source with a 75 ps rise time. Page 42 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5. Physical Interconnect Specification 5.1 . Overview DVT complaint host systems may provide either a digital only interface or a combined analog and digital interface. The system-side connector d.istinguishes the system capabilities. The two defined connectors have the same physical outer dimensions. In each case the digital signals are present, allowing a monitor with a digital interface to attach directly to either system connector. Because the digital only receptacle does not have sockets for the analog pins of an analog monitor, the plug of an analog monitor will not mate with the digital only system. 5.2. Mechanical Characteristics 5.2.1. Signal Pin Assignments 5.2.1.1 . Digital-Only Connector The d igital only connector contains 24 signal contacts organized in three rows of enght contacts. Signal pin assignments are listed in Table 5-1. Pin Signal Assignment Pin Signal Assignment Pin Signal Assignment I T.M.D.S. Data2- 9 T.M.D.S. Datal- 17 T. M.D.S. DataO- 2 T.M.D.S. Data2+ 10 T.M.D.S. Datal+ 18 T.M.D.S. DataO+ 3 T.M.D.S. Data2/4 Shield II T.M.D.S. DataJ/3 Shield 19 T.M.D.S. Data0/5 Shield 4 T.M.D.S. Data4- 12 T.M.D.S. Data3- 20 T.M.D.S. Data5- 5 T.M.D.S. Da ta4+ 13 T.M.D.S. Data3+ 21 T.M.D.S. DataS+ 6 DDCClock 14 +5V Power 22 T.M.D.S. Clock Shield 7 DDCData 15 Ground (for +5V) 23 T.M.D.S. Clock+ 8 No Connect 16 Hot Plug Detect 24 T.M.D.S. Clock- Table 5-l Digital-On!)' Connector Pin Assignments Page 43 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.2.1.2. Combined Connector The mechanical inte rconnect includes 29 signal contacts, which are divided into two sections. The first section is organized as three rows of eight contacts. The second section contains five signals that are designed specifically for analog video signals. Horizontal sync, Vertical sync, R, G, and 8 are all are required for a nalog implementations. Signal pin assignments are listed in Table 5-2. Pin Signal Assignment Pin Signal Assignment Pin Si.gnal Assignment 1 T.M.D.S. Data2- 9 T.M.D.S. Datal- 17 LM.D.S. DataO- 2 T.M.D.S. Data2+ 10 T.M.D.S. Datal+ 18 T.M.D.S. DataO+ 3 T.M.D.S. Data2/4 Shield I I T .M.D.S. Data l/3 Shield 19 T.M.D.S. Data0/5 Shield 4 T.M.D.S. Data4- 12 T.M.D .S. Data3- 20 T.M.D.S. Data5- 5 T.M.D.S. Data4+ 13 T.M.D.S. Data3+ 2 1 T.M.D.S. Data5+ 6 DDCCiock 14 +5V Power 22 T.M.D.S. Clock Shield 7 DDC Data 15 Ground 23 T.M.D.S. Clock+ (return for +5V, HSync, and VSync) 8 Analog Ve1tical Sync 16 Hot Plug Detect 24 T M.D.S. Clock- Cl Analog Red C2 Analog Green C3 Analog Blue C4 Analog Horizontal Sync cs A11alog Ground (analog R, G, & B return) Tahle 5·1 Combined Analog and Digital Connector Pin Assignments 5.2.2. Contact Sequence Connection Signal Pins First Make Connector shell Second Make C5 (analog ground, when present) Tl1ird Make Pins 1 through 13 and 15 through 24 Fourth Make Cl, C2, C3, C4 (analog signals, when present) Pin 14 (+5V power) Table 5-3 Mating Contact Sequence Page 44 of 76 Digital Visual Int erface Revision 1. 0 Digital Display Working Group 5.2.3. Digital-Only Receptacle Connectors 5.2.3.1 . Mating Interface Dimensions r------32.51------j r-----24.03------1 1------J6.% MA<. ------~ Figure 5-1 Digitcd- on~v Receptacle Connector Mating lnteJjace Dimensions 5.2.3.2. Recommended Printed Circuit Board Hole Pattern and Keep Out f------36.83 SH NOTE 1------i 1------130.731------l I X24l 00.86:0.05 -+-t--11.'305 l~l~0.l3~lt~ls l CK T I ------..._.t-----,. ' - I $-G-G- G-V -€7-t I EEl [IIi] i--'--t---~ 0 0 0 0 0 0 I I 1 ._!_l 10.'35 ·fi+·---Eft-$-G-G-G--&·E!r- -- ·-·---·-~ I I l . :~ ·----- + - _]"" '=P"'C"'B,..,E"'O'""G"'E,.;,_,..,_==--=-'"=-:Ir-~:-:-==--:::::-=1-:-==--==--=-'""-:-:;==-K-=-r -=- 2-4-=--=-+-""'-=-'""-'""-:-:-=--=--=-+--=-:;='"=:~-=--=-=-=-=--=--=-,..,r--->.., I : 0 1.93:0.05 : l9.05 I l'f)l¢0.!3@liAIBI 01.93:0.05 t W 1 I X2 - NO PLATE 1 HRU - l'fll¢0.t3<9IAIBI ______... SEE NOTE 2! I X2 PLATE THRU> RECOMMENDED PCB LAYOUT NOTE: I. HlESE Dl MENSJONS DEFINE THE CONNECTOR KEEP-OUT AREA. 2. THESE HOLES FOR USE WITH CONNECTOR PLASTIC RETENTION PEGS Figure 5-2 Recommended Dig itnl-on~v Receptacle Connector PCB Layout Page 45 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.2.4. Combined Analog and Digital Receptacle Connectors 5.2.4.1 . Mating Interface Dimensions r------l,.5•------, t-----24.0]------t 10.04 MAX. 1.12 1------36.96 MAX,------! Figure 5-3 Comhined Receptacle Connector Mating lnterjace Dime/l.Sions 5.2.4.2:. Recommended Printed Cir.cuit Board Hole Pattern and Keep Out t------36.83 SE£ NOTE 1------< t------130.731------i I 1.93 ---,--l ~------119.05 : 01.93,0.05_j l ·A· ! 0 1.93•0.05 I$ I¢0. 13@IAIBI ------' l$l¢e.tJ@IAIBI I X2 - PLATE THRU) IX2- NO PLAlE JHRU Sff NOTF 21 RECOMMENDED PCB LAYOUT NOTE: I. TII[St OIMCNS!ONS OEr JN[ Til[ CONNECTOR ~EEP·OUT AREA. 2. 1H£SE HOLES FOR USE WlTH CONNECTOR PLASTIC RETENTlON PEGS Figure j-4 Recommended Combined Receptacle Comu!ctor PCB Layout Page 46 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.2.5. Digital Plug Connectors 5.2.5.1 . Mating Interface Dimensions ;? r---oJ.J•- coo - r-r- !"'" ' I I ~.Pd~~~~~~ _I I I IS. IJ "' 1.8 .....·r ,.,.~~,.~"" \..v' I 10 - ~~tv~~~"' '' f _/ ' PIN 2•_) ~2.51 39.5t UAX, Figure 5-5 Dig ital Plug Conm:ctor Maring lntedace Dimensions 5.2.6. Analog Plug Connectors 5.2.6.1 . Mating Interface Dimensions l•.~ -o>J4- 1,9 1-- ;- !"'"' 1 I I q • !oo t p~~~o%,~ ...... " . . . {\ J. "' :1.! 6 ,0 G) \.. ..) I ~<• " ~ ~~~"~ "' "' f' i ~~~~~~~~ ..~. I r-.. / ••• ...J 32.~1 39.~1! I.IA)I;, Figure 5-6 Analog Plug Connector Mating fllletjace Dimensions Page 47 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.2.7. Recommended Panel Cutout R 0.64 1------32.51 ------i <2 PLCSl 03.05 9.14 03.05 J------27.43 ______, R 2.54 <2 PLCSl Figure 5-7 Recommended Panel Cutozil.for Receptacle Connectors Page 48 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.2.8. Mechanical Performance Tbis section summarizes the mechanical performance requirements for the DVI connector interface. Where appropriate the relevant ANSI/EIA-364 Test Procedures and Conditions are referenced. Please refer to section 5. 5 for detailed test sequence flow charts. ftem Test Condition ReqLLirement Vibration ANSI/EIA-364-28, Condition []I No disconrmuity at I J..LS or longer Method SA, 15 minute/axis (each contact) when continuity is tested per ANSIIEIA-364-46 Mechanical Shock ANSI/EIA-364-27 Condition A No discontinuity at l ~t s or longer (specified pulse) (eacJ1 contact) when continuity is tested per ANSI/ElA-364-46 Dmability /\NSI/ ElA-364-09 Low Level contact resistance per Automatic cycling to I 00 cycles ANSI/EIA-364-23 Rate: I 00 ± 50 cycles per hour I 0 nill maximum change from i:ni tial per contact pair All samples to be mated Mating & Unrnating ANSVEJA-364-13 Urunating force: Forces Insert and extract at a speed of 1 kg force minimum, 25mm/minute 4 kg force maximum Mating force: 4.5 kg force maximum Cable Flexing ANSJIEIA-364-41 Condition I Dielectric Withstanding Voltage tested Dimension X=3.7 x cable per requirements of section 5.3. diameter Insulation Resistance tested per 100 cycles in each of 2 planes requirements of section 5.3 Continuity tested per ANSl!ElA-364- 46 with no disoontinuities on contacts or shield greater than IJ..LS al lowed dming flexing. Page 49 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.3. Electrical Characteristics 5.3.1 . Connector Electrical Performance This section summarizes the electrical performance requirements for the DVI connector interface. Where approptiate the relevant ANSUELA-364 Test Procedures and Conditions are referenced. Please refer to section 5. 5 for detailed test sequence flow chat1s. Item Test Condition Requirement Contact Resistance ANSI!ETA-364-23 20 mn, maximum, initial per contact mated pair I 0 mQ, maximum change from original per contact mated pair Shell Resistance ANSlfETA-364-06A-83 50 mn, max imum initial Contact resistance measmed from 50 mn, maximum change from receptacle shell leg to p lug cable original braid. Test current = I QOmA; Test voltage = 5 V DC open circuit max_imum. Dielectric ANSifElA-364-20 No flashover, No sparkover, No Withstanding Test voltage 500 V DC ± 50V excess leakage, No breakdown. Voltage Method C, umnated and unmounted Barometric pressure of 15 psi Insulation ANSE/ElA-364-2 1 I GQ minimum between adjacent Resistance Test voltage 500 V DC ± 50 V contacts and contacts and shell. Method C. unmated and unmounted Contact Current ANSI/ElA-364-70, TP-70 1.5 A minimum Rating 55"C. maximum ambient 85°C, maximum temperature change Applied Voltage 40 Volts AC (rrns) continuous Rating maximum, on any signal pin with respect to the shield Electrostatic rEC 801-2 No evidence of discharge to contacts. Discharge Test unmated from 1 kV to 8kV in Discharge to the shell is acceptable. I kY steps using 8mm ball probe Page SO of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group Item Test Condition Requirement T.M.D.S. ANSI/EIA-364-108 Draft Proposal 100 Q ± 15% Signal Time Risetime = 330 pS ( J 0%-90%) Domain S:O ratio per DVl pin designation Impedance Differential Measurement Specimen Environment Impedance = I 00 Q d ifferential Source-side receptacle connector mounted on a controlled impedance pcb fixture T.M.D.S. ANSI/EIA-364-90 Draft Proposal 5% Maximum Signal Time Risetime = 330 pS ( I 0%-90%) Domain S:O ratio per DV! pin designation Crosstalk: Differential Measurement FEXT Specimen Environment Impedance= I 00 Q differential Source-side receptacle and the load side plug connector are mounted on a controlled impedance pcb fixture (I) Driven pair and ( I) victim pair T.M.D.S. ANSI/ElA-364-102 160 pS Signal Rise S:O ratio per DVI pin designation Maximum Time Differentia1 Measurement (Note: Converted Degradation Specimen Environment Impedance = 100 Q differential bandwidth using Source-side receptacle and the load side plug connector BW=0.35/trisc mounted are on a controlled impedance pcb fixture yields 2.2 OHz) Item Test Condition Requirement Analog ROB ANSI!ElA-364- 108 Draft Proposal 75 Q ± 10% Coaxial Signal Time Risetime = 700 pS (10%-90%) Domain impedance S:O ratio per DVI pin designation Single-ended Measurement Specimen Environment Impedance= 75 Q single-ended Source-side receptacle connector mounted on a controlled impedance pcb fixture Analog ROB ANSI/EIA-364-90 Draft Proposal 3%Maximwn Coaxial Signal Time Risetime = 700 pS (I 0%-90%) Domain Crosstalk: S:O ratio per DVI pin designation FEXT Single-ended Measurement Specimen Environment Impedance = 75 Q single-ended Source-side receptacle connector is mounted on a contro lled impedance pcb fixture and the load side plug connector is terminated to semi-rigid coax. (I) Driven line and ( 1) victim line Analog RGB ANSVEJA-364-1 02 140 pS Coaxial Signal Rise S:O ratio per DVI pin designation Maximrum T ime Degradation Single-ended Measurement (Note: Converted Specimen Environment Impedance = 75 Q single-ended bandwidth ustng Source-side receptacle connector is mounted on a BW=0.35 /tri~ controlled impedance pcb fixture and the load side plug yields 2.5 OHz) connector is tenninated to semi-rigid coax. Page 51 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.3.2. Cable Electrical Performance Tbis section summarizes the electrical performance requirements for coaxial cable used in tbe DVI cable assembly. ltem Test Condition Requirement Analog RGB Signal 75Q±4Q Conductor Impe·daoce Analog RGB Signal At20° c 1.8Q Ma;" Page 52 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.4. Environmental Characteristics This section summari zes the environmental performance requirements for the DVl connector interface. Where appropriate the relevant ANSl/EIA-364 Test Procedures and Conditions are referenced. Please l'efer to section 5.5 for detailed test sequence tlow charts. Item Test Condition Requirement The1mal Shock ANSJ ElA-364-32, Condition 1 Low Level contact resistance per I 0 eye les, mated AN Sl/EJA-364-23 I 0 mn maximum change from initial per contact pair All samples to be mated Cyclic Humidity ANSl/EIA-364-31, conditions A Low Level contact resistance per and B AN SUElA-364-23 Method Jll, omit 7A and 7B 10 mn maximum cbange from initial per contact pair All samples to be mated Temperature ANSI/EIA-364-17 Condition 4 Low Level contact resistance per Life I 05° C for 250 hours AN Sl/EIA-364-23 Method A, mated I 0 mn maximum change from initial per contact pair All samples to be mated Temperature Operating -20 oc to +85 °C' Rating Temperature Non-Operating -20 °C to +85 °C Rating Page 53 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.5. Test Sequences 5.5.1. Group 1: Mated Environmental I CONTACT AND SHELL RESISTANCE I I ( 1/2 SAMPLES) < 1/2 SAMPLES) DURABILITY AS 100 CYCLES RECEI VE D I I CONTACT AND I SHELL RESISTANCE I I THERMAL SHOCK I I EIA 364- 32 I I CONTACT AND SHELL RESIST ANCE I I THERMAL AGING EIA 364- 17 I I I CONTACT AND SHELL RESISTANCE CYCLIC HUMIDITY CONDITION B EIA 364- 31 I I CONTACT AND SHEL L RESISTANCE Number of Samples: (5) Receptacles assembled to printed circuit board (5) Cable assemblies with a plug assembled to one end, 25.4 em long Page 54 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.5.2. Group II : Mated Mechanical CONTACT AND SHELL RESISTANCE VIBRATION EIA 364- 28 CONTACT AND SHELL RESISTANCE MECHANICAL SHOCK EIA 364-27 CONTACT AND SHELL RESISTANCE Number of Samples: (2) Receptacles, assembled to plinted circuit board (2) Cable assemblies with a plug assembled to one end, 25.4 em long Note: Connector is to be mounted ot1 a fixture that simulates the typical application. The receptacle connector sbalJ be mounted to a panel, per the receptacle panel cutout in shown in Figure 5-7, which is permanently affixed to the fixture. The plug shall be mated to the receptacle with jackscrews fully engaged and the other end of the cable shall be permanently clamped to the fixture. Page 55 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.5.3. Group Ill: Mechanical Mate/Unmate Forces MATING FORCE I UNMATING FORCE I DURABILITY 100 CYCLES EIA 364-09 I MA T ING FORCE I UNMATING FORCE I THERMAL AGING EIA 364- 17 I MATING FORCE I UNMATING FORCE Number of Samples: (2) Receptacles, assembled to printed circuit board (2) Cable assemblies with a plug assembled to one end, 25.4 em long Page 56 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.5.4. Group IV: I nsu Ia tor In t egmy't DIELECTRIC WI THSTANDING EIA 364-20 THERMAL S HOC K EIA 3 6 4-32 DIELECTRIC WITHS T ANDING E I A 364-20 INSU L ATI ON RESISTANCE EIA 3 6 4 -21 C YCLIC HU MIDITY COND IT I O N A EIA 364-3 1 I NSUL ATION RESISTANC E EIA 364-21 Number of Samples: (2) Receptacles, assembled to printed circuit board (2) Cable assemblies with a plug assembled to one end, 25.4 em long Page 57 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group 5.5.5. Group V: Cable Flexing CABLE FLEXING EIA 364-4 I DIELECTRIC WITHS TAND ING VOLTAGE EIA 364-20 INSULATION RESIS TANCE EIA 364- 2 I Number of Samples: (2) Cable assemblies 5.5.6. Group VI: Electrostatic Discharge ELECTROSTATI C DISCHARGE Number of Samples: (I) Receptacle connector Page 58 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group Appendix A. Glossary of Tenns Active Data Period Time on the T.M.D.S. Link during wbich DE is active and pixel data encodings are present on the link. Blanking Period Time on the T.M.D.S. link during w hich DE is inactive and control signal encodings are present on the link. Channel A T.M.D.S. channel is a single difterential signaling pair. Contr·ol Signals Additional signals to be transported over the T.M.D.S. link. Data Enable A link-control signal indicating whether pixel data or control signals are to be transmitted. Dual T.M.D.S. Link Six T.M.D.S. data channels plus one T.M.D.S. clock cha1mel. The six data channels are referred to as channels 0 through 5. The clock channel is sometimes refeiTed to as channel C. HSync Horizontal synchronization signal typically used for CRT monitors. In-band characters The collection ofT.M.D.S. characters used to represent pixel data on the T.M.D.S. link. Link A T.M.D.S. link is the entire three channels and clock pair required to transmit RGB data Out-of-band characters The collection ofT .M .D.S. characters used to represent control signals on the T.M. D.S. link. Pel Pixel element. A pel is a pixel element, i.e. the singular red value or green value or blue value of and RGB pixel. Pixel Data 24-bit data to be transported over the T.M.D.S. link. The three individual bytes of the pixel data, which are mapped onto individual T.M.D.S. data channels, are sometimes referred to as red, grn, and b lu. Recovered Stream A T.M.D.S. input stream recreated a T.M.D.S. receiver. T.M.D.S. Transition minimized differential signal. T.M.D.S. characters These are encoded 10-bit values which appear, serialized, on the T.M.D.S. data channels. Page 59 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group T.M.D.S. Clock Channel A signal carrying a frequency reference for T.M.D.S. data channels. T.M.D.S. Data Channel A single serial stream ofT.M.D.S. encoded data. T.M.D.S. Data Link An infrequently used term to identify three T.M.D.S. data channels. A dual T.M.D.S. link might thus be referred to as two T.M.D.S. data links plus one T.M.D.S. clock channel. T.M.D.S. Input Stream The collection of input signals to a T.M.D.S. transmitter for transmission over the T.M.D.S. link. This includes 24-bit pixel data, six control signals to be transmitted over the li.nk, a link controlling data enable signal, and a clock to which all input signals are synchronous. T.M.D.S. Link Three T.M.D.S. data channels plus one T.M.D.S. clock channel. The three data channels are refe1Ted to as channel 0, channel I, and channel 2. The clock channel is sometimes referred to as channel C. VESA, Video Electronics Sta ndards Association North First Street, Suite 440 San Jose, CA 951.31-2029 VSync Vertical synchronization signal typically used for CRT monitors. Page 60 of 76 Digital Visual Interface Revision 1. 0 Digital Display Working Group Appendix B. Contact Geometry The following document, ES-74320-900 (sheets 1-14) contains the technical design details required for compliance to the DVJ plug and receptacle connector system. The information provided is covered by U.S. Patents 4,470,180 and 5, I 02,353 and is to be used solely for the purpose of compliance to the DVl specification. 1t is govemed by the DDWG license agreements and associated compliance documentation. Page 61 of 76 , 10 2 I 8 I 1 I & I 5 I ~ I 3 I I I 74320 ~ I 9 f/ 0.0 ·~= OU1ER I~ ,.:;.::F SHIELD I~~ I I lillJ F ... ~ Ai ,(/)7'i c 0 ~ ~ KEY\ i 1.91 .05 lt.l~02 I s- 1.29=0.05 ~ l$1. 00a®jB®I .~ Df !AI• ' X .311=.003 .t.B Q --~ ·~~~ E 7.90=0.08 ~._ - -- -~~~~~~- IBliCKGROUNO 0 .... OMMJT'fO 1(fTj . ~1 0@ I B® I .. , ~~ ~~ --1.-/-----=::=-..je....-----''----!~ .6]) _ FOR CLAR!I Yl I .075/11.91) ll 70 ~ '\__CONTACTS [±]1·'b1 0 ~~ 17:iB i'__j 0 A , SEE DETAIL 'X' .951<.002 -c 24.16>0.05 - ~ l$j. 01 0@IA@j 1'- .._ -++- .075/( 1.91) 215 0 - - - .IQ)(7b.002 li CONTACT -· - .075/( 1.91) ll 1--1- CONTACTS N c OUTER 2.54:0.05 HEIGHT --t NOTE • FOR CLARITY) '"C>t DRAONBY & DATE IITL£• DVJ CONNECTOR ~ I. TI-llS DRAWINGOUTLINES THE DVl DlC!TAL PLUG ASSEMBLY DETAILS. HIE INFORMATION IN THIS DRAWINGMUST BE USED IN CONJUNCTION < N/A t>.:CKEOBY& DATE DESIGN DETAILS ~ WITI-f THE DVI [NTERFACE DETA[LS AS OUTUNED IN THE REMAINDEROF ~ ~~~~~r ·~-~0~0:~5 ~2 Pt. ACESI' 0.13 I" N/ A APPROVEDBT & our •>~ERIAlNO. 11v1• • Nv NO. ,I s~trNO. A ES-7~321'1l·900AND THE COMPLETE DVI SPECIFICATION. 1 3 jl;; .. .x I P!.ACEI:N/A I< N/A I NONE ES-74320-900i10F 14A c 2. CONTACT HEIGHT FOR PIN • 14 IS TO BE . 185/14. 7(})1...... i< ~ !!- 0 I'CAD fl L(NAM£ s~IZE ~ ~ 0 ~ ~GUt..4R:!" I ES Q)XI OGN Tl'l: IWHl5WAJl'JN NrOVI0£0 I.H ES•14.J2t~·'W0 IS CDvEifUI B'f U.S 3.CONTACT RETENT!ON: 7432 roo .075/( 1.911CONTACTS: 71bs MIN. 1 > • PHlNtS ~.,4r;t.III:O•-.o ~.t:Z.l~SANDIS ro er usro som.v B FO'Wil114: PV!IP05£ Of COWPU,C.NC£ ICJ DVI SPEC!Hc• nCN. :::::1 • I ~ ht£ CJ)rl KEY: IQJ tbs MIN. o ...loor(J,Qt. "l v A 5 c 99103120 LlY[L lf 9 1 8 1 1 6 5 4 3 2 -0ro ·v; ·-...... · -> .QI QJ a~ Q.. 0= 10 I 9 I 8 7 I 6 I 5 2 743211l l5 " l)l) c .0334.(/)(02 1----t--+- ~ •0'4 [ 0.04•0.05 .!II: F ~ 1~1-006®lr®l looo l 0 ~ ~ - I~ liE.] ~I 2.54 I DETAIL ' Y" 3 .llJ33!,Ql02 Q.. ~BACKGROUND Ill 0.8~10.0"> OMMITTED Et=l ..• E l$1. 00t>@la®l .ej ~w Q FOR CLARIT'O ~.... ., "Ch rvov"l .075/( 1.91) I[ 5 CONTACTS • 100/12.54 ) It J CONTACTS 0 SEE DETAIL "Y GROUND 0.4 1•0.013 .100/11.27> II. 1.0 ,...... l<>l.006:l)IB®I·"''·"" 1'""' CO,T>CTS t / '"- c 0 ·M 1.0 .100/12.54) It . 143 ClJ CONTACT G3 Cl 3 ro HEIGHT • I F J /1////~JfJl//M\S::; - · MA.i!NG- · ;;;)) !J#Jt.J#}m;};,ff),tJJ..w));,))///};}";;!J" DETAILS. THE INFORMATION IN THIS DRAWING MUST BE USED IN CENt.JJALTOlERANCE~ · RtVISE ON CONJUNCTION WITH THE DVI INTERFACE DETAILS AS OUTLINED IN THE ''""LtSS Sf'(CfT 1£0> CAD QM._V REMAINDER OF ES-74320·900 AND THE COMPLETE DVI SPECIFICATION. ? . C:ONTAC:T RFTFNTION: Q) .0 75/11.91) CONTACTS: 7 lbs MIN. u .100/12.54) CONTACTS: 5 lbs MIN. A GROUND BLADE: 10 lbs MIN ~ 3. REFER TO SHEETS 1-8 FOR ALL OTHER RELEVANT PLUG CONNECTOR Q) .._. ASSEMBLY AND COMPONENT . DETAILS > ...... c 4. REFER TO SHEET • I FOR THE .075/1 1.91l 1!. CONTACT ASSEMBLY DETAILS. II' roo 9 8 6 5 :::J • 5c(/)rl - 0 1'0 'iii .._.·- ·rn> ·-00::Q) 10 9 8 6 5 ~ _.215 ISEE5.46 NOTE 4~ -- :;} .021 0.53 1 COIN DEPTH ~ -~-+J - E iMATING lDATUM - -+-- --t--- .05 1±.002 .110·.003 Sl IIRT OF 1.29•0.05 TWiST INOTF 3> 2.l9•0.08 B I. THIS DRAWINGREFLECTS THE GEOMrTRY OF HIF .~75/11.91l THE REMAINDER OF ES-7432111-900 AND THE COMPLETE DV! SPECIFICATION. G1:HtR• L rom ...cts, REVIS£ 01~ .028• 002 ,_...,W ,,.;_., .0351,002 I R •0 14•.002 ' 0.89•0.05 !MATING 0.36•0 .05 El ·DATUM MAERIAL I .01~1,000~ I r-- .046 0.30•0.i'J 13 I Ll7 "''7)~~. \ X ' - .035 Dl I I 1\ END OF MATERIAL D ""'- INOTE 31TWIS T SEE DETAIL I / X 0.89 REf. .012d1J005 START OF 0.30•0.013 TWIST INOTE 31 .057<.003 .003..G102 0 1.45•0.05 0.06•0 .05 1.0,..... l~le@IAC01 c I ArTER ..... COINING 0 I.J"l 1.0 DETAIL I B B NOTES: 5>11 I RlV I. THIS DRAWING RELECTS THE GEOMETRY OF THE . 100/12.541 It PLUG ,----..,--,-- = =::-===c:-- -rern-r- TN' F F - .0 16•.0005 E 0.41•0.0 13 E [±] - -1------+- -- .176• .002 .008 4.47•0.05 - MAX. 0.20 .008 MI N. 1~1.002®>IA0>1 0.20 3) 3> B B SHT REV G(~[RALtCL.£"RAt«::£Sl REVISE ON - I NOTES: tUtf..(SS 'SPECIFI£0) C/1.[) ONLY mm !N(; I TITl[t I. THIS DRAWING REFLECTS THE GEOMETRY OF THE DVI ANALOG PLUG 4 ± N/A GROUND BLADE CONTACT. THE INFORMATION IN THIS DRAWING MUST PLACESIt N/A DVT CONNECTOR J. .0QJ!j !CHE_CI(£06V &. DUE. BE USED IN CONJUNCTION WITH THE DVI INTERFACE DETAILS AS J ..,_Atl.~It N/ A DESIGN DETAILS OUTLINED I N ES-74320-900 AND THE COMPLETE DVI SPECIFICATION. 2 PLAC£S 1 0.13 ' N/A 1.-PROv£0 BY & OAT£ lo#aT[RIAL J.IO. ~ A 2. MA TERl AL: COPPER ALLOY, .0 16•.«11005/CI1J.41•0.013) THICK, OR EQUIVALENT. t N/A NONE ~ C:A.DFILf~Air.! ( 3. THE COIN FINISH IS TO BE SMOOTH AND FREE OF TOOL MARKS. t-""""...E..,l,!..~;\-[S:ir7_143:!::2]01.JX5.0!£G(!N!!...j,.,,,.'·''"·~• AND tO> IS BE uS£D 2:l ---===-=-_:_--jj[ ] ~1J 11 s. .JSJ ..., ,. SOLW FOff ll£ ~OS( Of CCMol"t.I•·V.:E ~g Ul£ DYISP(ClllCATIDH...... c o"loorc.1)~~ ~(v A 9 8 6 5 reo 99/0:lllfll L£Vll 41 T T T T T I 2 :::J • 5c(/)rl - 0 rc 'ii) ...-·- :§1~ 00:: , 10 9 1 s I 1 I s I s I 4 I 3 I 2 I I 7~320 I V F F ----r-;-- .0 16• •(1)(1)05 <0·4 1•0.013) - El --Itt!--- .01118 . 100±.002 <0.2illl MAX. <2.54•0.05) E E 1~1.002@IA<1>1 I .0 15•.003 - , ((1J.38•(1).(1)8l -- CHAMFER .008 MIN <2 PLCSl (0.20) • !SEE NOTE 3> D • D 'l77T/77:77 . ....MAJJtl G...OAI UM... _ 77r77777T77777 7 - SIDE FRONT VIEW VIEW ,.....\0 ..... c c 0 ,..... \0 B B I SHT REV NOTES: REVISE ON - C/1.[) ONLY I. THIS DRAWING REFLECTS THE GEOMETRY OF THE DVI DIGITAL PLUG TITl[t KEY CONTACT. THE INFORMATION lN THIS DRAWING MUST BE USED IN CONJUNCTION WITH THE DVI INTERFACE DETAILS AS DVT CONNECTOR OUTLINED I N THE REMAINDER OF ES-74320·9(1)0 AND THE COMPLETE DVI j ~Au:.~It N/ A I J..0QJ!:J 1CHEC I(ED av &. DUE. DESIGN DETAILS SPECIFICATION. 2 PLACEsI• 0.13 1•N/A I•PPROvroev & OAT£ I.I;AT[R ! At J.IO. ~ A tar~ NONE 2. MATERIAL: COPPER ALLOY •• (])16• .011105/<0.4 1•0.0 13l THICK, OR EQUIVALENT. 1 PL 1:: N ~ C:AOFILfJt.,lol.l ( 3. THE. COIN FINISH IS TO BE SMOOTH AND FREE OF TOOL MARKS. t-..,...2..,l,!..~;\.--.:::::.:..:_..:__,;:!.]74~2~(1)1!2S ::.,.Dill!GtJN,.:111S'·''"·~•AND s . tO>.JSJ IS 10 BE uS£D 2:l = __ j_£ES~~3 X§6 4 11 ..., sotW FOff ll£ l\IRPOS( Of CCMol"t.I•·V.:E ~g Ul£ DYISP(ClllCATIDN...... c o"loorc.Q(:i~~(V A 9 8 6 5 J 2 I reo 99/e:Jnra u:vtt 41 T T T T T :::J • 5c(/)rl - 0 rc 'ii) ...-·- :§1~ 00:: 10 9 8 7 6 !) ~ 3 2 ' I I I I I I I I I I 7~320 / . MAX. 1.002 F 125.451 .951•.002 - 124.16•0.051 R .028>.003 TO START . 193•.003 10.70•0 .081 OF RADIUS 14.90±0 .081 : 1 E t .3 11•. 003 J - 17.90•0.081 (:) MAX .358 ._,/ 8 ' 9 10 ! .},., ·~ I D // \ •••I 1.04•0.08141•.00~ ~ · 15°> 1 - R .074•.003 - I 1.89•0 .081 \0,..... "'- c 0 \000 ~ .018 MIN Ol~S[O~S. S>IT REV NOTE CitN,RAt. lOL.EAlt.C(S; I"'"L< IDES IGN UNITS @ C] THIRD •> BE USED IN CONJUNCTION WITH THE DVI INTERFACE DETAILS AS F F . 154•.012 - 13. 90•0.3 I l 1.280±.002 THREAD RUN-OUT <32.51•0.05J - •035 1.100/12.54) MAX. E E - <0.89) RUN-OUT DIAMETER - f- 10 I ~ ~~ ~ D \_ " 4-40 UNC-2A Jr ROLLED THREAD JACKSCREW CABLE ASSEMBLY NOT__/ SHOWN FOR - JACKSCREW CLARITY <2 PLACES) \0,..... "'- c 0 \0"' D m------t-----t------==='-1 - .038 (. 100/12.54) I( ~ 0.97 CONTACT POINT I 1.0,..... c MATJNG MA HNG c "- . Jl..A_T_illA__ _ __ . .. . _____ O~T_U_M__ 0 """"'" ' , 0 ,..... ~ ! ! ! ~~~I ~ ~~ .f ,. t=_ 052 I. THIS DRAWING OUTLINES THE DVI ANALOG & DIGITAL RECEPTACLE CftN[RAL TCL.(~AtC::£51 st>c o"'E"s•"'oN""""u"'••~rs,-,- C]--TH-,RO-.-ccElo mm llll'"'" 0 mm 1 oN @0- - - "'"'" CONNECTOR ASSEMBLY DETAILS. THE INFORMATION IN THIS DRAWING tUIIL(SS 5PECifiEDI NTS omm I!DJHC.. PRo.JECflON I lNo-i mm ll'Hll l , ...0 o~u - ·- MUST BE USED IN CONJUNCTION WITH THE DVI INTERFACE DETAILS AS 7. ~ mtn--IN_('_t_tiffnN BY a. DAlE:. Tl'flf t OUTLINED IN THE REMAINDER OF ES-74320·9~0 AND THE COMPLETE DVI ~t.PLACEd• N/A J• N/A ovr coNNECTOR SPEC IF !CAT ION. 5 0 ~num • N/A ".00~CHEC F KEY SLOf IE .108r.QJIIJ2 2.74•11l.0C. 1~1-002!9>1~®1 o 1 I I _II m1ii5 .1t:51i:51Ci1Ci1CiRi:i. -~ -l.Li .020 •• 002 o (0.51•0.051 ±±:~0751g 1 I ~ "'""-..._ .005.010 DEEPHJGH X "-~ .07 15 . ~ CHAMFER REQUIRED 0 c I 1:82 17.78 • OUTER (SEE NOTE 21 ...-i REF. r:A-l SHIELD c ,...._ B B SHT I REV G[h(.RioL TOI.tftA~ES: R(VIS£ ON f\it.'LESS SPEC:lFIEOl r.AO ONI Y mm I INCH !DRAWNBY S OAl £ llfl[z Q) NOTES: u • PLACES ,, N/A I ' N /A DVI CONNECTOR I. THIS DRAWING OUTLINES THE DVf DIGITAL RECEPTACLE CONNECTOR 3 PLACES I' N/ A 1 < .005 oC>f:CKEO BY ~ DATE DESfGN ~ ASSEMBLY OtT AILS. THE INFORMA ION IN THIS DRAWING MUST BE USED DETAILS Q) .._. A IN CONJUNCTION WITH THE OVI INTERFACE DETAILS AS OUTLINED IN THE REMAINDER OF ES-74320-900 AND THE COMPLETE DVI SPECIFICATION. l.s~:-r4320-900--i0 ·-·1A c ~~~a: ...... CAD Fll(NAME ANGULARz 1 f 0 roo 2. NO CHAMI'"ERS ALLOWED AT THE ENDS OF THE . 1081<2. 741 KEY SLOT. ~~~~ ES 7 432010.DGN :::J(f)rl • ~ Clv oor 1 R .023•:j003 L __/ E 1------. 183±.CIJ03 4,65•0.:38 SECTION X-X R .0 13~.003 I.. ,..... i 'il-j;.. .,1 1- "' ®1•®1 I I 1.30•0J ..05 •, D Dl __ ', ,-, - -1- -t- - .024•.004 .0 13•.0005 -- SEE 0 .61•0.10 0.33•0.013 NOTE 3 I$I0~IA®I ~SEEDETA IL 1 w .001t .002 ISEE. NOTE 41 ~ NOTES ISEE NOTES 5&6l ""'- c .022•.003 0 I. THIS DRAWING REFLECTS THE GECMETRY OF THE .075/(1 .91) It RECEPTACLE 0 .56•0.08 N CONTACT. THE DETAILS IN THIS DRAWING MUST BE USED IN CONJUNCT!ON WITH THE DVI INTERFACE DETAILS AS OUTLINED IN THE REMAINDER OF l$l0~ls®l !SEE NOTE 4! D -+- -+~ -·1)16±.003 D ( - ~ 0.41•0.08 .01!T I REV 4. THIS DIMENSION IS .0 13/10.33) AT MMC GrNti ' F R .050=.003 .890 MIN - ·· .030 <'SEE - 22.61 • 1.27=0.08 OUTER 0. 76 NOTE " 2> r <2 PLCS> r MAX. SHIELD\ I I 1 : <2 PLCS) I E TO START .190t.012l3 f .256 I OF RADIUS 4.83<~lJ.08 .304•.003 6.50' I 7. 72t.08 I M~N. I t ./ I - / ~\. <2 PLCS) / ' R .038:.QJ03 R .072dll03 .23~ I 0.'3R,0.08 ~ l D 1.83!0,08 - IS"'± I_ ~ <2 PLCSl MfN. l= - ATING DATUM \0,..._, "- .946>.0lil3 c 0 24.03•0 .08 ,..._,<::t I I B NOTE DlMENSIOt\St S>IT REV I. THIS DRAWING OUTLINES THE DVI RECEPTACLE SHIELD 'D' PROFILE G(N(RAL TOL.(~IU££S: ~~All DESIGN UNITS I @ CJ THIRD ~•CLE10mm ~ I"<:H 0 mm,l REVISE ON AND MATING DETAILS. THE INFORM~TJON JN THIS DRAWING MUST BE USED JN HliUSS SPECifi(DI NTS omm JXIINCH PRo.JEC.fiON INC>i mm DNl'4' C/1.[) ONLY ou~uNE.D mm INCII DRu·N B'l' a. CIAlE Tlllft CONJUNCTION WI Ill Tll[ DVI !NTERr ACE OET AILS AS ~ IN THE REMAINDER Of [5-74320-900 AND THE COMPLETE DV! SPEC IF !CA T ION. ~ of PLACCS t N/A ± N/A DVT CONNECTOR CHE.CI(EO SY & 0111£. ..,_t -1.0®!) ~ J Atl:.~N/A DESIGN DETAILS 2. THE DESIGN OF THE PLUG CONNECTOR MUST ALLOW FOR THE POTENTIAL ~ 2 PLACES • 0.13 ' N/A APPROv£0BY & OAT£ lo#•TERIAL J.IO. ~ 1" SHH NO. A OF .030/(0.761 PROTRUSION OF THE RECEPTACLE SHIELD BEYOND THE MATING I PLACE. ' N/A ' NONE [5""7'43209001 I; ~ z .. c£ N/A DATUM. ~ ~0.. C:A.O FILfN,Uol( ~ 0 ~NQJLI\A'1!. ~ T~I!EOI M TICIN"CIYl0£1),. [S-UJ2t-,._ IS COV{R[Q6T 0.5 ~~ 5 ~ ES74320 13.DGN ~ 2:l > PAl[lrO'S ... 114.141 AND'5.tt2' .JSJ lHl IS 10 BE USEDSOt.H ..Y B I FOil' Tl£ """'OS( Of CCMol"t.I•·V.:E ~g Ul£ DYISP(ClllCAT IOX...... c "' ,... ,,"'..._.. .., nr.w ~ltv 6. ------reo ' :::J • 5c(/)rl - 0 rc 'iii ...-·- :§1~ OtY 10 I 9 I 8 I I 6 I 5 I I I 2 I 1.280 ------! 32.51 F F ' t ~I - MAX. 216 ACROSS-· POINTS 5.48 ] 02 E T E MAX• - • 18'1 ACROSS ~.80rLAT<; D D RECEPTACLE MOUNTING HARDWARE - CSEE NOTE 2> .....-t- 1.0 ..... c c "0 I Ld-r!~9 MAX. IJ"l -""==~~~====~====u~6 " Appendix C. Digital Monitor Power States Power Switch OtT AND Power Switch Off AND +SV = FALSE Note: Transitions on the +5 volts signal take precedence over Link Active/Inactive and timer transitions Page 76 of 76