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Evaluation of the Hardwired Sequence Control System Generated by High-Level Synthesis,” Proc This is the accepted version of the following article: Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, and Tasuku Tanaka, “Evaluation of the hardwired sequence control system generated by high-level synthesis,” Proc. 2017 IEEE International Symposium on Industrial Electronics (ISIE 2017) (06/2017), which has been published in final form at http://dx.doi.org/10.1109/ISIE.2017.8001426. ⃝c 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Evaluation of the hardwired sequence control system generated by high-level synthesis Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, and Tasuku Tanaka Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, Aichi, Japan [email protected] (Naoki Fujieda), [email protected] (Shuichi Ichikawa) Abstract—This study presents the application of the commer- because the logic circuit is more difficult to target for analysis cial High Level Synthesis (HLS) to a hardwired control appli- and duplication than software. cation with quantitative comparison to the traditional approach that uses logic synthesis with HDL. Though the derived circuits In early studies, Hardware Description Languages (HDL) from HLS are comparable to that of logic synthesis, the design and logic synthesis systems were used to generate a hardwired trade-offs in HLS are difficult to control. This study also presents control circuit. Then, High Level Synthesis (HLS) systems the design and evaluation of the whole system of hardwired appeared and became commercially available to generate a control with a Xilinx Zynq-7000 FPGA platform. From our logic circuit from a popular programming language (e.g. C experiments, two performance bottlenecks were identified: the RAM for memory elements that serializes the read/write accesses, language). With HLS systems, designers can specify hardware and data transfer time via the peripheral bus. According to our functionality at higher level of abstraction to reduce the time results, the sole hardwired control was 10 times faster than the and efforts required for hardware design [14]. original software, while the overall performance was 4 to 50 times worse than the original software. The use of flipflops and On the other hand, HLS tends to be more complex in nature dedicated I/O pins are necessary for high-performance systems. than logic synthesis. Many techniques and optimizations are applied to the design, which involves a large numbers of options and settings. Though the default features of HLS may I. INTRODUCTION yield good results in many cases, it is not always optimal Programmable Logic Controller (PLC) is widely adopted for for a specific application. It might be difficult for users to the sequence control of industrial machinery. Although PLC is control HLS to generate a good hardwired control circuit, and flexible and reliable, there are two problems; i.e., performance the derived circuit might be larger or slower than the circuit and security. The first problem is that the performance of PLC generated from HDL with logic synthesis. All these points does not always satisfy the requirements of large or highly should be clarified before adopting HLS for practical projects. responsive control systems. The second problem comes from The first purpose of this study is to examine the potential of the fact that PLC software is an easy target to duplicate and commercial HLS for control applications, compared to the tra- analyze. ditional approach that adopts logic synthesis and HDL. Three As an answer to these problems, there have been studies to sample programs are converted to logic circuits with HLS and implement PLC software as a hardwired control circuit on a traditional methods, and the derived circuits are quantitatively reconfigurable logic device, e.g. FPGA (Field Programmable evaluated and compared. Though various preceding studies Gate Array). The performance of hardwired logic is generally reported the hardwired control generated by synthesis, HLS, higher than PLC software, and the flexibility of control logic and specially developed tools, they did not compare different can be sustained by the reconfiguration of an FPGA device. approaches in a quantitative manner. To the best of the authors’ Hardwired control is also resistant to duplication and analysis, knowledge, this is the first work that quantitatively discusses the pros and cons of the HLS approach over the traditional approach for hardwired control circuits. ^_ '$SS ,"S,-2 TTX\\T2&#, Another purpose of this work is to examine the performance [X\\. #*1# and the resource requirements of the whole system, which [X\ \. includes the hardwired control circuit as a peripheral device. #,"'$. Though the preceding studies focused on the hardwired control circuit itself (e.g., [5]), a practical system consists of many other parts such as an embedded processor, bus interfaces, Fig. 1. An example of conversion from PLC program to VHDL [6]. memory modules, etc. The performance of the whole system might be much different from that of the sole hardwired control part, because various overheads are involved in the optimization efforts might be drastically reduced by using whole system. The resource requirement of the whole system HLS, which incorporates such optimization techniques [14]. should be also examined along with the performance. This To utilize recent HLS system, PLC instructions have to be study quantitatively discusses such practical aspects of the converted into C language (Figure 2). hardwired control. Economakos [3][4] translated the STL language of Siemens The rest of this paper is organized as follows. Section II S7 PLC into C language, which was then converted to HDL outlines the background and related studies of this work. with Catapult C HLS software. Economakos discussed the Section III introduces the methods to convert PLC software effects of coding styles to the area and the performance in into hardware. Section IV describes the overall design of the FPGA implementations. The use of C-based HLS is par- hardware control system, and Section V presents the evaluation ticularly attractive when the user would like to implement the results. Section VI concludes the paper. hardware partially, leaving most of the software executed as software. Recent HLS systems support hardware/software co- II. RELATED STUDIES design, which enables users to examine the trade-offs between The hardware implementation of control logic has been software and hardware. This approach is also expected to studied since the middle of 1990s, along with the rapid be applicable to C-based PLCs, which have become popular evolution of FPGA technologies. Adamski [1] and Wegrzyn among PLC users. [15] presented systems that transfer the PLC program in Despite the pioneering works by Economakos, it is still Petri-net format into HDL. Ikeshita et al. [7] converted PLC indefinite whether the current HLS system can replace the old software in SFC into Verilog HDL, while Miyazawa et al. [13] design scheme. If the optimizations of HLS are insufficient proposed to convert the ladder diagram to VHDL. These early or not suited to hardwired control, the derived circuit might studies adopted HDL and logic synthesis to generate the logic be slower or larger than that generated by HDL and logic circuit that corresponds to the original PLC software. synthesis. Even if HLS is well established, it might be difficult Figure 1 illustrates an example of PLC software and the to derive the best result, since a commercial CAD system is a corresponding VHDL code [5]. First, a rung of ladder diagram kind of black box. It applies every possible techniques in the is compiled into the corresponding PLC instructions. The black box, and shows the sole result of trade-offs out of vast converter then reads the PLC instructions and converts them variety of possibilities. It is sometimes difficult to control the into the corresponding VHDL, rung by rung. The condition optimization process, and to analyze the factors separately. part of the rung is converted into the corresponding conditional This work discusses the pros and cons of an HLS approach statement, and the output part is converted into the correspond- over the traditional approach for hardwired control circuits, ing assignments. using Xilinx tools and FPGAs. The following studies explored the optimization schemes for hardwired control. As an example, Ichikawa et al. [5][6] III. CONVERSION OF PLC PROGRAM proposed to convert PLC software into logic circuit for higher Throughout this study, Mitsubishi MELSEC-Q series performance and higher security. They converted PLC instruc- PLC [12] is assumed as the target platform. Mitsubishi GX tions to VHDL code, which was then synthesized by using the Works [11] software with GX Converter [10] is adopted commercial logic synthesizer. The performance advantages of to generate the instruction list as a text file. The derived three design options (Sequential Design, Levelized Design, instruction list is specific to MELSEC PLCs, while it well and Flat Design) were quantitatively evaluated, where the resembles to the IEC-61131 instruction list. It is thus expected parallelism in hardwired control was utilized. Du et al. [2] that the following discussion holds good in IEC-compliant and Milik [9][8] also discussed the optimization techniques PLCs. to generate a high-performance control circuit from a PLC instruction sequence. A. PLC-to-C conversion Though the above studies discussed the techniques to utilize A custom-made converter was developed to convert a PLC the parallelism in the PLC instruction sequence, many of instruction sequence into the corresponding code of standard these techniques are common and well known in the com- C language. This converter is designated as the C-converter in puter architecture or design automation communities.
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