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CISC Processor - Intel X86
Architecture of Computers and Parallel Systems Part 4: Intel x86 History Ing. Petr Olivka [email protected] Department of Computer Science FEI VSB-TUO Architecture of Computers and Parallel Systems Part 4: Intel x86 History Ing. Petr Olivka [email protected] Department of Computer Science FEI VSB-TUO Architecture of Computers and Parallel Systems Part 4: Intel x86 History Ing. Petr Olivka [email protected] Department of Computer Science FEI VSB-TUO CISC Processor - Intel x86 This chapter will introduce the CISC processors evolution. We will try to illustrate the history on one typical processor, because the comparison of multiple processors simultaneously would not be clear for readers. But the selection of one typical processor is complicated due to a variety of products and manufactures in the past 30 years. We have decided to describe in this presentation one of the best- known and longest mass-produced processors in existence. We definitely do not want to say that it is the best technology or that these are processors with the highest performance! The Intel x86 processors are the selected product line. Intel 8080 (Year-Technology-Transistors-Frequency-Data bus-Address Bus) Y: 1974 T: NMOS 6μm Tr: 6000 F: 2MHz D: 8b A: 16b This 8 bit processor is not directly the first member of x86 series, but it can not be skipped. It is one of the first commercially successful microprocessors. This microprocessor became the basis for a number of the first single-board computers and its instruction set inspired other manufacturers to develop 8-bit processors. -
Software Problems of an Experimental Robot
PERIODICA POLITECHHICA SER EL ENG. VOL 46, NO J-J. PP. 151-16112002) SOFTWARE PROBLEMS OF AN EXPERIMENTAL ROBOT CONTROLLER BASED ON QNX REAL-TIME OPERATING SYSTEMS Istvan OLAH and Gdbor TEVESZ Department of Auiomation and Applied Informatics Budapest University of Technology and Economics H-l 111 Budapest, Goldmann Gyorgy tc"r 3. Hungary Phone: (+36-1)463-2870, Fax: (436-1)463-2871 e-mail: [email protected]; [email protected] Received: July 1,2003 Abstract At the Department of Automation and Applied Informatics an experimental robot control system has been developed. The purpose of this research is to study modern robot control algorithms and their realization in a real environment. The project focuses on the problems of multiprocessor systems including the task distribution and communication. Another field of this research is to integrate a six-component forcc-torquc sensor into the robot control system and making use of this information in new robot control algorithms. Another purpose of this study is to examine the software problems of an IBM PC-based multiprocessor system controlling a NOKIA-PUMA 560 humanoid robot arm. The features and system services of the new QNX Neutrino operating system is presented in comparison with the previously used QNX v4. The main areas of the version upgrade will be shown focusing on the interprocess communication questions. The processing components of this multiprocessor robot control system with its external interfaces will be discussed later and some further system level development possibilities will be outlined. This final part of the study gives the summary of the architectural and communication requirements of a hybrid position and force control system in the above environment. -
Communication Theory II
Microprocessor (COM 9323) Lecture 2: Review on Intel Family Ahmed Elnakib, PhD Assistant Professor, Mansoura University, Egypt Feb 17th, 2016 1 Text Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey, Prentice Hall, 2009 2. Assembly Language for x86 processors, 6th edition, K. R. Irvine, Prentice Hall, 2011 References: 1. Computer Architecture: A Quantitative Approach, 5th edition, J. Hennessy, D. Patterson, Elsevier, 2012. 2. The 80x86 Family, Design, Programming and Interfacing, 3rd edition, Prentice Hall, 2002 3. The 80x86 IBM PC and Compatible Computers, Assembly Language, Design, and Interfacing, 4th edition, M.A. Mazidi and J.G. Mazidi, Prentice Hall, 2003 2 Lecture Objectives 1. Provide an overview of the various 80X86 and Pentium family members 2. Define the contents of the memory system in the personal computer 3. Convert between binary, decimal, and hexadecimal numbers 4. Differentiate and represent numeric and alphabetic information as integers, floating-point, BCD, and ASCII data 5. Understand basic computer terminology (bit, byte, data, real memory system, protected mode memory system, Windows, DOS, I/O) 3 Brief History of the Computers o1946 The first generation of Computer ENIAC (Electrical and Numerical Integrator and Calculator) was started to be used based on the vacuum tube technology, University of Pennsylvania o1970s entire CPU was put in a single chip. (1971 the first microprocessor of Intel 4004 (4-bit data bus and 2300 transistors and 45 instructions) 4 Brief History of the Computers (cont’d) oLate 1970s Intel 8080/85 appeared with 8-bit data bus and 16-bit address bus and used from traffic light controllers to homemade computers (8085: 246 instruction set, RISC*) o1981 First PC was introduced by IBM with Intel 8088 (CISC**: over 20,000 instructions) microprocessor oMotorola emerged with 6800. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Evolution of the Pentium
Chapter 7B – The Evolution of the Intel Pentium This chapter attempts to trace the evolution of the modern Intel Pentium from the earliest CPU chip, the Intel 4004. The real evolution begins with the Intel 8080, which is an 8–bit design having features that permeate the entire line. Our discussion focuses on three organizations. IA–16 The 16–bit architecture found in the Intel 8086 and Intel 80286. IA–32 The 32–bit architecture found in the Intel 80386, Intel 80486, and most variants of the Pentium design. IA–64 The 64–bit architecture found in some high–end later model Pentiums. The IA–32 has evolved from an early 4–bit design (the Intel 4004) that was first announced in November 1971. At that time, memory came in chips no larger than 64 kilobits (8 KB) and cost about $1,600 per megabyte. Before moving on with the timeline, it is worth recalling the early history of Intel. Here, we quote extensively from Tanenbaum [R002]. “In 1968, Robert Noyce, inventor of the silicon integrated circuit, Gordon Moore, of Moore’s law fame, and Arthur Rock, a San Francisco venture capitalist, formed the Intel Corporation to make memory chips. In the first year of operation, Intel sold only $3,000 worth of chips, but business has picked up since then.” “In September 1969, a Japanese company, Busicom, approached Intel with a request for it to manufacture twelve custom chips for a proposed electronic calculator. The Intel engineer assigned to this project, Ted Hoff, looked at the plan and realized that he could put a 4–bit general–purpose CPU on a single chip that would do the same thing and be simpler and cheaper as well. -
Dstni-LX Data Book
DSTni-LX Data Book Revision F Part Number GC-900-252 Copyright and Trademark © 2003 Grid Connect, Inc. All rights reserved. No part of this manual may be reproduced or transmitted in any form for any purpose other than the purchaser's personal use, without the express written permission of Grid Connect, Inc. Grid Connect, Inc. has made every effort to provide completeness and accuracy of this material, but makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose. In no event shall Grid Connect, Inc. be liable for any incidental, special, indirect, or consequential damages whatsoever included but not limited to lost profits arising out of errors or omissions in this manual or the information contained herein. Grid Connect, Inc. products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of a Grid Connect, Inc. product could create a situation where personal injury, death, or severe property or environmental damage may occur. Grid Connect, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Grid Connect and the Grid Connect logo, and combinations thereof are registered trademarks of Grid Connect, Inc. DSTni is a registered trademark of Lantronix, Inc. Ethernet is a registered trademark of Xerox Corporation. Am186 is a trademark of Advanced Micro Devices, Inc. -
CV Full Version
CURRICULUM VITAE M C Willett Name : Mike Willett Online CV at : http://vsmt.21-dc.com Address : 16011 Arenzano (GE), Italy. Poole, Dorset, BH16 5LF, England Telephone : t. +44 1212 886044 (24/7) m. +39 348 002 0847 E-mail : [email protected] Nr. of Years in Industry : 39 years Nationality : English Marital Status : Married with a son. Date of Birth : 6th October 1960 Languages : Italian and basic German. Summary of Experience I have over 30 years of embedded software experience and consider myself an expert in developing real-time embedded software using the C programming language. When I refer to real-time embedded software, I mean true multi-tasking software on a proper pre-emptive operating system with interfaces to the event driven world of hardware control and user interfaces. I have in-depth knowledge of device drivers, software control of system hardware components and product specific electro-mechanical devices. Additionally, I have a good understanding of hardware at the device level. I also have enthusiasm and expertise in requirements capture and specification. Key to any project is communication and I feel this is something that I am good at both in the written and spoken word – most importantly, I enjoy helping to bring clarity and visibility to a project, a pre- requisite for success. Specialist Skills Real-time, multi-tasking operating systems and device drivers for embedded products. Software development, firmware and 'bare metal' programming. SoCs and ASICs. Software architecture, technical auditing, project management of full product lifestyle, SW porting and reverse/re-engineering. Excellent communicator and documentation skills. -
CPU History [Tualatin] [Banias] [Dothan] [Yonah (Jonah)] [Conroe] [Allendale] [Yorkfield XE] Intel Created Pentium (From Quad-Core CPU
2nd Generation 4th Generation 5th Generation 6th Generation 7th Generation 3rd Generation Intel Pentium III-S Intel Pentium-M (Centrino) Intel Pentium-M (Centrino) Intel Core Duo (Viiv) Intel Core 2 Duo (Viiv)/Xeon Intel Core 2 Duo (Viiv) Intel Core 2 Extreme (Viiv) Intel had the first consumer CPU History [Tualatin] [Banias] [Dothan] [Yonah (Jonah)] [Conroe] [Allendale] [Yorkfield XE] Intel created Pentium (from quad-core CPU. x86/CISC Microprocessors Greek penta which means (2001) (2003) (2004) (2006) (2006) (2007) (2007) 1st Generation Intel Pentium II Xeon Intel Pentium III Xeon Centrino is not a CPU; it is Begin Core five) to distinguish the Intel [P6] [Tanner] a mobile Intel CPU paired nomeclature brand from clones. Names (1998) (1999) Intel Celeron with an Intel Wi-Fi adapter. Intel Celeron Intel Core Solo can be copyrighted, product [Tualeron] [Dothan-1024] Intel Xeon LV Intel Celeron Intel Celeron [Yonah] ID's cannot. (2001) (2004) [Sossaman] [Banias-512] [Shelton (Banias-0)] (2006) (2006) Intel Core 2 Duo Intel Core 2 Extreme Intel Celeron Intel 80386 DX Intel 80486 DX Intel Pentium Intel Pentium Pro Intel Pentium II Intel Pentium II Intel Pentium III Intel Pentium III Intel Pentium 4 Intel Pentium 4 (2004) (2004) Intel Pentium 4 Intel Pentium 4 Intel 4004 Intel 8008 Intel 8086 Intel 80286 [Conroe XE] [Conroe-L] [P3] [P4] [P5/P54/P54C] [P6] [Klamath] [Deuschutes] [Katmai] [Coppermine] [Williamette] [Northwood] [Prescott] [Cedar Mill] END-OF-LINE (Centrino Duo) (1971) (1972) (1978) (1982) (2006) (2007) (1985) (1989) (1993) (1995) (1997) (1998) (1999) (1999) (2000) (2002) (2004) (2006) [Merom] (2006) Yonah is Hebrew for Jonah. -
Microprocessors and Microcontrollers Material
MICROPROCESSORS AND MICROCONTROLLERS MATERIAL UNIT – I OVERVIEW ➢ Introduction to microprocessors ➢ Evolution of microprocessors ➢ Features of 8085 microprocessor ➢ Pin Diagram of 8085 microprocessor ➢ Architecture of 8085 ➢ Addressing modes of 8085 ➢ Timing Diagrams ➢ Instruction set DEPARTMENT OF ECE 1. MICROPROCESSORS AND MICROCONTROLLERS MATERIAL UNIT-I INTRODUCTION: Microprocessor acts as a CPU in a microcomputer. It is present as a single IC chip in a microcomputer. Microprocessor is the heart of the machine. A Microprocessor is a device, which is capable of 1. Receiving Input 2 Performing Computations 3. Storing data and instructions 4. Display the results 5. Controlling all the devices that perform the above 4 functions. The device that performs tasks is called Arithmetic Logic Unit (ALU). A single chip called Microprocessor performs these tasks together with other tasks. “A MICROPROCESSOR is a multipurpose programmable logic device that reads binary instructions from a storage device called memory accepts binary data as input and processes data according to those instructions and provides results as output.” Figure shows a programmable machine, which consists of a microprocessor, memory, I/O. All these three components work together to perform a given task. EVOLUTION OF MICROPROCESSORS: The microprocessor age began with the advancement in the IC technology to put all necessary functions of a CPU into a single chip. Intel started marketing its first microprocessor in the name of Intel 4004 in 1971. This was a4-bit microprocessor having 16-pins in a single chip of PMOS technology. This was called the first generation microprocessor. The Intel 4004 along with few other devices was used for making calculators. -
Advanced Microprocessors 1
Advanced Microprocessors 1 Intel 80186 80186 contain a 16-bit data bus. The internal register structure of the 80186 is virtually identical to the 8086. The only difference is that the 80186 contain additional reserved interrupt vectors and some very powerful built in I/O features. The 80186 and 80188 are often called embedded controllers because of their application as a controller, not as a microprocessor-based computer. Features The 80186 contains 16 bit data bus. The internal register structure of 80186 is virtually identical to the 8086. Enhanced 8086-2 CPU. Clock Generator. 2 Independent DMA Channels. Programmable Interrupt Controller. 3 Programmable 16-bit Timers. Programmable Memory and Peripheral Chip-Select Logic. Available in 10 MHz and 8 MHz Versions. Direct Addressing Capability to 1 Mbyte of Memory and 64 Kbyte I/O. Architecture Muhammed Riyas A.M, Asst.Professor,Dept. Of E.C.E,MCET Pathanamthitta Advanced Microprocessors 2 In addition to the BIU and EU, the 80186 family contains a clock generator, a programmable interrupt controller, programmable timers, a programmable DMA controller and a programmable chip selection unit. These enhancements greatly increase the utility of the 80186 and reduce the number of peripheral components required to implement a system. Clock Generator. The internal clock generator replaces the external 8284A clock generator used with the 8086/8088 microprocessors. This reduces the component count in a system. The internal clock generator has three pin connections: X1, X2, and CLKOUT. The X1 (CLKIN) and X2 (OSCOUT) pins are connected to a crystal that resonates at twice the operating frequency of the microprocessor. -
Microprocessor, Microcomputer and Their Applications Fourth Edition
Microprocessor, Microcomputer and their Applications Fourth Edition A.K. Mukhopadhyay Alpha Science International Ltd. Oxford, U.K. Contents vii Preface to the Fourth Edition Preface to the First Edition ix 1. Microprocessor-A Physical System 1 2. The Microprocessor System 5 2.1 Central Processing Unit (CPU) 5 2.2 Arithmetic-Logic Section 6 2.3 Accumulator 6 2.4 Status Registers 7 2.5 ALU 7 2.6 General Purpose Registers 8 2.7 Control Registers 8 2.8 Program Counter (PC) 8 2.9 Stack Pointer (SP) 8 2.10 Index Register (IX) 9 2.11 Instruction Register (IR) and Decoder 9 2.12 Timing and Control Unit 9 2.13 The Clock 70 2.14 Reset 70 2.15 Interrupt 70 2.16 Hold 70 2.17 READ and WRITE 7 7 2.18 IORandMR77 2.19 Address Latch Enable 77 3. The 8085A Microprocessor 12 3.1 Architecture and Organisation of 8085A 72 3.2 The ALU 14 3.3 Registers 14 3.4 Timing and Control Unit 75 3.5 Pin Configuration of 8085A 77 3.6 Interface 18 INTEL 8085 Assembly Language Programming 4.1 Instruction Set for 8085/8085A 22 4.2 Data Movement Instructions 23 4.3 PUSH and POP 25 4.4 Increment and Decrement Instructions 26 4.5 Rotate and Shift Instructions 26 4.6 Set, Compliment and Decimal Adjustment Instructions 28 4.7 Add, Subtract and Compare Instructions 29 4.8 AND, OR EXCLUSIVE-OR Instructions 30 4.9 JUMP, CALL and RESTART Instructions 31 4.10 CONDITIONAL JUMP, CALL and RETURN 31 4.11 Loops in Programs 32 4.12 Uses of Subroutines 33 4.13 Delay Subroutine 38 4.14 Instruction Modes 43 4.15 Instruction Bytes 43 Memories 5.1 Semiconductor Memories 45 5.2 Non-volatile RAM 46 5.3 Pin Configuration of RAM, EPROM and EEPROM 47 5.4 Dynamic RAM 48 5.5 Memory Map 49 Interfacing the Microprocessors 6.1 Speed 50 6.2 Level 50 6.3 Data Form 57 6.4 Control Bus Function 51 6.5 Bus-Demultiplexing 54 6.6 Decoder and Address Decoding 54 6.7 Mapping 58 6.8 Timing Parameters 60 6.9 READ Operation 60 6.10 WRITE Operation 61 6.11 WAIT State 63 6.12 HOLD State 64 6.13 HALT State 65 6.14 Interrupt States 65 Contents 7. -
Intel80386ex Emulator/Analyzer Installation/Service
Installation/Service/Terminal Interface Guide Intel80386EX Emulator/Analyzer (HP 64789B) Notice Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material. Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Hewlett-Packard. © Copyright 1995, 1996 Hewlett-Packard Company. This document contains proprietary information, which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced or translated to another language without the prior written consent of Hewlett-Packard Company. The information contained in this document is subject to change without notice. UNIX(R) is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company Limited. Intel386, Intel80386, Intel486, and Intel80486 are U.S. trademarks of Intel Corporation. Hewlett-Packard Company P.O. Box 2197 1900 Garden of the Gods Road Colorado Springs, CO 80901-2197, U.S.A. RESTRICTED RIGHTS LEGEND. Use, duplication, or disclosure by the U.S. Government is subject to restrictions set forth in subparagraph (C) (1) (ii) of the Rights in Technical Data and Computer Software Clause at DFARS 252.227-7013. Hewlett-Packard Company, 3000 Hanover Street, Palo Alto, CA 94304 U.S.A. Rights for non-DOD U.S. Government Departments and Agencies are as set forth in FAR 52.227-19(c)(1,2).