Plastic Low-Cost Circuits Enabled Through Nanotechnology

Wright State University CORE Scholar

Physics Seminars Physics

2-12-2013

Paul R. Berger

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Repository Citation Berger , P. R. (2013). Plastic Low-Cost Circuits Enabled Through Nanotechnology. .

This Presentation is brought to you for free and open access by the Physics at CORE Scholar. It has been accepted for inclusion in Physics Seminars by an authorized administrator of CORE Scholar. For more information, please contact [email protected]. Plastic Low-Cost Circuits Enabled Through Nanotechnology

“Quantum Functional Circuitry”

Paul R. Berger Department of Electrical and Computer Engineering Department of Physics The Ohio State University Columbus OH, 43210 USA

PDL Wight State Univ. visit (Berger) Feb. 12, 2013 Research at OSU

 Nanoelectronics and Optoelectronics Lab

 OSU Campus Electron Optics Facility

 Nanotech West Lab  5000 square foot class 100 cleanroom The Ohio State University

 Largest Single-Campus University in USA (~7 km2)  Largest University by Enrollment (63,217 as of 2010)  5 Campuses including Main Campus in Columbus 175 undergrad majors; 12,000 courses, 465,000 living alums

 Space Grant  Ohio Space Grant Consortium  OSU Airport

 Land Grant  Sea Grant

 ATI  Stone Lab.  OARDC ECE at OSU

 48 faculty members and 14 researchers are active in the areas of:  Communication, Electromagnetics, Computer Systems, Computer Networks, Computer Vision, Control Systems, Electro-Mechanical Systems, Electronic Materials and Devices (EMDL, EMNLAB, NOEL, PDL) , High Performance Networking and Computing, Intelligent Transportation Systems, Mixed-Signal VLSI Circuit Design, Power Engineering, Signal Processing, and Wireless Communication.  Our annual external funding is about $17M.  17 are IEEE fellows and 3 National Academy of Engineering members.  In the last three years, six of our faculty won the prestigious NSF CAREER award.  Our research laboratories are housed in four buildings: Dreese Labs, Caldwell Labs and the Electro Science Lab (I & II).

 Undergraduate ECE enrollment is ~1200 students.  Graduate enrollment is ~400 students.  About 20 Ph.D. and 70 M.S. degrees awarded every year. Solid State Electronics at OSU

Institute of Materials Research  More than 120 faculty members, including 9 ECE professors  Research groups from 19 departments

Notable OSU ECE Alumni in Solid State Area

 (Ph.D, ‘52)  Dawon Kahng (Ph.D, ‘59) John L. Moll  Robert S. Chau (Ph.D, ‘89)  Ebers-Moll Transistor model  Invented the First Practical  Intel Senior Fellow MOSFET  Director of Transistor  Invented Floating Gate Memory Research and Nanotechnology, Cell Intel Ohio Wright Center for Photovoltaics Innovation and Commercialization (PVIC)

 Funded by Ohio Department of Development Third Frontier Program

 $18.6M initial State funding with $29.7M in cost-share from members

 Approximately half of ODOD funding is capital

 OSU portion of PVIC State funding is $6.8M

 A major focus is on technology brought to the marketplace instead of exclusive academic research

 Initial team: three universities (OSU, U. Toledo, Bowling Green State U.), three not-for-profits (Battelle, EMTEC, Green Energy Ohio), and sixteen industry members (Founding Members)

 Membership now open to new companies for low annual fees Selected Labs at OSU

 Nanotech West Lab  5000 square foot class 100 cleanroom

 Campus Electron Optics Facility  4 transmission electron microscopes (TEMs),  3 scanning electron microscopes (SEMs),  2 Dual-Beam FIBs, and  4 X-ray diffractometers (XRDs).  FEI’s Titan S/TEM is a state-of-the-  Vistec EBPG-5000 20 / 50 / 100 keV art STEM with an aberration- electron beam nanolithography tool corrected probe-forming system,  Zeiss Ultra 55 Plus field emission monochromator and high- scanning electron microscope resolution spectrometer capable of (FESEM) Angstrom scale nanoanalysis. New PVIC Equipment at Nanotech West - I

 Picosun® atomic layer deposition (ALD) • Capable of atomically precise deposition on samples and wafers up to 150mm • This tool can utilize solid source precursors

• Currently capable of depositing Al2O3, ZnO, Ta2O5 , TiO2 • Currently developing deposition procedures with conjugated polymers New PVIC Equipment at Nanotech West - II

 Aixtron Swan® metalorganic chemical vapor deposition (MOCVD) tool grew first epi layers in 3Q09

. Industry-style tool capable of fast growth of arsenides, phosphides, and [future] antimonides

. 3x2” close-coupled showerhead (CCS) design

. $1.6M installation

. Already have 3 industrial customers for epitaxial growth with this tool, including 2 Ohio customers, one with non-PV product application New PVIC Equipment at Nanotech West - III

 AJA International Orion® five-gun RF/DC sputter deposition tool

. Commissioned in November 2009

. Load-locked system with UHV gun option from AJA

. Intended for general use sputter depositions (W, Pd, Ti, Ni, Cr, Ti/W, Al, Cu, …) filling a need for the OSU materials research community

Moore’s law 6T SRAM cache memory dominates footprint Intel’s Core i7 and power consumption, operates about 1 volt (→ 8T SRAM)

Power consumption related to voltage squared (~1 volt state-of-the-art) NOEL 2005 ITRS – Emerging Research Devices Why use with transistors? TD • • How to characterize tunnel diode? to characterizetunnel How • NOEL Simple integrationwithtransistor – Lowerscircuitpower – circuitcomplexity Reduces – Increases circuitspeed – Speed index – – – Peak currentdensity Peak-to-valley currentratio s = J s = J PVCR =I p = I p p / C / Area Introduction toAdvantagesof j p / I v Tunnel Diodes

Current I p I v Voltage negative differential resistance (NDR)

“N-shaped”

Opportunity: Tunnel Diode Memory

• One Transistor 2-Tunnel Diode SRAM (1T TSRAM) • Robust operation at low voltages • Refresh-free – Low active and standby power Consumption

• J. P. A. van der Wagt, A. C. Seabaugh, and E. A. Beam, III, “RTD/HFET low standby power SRAM gain cell,” IEEE Electron Dev. Lett. 19, pp. 7-9 (1998).

• J. P. A. van der Wagt, “Tunneling-Based SRAM,” Proc. of IEEE, 87, pp. 571-595 (1999). LATCHED COMPARATOR 25 GHz DESIGN (Courtesy A. Seabaugh, formerly Raytheon Systems) Conventional Quantum • Latching behavior is inherent to RTD VDD VDD2 • Settling time is determined by RTD OUT OUT VDD VDD2 switching speed

CLK IN VREF OUT •Regenerative feedback gives latching IN • Feedback loop has long settling time

GND Quantum Conventional VSS 2 2 25 GHz clock 2 RTDs V CLK out V GND 2 HFETs out 1 Area=1 V V ref VSS in 1 Voltage Voltage clk 0 12 HFETs 25 GHz clock 6 Schottky V in clk Diodes 0 -1 0 -12 -12 0 -12 -12 Area=6 0 10 400 10 800 10 0 10 400 10 800 10 Time SPICE Simulations Time NOEL MOBILE Logic

V • MOBILE (Monostable-Bistable) Logic CLOCK –Two serially connected Tunnel Diodes driven by a clock TD – Self Latching action of tunnel diodes VOUT – When clock high, final state latched depending on relative peak current of the two tunnel diodes. Device with lower peak TD current switches from on to off state (controlled quenching).

Low State Latch Monostable Device with lower peak current - off state Bistable (low)

VOUT V V V CLOCK VOUT V VOUT LOW CLOCK High State Latch CLOCK Monostable Device with lower peak Bistable (high) current - off state

VOUT V V CLOCK VOUT VCLOCK VOUT HIGH VCLOCK Boolean Logic

• Inverter – Peak current is proportional to device area. Device with larger

area has higher current (assuming VCLOCK constant current density). Here AreaTDL>AreaTDD – Peak current of driver tunnel diode varied by addition of parallel tunnel TDL diode. Currents in parallel branches V add OUT – Transistor acts as a switch to TD activate parallel branch TDD V – When VIN =‘0’, ITDL>ITDD output=1, IN when VIN=‘1’ ITDD+ITD>ITDL output=0 • Output changes only on positive clock edge – Nanopipelining: each logic gate is clocked enabling very high clock frequencies without the need of additional circuitry for pipelining

“Threshold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices”, C. Pacha et.al., IEEE Trans. On VLSI Systems, 8(5), 558, 2000 Multi-value Logic

• Stacked NDR Devices • Same principle can be extended to obtain multi-value logic inverter

Normalized peak current value y= 2-x1 Logic levels ‘0’, ‘1’, ‘2’

3 valued inverter circuit

clock

Input Inverted output

“Multiple-Valued Logic Circuits Design using Negative Differential Resistance Devices”, K. S. Berezowski et.al., ISMVL, 2007 Reconfigurable Logic

Same circuit can be configured to act as different logic gates depending on control bit values

Reconfigurable AND/XOR gate

Control c = 0, Control c = 1, AND gate XOR gate

“Reconfigurable RTD-based Circuit Elements of Complete Logic Functionality”, Y. Zhang et.al., ASPDAC, 2008 The Payoff: TDs Integrated with Transistors

More computational power per unit area  Fewer devices required  Faster circuits and systems  Reduced power consumption

Result: Extension of CMOS if a Si-Based TD is available that is compatible with CMOS!

NOEL Outline

 Motivation & Circuit Application  Epitaxy constraints on Si-based NDR devices  Our MBE-grown RITD device  CVD-grown RITDs with IMEC  TSRAM memory array  Future: TFETs?

NOEL Basic Physics: Esaki Tunnel Diode

(Interband) E

E E E E E E E E E E E V n(E) V V V V n(E) n(E) p(E) p(E) n(E) p(E) n(E) p(E) p(E) n(E) p(E) Thermal diffusion current Tunneling current Peak Excess current Tunneling current

I I I I I I

V V V V V V

(a) (b) (c) (d) (e) (f) Degenerate Doping Required – Difficult with conventional epitaxy

For more info see L. Esaki, “New phenomenon in narrow Germanium p-n junctions,” Phys. Rev., vol. 109, p. 603, 1958. Prior Art: Lack of Si-Based TDs that can be Monolithically Integrated with Si transistors

Ge Esaki Diode Si Esaki Diode • Vintage 1960’s alloy technology prevents large-scale batch processing • Discrete Esaki diodes are ideal for niche applications. • However the alloy process does not lend itself to an integrated circuit. Basic Physics: Resonant Tunneling Diode (Intraband) intrinsic

V V V emitter collector Tunneling current I Excess current Thermal diffusion current I I I

V V V V (a (b (c (d ) ) ) ) Large Band Offset Required Si/SiGe heterojunction has limited band offset

For more info see L. L. Chang, L. Esaki without a thick relaxed buffer and R. Tsu, “Resonant tunneling in Alternative barriers (i.e. SiO2) present difficult semiconductor double barriers,” Appl. Phys. Lett., vol. 24, pp. 593-595, 1974. heteroepitaxy of single crystal Si quantum well atop amorphous barrier Basic Physics: Resonant Interband Tunneling Diode n ‐delta doping

V V V

p‐ delta doping

Tunneling current Excess current Thermal diffusion current

I I I I

V V V V

(a) (b) (c) (d)

For more info see M. Sweeny and J. Xu, δ-doping to form quantum wells; “Resonant interband tunnel diodes,” Appl. Phys. eliminates need for degenerately Lett., vol. 54, pp. 546-548, 1989. doped junctions NOEL

current in therefore higher PVCRs valley region and Greater defect annihilation leads tolessexcess Current (mA) 0 1 2 3 4 5 6 7 . 02 . 06 . 1.0 0.8 0.6 0.4 0.2 0.0 PCD: 142A/cm PVCR: 4.03 High Peak-to-Valley CurrentRatios OSU/NRL RITDs OSU/NRL 800 Voltage (V) etched byetched HBr o C, 1-min anneal 1-min C,

2 (#050322.2) (#050322.2)

Si/Si Energy (eV) Grown at 320 -0 .5 -1 .5 0.5 -1 0.6 0 1 5 0 60 5 5 50 45 Ge V = 0 .4 V |X 0.4 xy

> S RITDs /Si |X z > P os ition (n m ) MBE Heterostructure o C

HH Tunnel

X Barrier z SO X 4 nm undoped Si 4 nmundoped xy LH 1 nmp+Si |H H > 4 nm undoped Si 4 nmundoped B  P p+ Sisubstrate 100 nm p+ Si 100 nmp+  Si 100 nmn+ |L H > -doping plane -doping plane 0.6 R. Lake(UC Riverside) Courtesy Ge 0.6 0.4 Ge 0.4

First Si-Based Resonant Interband Tunnel Diodes

EC Upper Quantum Lower Barrier Well Barrier Production Approach (eV) Status Crystalline Crystalline Crystalline Potential

SiO2/a-Si/SiO2 3.2 No No No High Abandoned -H igh scattering in quantum, no room temperature PVR

CaF2/Si/CaF2 2 Yes Yes Yes Low Abandoned - Tendency for island growth, defect-assisted transport below 10 nm

ZnS/Si/ZnS 1 Yes Yes Yes Med. ZnS on Si growth established, Si quantum well growth under study Front page of the Wall SiO2/Si/SiO2 3.2 No Yes No Med. Process for forming oxide islands established, Lateral overgrowth overgrowth process under development Street Journal ZnS/Si/ZnS 1 Yes Yes Yes Med. ZnS islands have been prepared for first Lateral overgrowth overgrowth experiments (October 1, 1998).

SiO2/SiGe(C)/SiO2 3.2 No Yes No Med. Oxide islands have been prepared for first Lateral overgrowth overgrowth experiments

Si/SiGe - - - - High World’s first demonstration on Si; resonant interband room temperature peak-to-valley tunnel diode current ratio of 1.6

980505

A paradigm shift from other approaches was spearheaded by a team of researchers lead by Berger (then at the University of Delaware), Naval Research Laboratory and Raytheon Systems. • DARPA Award of Excellence (1998) • Late News at International Electron Devices Meeting (1998) • Best Science/Engineering Dissertation (2000) • Special Invitation to 2003 ITRS Meeting • IEEE Fellow (2011) NOEL NOEL Tampere (Berger) visit current in therefore higher PVCRs valley region and Greater defect annihilation leads tolessexcess Current (mA) 0 1 2 3 4 5 6 7 . 02 . 06 . 1.0 0.8 0.6 0.4 0.2 0.0 PCD: 142A/cm PVCR: 4.03 High Peak-to-Valley CurrentRatios OSU/NRL RITDs OSU/NRL 800 Voltage (V) etched byetched HBr o C, 1-min anneal 1-min C,

2 (#050322.2) (#050322.2)

Si/Si Energy (eV) Grown at 320 -0 .5 -1 .5 0.5 -1 0.6 0 1 5 0 60 5 5 50 45 Ge V = 0 .4 V |X 0.4 xy

> S RITDs /Si |X Oct. 28, 2010 z > P os ition (n m ) MBE Heterostructure o C

HH Tunnel

Tailorable Peak Current Densities

Current densities can be 4 10 engineered over ~8 orders of 103 magnitude by controlling RITD 8 nm

) spacer thickness between the δ 2 102 10 nm doping pair from 1 nm up to 16 nm. 1 10 5 ) 10

12 nm 2

4 Red data points 100 10 indicated occur at 14 nm Mixed signal maximum PVCR 103 10-1 15 nm 102 Logic 10-2 16 nm 101 Current Density (A/cm -3 10 o 100 825 C annealed, 1 min Memory -1 10-4 10 0.0 0.20.4 0.60.8 1.0 -2

Peak Current Density (A/cm Density Current Peak 10 Voltage (V) 02 4 6 8 10 12 14 16 Spacer Thickness (nm) By widening spacer, below 20 mA/cm2 current density! Low current densities valuable for memory and low power consumption

NOEL Tampere visit (Berger) Oct. 28, 2010 Quantum Memory 104

103 8 nm ) 2 102 -2 10 nm 101 -4

12 nm (V) Word

100 14 nm 1 -1 15 nm 10 0 Bit (V)

10-2 Write into "0" Write into "1" 16 nm

Current Density (A/cm 0.5 10-3 825oC annealed, 1 min 0.3

SN (V) 0.0 10-4 0.00.2 0.4 0.6 0.8 1.0 -10-8 -6 -4-2 0 2 4 6 8 10 Voltage (V) Time (sec)

I–V characteristics of Si-based Oscilloscope capture of the RITDs annealed at 825 ◦C with the waveform with Word, bit and SN spacer thickness varied from 8 to showing write functionality. 16 nm on a semilog plot.

"The Effect of Spacer Thickness on Si-based Resonant Interband Tunneling Diode Performance and their Application to Low-Power Tunneling Diode SRAM Circuits," Niu Jin, Sung-Yong Chung, Ronghua Yu, Roux M. Heyns, Paul R. Berger, and Phillip E. Thompson IEEE Transactions on Electron Devices, 53, pp. 2243-2249 (September 2006). NOEL Tampere visit (Berger) Oct. 28, 2010 Monolithic Quantum Memory

Binary 2TD-1T Word • Low voltage operation down to 0.37 V V NFET SN and %VSWING up to 53.5%. Bit RITD Drive 1.0 V = 0.57V 0.8 DD Ground 0.6 RITD Load 0.4

20 m Bit (V) 0.2 051003.3 VDD 0.0

V = 0.59V 3.0 WL SB WH SB WL SB WH SB WL 0.6 H

0.0V - 1.0V 2.0 0.5 1.0V - 0.0V 0.44V 1.0 Word (V) 0.4 0.36V 0.0

(V) (V) 0.5 SN 0.3 "1" "1" V 0.4 V = 0.21V 0.43 V L 0.3 0.2 0.13V (V) 0.30 V 0.12V SN 0.2 "0" "0" 0.57V 0.78V V 0.1 0.47V 0.1 0.13 V 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 V (V) Time DD th S.L. Rommel S. Sudirgo, et al., Proc. 64 Annual Device Research Conference, pp. 265-6, (2006) Quantum Logic

0.8

0.7

0.6 V H 0.5

0.4 (volts) SN

V 0.3

0.2 V L V = 0 V G 0.1 V = 3.5 V G Circuit schematics of a MOBILE logic circuits using TDs. 0.0 Latching properties of a 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 MOBILE circuit realized using V (volts) Si-based RITDs with CLK modulation.

“Monolithically Integrated Si/SiGe Resonant Interband Tunnel Diode/CMOS Demonstrating Low Voltage MOBILE Operation,” S. Sudirgo, R.P. Nandgaonkar, B. Curanovic, J.L. Hebding, R.L. Saxer, S.S. Islam, K.D. Hirschman, S.L. Rommel, S.K. Kurinec, P.E. Thompson, N. Jin, and P. R . B e r g e r, Solid State Electronics, 48, pp. 1907-1910 (2004).

NOEL Tampere visit (Berger) Oct. 28, 2010 IEEE Elect. Dev. "0" "1" P3 than P1 → P2 ally ally Integrated Si Resonant h Double NDR,” h Niu Double Jin, Sung- "2" → Time (ms) (ms) Time "1" Oct. 28, 2010 2 4 6 8 "0" 8 6 4 2

2.5 2.0 1.5 1.0 0.5

pulse Reduced device count potential. out

(V) (V) V (V) (V) V 2004). (September 25 , pp. 646-648 “Tri-State “Tri-State Logic Using Vertic Lett. , Interband Tunneling Diodes wit Interband Tunneling Yong Yong Chung, Roux M. Heyns, Paul R. Berger, Ronghua Yu, Phillip E. Thompson, and Sean L. Rommel,

However, there is a large series resistance there a large series is However, created by the vertical stacking and a lower noise margin from P2

n n

P1 p

Voltage (V) Voltage e e

p p U

w 0.0 0.5 1.0 1.5 2.0 2.5 S 8 6 4 2 0

10 Current (mA) (mA) Current Backward diode Integrated Pair RITD and Energy Efficient Circuitry Voltage (V) Upper RITD Lower RITD

Multi-valued Quantum Logic For Compact

-1.0 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 8 6 (mA) 4 Current 2 0 Tampere visit(Berger) Tampere NOEL Si-Based RITD Results Summary

Device Optimization Hybrid Circuit Prototyping •High PVCR (4.0) • Vertically stacked back-to-back RITDs for symmetric NDR •High PCD (≥ 218 kA/cm2) • Tri-state logic with vertically stacked RITDs •Low PCD (≤ 20 mA/cm2) • Low voltage MOBILE latches (CMOS-RITD)

Device Integration Monolithic Circuits

•Monolithic integration with CMOS •Low power/low voltage TSRAM •Monolithic Integration with SiGe HBTs •Low power/low voltage MOBILE •CVD Integration •Adjustable PVCR (HBT-RITD)

NOEL For Further Reading

 Paul R. Berger, Anisha Ramesh “Negative Differential Resistance Devices and Circuits” in Comprehensive Semiconductor Science and Technology, Elsevier, Volume 5, Chapter 13, pp. 176–241 (2011).

 A. C. Seabaugh, B. Brar, T. Broekaert, G. Frazier, and P. van der Wagt, “Resonant tunneling circuit technology: has it arrived?” 1997 GaAs IC Symposium, pp. 119-122.

 A. Seabaugh and R. Lake, “Tunnel diodes,” Encyl. Appl. Phys., vol. 22, pp. 335-359 (1998).

 J.P. Sun, G.I. Haddad, P. Mazumder, J.N. Schulman, “Resonant tunneling diodes: Models and properties,” Proc. of IEEE, vol. 86, pp. 641-661 (1998).

 P. Mazumder, S. Kulkarni, Bhattacharya M, J.P. Sun, G.I. Haddad, “Digital circuit applications of resonant tunneling devices, Proc. IEEE, vol. 86, pp. 664-686 (1998).

 J. P. A. van der Wagt, “Tunneling-Based SRAM,” Proc. of IEEE, vol. 87, pp. 571-595 (1999).

 A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, “Resonant tunneling mixed-signal circuit technology,” Solid State Electronics, vol. 43 pp. 1355-1365 (1999).

 K. Maezawa, T. Akeyoshi, and T. Mizutani, “Flexible and reduced-complexity logic circuits implemented with resonant tunneling transistors,” International Electron Devices Meeting Technical Digest, pp. 415-418 (1993).

NOEL NDR in an Organic System

Now let’s turn our attention to organic systems.

First, let’s review some prior art.

PDL SmartCards – Flexible Electronics

Memory

Lithium Logic Battery

Connectors

keyslot

Edge Connector

PDL NDR in an Organic System (Reed and Tour)

Large On-Off Ratios and Negative Differential Resistance in a Molecular Electronic Device J. Chen, M. A. Reed, A. M. Rawlett, J. M. Tour Science, vol. 286, pp. 1550-1552 (November 19, 1999).

PDL Abstract

● A significant discovery for fashioning strong room temperature negative differential resistance (NDR) devices using organic semiconductors was made. ● NDR devices enable compact, low power consumption logic and memory circuits with fewer devices, exploiting their quantum functionality that would be ideal for distributed computing needs on flexible substrates, such as Smartcards and portable displays. ● The work which appeared in Applied Physics Letters (Nov. 2005) reports on a robust process that utilizes simple solution processing and large area devices, circumnavigating the need for molecular-sized junctions for NDR. ● The Key: Controlled oxidation and crystallinity of a thin (<

10 nm thick) TiO2 layer.

PDL Polymer material and device structure with its associated energy band diagram poly[2-methoxy-5-(2'-ethyl- hexyloxy)-1,4-phenylenevinylene] Indium tin oxide (ITO) coated glass (MEH-PPV) substrates with a sheet resistance (Rs) 2 LUMO below 10 Ω-cm. (A=0.19 cm ) -3.0 eV -3 TiO2 -4 MEH-PPV A thin layer of Ti metal (2-20 nm) Al -5 ITO EF=-4.2 eV electron beam evaporated was oxidized E =-4.8 eV HOMO -6 F -5.1 eV O (eV) Energy using oxygen plasma at an RF power of -7 80 W at room temperature.

Thin films of MEH-PPV were then spin O (–) TiO coated atop the TiO2 layer from a 0.5% 2 MEH-PPV solution in 80% toluene and (+) Al 20% THF.

ITO The devices were completed by a shadowmask evaporation of an Al Glass Substrate cathode, about 250 nm thick.

PDL Surface image of room-temperature

plasma-oxidized thin TiO2 film

1.0µm

AFM image (5m5m) of O2 plasma-oxidized TiO2 layer on ITO SEMimageofO 2 plasma-oxidized TiO2 layer on ITO

 AFM data indicates that the as-deposited metallic Ti layer with a grain structure converted to a smoother surface after oxygen plasma oxidation , root mean square roughness (RMS) ~ 1 nm. PDL a

2 c

PDL 2 Current density (A/cm ) Current density (A/cm ) -0.3 -0.3 -0.2 -0.1 -0.3 -0.3 -0.2 -0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.0 0.0 0.1 0.2 0.3 0.4 -10 -8 -6 -4 -2 0 2 4 -10 -8 -6 -4 -2 0 2 4 ITO/TiO PVCR = 12 6 nm thick TiO PVCR = 35 ITO/TiO 2 nm thick TiO 2 /MEH-PPV/Al 2 /MEH-PPV/Al

2 2 Voltage (V) (V) Voltage Voltage (V) (V) Voltage Current-voltage characteristics with

large andreproducible NDR

b 2 d 2 Current density (A/cm ) Current density (A/cm ) -0.4 -0.3 -0.2 -0.1 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.0 0.1 0.2 0.3 0.4 -10 -8 -6 -4 -2 -100 2 4 -8 -6 -4 -2 0 2 4 PVCR =PVCR 53 4 nm thick TiO 2 PVCR = 1.2 ITO/TiO 8 nm thick TiO C urrent density (A /cm) -0.3 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4

-10 -8 -6 -4 -2 0 2 4 ITO/TiO 2 /MEH-PPV/Al Voltage (V) (V) Voltage 2 2 Vo ltage (V ) /MEH-PPV/Al 2 Voltage (V) (V) Voltage

     Thicker TiO hysteresis sweep – Forward andbackward reproducible PVCR up to53! residual metallic Ti incomplete oxidation – each TiO 5 adjacentdevicesfor as expected thicknesses – 4 different TiO lack of 2 thickness – 2 – 2 tracks Summary of current-voltage characteristics

Tunneling J V J V barrier peak peak valley valley PVCR (A/cm2) (V) (A/cm2) (V) (nm)* 2 -0.13 -3.3 -0.004 -6.4 34.5 4 -0.29 -4.4 -0.006 -7.4 53.4 6 -0.16 -3.5 -0.013 -6.1 12.4 8 -0.23 -5.6 -0.199 -5.6 1.20

* The thickness of the as-deposited titanium layers before the plasma process is referred to as the

thickness of the final TiO2 layers.

The lack of the measured peak current density to exponentially decrease with

increasing TiO2 layer thickness suggests that the observed reverse-biased NDR behavior does NOT occur via tunneling across the thin-TiO2 layer acting as a traditional tunneling barrier.

PDL PDL Current Density (A/cm2) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 -10 -8 -6 -4 -2 0 2 4 ITO/PEDOT:PSS/MEH-PPV/Al ITO/PEDOT:PSS/MEH-PPV/Al Current Density (A/cm2) -0.04 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 Current-voltage characteristicof a 1 - - - - 0 4 2 0 -2 -4 -6 -8 -10 ITO/PEDOT:PSS/MEH-PPV/Al control device(ITO/PEDOT:PSS/ Voltage (V) Voltage (V)

MEH-PPV/Al)

disappears observed NDReffect the previously TiO With 2 removed, Robust stability after 30 days

0.00 ) 2

-0.05

-0.10

ITO/TiO /MEH-PPV/Al 2 -0.15 2 nm thick TiO 2 As-fabricated Current Density (A/cm Current Density After 30 days -0.20 -10-8 -6 -4 -2 0 Voltage (V)

After testing, the devices were stored (un-encapsulated) in an inert glove box for 30 days with little variation in their peak current density and peak current position.

PDL . . PDL I (mA) tunnel diodes MOBILE latch with 51% voltage swing of the applied V TiOand ramped in bias -16 from V to 0 V, showing multiple NDR regions. thick nm 2 (a diodes tunnel polymer Two

otg a te es nd a a ucin f lc vlae f JFET-polymer of voltage clock of function a as node sense the at Voltage thru -25 -20 -15 -10 -5 0 1 -4 1 -0 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 Logic Element (MOBILE) operation Logic Element Monostable-bistable Transition V DD (V)

PD PD 2 1 V DD I thru thru

V (V) SN -10 -8 -6 -4 -2 0 1 -4 1 -0 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 2 ae) ee eily connected serially were layer) V CLK V V H (V) L V CLK D V G at -8 V V V V G G CLK CLK = 1.5 V =-3 V PD PD V SN 2 1 .

Questions?

Science and Vie (France's Scientific American): “ Plastic diodes promise low cost memory" (July 2006).

PDL The NDR effect in the polymer tunnel diode is hypothesized to occur due to

local defect sites within the TiO2 film?

 Results suggest that the NDR seems to occur as a result of tunneling

through localized defect sites within the thin TiO2 layers that are confined to a small range of energies within the TiO2 bandgap near the TiO2 conduction band. - The lack of the measured peak current density to exponentially

decrease with increasing TiO2 layer thickness - Switching effect in the current-voltage curves

- Using 380°C with the O2 plasma treatment resulted in more thorough conversion to a thin TiO2, and diodes built using this layer did not exhibit the significant NDR effect.

 The mechanism for NDR under reverse bias in these ITO/TiO2/MEH-PPV/Al tunnel diodes is speculated to occur via electrons emitted from the n-type

ITO, tunneling through defect states in the TiO2, which are then collected by the lowest unoccupied molecular orbital (LUMO) level in the MEH-PPV.

PDL I-V characteristics with high

temperature plasma-oxidized TiO2

0.4 ITO/TiO /MEH-PPV/Al ) 2 2 4 nm thick TiO 0.3 2

High-tmeperature plasma-oxidation of TiO2 film 0.2 (at 380 oC)

0.1

0.0

-0.1

-0.2 Current Density (A/cm Current Density

-0.3 -10-8 -6 -4 -2 0 2 4 Voltage (V)

As the conversion of Ti to TiO2 takes place at higher temperatures, the TiO2 crystallinity is improved. Therefore, fewer defects. Observed NDR behavior diminishes, indicative of defect related tunneling. PDL The schematic of band diagram for NDR under reverse

bias in these ITO/TiO2/MEH-PPV/Al tunnel diodes

EC 4.2 eV LUMO 3.0 eV ITO Carrier tunneling? 4.8eV4.8eV MEH-PPV Applied Al VR ++ Diagram of photoconductivity model. The ++ 4.2eV diagram represents the conduction and HOMO valence bands in a nanoparticle of TiO2 and the energy levels of a trap state, and an Reverse bias 5.1 eV electron scavenging state, S/S− on the surface of the nanoparticle. The arrows TiO represent the different possible electron 2 transitions. (1) photogeneration, (2) band-to band recombination, (3) electron trapping, (4) hole trapping, (5) electron scavenging. Charge transport in porous nanocrystalline titanium dioxide E 7.4 eV Eppler, Anuradha M.; Ballard, Ian M.; Nelson, Jenny v Physica E vol.14 pp. 197-202 (2002)

PDL Forward Bias NDR Forward bias LUMO 3.0 eV Al

4.2eV MEH-PPV 0.10 E 4.2 eV Applied ) C 2 0.08 TiO (6 nm) 2 VF 0.06 ITO Carrier tunneling? 0.04 4.8eV 4.8eV HOMO 0.02 PVCR (~73) PVCR (~2.6) 5.1 eV 0.00 TiO2

-0.02 Current Density (A/cm Current Density -0.04

-10-8-6 -4-2 0 2 4 6 8 10

Voltage (V) Ev 7.4 eV

PDL UV-VIS Absorption Spectrometry

for Plasma Oxidized TiO2 thin film

 Using a standard double ITO/glass 0.30 beam instrument recording Ti (2 nm)/ITO/glass UV Visible spectrum (Perkin TiO (2 nm, 100 sec)/ITO/glass Elmer Lambda 20 UV-vis 0.25 2 Ti/ITO/glass Substract ITO/glass spectrometer), the defect level TiO /ITO/glass Substract ITO/glass characterization of plasma 0.20 2 TiO /ITO/glass Substract Ti/ITO/glass oxidized TiO2 thin film is 2 conducted. 0.15

Optical absorption  Advantages of a double beam 0.10 instrument:  It compensates for most Absorbance 0.05 short-term fluctuation in the radiant output sources 0.00 as well as for drift in the transducer and amplifier.  It compensate for wide -0.05 variations in source 300 400 500 600 700 800 intensity with wavelength. Wavelength (nm)

PDL PDL estimated be to about 2.57 eV. range of energies within the TiO Localized defect sites within the thin TiO UV-VIS absorption spectrometry for Absorbance plasma oxidized TiO 0.00 0.05 0.10 0.15 0 40 0 60 0 800 700 600 500 400 300 TiO 2 (2 nm)/ITO/glass Substract ITO/glass ITO/glass Substract nm)/ITO/glass (2

1/2  

( h ) 1000 1200 1400 200 400 600 800 0 TiO Wavelength (nm) Wavelength . 25 . 35 . 4.5 4.0 3.5 3.0 2.5 2.0 2 (2 nm)/ITO/glass Subtract ITO/glass ITO/glass Subtract nm)/ITO/glass (2 2 bandgap near the TiO h 

(eV)

2 layers that are confined a small to

2 2 conduction band was thin film

Conclusions

 A significant discovery for fashioning strong room temperature negative differential resistance (NDR) devices [PVCR up to 53] using organic semiconductors was developed and applied towards a latching circuits.  Room temperature NDR operation, large area, bulk-like thicknesses and simple solution processable platform are key advantages.  The mechanism for NDR under reverse bias in these polymer tunnel diodes is speculated to occur by tunneling through defect

states in the TiO2.  Organic NDR devices enable compact, possible low power consumption logic and memory circuits with fewer devices, exploiting their quantum functionality that would be ideal for distributed computing needs on flexible substrates, such as Smartcards and portable displays.

PDL Si-Based Work - Collaborators

Naval Research Laboratory Phillip E. Thompson, Karl Hobart, and Brad Weaver

IMEC Roger Loo, Ngoc Duy Nguyen (now Univ-Liege), Shotaro Takeuchi (now Covalent Silicon), and Matty Caymax

Rochester Institute of Technology Sean L. Rommel, Santosh K. Kurinec, and Karl D. Hirschman

University of California, Riverside Roger Lake

NIST, Gaithersberg David Simons

NOEL Si-Based Work - Students

Current Graduate Students & Researchers Tyler Growden

Former Graduate Students Ms. Anisha Ramesh (Ph.D. 2012) Si-Young Park (Master’s Thesis 2006, Ph.D. 2009) Ronghua Yu (Ph.D. 2007) Sung-Yong Chung (Master's Thesis 2002, Ph.D. 2005) Sandro Di Giacomo (Master's Thesis 2005) Niu Jin (Master's Thesis 2001, Ph.D. 2004) Anthony Rice (Master's Thesis 2003) Sean L. Rommel (Ph.D. 2000)

NOEL Si-Based Work - Past and Current Support

This work was financially supported by:

. National Science Foundation [ECS-9624160 (CAREER); ECS-9622134 (REG); DMR-0103248 (NIRT); ECS-0196054 (w/ RIT); ECS-0196208 (GOALI w/ Raytheon); DMR-0216892 (IMR); ECS-0323657 (GOALI w/ Motorola); ECS-1028650 (GOALI w/ Traycer) ]

. DARPA/AFOSR (F49620-96-C-0006).

. Naval Research Laboratory (N00173-99-1-G010). This work is indebted to the MBE sample exchanges by: Phillip E. Thompson (Naval Research Laboratory) And the CVD sample exchanges by: Roger Loo (IMEC)

NOEL Polymer Work - Students

Current Students Sarah Al-Issa (Undergrad Researcher) Nadia Ahlborg (Undergrad Researcher) Minjae Kim (Ph.D. Candidate @ IMEC)

Fomer Students Woo-Jun Yoon (Ph.D. 2009) Sita Asar (Physics Undergrad Researcher)

Ohio State University Prof. Richard L. McCreery & Andrew P. Bonifas Prof. Steven A. Ringel & Maria Gonzalez

PDL Acknowledgements

This work was supported by the National Science Foundation (ECCS-1002240).

And the authors wish to thank Gary Farlow (WSU); Don Lupo (TUT); Ioan Stamatin (UB); Filip Tuomisto (Aalto) for technical discussions and collaborations.

PDL STOP!

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