DOCSLIB.ORG

A High-Performance, Parallel Virtual Machine for Python

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A High-Performance, Parallel Virtual Machine for Python Research Collection Doctoral Thesis A High-Performance, Parallel Virtual Machine for Python Author(s): Meier, Remigius Publication Date: 2019 Permanent Link: https://doi.org/10.3929/ethz-b-000371019 Rights / License: Creative Commons Attribution-ShareAlike 4.0 International This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library Diss. ETH No. 26030 AHIGH-PERFORMANCE, PARALLELVIRTUALMACHINE FORPYTHON A dissertation submitted to attain the degree of DOCTOROFSCIENCES of ETHZURICH (Dr. sc. ETH Zurich) presented by REMIGIUSJONASMEIER MSc ETH CS, ETH Zürich born on 02.05.1988 citizen of Gempen SO accepted on the recommendation of Prof. Dr. Thomas R. Gross Prof. Dr. Dr. h.c. Hanspeter Mössenböck Prof. Dr. Martin Schulz 2019 Remigius Jonas Meier: A High-Performance, Parallel Virtual Machine for Python, © 2019 ACKNOWLEDGMENTS I would rst like to thank my advisor, Professor Thomas Gross, who gave me the opportunity to conduct this research. His guidance and support throughout the years at the Laboratory for Software Technology promoted my growth not only as a researcher, but as a person. I am deeply grateful for everything that I have learned from him. My heartfelt gratitude goes to the external co-examiners, Professor Mössenböck and Professor Schulz. From them, I received many comments that helped to greatly improve this dissertation, and I appreciate that they took the time to travel to Zürich for my defense. Many thanks to the people of the PyPy project. Back in 2012, it was a project proposal from Armin Rigo that sparked my interest in the topic of this dissertation. Since then, I was fortunate to work together with Armin on many occasions. I thank him for his invaluable support, his ideas, and his contributions throughout this endeavor. To my fellow PhD students at ETH Zürich, many thanks for the great time and all the support. Due to our all-too-common, deep, and intense discussions — and my inability to withdraw from them early enough — I probably spent the most time over the years with the LLT group members Aristeidis, Luca, and Michael. It was fun. Nobody is more important to me than my friends and, especially, my family. It is because of their support that I managed to overcome all obstacles during my PhD and life in general. I thank them especially for their patience during the months of writing this dissertation and hope to nally see them all more often again. Thank you very much, everyone! Remigius Jonas Meier Zürich, September 3, 2019 iii CONTENTS acknowledgments iii abstract ix zusammenfassung xi 1 introduction 1 1.1 Thesis Statement . 2 1.2 Overview and Contributions . 3 2 problem statement 5 2.1 Python’s Concurrent Execution Model . 6 2.1.1 Serialization Semantics . 7 2.1.2 Sequential Consistency . 9 2.1.3 Atomic Operations . 10 2.2 Challenges for an Ecient, Parallel Virtual Machine . 11 2.2.1 Implementation Languages . 11 2.2.2 Fine-Grained Locking . 13 2.2.3 Just-in-Time Compilation and Concurrency . 16 2.3 Summary . 20 2.4 Related Work . 21 3 approach 23 3.1 The RPython Approach . 23 3.1.1 Specifying Sequential Semantics . 24 3.1.2 Specifying Concurrency Semantics . 26 3.1.3 Observations . 28 3.2 Parallel RPython ...................... 30 3.2.1 The Execution Model . 30 3.2.2 Specifying Concurrency Semantics with Parallel RPython ....................... 33 3.3 The Design of a Concurrency Control Component . 36 3.3.1 Parallel Execution for Quanta . 37 3.3.2 A Parallel Implementation . 40 3.3.3 External Code . 42 3.3.4 External Code and the Concurrency Control Com- ponent . 46 3.4 Summary . 48 3.5 Related Work . 49 v vi contents 4 realization of parallel rpython 51 4.1 Challenges for an stm Component . 51 4.2 RPython’s jit ......................... 54 4.3 Design of an stm System . 56 4.3.1 Terminology . 56 4.3.2 Validation . 57 4.3.3 Aborting . 58 4.3.4 Atomic Commit and Parallel Worlds . 58 4.3.5 Key Design Decisions . 59 4.4 Ecient Parallel Worlds . 60 4.4.1 State-Sharing Worlds . 60 4.4.2 Page Sharing . 63 4.5 Page Management . 65 4.5.1 Challenges . 65 4.5.2 On-Demand Page Mapping . 68 4.5.3 Page Reconstruction . 70 4.5.4 World Reconciliation . 72 4.5.5 Ecient Bookkeeping . 75 4.6 Related Work . 76 5 case study: pypy 79 5.1 Parallelization of PyPy .................... 79 5.2 The Impact of Conicts . 81 5.3 Inline Caching . 82 5.4 Built-in Data Types . 84 5.5 Findings . 85 6 evaluation 87 6.1 Python vm Representatives . 88 6.2 Benchmarks . 89 6.3 Host Environment . 91 6.4 Methodology . 92 6.5 Speculation Overhead . 93 6.6 Performance Classication . 95 6.6.1 Parallel Performance Levels . 97 6.7 Comparison with Increased Workloads . 101 6.7.1 Scalability Comparison . 104 6.7.2 Scalability and the World Limit . 106 6.8 Summary . 110 7 conclusions 113 7.1 Implications . 115 contents vii 7.1.1 Implications for Python . 117 7.2 Closing Remarks . 118 a appendix 119 a.1 Jython Atomicity Violation . 119 a.2 IronPython Atomicity Violation . 119 bibliography 120 ABSTRACT Today’s hardware is increasingly parallel, and modern programming lan- guages must thus allow a programmer to use this parallelism eectively. For languages that depend on a virtual machine (vm), it is the responsibility of the vm to execute code eciently and in parallel. In the case of Python, a popular dynamic language, several vms exist, but none of them can deliver high performance and parallel execution at the same time. The reason for the lack of such a high-performance, parallel vm for Py- thon lies with Python’s concurrency semantics, which is based on a strong memory model and atomic operations on large entities. Such a concurrency semantics does not map well to modern hardware architectures, which is why parallel vms must emulate this semantics under parallel execution through expensive synchronization. This dissertation introduces a new approach to the design and construc- tion of high-performance, parallel vms with a concurrency semantics such as Python’s. The introduction of large-scale atomicity to the implementa- tion language of a vm lets a vm developer specify the concurrency semantics independently from the vm’s synchronization mechanism. Thereby, the used synchronization mechanism becomes an exchangeable vm component. For the high-performance execution of Python code, just-in-time com- pilation is an essential concern. Unfortunately, Python’s strong memory model inhibits basic compiler optimizations under concurrency. Hence, to allow a compiler to optimize eectively, the concept of Parallel Worlds is introduced. Parallel Worlds transparently isolate concurrent computations from each other, and thereby allow for eective optimizations under the assumption of no concurrency. The transparent isolation of Parallel Worlds is supported by a special-purpose software transactional memory system (stm). Apart from isolation, this stm is the key enabler for the ecient parallel execution of Python code. Parallel execution builds on the speculative execution capability of the stm. The product of this dissertation is PyPy-stm, a high-performance, parallel vm for Python. With PyPy-stm, multi-threaded Python programs can take advantage of the parallelism in modern hardware. On a set of benchmark programs, PyPy-stm outperforms established Python vms such as CPython, ix x contents Jython, IronPython, and PyPy. Compared with PyPy, the current top-of- class in program performance, PyPy-stm achieves speedups in the range of 1:5 to 8:0× with 8 threads available. These results conrm the viability of the approach and show that PyPy-stm deserves the designation as a high-performance, parallel vm for Python. ZUSAMMENFASSUNG Die heutigen Rechnerarchitekturen arbeiten zunehmend parallel, weshalb es moderne Programmiersprachen den Programmiererinnen und Program- mierern ermöglichen sollten, diese Parallelität eektiv zu nutzen. Bei Spra- chen, die auf eine virtuelle Maschine (vm) setzen, ist es die Aufgabe dieser vm, Programme ezient und parallel auszuführen. Im Falle von Python, einer weit verbreiteten dynamischen Programmiersprache, gibt es zwar bereits verschiedene vms, von diesen kann aber keine zugleich parallele Ausführung und hohe Ausführungsgeschwindigkeit bieten. Der Grund für das Fehlen einer solchen performanten, parallelen vm für Python liegt in der Nebenläugkeitssemantik von Python, welche auf einem strikten Speichermodell und atomaren Operationen auf grossen Entitäten basiert. Eine solche Nebenläugkeitssemantik lässt sich nicht direkt auf modernen Rechnerarchitekturen umsetzen, weshalb parallele vms diese Semantik bei nebenläuger Ausführung durch aufwändige Synchronisation genau nachbilden müssen. Diese Dissertation stellt einen neuen Ansatz für das Design und die Konstruktion von performanten, parallelen vms mit einer Nebenläugkeits- semantik wie der von Python vor. Die Einführung von ächendeckender Atomizität in der Implementierungssprache einer vm ermöglicht es bei der vm-Entwicklung die Semantik der Nebenläugkeit unabhängig des Synchro- nisationsmechanismus der vm zu denieren. Der verwendete Mechanismus wird dabei zu einer austauschbaren Komponente der vm. Eine wesentliche Bedeutung für die hohe Ausführungsgeschwindigkeit von Python-Programmen kommt der Just-in-Time-Kompilierung zu. Doch das strikte Speichermodell von Python verhindert bei nebenläuger Aus- führung grundlegende Optimierungen des Kompilierers. Um Kompilierern trotzdem das wirksame Optimieren unter diesen Bedingungen zu ermögli- chen, wird das Konzept der Parallelwelten eingeführt. Parallelwelten isolieren nebenläuge Berechnungen transparent von- einander. So bleiben Optimierungen wirksam, da sie unter der Annahme arbeiten können, dass keine nebenläuge Ausführung stattndet. Die trans- parente Isolierung von Parallelwelten wird durch einen softwarebasierten transaktionalen Speicher (stm) unterstützt. Neben der Isolation ist die- ser stm der Schlüssel zur ezienten parallelen Ausführung von Python- xi xii contents Programmen. Parallele Ausführung wird durch die Fähigkeit des stms zu spekulativer Ausführung ermöglicht. Das Ergebnis dieser Arbeit ist PyPy-stm, eine performante, parallele vm für Python.
Load more

Recommended publications
  • Analysis of GPU-Libraries for Rapid Prototyping Database Operations
    Analysis of GPU-Libraries for Rapid Prototyping Database Operations A look into library support for database operations Harish Kumar Harihara Subramanian Bala Gurumurthy Gabriel Campero Durand David Broneske Gunter Saake University of Magdeburg Magdeburg, Germany fi[email protected] Abstract—Using GPUs for query processing is still an ongoing Usually, library operators for GPUs are either written by research in the database community due to the increasing hardware experts [12] or are available out of the box by device heterogeneity of GPUs and their capabilities (e.g., their newest vendors [13]. Overall, we found more than 40 libraries for selling point: tensor cores). Hence, many researchers develop optimal operator implementations for a specific device generation GPUs each packing a set of operators commonly used in one involving tedious operator tuning by hand. On the other hand, or more domains. The benefits of those libraries is that they are there is a growing availability of GPU libraries that provide constantly updated and tested to support newer GPU versions optimized operators for manifold applications. However, the and their predefined interfaces offer high portability as well as question arises how mature these libraries are and whether they faster development time compared to handwritten operators. are fit to replace handwritten operator implementations not only w.r.t. implementation effort and portability, but also in terms of This makes them a perfect match for many commercial performance. database systems, which can rely on GPU libraries to imple- In this paper, we investigate various general-purpose libraries ment well performing database operators. Some example for that are both portable and easy to use for arbitrary GPUs such systems are: SQreamDB using Thrust [14], BlazingDB in order to test their production readiness on the example of using cuDF [15], Brytlyt using the Torch library [16].
    [Show full text]
  • Concurrent Cilk: Lazy Promotion from Tasks to Threads in C/C++
    Concurrent Cilk: Lazy Promotion from Tasks to Threads in C/C++ Christopher S. Zakian, Timothy A. K. Zakian Abhishek Kulkarni, Buddhika Chamith, and Ryan R. Newton Indiana University - Bloomington, fczakian, tzakian, adkulkar, budkahaw, [email protected] Abstract. Library and language support for scheduling non-blocking tasks has greatly improved, as have lightweight (user) threading packages. How- ever, there is a significant gap between the two developments. In previous work|and in today's software packages|lightweight thread creation incurs much larger overheads than tasking libraries, even on tasks that end up never blocking. This limitation can be removed. To that end, we describe an extension to the Intel Cilk Plus runtime system, Concurrent Cilk, where tasks are lazily promoted to threads. Concurrent Cilk removes the overhead of thread creation on threads which end up calling no blocking operations, and is the first system to do so for C/C++ with legacy support (standard calling conventions and stack representations). We demonstrate that Concurrent Cilk adds negligible overhead to existing Cilk programs, while its promoted threads remain more efficient than OS threads in terms of context-switch overhead and blocking communication. Further, it enables development of blocking data structures that create non-fork-join dependence graphs|which can expose more parallelism, and better supports data-driven computations waiting on results from remote devices. 1 Introduction Both task-parallelism [1, 11, 13, 15] and lightweight threading [20] libraries have become popular for different kinds of applications. The key difference between a task and a thread is that threads may block|for example when performing IO|and then resume again.
    [Show full text]
  • Scalable and High Performance MPI Design for Very Large
    SCALABLE AND HIGH-PERFORMANCE MPI DESIGN FOR VERY LARGE INFINIBAND CLUSTERS DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Sayantan Sur, B. Tech ***** The Ohio State University 2007 Dissertation Committee: Approved by Prof. D. K. Panda, Adviser Prof. P. Sadayappan Adviser Prof. S. Parthasarathy Graduate Program in Computer Science and Engineering c Copyright by Sayantan Sur 2007 ABSTRACT In the past decade, rapid advances have taken place in the field of computer and network design enabling us to connect thousands of computers together to form high-performance clusters. These clusters are used to solve computationally challenging scientific problems. The Message Passing Interface (MPI) is a popular model to write applications for these clusters. There are a vast array of scientific applications which use MPI on clusters. As the applications operate on larger and more complex data, the size of the compute clusters is scaling higher and higher. Thus, in order to enable the best performance to these scientific applications, it is very critical for the design of the MPI libraries be extremely scalable and high-performance. InfiniBand is a cluster interconnect which is based on open-standards and gaining rapid acceptance. This dissertation presents novel designs based on the new features offered by InfiniBand, in order to design scalable and high-performance MPI libraries for large-scale clusters with tens-of-thousands of nodes. Methods developed in this dissertation have been applied towards reduction in overall resource consumption, increased overlap of computa- tion and communication, improved performance of collective operations and finally designing application-level benchmarks to make efficient use of modern networking technology.
    [Show full text]
  • DNA Scaffolds Enable Efficient and Tunable Functionalization of Biomaterials for Immune Cell Modulation
    ARTICLES https://doi.org/10.1038/s41565-020-00813-z DNA scaffolds enable efficient and tunable functionalization of biomaterials for immune cell modulation Xiao Huang 1,2, Jasper Z. Williams 2,3, Ryan Chang1, Zhongbo Li1, Cassandra E. Burnett4, Rogelio Hernandez-Lopez2,3, Initha Setiady1, Eric Gai1, David M. Patterson5, Wei Yu2,3, Kole T. Roybal2,4, Wendell A. Lim2,3 ✉ and Tejal A. Desai 1,2 ✉ Biomaterials can improve the safety and presentation of therapeutic agents for effective immunotherapy, and a high level of control over surface functionalization is essential for immune cell modulation. Here, we developed biocompatible immune cell-engaging particles (ICEp) that use synthetic short DNA as scaffolds for efficient and tunable protein loading. To improve the safety of chimeric antigen receptor (CAR) T cell therapies, micrometre-sized ICEp were injected intratumorally to present a priming signal for systemically administered AND-gate CAR-T cells. Locally retained ICEp presenting a high density of priming antigens activated CAR T cells, driving local tumour clearance while sparing uninjected tumours in immunodeficient mice. The ratiometric control of costimulatory ligands (anti-CD3 and anti-CD28 antibodies) and the surface presentation of a cytokine (IL-2) on ICEp were shown to substantially impact human primary T cell activation phenotypes. This modular and versatile bio- material functionalization platform can provide new opportunities for immunotherapies. mmune cell therapies have shown great potential for cancer the specific antibody27, and therefore a high and controllable den- treatment, but still face major challenges of efficacy and safety sity of surface biomolecules could allow for precise control of ligand for therapeutic applications1–3, for example, chimeric antigen binding and cell modulation.
    [Show full text]
  • A Cilk Implementation of LTE Base-Station Up- Link on the Tilepro64 Processor
    A Cilk Implementation of LTE Base-station up- link on the TILEPro64 Processor Master of Science Thesis in the Programme of Integrated Electronic System Design HAO LI Chalmers University of Technology Department of Computer Science and Engineering Goteborg,¨ Sweden, November 2011 The Author grants to Chalmers University of Technology and University of Gothen- burg the non-exclusive right to publish the Work electronically and in a non-commercial purpose make it accessible on the Internet. The Author warrants that he/she is the au- thor to the Work, and warrants that the Work does not contain text, pictures or other material that violates copyright law. The Author shall, when transferring the rights of the Work to a third party (for ex- ample a publisher or a company), acknowledge the third party about this agreement. If the Author has signed a copyright agreement with a third party regarding the Work, the Author warrants hereby that he/she has obtained any necessary permission from this third party to let Chalmers University of Technology and University of Gothenburg store the Work electronically and make it accessible on the Internet. A Cilk Implementation of LTE Base-station uplink on the TILEPro64 Processor HAO LI © HAO LI, November 2011 Examiner: Sally A. McKee Chalmers University of Technology Department of Computer Science and Engineering SE-412 96 Goteborg¨ Sweden Telephone +46 (0)31-255 1668 Supervisor: Magnus Sjalander¨ Chalmers University of Technology Department of Computer Science and Engineering SE-412 96 Goteborg¨ Sweden Telephone +46 (0)31-772 1075 Cover: A Cilk Implementation of LTE Base-station uplink on the TILEPro64 Processor.
    [Show full text]
  • Library for Handling Asynchronous Events in C++
    Masaryk University Faculty of Informatics Library for Handling Asynchronous Events in C++ Bachelor’s Thesis Branislav Ševc Brno, Spring 2019 Declaration Hereby I declare that this paper is my original authorial work, which I have worked out on my own. All sources, references, and literature used or excerpted during elaboration of this work are properly cited and listed in complete reference to the due source. Branislav Ševc Advisor: Mgr. Jan Mrázek i Acknowledgements I would like to thank my supervisor, Jan Mrázek, for his valuable guid- ance and highly appreciated help with avoiding death traps during the design and implementation of this project. ii Abstract The subject of this work is design, implementation and documentation of a library for the C++ programming language, which aims to sim- plify asynchronous event-driven programming. The Reactive Blocks Library (RBL) allows users to define program as a graph of intercon- nected function blocks which control message flow inside the graph. The benefits include decoupling of program’s logic and the method of execution, with emphasis on increased readability of program’s logical behavior through understanding of its reactive components. This thesis focuses on explaining the programming model, then proceeds to defend design choices and to outline the implementa- tion layers. A brief analysis of current competing solutions and their comparison with RBL, along with overhead benchmarks of RBL’s abstractions over pure C++ approach is included. iii Keywords C++ Programming Language, Inversion
    [Show full text]
  • Intel Threading Building Blocks
    Praise for Intel Threading Building Blocks “The Age of Serial Computing is over. With the advent of multi-core processors, parallel- computing technology that was once relegated to universities and research labs is now emerging as mainstream. Intel Threading Building Blocks updates and greatly expands the ‘work-stealing’ technology pioneered by the MIT Cilk system of 15 years ago, providing a modern industrial-strength C++ library for concurrent programming. “Not only does this book offer an excellent introduction to the library, it furnishes novices and experts alike with a clear and accessible discussion of the complexities of concurrency.” — Charles E. Leiserson, MIT Computer Science and Artificial Intelligence Laboratory “We used to say make it right, then make it fast. We can’t do that anymore. TBB lets us design for correctness and speed up front for Maya. This book shows you how to extract the most benefit from using TBB in your code.” — Martin Watt, Senior Software Engineer, Autodesk “TBB promises to change how parallel programming is done in C++. This book will be extremely useful to any C++ programmer. With this book, James achieves two important goals: • Presents an excellent introduction to parallel programming, illustrating the most com- mon parallel programming patterns and the forces governing their use. • Documents the Threading Building Blocks C++ library—a library that provides generic algorithms for these patterns. “TBB incorporates many of the best ideas that researchers in object-oriented parallel computing developed in the last two decades.” — Marc Snir, Head of the Computer Science Department, University of Illinois at Urbana-Champaign “This book was my first introduction to Intel Threading Building Blocks.
    [Show full text]
  • Lecture 15-16: Parallel Programming with Cilk
    Lecture 15-16: Parallel Programming with Cilk Concurrent and Mul;core Programming Department of Computer Science and Engineering Yonghong Yan [email protected] www.secs.oakland.edu/~yan 1 Topics (Part 1) • IntroducAon • Principles of parallel algorithm design (Chapter 3) • Programming on shared memory system (Chapter 7) – OpenMP – Cilk/Cilkplus – PThread, mutual exclusion, locks, synchroniza;ons • Analysis of parallel program execuAons (Chapter 5) – Performance Metrics for Parallel Systems • Execuon Time, Overhead, Speedup, Efficiency, Cost – Scalability of Parallel Systems – Use of performance tools 2 Shared Memory Systems: Mul;core and Mul;socket Systems • a 3 Threading on Shared Memory Systems • Employ parallelism to compute on shared data – boost performance on a fixed memory footprint (strong scaling) • Useful for hiding latency – e.g. latency due to I/O, memory latency, communicaon latency • Useful for scheduling and load balancing – especially for dynamic concurrency • Relavely easy to program – easier than message-passing? you be the judge! 4 Programming Models on Shared Memory System • Library-based models – All data are shared – Pthreads, Intel Threading Building Blocks, Java Concurrency, Boost, Microso\ .Net Task Parallel Library • DirecAve-based models, e.g., OpenMP – shared and private data – pragma syntax simplifies thread creaon and synchronizaon • Programming languages – CilkPlus (Intel, GCC), and MIT Cilk – CUDA (NVIDIA) – OpenCL 5 Toward Standard Threading for C/C++ At last month's meeting of the C standard committee, WG14 decided to form a study group to produce a proposal for language extensions for C to simplify parallel programming. This proposal is expected to combine the best ideas from Cilk and OpenMP, two of the most widely-used and well-established parallel language extensions for the C language family.
    [Show full text]
  • SYCL – a Gentle Introduction
    SYCL – A gentle Introduction Thomas Applencourt - [email protected], Abhishek Bagusetty Argonne Leadership Computing Facility Argonne National Laboratory 9700 S. Cass Ave Argonne, IL 60349 Table of contents 1. Introduction 2. DPCPP ecosystem 3. Theory Context And Queue Unified Shared Memory 4. Kernel Submission 5. Buffer innovation 6. Conclusion 1/28 Introduction What programming model to target Accelerator? • CUDA1 / HIP2 / OpenCL3 • OpenMP (pragma based) • Kokkos, raja, OCCA (high level, abstraction layer, academic project) • SYCL (high level) / DPCPP4 • Parallel STL5 1Compute Unified Device Architecture 2Heterogeneous-Compute Interface 3Open Computing Language 4Data Parallel C++ 5SYCL implementation exist https://github.com/oneapi-src/oneDPL 2/28 What is SYCL™? 1. Target C++ programmers (template, lambda) • No language extension • No pragmas • No attribute 2. Borrow lot of concept from battle tested OpenCL (platform, device, work-group, range) 3. Single Source (two compilation pass) 4. Implicit or Explicit data-transfer 5. SYCL is a Specification developed by the Khronos Group (OpenCL, SPIR, Vulkan, OpenGL) • The current stable SYCL specification is SYCL2020 3/28 SYCL Implementation 6 6Credit: Khronos groups (https://www.khronos.org/sycl/) 4/28 What is DPCPP? • Intel implementation of SYCL • The name of the SYCL-aware Intel compiler7 who is packaged with Intel OneAPI SDK. • Intel SYCL compiler is open source and based on LLVM https://github.com/intel/llvm/. This is what is installed on ThetaGPU, hence the compiler will be named 8 clang++ . 7So you don’t need to pass -fsycl 8I know marketing is confusing... 5/28 How to install SYCL: Example with Intel implementation • Intel implementation work with Intel and NVDIA Hardware 1.
    [Show full text]
  • High Performance Integration of Data Parallel File Systems and Computing
    HIGH PERFORMANCE INTEGRATION OF DATA PARALLEL FILE SYSTEMS AND COMPUTING: OPTIMIZING MAPREDUCE Zhenhua Guo Submitted to the faculty of the University Graduate School in partial fulfillment of the requirements for the degree Doctor of Philosophy in the Department of Computer Science Indiana University August 2012 Accepted by the Graduate Faculty, Indiana University, in partial fulfillment of the require- ments of the degree of Doctor of Philosophy. Doctoral Geoffrey Fox, Ph.D. Committee (Principal Advisor) Judy Qiu, Ph.D. Minaxi Gupta, Ph.D. David Leake, Ph.D. ii Copyright c 2012 Zhenhua Guo ALL RIGHTS RESERVED iii I dedicate this dissertation to my parents and my wife Mo. iv Acknowledgements First and foremost, I owe my sincerest gratitude to my advisor Prof. Geoffrey Fox. Throughout my Ph.D. research, he guided me into the research field of distributed systems; his insightful advice inspires me to identify the challenging research problems I am interested in; and his generous intelligence support is critical for me to tackle difficult research issues one after another. During the course of working with him, I learned how to become a professional researcher. I would like to thank my entire research committee: Dr. Judy Qiu, Prof. Minaxi Gupta, and Prof. David Leake. I am greatly indebted to them for their professional guidance, generous support, and valuable suggestions that were given throughout this research work. I am grateful to Dr. Judy Qiu for offering me the opportunities to participate into closely related projects. As a result, I obtained deeper understanding of related systems including Dryad and Twister, and could better position my research in the big picture of the whole research area.
    [Show full text]
  • Trisycl Open Source C++17 & Openmp-Based Opencl SYCL Prototype
    triSYCL Open Source C++17 & OpenMP-based OpenCL SYCL prototype Ronan Keryell Khronos OpenCL SYCL committee 05/12/2015 — IWOCL 2015 SYCL Tutorial • I OpenCL SYCL committee work... • Weekly telephone meeting • Define new ways for modern heterogeneous computing with C++ I Single source host + kernel I Replace specific syntax by pure C++ abstractions • Write SYCL specifications • Write SYCL conformance test • Communication & evangelism triSYCL — Open Source C++17 & OpenMP-based OpenCL SYCL prototype IWOCL 2015 2 / 23 • I SYCL relies on advanced C++ • Latest C++11, C++14... • Metaprogramming • Implicit type conversion • ... Difficult to know what is feasible or even correct... ;• Need a prototype to experiment with the concepts • Double-check the specification • Test the examples Same issue with C++ standard and GCC or Clang/LLVM triSYCL — Open Source C++17 & OpenMP-based OpenCL SYCL prototype IWOCL 2015 3 / 23 • I Solving the meta-problem • SYCL specification I Includes header files descriptions I Beautified .hpp I Tables describing the semantics of classes and methods • Generate Doxygen-like web pages Generate parts of specification and documentation from a reference implementation ; triSYCL — Open Source C++17 & OpenMP-based OpenCL SYCL prototype IWOCL 2015 4 / 23 • I triSYCL (I) • Started in April 2014 as a side project • Open Source for community purpose & dissemination • Pure C++ implementation I DSEL (Domain Specific Embedded Language) I Rely on STL & Boost for zen style I Use OpenMP 3.1 to leverage CPU parallelism I No compiler cannot generate kernels on GPU yet • Use Doxygen to generate I Documentation; of triSYCL implementation itself with implementation details I SYCL API by hiding implementation details with macros & Doxygen configuration • Python script to generate parts of LaTeX specification from Doxygen LaTeX output triSYCL — Open Source C++17 & OpenMP-based OpenCL SYCL prototype IWOCL 2015 5 / 23 • I Automatic generation of SYCL specification is a failure..
    [Show full text]
  • Optimizing Apache Spark* to Maximize Workload Throughput
    TECHNOLOGY BRIEF Data Center Big Data Processing Optimizing Apache Spark* to Maximize Workload Throughput Apache Spark* throughput doubled and runtime was reduced by 40% with Intel® Optane™ SSD DC P4800X and Intel® Memory Drive Technology. Executive Summary Apache Spark* is a popular data processing engine designed to execute advanced analytics on very large data sets which are common in today’s enterprise use cases involving Cloud-based services, IoT, and Machine Learning. Spark implements a general-purpose clustered computing framework that can ingest and process real-time streams of very large data, enabling instantaneous event- and exception- handling, analytics, and decision-making for responsive user interaction. To enable Spark’s high performance for different workloads (e.g. machine-learning applications), in-memory data storage capabilities are built right in. Consequently, Spark significantly outperforms the alternative big data processing technologies. However, Spark’s in-memory capabilities are limited by the memory available in the server; it is common for computing resources to be idle during the execution of a Spark job, even though the system’s memory is saturated. To mitigate this limitation, Spark’s distributed architecture can run on a cluster of nodes, thus taking advantage of the memory available across all nodes. While employing additional nodes would solve the server DRAM capacity problem, it does so at an increased cost. DRAM is not only expensive, it also requires that the operator provision additional servers in order to procure the additional memory. Intel® Memory Drive Technology is a software-defined memory (SDM) technology, which combined with an Intel® Optane™ SSD, expands the system’s memory.
    [Show full text]