California State University, Northridge

CALIFORNIA STATE UNIVERSITY, NORTHRIDGE

Design of a 5.8 GHz Two-Stage Low Noise Amplifier

A graduate project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering

By Yashika Parwath

August 2020 The graduate project of Yashika Parwath is approved:

Dr. John Valdovinos Date

Dr. Jack Ou Date

Dr. Brad Jackson, Chair Date

California State University, Northridge ii

Acknowledgement

I would like to express my sincere gratitude to Dr. Brad Jackson for his unwavering support and mentorship that aided me to finish my master’s project. With his deep understanding of the subject and valuable inputs this design project has been quite a learning wheel expanding my knowledge horizons. I would also like to thank Dr. John Valdovinos and Dr. Jack Ou for being the esteemed members of the committee.

iii Table of Contents

Signature page ii Acknowledgement iii List of Figures v List of Tables vii Abstract viii Chapter 1: Introduction 1 1.1 Communication System 1 1.2 Low Noise Amplifier 2 1.3 Design Goals 2 Chapter 2: LNA Theory and Background 4 2.1 Introduction 4 2.2 Terminology 4 2.3 Design Procedure 10 Chapter 3: LNA Design Procedure 12 3.1 Transistor 12 3.2 S-Parameters 12 3.3 Stability 13 3.4 Noise and Noise Figure 16 3.5 Cascaded Noise Figure 16 3.6 Noise Circles 17 3.7 Unilateral Figure of Merit 18 3.8 Gain 20 Chapter 4: Source and Load Reflection Coefficient 23 4.1 Reflection Coefficient 23 4.2 Source Reflection Coefficient 24 4.3 Load Reflection Coefficient 26 Chapter 5: Impedance Matching 28 5.1 Need for Impedance Matching 28 5.2 L-Section Matching Network 29 5.3 Single Stub 37 Chapter 6: Design Simulation on ADS 42 6.1 DC Biasing 48 6.2 Final Schematic 49 Chapter 7: Layout and EM Simulations 53 7.1 Layout 53 Chapter 8: Conclusion 58 References 59

iv List of Figures

Figure 1.1: Block diagram of a communication System 1 Figure 1.2: Signal representation of amplification process 2 Figure 2.1: Different system impedance performance 5 Figure 2.2: Signal to noise ratio 7 Figure 2.3: Linearity and dynamic range 7 Figure 2.4: Two-port network 8 Figure 2.5: S-parameters of a two-port network 8 Figure 2.6: Design flow chart 11 Figure 3.1: Schematic for plotting S-parameters 1 2 Figure 3.2: Magnitude and phase of the S-parameters for the BFU725F transistor 1 3 Figure 3.3: Schematic of transistor for stability check 15 Figure 3.4: Transistor stability K-factor output 15 Figure 3.5: Δ of the transistor 15 Figure 3.6: General transistor amplifier circuit with source and load gains 20 Figure 4.1: Reflection coefficient of a transmission Line 2 3 Figure 4.2: Gain circle of 16 dB intersecting noise circle of 1.3 dB 24 Figure 4.3: Gain circle of 16.5 dB 25 Figure 4.4: Gain circle of 17.12 dB 25 Figure 4.5: Gain circle of 17.3 dB 25 Figure 5.1: Block diagram of LNA with matching networks 28 Figure 5.2: 1+jx circle on the Smith chart 29 Figure 5.3: L-section matching for zL inside 1+jx circle 30 Figure 5.4: L-section matching for zL outside 1+jx circle 30 Figure 5.5: L-section source impedance matching on the Smith chart 33 Figure 5.6: L-section source matching network 34 Figure 5.7: L-section load impedance matching on the Smith chart 36 Figure 5.8: L-section load matching network 37 Figure 5.9: Single stub source impedance matching on the Smith chart 38 Figure 5.10: Single stub source matching network 39 Figure 5.11: Single stub load impedance matching on the Smith chart 40 Figure 5.12: Single stub load matching network 41 Figure 6.1: L-section source and load matching networks 42 Figure 6.2: Output of the L-section matching networks 42 Figure 6.3: Schematic of single stub source and load matching network 43 Figure 6.4: Output of matching networks using single stub matching 44 Figure 6.5: LineCalc tool in Ads for MLIN 45 Figure 6.6: Single stage LNA using MLIN 46 Figure 6.7: Output of single stage LNA using MLIN 46 Figure 6.8: Two-stage LNA with MLIN 47 Figure 6.9: Output of the two-stage LNA 47 Figure 6.10: DC biasing network 48 Figure 6.11: Two-stage LNA with DC biasing circuit 49 Figure 6.12: MAPER in ADS 50 Figure 6.13: Final schematic of the two-stage cascaded low noise amplifier 51

v Figure 6.14: Output of two-stage cascaded low noise amplifier 52 Figure 7.1: Final layout of the two-stage 53 Figure 7.2: Substrate properties for EM simulations 54 Figure 7.3: 3D view of the layout 54 Figure 7.4: Schematic with EM symbol for cosimulation 55 Figure 7.5: EM cosimulation output 56 Figure 7.6: Final layout for fabrication 56 Figure 7.7: PCB of the two-stage LNA 57

vi List of Tables

Table 1.1: Overall design specifications 3 Table 3.1: Transistor S-parameter values at 5.8 GHz 12 Table 6.1: Parameters of the microstrip substrate 45

vii Abstract

Design of a 5.8 GHz Two-Stage Low Noise Amplifier

Yashika Parwath

Master of Science in Electrical Engineering

Efficient communication systems are essential in the modern-day world. There are various blocks that constitute a communication system. This project emphasizes one such block: the low noise amplifier (LNA). LNAs are used in the receiver to amplify weak signals while contributing the least noise possible to the system. These attributes of high gain and low noise figure of an LNA are called for in any receiver block.

A low noise amplifier operating in the microwave frequency range will find applications in satellite radio, cellular devices, radar, and microwave communication systems. The objective of this project is to design a low noise amplifier operating at 5.8 GHz with a target gain of greater than or equal to 30 dB and a noise figure of less than 2 dB from a cascaded two-stage design using two NXP

BFU725F transistors.

To ensure the design’s empirical performance is on par, it is supported with the respective theory and analytical calculations. The software simulations are done using Keysight ADS software while a graphical tool, the Smith chart, is used for the transmission line design. A layout of the final schematic is generated and an electromagnetic (EM) simulation of it is run to verify the performance at the layout level. The final design met the project goal with a gain of 30.06 dB and a noise figure of 1.36 dB at 5.8 GHz. The final design was fabricated and was ready for testing in the lab, but this could not be done due to COVID-19.

viii Chapter 1: Introduction

Modern wireless communication systems operate using high frequency signals. Signals operating at high frequency have greater bandwidth, higher data rate, and reduced antenna size. These advantages only follow if the system is designed to operate at these high frequencies called as radio frequencies (RF). RF ranges from 3 KHz to 3 GHz sometimes amalgamated with microwave frequencies that range from 1 GHz up to 300 GHz. Because of this, communication and high frequency signals are interdependent.

1.1 Communication System

Communication is defined as the means of propagating information from one point to another point. A simple RF communication block is seen in Figure 1.1. In the transmitter, a low frequency modulated signal is upconverted to high frequency signal by mixing it with a local oscillator signal then it is amplified by a power amplifier to facilitate long distance transmission. As mixer in up conversion generates multiple frequencies, and a transmitter filter is used before sending the message carrying signal out into free space via an antenna.

Figure 1.1: Block diagram of a communication system.

In the receiver, the weak signals received are filtered first to discard the undesired frequencies, followed by amplification through a low noise amplifier then down conversion to a low frequency baseband signal using a mixer and a local oscillator to retrieve the original transmitted signal.

While this briefly outlines the concept of communication, this project focuses on the definition, theory, and design of a low noise amplifier which finds its application specifically in the receiver side of a communication system.

1.2 Low Noise Amplifier

A low noise amplifier is a critical block used to increase the strength of the weak received signals while adding the least noise possible to the system. Figure 1.2 shows the process of amplification. The gain resulting from amplification and noise figure are crucial parameters to establish the performance of an LNA. A major difference between power amplifiers and LNAs is the noise each contribute to the system. LNAs have significantly lower noise figure as compared to power amplifiers. There are numerous applications that require amplification of signals with minimum noise such as satellite communications, RADAR, smart phones, Wi-Fi, GPS (global positioning system), etc. Based on the frequency of operation, LNAs find their application in the above. For example, an LNA operating at 900 MHz is used in cellular communication where as an LNA operating at 12 GHz finds its application in high frequency RADAR.

Figure 1.2: Signal representation of amplification process. 1.3 Design Goals

The aim of this project is to design a low noise amplifier finding its application in Wi-Fi, analog and digital cordless applications, microwave communications and satellite radio. Typically, a low noise amplifier is expected to have a gain nominally between 15 dB to 30 dB and a noise figure between 1 dB to 2 dB for use in modern electronic devices. A cascaded design of two stage low noise amplifier is used to achieve the gain target as realizing a gain of greater than 20 dB from a single stage LNA is often not possible.

A design target of gain greater than or equal to 30 dB, noise figure less than 2 dB and operating frequency of 5.8 GHz is set to design the LNA. A BFU725F NXP semiconductor’s wideband silicon germanium RF transistor is used for the design. Hence, the design specifications set to be met from this project are as shown in Table 1.1.

Transistor BFU725F Operating Frequency 5.8 GHz Gain ≥ 30dB Total Noise Figure < 2dB

Table 1.1 Overall design specifications.

Chapter 2: LNA Theory and Background

2.1 Introduction Before delving into the detailed design procedure of an LNA, we require the understanding of several concepts. The high frequency design in the GHz region brings in the complexity of design along with the required understanding of transmission line theory [1]. For a transmission line of length l and wavelength λ, at low frequencies transmission line theory is negligible as l / λ is very small whereas for the values of l / λ > 0.01 occurring at high frequencies we consider the transmission line theory. For the higher frequencies, there is a change in phase of the voltages and currents with the time delay potentially causing reflections in the wave. Hence, this exhibition of electrical behavior at high frequencies warrants the consideration of transmission line theory.

Designing an amplifier in the microwave frequency range is challenging as the concept of lumped elements which is valid for low frequencies is not applicable here. At higher frequencies, microwave components act as distributed elements where the phases change significantly over the physical extent of the device. So, the earlier concepts of electronics relating to lumped elements are no longer sufficient for designing an amplifier at this frequency.

2.2 Terminology

The understanding of few terms is called for to make sense of the design procedure.

In RF electronics, impedance is one of the important concepts. It is the measure of restriction of circuit to the flow of alternating current. This is analogous to the DC concept of resistance where there is only magnitude whereas in AC concepts the signals are represented by magnitude as well as phase. This is exhibited by the time invariant properties such as inductance and capacitance. It is a complex quantity.

Impedance is represented by Z and is mathematically given as

Z = |Z| ∠θ

푍 = 푅 + 푗푋 (2.1)

4 where, |Z| is the magnitude of the impedance and θ represents the phase. R is the real resistance and X is the reactance which is an imaginary concept. Its units are ohms (Ω).

Reactance is the imaginary portion of the impedance. Currents varying with time produce time- varying magnetic fields, voltages varying with time produce time-varying electric fields, and this opposition to the flow of currents of capacitor and inductor is represented by reactance. It is a frequency dependent component that differs for both capacitors and inductors.

For a capacitor, its reactance is given by

1 1 XC = = 휔푐 2휋푓푐

For an inductor, its reactance is given by

XL = 휔퐿 = 2휋푓퐿 where 휔 is the angular frequency (rad/s), f is frequency (Hz), C is capacitance (F) and L is inductance (H). One of the ways to determine the efficiency of the system or the block is by the transfer of the signals, i.e., the maximum power from the input (source) has to be delivered to the output (load). This can be achieved if all the impedances of the path of the circuit are matched. This is conducive for allowing maximum power from the input to the output.

There are different potential impedances for a system like 30 Ω, 50 Ω, and 77 Ω. Maximum power transfer is observed at 30 Ω [2] implying that the capacity of the system to handle the power peaks at 30 Ω. Different system impedance performance is seen in Figure 2.1.

Figure 2.1: Different system impedance performance.

When travelling in a system, signals suffer from attenuation. It is required to have the lowest possible signal attenuation as it directly facilitates high power transfer. Systems have the lowest attenuation at 77 Ω. Maximum power transfer and low signal attenuation are both important for the system to perform better. As a trade-off between the two, 50 Ω is chosen as the standard impedance by most of the systems.

Decibels (dB) are unit of power used in RF communications. It is a unitless measure where it measures a ratio. All the measurements made are referred in terms of dB. This metric of addressing the power is preferred over the linear ratio as the values ascending to larger powers are complex to deal with in linear ratio. Sometimes, the values are given in dBm as well meaning the power values are taken with regards to one milliwatt. For a given power value in its linear form, the dB conversion s given by

푃 (2.2) 푑퐵 = 10 × 푙표푔 ( 1) 푃2 where P1 and P2 are power values in watt. The contrast between the dBW and dBm power values is shown by below formulas,

푃 푑퐵푊 = 10 × 푙표푔 ( ) (2.3) 1푊 푃 푑퐵푚 = 10 × 푙표푔 ( ) (2.4) 1푚푊 Even though (2.3) and (2.4) look alike, the power value in (2.3) is in the units of watt whereas the power value is in the range of milliwatts in (2.4). The relation between dB and dBm is given by,

dBm = dBW + 30 dB

SNR, an acronym for signal to noise ratio, is a metric for receiver sensitivity. It is defined as the ratio of the desired signal average power to the undesired noise signal average power measured in dB.

푃 SNR = 10 × log ( 푆 ) 푃푁 where PS is the average signal power and PN is the average noise power. Both signal power and noise power are typically in units of Watts. If all values are expressed in dB then

SNR (dB) = PS (dB) – PN (dB)

Figure 2.2 shows the signal to noise ratio. The higher the signal to noise ratio, the better the system performance. Practically, for wireless systems like Wi-Fi, it is deemed to have optimal performance for values of SNR above 40 dB. The noise introduced by an amplifier will be added to the signal and on to the rest of the system, amplified by subsequent amplifiers in the design. Hence, it is important to have a low noise amplifier as the first block in receiver chain as it adds low noise into the system improving its sensitivity [3].

Figure 2.2: Signal to noise ratio.

Figure 2.3: Linearity and dynamic range.

Figure 2.3 shows linearity and dynamic range of an amplifier. Linearity is a measure of input- output relationship on how proportional they are to each other. In a practical scenario, linearity is achieved by making the input and output directly proportional to each other to the closest degree possible. There comes a point in this linear graph beyond which the further increase in input does not cause an increase in the output. This is called as the saturation point. The input power for which

7 the output power is less than 1 dB from the linear output expected is called the P1dB gain compression point. The region between the noise floor of the system and the 1 dB compression point is called the dynamic range of the amplifier where it exhibits the linear behavior.

An electrical circuit with two terminals that can be connected to an external circuit is known as a two-port network, as shown in Figure 2.4. The behavior of a two-port network can be described by the scattering parameters as opposed to the impedance parameters (or Z-parameters) and admittance parameters (Y-parameters). Scattering parameters (S-parameters) seen in Figure 2.5 represent the signal in terms of wave ratios of the incident, reflected and transmitted waves. The difficulty addressing the measurement through voltages and currents at high frequencies is better answered through S-parameters. For a scattering parameter defined as Sij, the input is given from port j and the output is measured at port i.

− 푉푖 푆푖푗 = + 푉푗

− + where 푉푖 represents the amplitude of reflected wave from port i and 푉푗 represents the amplitude of incident wave at port j.

Figure 2.4: Two-port network.

Figure 2.5: S-parameters of a two-port network.

For a given two port network there exist four scattering parameters, namely, S11, S12, S21, and S22.

S11 defines the ratio of reflected voltage wave from port one to the incident voltage wave on port one. S12 defines the ratio of voltage wave received from port one to the voltage wave incident on port 2. S21, the ratio of voltage wave received from port two when transmitted from port one. S22, the ratio of reflected wave from port two when voltage wave is incident on port two.

− 푏1 푉1 S11 = = + 푎1 푉1

− 푏1 푉1 S12 = = + 푎2 푉2

− 푏2 푉2 S21 = = + 푎1 푉1

− 푏2 푉2 S22 = = + 푎2 푉2

The common terms used for S-parameters of a two-port network are:

S11: Input reflection coefficient

S21: Reverse gain

S12: Forward gain or insertion loss

S22: Output reflection coefficient

In LNA design, transmission lines are designed using the graphical tool called the Smith chart. It can represent impedance and admittance of a system and is a convenient tool used for plotting reflection coefficients, designing matching circuits, and for stability analysis. The center of the Smith chart represents the matched point (50 Ω), the left most point represents the short circuit point (0 Ω), and the right most point represents the open circuit point (∞ Ω). The performance of a system can be better analyzed by viewing it on a Smith chart.

Software simulations for LNA design are done using Keysight Advanced Design System (ADS). It is an electronic design automation (EDA) tool which facilitates RF/Microwave circuit designs. Time domain, frequency domain, lumped and distributed elements simulations are possible on ADS. It also offers electromagnetic (EM) simulations for virtual prototypes.

2.3 Design Procedure

The step by step procedure to design the amplifier is seen below:

• A transistor meeting the required design specifications, performance characteristics and applications is to be chosen. This is vital as the whole design’s performance relies to a major extent on this sole component itself. • The scattering parameters (S-parameters) of the transistor at the design frequency are to be noted. This will be available to downloaded along with the data sheet package of the transistor. • Check for the stability of active device, i.e., the transistor. For this, Rollet’s stability factor (K- Δ) is used. For a given formula of K and Δ resulting in scalar values if the value of K is greater than 1 and Δ is less than 1 the device is said to be unconditionally stable if not it is potentially unstable.

• Then the device is checked for the unilateral condition of S12 being zero. Unilateral figure of merit (U) determines the error range if it is considered unilateral. If the error range is ±5% of the maximum gain, then it is considered unilateral, if not it will be operating in bilateral case. • Source and load reflection coefficients are to be determined in order to design the input output matching network facilitating the maximum power transfer from source to load. This is done using the graphical tool known as the Smith chart. Lumped components involving inductor and capacitor, open or short circuit stubs using microstrip transmission lines are few of the various techniques to design the impedance matching network. • Design a DC bias circuit to turn on the active device for it to perform the amplification. Once a single stage amplifier is designed, it is cascaded with the same amplifier for larger gain. • The layout of the final schematic is generated and run for electromagnetic simulations to verify the same performance and given for fabrication. • The final PCB created is tested to check the performance that is expected to be aligned with the software EM results. The fabricated PCB could not be tested due to COVID-19.

The flow chart of the LNA design procedure is seen in Figure 2.6.

Select the transistor

Stability check transistor

Unilateral check

Impedance matching

DC biasing

Layout and EM simulation

Fabrication and testing

Figure 2.6: Design flow chart.

Chapter 3: LNA Design Procedure

3.1 Transistor

For the design of a low noise amplifier operating at a frequency of 5.8 GHz, the BFU725F transistor was chosen. Designed by NXP semiconductor in 2011, this is a very low noise silicon germanium transistor used for microwave applications. As per the data sheet, this transistor provides gain between 16 dB to 18 dB from a single stage at 5.8 GHz with a noise figure as low as 0.9 dB. It is a four pin NPN wide band RF transistor with low parasitic losses.

3.2 S-Parameters

The transistor BFU725F comes with its own s2p file package which can be used in the ADS simulation [4]. At a frequency of 5.8 GHz with the DC conditions of VCE = 2V and Ic = 25 mA, it has the S-parameters as seen in Table 3.1. S-parameters of the transistor are plotted using the schematic in Figure 3.1 in ADS.

S-parameters Value

S11 0.4979∠150.81°

S21 5.9489∠39.68°

S12 0.0699 ∠29.46°

S22 0.1220 ∠-139.16° Table 3.1 Transistor S-parameter values at 5.8 GHz.

Figure 3.1: Schematic for plotting S-parameters.

A 50 Ω termination is connected at the input and the output side with transistor s2p file loaded onto the two-port network. ADS has built in library for S-parameter simulations with an option of start frequency, stop frequency and its step size. After running the schematic, output is plotted on rectangular plot for the magnitude and phase of S-parameters as seen in Figure 3.2 which matches the values extracted from the transistor data sheet.

Figure 3.2: Magnitude and phase of the S-parameters for the BFU725F transistor.

3.3 Stability

Once the S-parameters of the transistor are noted then the next design step is to check the stability of the transistor. This step is important to know how stable the device at the respective frequency is. If it is not stable it could produce oscillations, derailing from the performance of an amplifier and acting more like an oscillator which is undesirable. Thus, the stability check is for determining the immunity of amplifier from spurious oscillations.

In the year 1962, John Rollett published an IRE (International Review of Physics) paper introducing the concept of stability for two port networks [5]. He is credited for this contribution in the microwave world. Rollett’s stability factor, called the K-∆ test, the scalar quantity output gives the valuable measure of stability at a given frequency. The formula of K and ∆ is given in (3.1) and (3.2) [1]. For K value greater than one and |Δ| value less than one, the device is said to be unconditionally stable. If these conditions are not met it is potentially unstable.

|Δ| = |S11 S22 -S12 S21| (3.1) = |(0.4979∠50.81)(0.1220∠-139.16) – (0.0699∠29.46)(5.9489∠39.68)

= |0.3871∠-103.253|

= 0.3871

2 2 2 1 − |푆11| − |푆22| + |훥| (3.2) 퐾 = 2|푆21푆12| 1-(0.4979)2-(0.122)2+(0.3871)2 = 2|(5.9489∠39.68)(0.0699∠29.46|

= 1.065

Using the values of S-parameters for the BFU725F transistor at 5.8 GHz, the K value was found to be 1.065 (>1) and |Δ| was 0.3871 (<1). Hence, it can be deduced that the transistor is unconditionally stable. Another way of determining the stability is through μ-Δ test. While the condition and formula for |Δ| is same as for K-Δ test, the formula of μ is given by [1]

2 1−|푆11| (3.3) μ = ∗ |푆22−훥푆11|+|푆12푆21| 1-|0.4979|2 = |(0.1220 ∠-139.16)-(0.3871∠-103.253)(0.4979 ∠-150.81)|+| (0.0699 ∠29.46)(5.9489 ∠39.68)|

0.7520 = 0.6844

= 1.098

For μ > 1 and |Δ| < 1 the device is said to be unconditionally stable. Inputting the values of S- parameters, the value of μ was calculated to be 1.098 (>1). Hence, the transistor satisfied both the conditions of unconditional stability. The theoretical calculations for the stability of the transistor are supported by the software simulations as well. Using ADS, the transistor was connected to the matched terminations of 50 Ω at the input and output side as seen in Figure 3.3. Stability is measured using the ‘StabMeas’ component from component palette. For Δ measurement, its equation is defined in ‘MeasEqn’ and the schematic is run for output. Figure 3.4 and Figure 3.5 show the value of K and Δ which is same as the value calculated from (3.2) and (3.1), respectively. Hence, the stability of the transistor is verified theoretically as well as through software simulations.

Figure 3.3: Schematic of transistor for stability check.

Figure 3.4: Transistor stability K-factor output.

Figure 3.5: Δ of the transistor.

3.4 Noise and Noise Figure

Noise is a parameter whose presence is inevitable and undesirable at the same time. The lowest power signal that can be detected in its presence is called the minimum detectable signal of the receiver. Noise can be added from the external environment or generated within the circuitry itself. External environment factors comprise of cosmic noise, ground thermal noise, presence of gases, microwave ovens, and jamming devices. While these can potentially be evaded, there are some internally generated noise sources that cannot be such as thermal noise from the thermal vibration of the charges (also known as Nyquist noise), shot noise from the random fluctuations of charge carriers, flicker noise occurring in solid state devices, and the quantized nature of the charge carriers causing the quantum noise. While the existence of noise cannot be completely eliminated it is gauged through a figure of merit called the noise figure [6].

Signal to noise ratio is defined as the ratio of signal power to the noise power. The ratio of input signal to noise ratio to the output signal to noise ratio is termed as noise figure. It is represented by F. For an ideal noiseless system both the input signal power as well as the noise power will be amplified by the same ratio, however in reality this does not happen. The output noise signal is observed to be amplified more than the signal power proving the existence of the component added noise. The mathematical formula of noise figure is given in (3.4) where Si/Ni is input signal to noise ratio and So/No is output signal to noise ratio.

푆푖 (3.4) 푁푖 F = 푆표 푁표 3.5 Cascaded Noise Figure

Each stage present in the system design will have its own noise figure where the noise of the previous stages follows and contributes to the later stages. For a cascaded design of a system the final noise figure of the system is given by,

퐹2−1 퐹3−1 (3.5) Fcas = 퐹1 + + + ⋯ 퐺1 퐺1퐺2

Where F1 is the noise figure of stage one, F2 is the noise figure of stage two and this follows to th the third and all the way to the n stage. G1 is the gain of the first stage, G2 is the gain of the second stage following the similar nomenclature to all the n stages.

From the equation of the cascaded noise figure it can be understood that the noise figure of the first stage has a significant factor to contribute to the final value whereas the noise figure of the later stages are divided by the previous stage’s gain and thus adds a lower value to the final cascaded noise figure Fcas compared to the first stage. This results in the imperative need to design an initial stage with the lowest noise figure and highest gain possible so as to mitigate the effect it has on the entire system.

3.6 Noise Circles

The need for lowest noise figure for the initial stage is understood with the cascaded noise figure formula in (3.5). While minimum noise figure and maximum gain are desired it may not be possible to achieve both simultaneously. A specific gain is achieved by introducing mismatches in the design to obtain lower gain than its maximum through circles called gain circles. Similarly, a specific noise figure is achieved by constant noise figure circles called noise circles. These circles offer a specific value of gain and noise figure as a compromise for getting best of both the values. The point of intersection of the gain circle and noise circle gives the source reflection coefficient deciding on how much noise figure can be expected from the low noise amplifier. In order to find the center and radius of the noise circle, firstly the noise figure parameter N is determined from (3.6).

퐹−퐹푚푖푛 2 (3.6) 푁 = 푅 |1 + 훤표푝푡| 4 푁 푍표 where F is the fixed noise figure desired, Fmin is the minimum noise figure of transistor, RN is the equivalent noise resistance of transistor, Z0 is the characteristic impedance of 50 Ω, and Γopt is the optimum gamma (complex reflection coefficient) which signifies that the minimum noise figure occurs at this value. The values in (3.6) are taken from the s2p file of the transistor which are,

Fmin = 1.1274 dB

RN/Z0 = 0.1057

Γopt = 0.1360∠-145.14°

For noise figure F as per the design specifications a value less than 2 dB is required. Choosing a noise figure too low requires less gain. Hence, a trade off value of 1.3 dB is chosen as it is within

17 the design requirements set for the project. Note that (3.6) takes only linear values. Converting F and Fmin into linear values,

dB = 10 × 푙표푔(푥) where x is the linear ratio of power values.

F = 10 × 푙표푔(1.349) = 1.3 dB

Fmin = 10 × 푙표푔(1.296) = 1.1274 dB

Inserting these values in (3.6),

1.349-1.296 N = |1 + 0.1360∠-145.14 |2 4×0.1057

= 0.125 × 0.795

= 0.0994

This value of N is required to calculate the center and the radius of the noise figure circle. They are given in (3.7) and (3.8) [1].

훤표푝푡 (3.7) 퐶 = 퐹 푁 + 1 0.1360∠-145.14 = 1.0994

= 0.124∠-145.14

2 (3.8) √푁(푁+1)−|훤표푝푡| 푅 = 퐹 푁+1 = 0.298

With this, the center and radius of the noise circles are determined and are all set to be drawn on the Smith chart.

3.7 Unilateral Figure of Merit

The unilateral figure of merit is calculated to determine if transistor can be considered a unilateral device (S12 = 0). When the value of |S12| is so small that it is almost negligible then it is still considered as unilateral case. Represented by U, unilateral figure of merit is given by (3.9).

|푆11||푆12||푆21||푆22| (3.9) U = 2 2 (1−|푆11| )∗(1−|푆22| ) 0.253 = 0.752×0.9851

= 0.034

Using the value of U calculated from (3.9) the lower and upper limit of error are calculated as per (3.10) and (3.11).

1 Lower Limit = (3. 10 ) (1+푈)2 1 = 1.069

= 0.945

= -0.245 dB

1 Upper Limit = (3.11) (1−푈)2 1 = 0.933

= 1.063

= 0.265 dB

The final error range is given by (3.12) where GT is the transducer gain defining how much power is delivered to the load from the source. GT/ GTU gives the ratio of transducer gain to transducer gain in unilateral case. The error range up until a few tenths of dB above and below the ratio of

GT/ GTU is permissible to consider it as a unilateral device. Since, the final limits are 0.2 dB in variance from GT/ GTU ratio the transistor can be considered a unilateral device.

1 퐺푇 1 (3.12) 2 < < 2 (1+푈) 퐺푇푈 (1−푈)

퐺 -0.245 dB < 푇 < 0.265 dB 퐺푇푈

3.8 Gain

In the design of the amplifier, the preliminary factor to account for is the gain. Called the transducer gain, it takes into consideration the source gain, transistor gain, and output load gain. Since, it accommodates the source and load mismatches, it is considered the most useful amplifier power gain. Mathematically it is defined as

GT = Gs G0 GL where GT is the transducer gain, Gs is the input source gain, G0 is the transistor gain, GL is the output load gain which are seen in Figure 3.6.

Figure 3.6: General transistor amplifier circuit with source and load gains.

The gains that can be achieved with the selected transistor are given by

1 (3.13) 퐺푆푀퐴푋 = 2 1−|푆11| 1 = 1-(0.49799)2

= 1.329

= 1.237 dB

2 퐺0 = |푆21| (3.14) = 45.58

= 16.58 dB

1 (3.15) 퐺퐿푀퐴푋 = 2 1−|푆22| = 1.015

= 0.0646 dB

From (3.12) the final transducer power gain is given by

GT = Gs G0 GL

= 1.237 dB + 16.58 dB + 0.0646 dB

= 17.8816 dB

Since, the transistor gain cannot be changed, the overall gain of the amplifier is controlled by the gain from the source and the load section. While GT is the maximum stable transducer gain provided by the amplifier, we choose a gain where the noise figure is minimum. There exists a tradeoff between the gain and noise figure. Taking that into account, the specific gain approach for the source matching network was used. From the maximum value of source gain of 1.237 dB

(Gsmax) only a gain of 0.4474 dB (Gs) is needed in order to achieve an amplifier gain of 17.1 dB.

The amplifier gain of 17 dB is chosen so that the cascaded two-stage design offers a combined gain of 34 dB in an ideal lossless medium. When the design is simulated in real time lossy conditions this would leave a head room of 4 dB over the 30 dB gain for loss constraints reducing the performance while still meeting the design target of gain greater than or equal to 30 dB.

To find the center and radius of the gain circles, the normalized source gain factor gs has to be determined. It is given as the ratio of the gain we need from the source to the maximum gain provided by the source [1].

퐺푆 (3.16) 푔푠 = 퐺푠푚푎푥 0.4474 = 1.237

= -0.7889 dB

= 0.833 (linear ratio)

With the normalized source gain factor determined, the gain circles are plotted whose center Cs and radius Rs are calculated using [1]

∗ 푔푆 푆11 (3.17) 퐶푠 = 2 1 − (1 − 푔푠) |푆11|

0.4148∠-150.81 = 0.9585

= 0.4327∠-150.81

2 √1 − 푔푠(1 − |푆11| ) (3.18) 푅푆 = 2 1 − (1 − 푔푆)|푆11|

√1-0.833 (1-|0.49799|2) = 1-(1-0.833)|0.49799|2

0.4263*(1-(0.49799)2) = 0.9585

= 0.3205

Since the noise figure of 1.3 dB and the required gain of 17.1 dB are set for the design, the cascaded noise figure from the two stages of the low noise amplifier from (3.5) can be calculated as,

퐹2−1 퐹3−1 Fcas = 퐹1 + + + ⋯ 퐺1 퐺1퐺2

1.349-1 = 1.349 + 51.286

= 1.355

Hence, this value of the cascaded noise figure serves as the basis for verifying the noise figure of the designed schematic. So far, all the data required for plotting the noise circles and the source gain circles have been calculated. The following chapters will discuss in detail where these values are used to design the amplifier.

Chapter 4: Source and Load Reflection Coefficient

4.1 Reflection Coefficient

For a given transmission line, the characteristic impedance of the line Z0, is one of the most important parameters, defined as the ratio of voltage amplitude to the current amplitude for each individual wave propagating in a particular direction. For a given transmission line terminated in a load ZL, the load impedance is the ratio of the voltage and current at that load terminal. In the similar fashion there exists source impedance ZS as well as seen in Figure 4.1.

Figure 4.1: Reflection coefficient of a transmission line. In designing a low noise amplifier, it is important to have the source and the load impedances matched to the characteristic impedance of the transmission line. This facilitates the maximum power transfer from source to the network and network to the load with as much low power loss as possible. If the source and load impedances are not matched it results in a reflection of the wave resulting in power loss.

The reflection coefficient is defined as the ratio of the voltage amplitude wave reflected to the voltage amplitude wave incident. It is represented as Γ. Mismatches at the source and load result in a non-zero source reflection coefficient ΓS and load reflection coefficient ΓL. These points of source and load reflection coefficient are to be found first, and then matched to the center of the Smith chart to facilitate maximum power transfer and low power loss.

4.2 Source Reflection Coefficient

The center and radius of noise circle and source gain circle were calculated in Chapter 3. The point of intersection of these two circles gives the value of source reflection coefficient ΓS. The tangential point of intersection between the noise circle and the source gain circle gives one point where there exists the optimum noise figure that can be obtained from the design while not compromising on the gain.

With the help of ADS software, the noise and gain circles are plotted. There are multiple gain circles that can be plotted based on how much gain we choose to get out of the transistor while looking for low noise figure. Figure 4.2 and Figure 4.3 show the gain circles of 16 dB and 16.5 dB respectively that intersect with the noise figure circle of 1.3 dB. While the gain of 16 dB is high enough to obtain the design goal of 30 dB from two stages, these circles intersect the noise circle at more than one point implying they are not in tangency with noise circle and there is scope to achieve more gain.

Figure 4.2: Gain circle of 16 dB intersecting noise circle of 1.3 dB.

Figure 4.3: Gain circle of 16.5 dB. Figure 4.4: Gain circle of 17.12 dB.

Figure 4.5: Gain circle of 17.3 dB.

Figure 4.4 shows the point which is tangential to the noise figure circle offering a gain of 17.1 dB which is 1 dB greater compared to the previous lower gain circles. The gain can be increased further to check the highest value that can be attained from it but the gain circle of 17.3 dB seen in

Figure 4.5 does not intersect the noise figure circle at any point. Hence, from Figure 4.4 the point of convergence 0.421∠-153.66 was chosen as the source reflection coefficient point, ΓS = 0.421∠- 153.66.

4.3 Load Reflection Coefficient

In order to determine the load reflection coefficient ΓL, the maximum gain approach is used. This technique is used to acquire maximum gain from amplifier design unlike the source where the specific gain approach was used. No mismatches are introduced deliberately to lower the gain. This technique is simple as it does not have any source and gain circles to determine load reflection coefficient. The output matching network has to be conjugately matched to the impedance to allow the maximum power transfer from transistor to load.

* Γout = ΓL

The solution for maximum power transfer from transistor to load is obtained by solving the quadratic equation [1]

2 2 (4.1) 퐵2 ± √퐵2 − 4|퐶2| 훤퐿 = 2퐶2 where B2 and C2 are variables defined as [1]

B2 = 1 + |S22|2- |S11|2- |Δ|2 (4.2) = 1+ 0.0148 – 0.2479 – 0.1498

= 0.6170

∗ 퐶2 = 푆22 − Δ푆11 (4.3)

= 0.12205∠-139.16 – 0.3871∠-103.253 (0.49799∠-150.81

= 0.2680∠-98.452°

Solving (4.1) we get,

0.6170 ± √0.61702-4(0.2680)2 ΓL = 2(0.2680)

0.6170 ±0.3057 = 0.536

= 1.721∠98.452° and 0.5809∠98.452°

The load reflection coefficient takes two values after solving (3.1). The value of 1.721∠98.452° is not possible for reflection coefficient as it takes the value that ranges between 0 < Γ < 1. Hence, this value is not considered. Load reflection coefficient takes the value of, ΓL = 0.5809∠98.452°.

Chapter 5: Impedance Matching

5.1 Need for Impedance Matching In designing any microwave component emphasis is laid on the concept of impedance matching because the impedance matched circuit has maximum power transfer from the source (e.g., the generator) to the network, and the network to the load. Further, a better signal to noise ratio is achieved in RF components (like low noise amplifiers), as well as the phase errors and amplitude errors are also low. The paramount ascribed to impedance matching is due to all these advantages.

In the LNA design procedure, the design’s performance depends on impedance matching. How well the circuit is matched to the transmission line’s characteristic impedance and which part of the matched network needs tuning for optimum results all pertain to this core design step, i.e., impedance matching. The vicissitudes of the design’s performance can be ascribed to impedance matching for majority of the time.

A typical block diagram of the low noise amplifier is seen in Figure 5.1. The single stage LNA has a voltage source VS and an input impedance of Z0. The input matching network is used to match the source reflection coefficient to the transmission line characteristic impedance of 50 Ω to allow maximum power from source to the transistor. Then the output matching network is used to match the load reflection coefficient to the transmission feed line impedance to have the maximum power transferred from the transistor to the load with minimum reflections. The value of the source and load reflection coefficient depends on the source and load impedance respectively [7].

Figure 5.1: Block diagram of LNA with matching networks.

There are various techniques developed for impedance matching. In this chapter we will see an L- section matching network and a single stub matching network for the amplifier design.

5.2 L-Section Matching Network

Standing for lumped element matching network, L-section matching uses discrete components such as capacitors and inductors to achieve impedance matching. These reactive elements help to match the resistances of the load to the transmission line. Figure 5.2 shows the impedance Smith chart. The highlighted circle is the 1+jx circle which has a resistance of 1 (r = 1).

Figure 5.2: 1+jx circle on the Smith chart.

Dividing the impedance by the characteristic impedance of the transmission line gives the normalized impedance (zL). Based on the position of normalized impedance there are two topologies possible for L-section matching network. For a value of normalized load impedance

(zL = ZL/Z0) lying inside the 1+jx circle, the topology in Figure 5.3 is used and for the normalized load impedance lying outside the 1+jx circle, the topology in Figure 5.4 is used. Here, jX is the series reactance and jB is the shunt susceptance. The variation between the two topologies is whether the network has shunt component first followed by the series component or vice versa when seen from the side of the matching network followed by the load.

Figure 5.3: L-section matching for zL inside 1+jx circle.

Figure 5.4: L-section matching for zL outside 1+jx circle.

The reactive elements X and B can take the values of inductor or capacitor based on the solutions obtained after solving their respective topology equations. For the first topology in Figure 5.3, the values of X and B is given by [1]

2 2 푋퐿 ± √푅퐿/푍0 √푅퐿+푋퐿 −푍0푅퐿 B = 2 2 푅퐿+푋퐿

1 푋 푍 푍 푋 = + 퐿 0 − 0 퐵 푅퐿 퐵푅퐿

30 where, say for a load impedance, ZL = RL + jXL, RL is the real part of the load impedance representing the resistance whereas XL is the imaginary part of the load impedance, Z0 is the characteristic impedance of the transmission line. Similarly, for the second topology in Figure 5.4, X and B are given by

푋 = ± √푅퐿 (푍0 − 푅퐿) − 푋퐿

(푍 − 푅 ) / 푅 ) B = ± √ 0 퐿 퐿 푍0

Solving the above equations X and B can take positive values or negative values. Positive B is a capacitor and negative B is an inductor while positive X is an inductor and negative X is a capacitor. Determining them as capacitors and inductors from the positive and the negative values of X and B holds good for both the topologies. Hence, for a given load impedance there are multiple solutions possible based on the topology it follows and the values of reactance and susceptance.

The value of source reflection coefficient and load reflection coefficient was found to be ΓS =

0.421∠-153.66° and ΓL = 0.5809∠98.452° from Chapter 4. The input matching network is designed first. The source reflection coefficient ΓS is matched to the characteristic impedance Z0 of 50 Ω which is the impedance of the transmission feedline. On the Smith chart, a straight line is drawn from the center at an angle of -153.66°. The magnitude of 0.421 of ΓS is plotted, which lies outside the 1+jx circle. Hence, second topology seen in Figure 5.4 is used. Seen from the load there is a series reactance followed by a shunt susceptance. Once ΓS is marked, a circle is drawn with the radius of ΓS and with center of the Smith chart as its center. This is called as the SWR (standing wave ratio) circle. Another circle similar to r = 1 impedance circle is drawn on the admittance side. This circle has conductance g = 1. This helps to switch between the impedance and admittance circles.

ΓS touches the 1+jb circle at A as seen in Figure 5.5 reading the value of 0.42-0.5j. Moving down the admittance circle from ΓS to A gives a reactance of -0.3j. This negative value of reactance x = -0.3 implies it is a capacitor. Now from A on admittance circle impedance circle is reached by drawing a straight line from A through the center of the Smith chart and extending it on to the opposite side. This line intersects the 1+jx impedance circle at B reading 1+1.1j. To achieve the transmission line impedance of 50 Ω the center of the Smith chart must be reached. The center of

31 the Smith chart signifies the matched condition at which r = 1 with no imaginary quotient. From B, the center of the Smith chart can be reached by removing the imaginary part of the susceptance, i.e., by adding a value of -1.1j. The value of b = -1.1 implies it is an inductor. Hence, for the source L-section matching the reactive elements and their topology has been determined. Solving (5.1) and (5.2) [1] the values of the capacitor and inductor are obtained. The source matching network is seen in Figure 5.6.

−1 C = (5.1) 2휋푓푥푍0 -1 = 2×3.14×5.8×109×(-0.3)×50

= 1.83 pF

−푍 L = 0 (5.2) 2휋푓푏 -50 = 2×3.14×5.8×109× (-1.1)

= 1.248 nH

Figure 5.5: L- section source impedance matching on the Smith chart.

Figure 5.6: L-section source matching network.

Now, for the load matching network the value of ΓL = 0.5809∠98.452° is plotted on the Smith chart. An angle of 98.452° is drawn and the magnitude of ΓL = 0.5809 is marked on it from the center of the chart. The value of ΓL lies outside the 1+jx circle therefore, topology seen in Figure 5.4 is followed with a series reactance followed by a shunt susceptance seen from the load side. Repeating the same procedure as the source matching network, an SWR circle with the radius of

ΓL and center of the Smith chart as its center is drawn. The admittance circle 1+jb is drawn. The

ΓL point is extended to meet the 1+jb circle at A as seen in Figure 5.7 reading 0.45-j0.48 with a reactance of 1.23 i.e., x = -1.23. Negative reactance implies it is a capacitor. Then the point A on 1+jb circle is extended to the impedance chart by drawing a straight line from A through the center of the chart intersecting the 1+jx circle at B reading 1+1.2j. The center of the Smith chart can be reached from B by adding a susceptace of -1.2j. Negative susceptance indicates an inductor. Solving (5.1) and (5.2) with the values of x = -1.23 and b = -1.2 the values of capacitor and inductor are determined, and the load matching network is seen in Figure 5.8.

−1 C = 2휋푓푥푍0 -1 = 2×3.14×5.8×109×(-1.25)×50

= 54.92 pF

−푍 L = 0 2휋푓푏 -50 = 2×3.14×5.8×109× (-1.1)

= 0.98 nH

Hence, the load matching network with lumped elements is designed using the Smith chart. L- section network has certain limitations that is the circuit is realizable for frequencies for which the component size is way smaller than the design wavelength. For the frequencies satisfying the condition of l < λ/10 L-section matching is more useful. However, at higher frequencies the performance of the reactive elements is far from ideal as they cause unwanted effects such as parasitic capacitance, inductance, losses and fringing resonance. Because of the exhibition of such unstable behavior at high frequencies the stub matching is often preferred over lumped element matching.

Figure 5.7: L-section load impedance matching on the Smith chart.

Figure 5.8: L-section load matching network.

5.3 Single Stub

The second technique considered for achieving impedance matching is through single stub tuning. A stub is a transmission line connected either in shunt or series at a distance d from the load. Shunt stubs are designed using admittance chart whereas series stubs are designed using impedance chart of the Smith chart. These stubs can be short circuited or open circuited [8]. Even though the same performance is obtained from short circuit and open circuit stubs, usually open circuit stubs are preferred as it evades the hassle of inserting an extra via near each stub to connect it to the ground plane while fabricating, which is mandatory for short circuit stubs.

For the source impedance matching, the point of source reflection coefficient ΓS = 0.421∠-153.66° is marked first. For this, a straight line is drawn at an angle of -153.66° and the magnitude of ΓS =

0.421 is plotted. Then with ΓS as the radius from the center of the chart, an SWR circle is drawn.

A straight line touching ΓS and passing through the center of the chart is drawn extending to the opposite end of the circle to yS. The chart is now viewed as the admittance Smith chart. yS touches the 1+jb circle at point A as seen in Figure 5.9 and the distance between yS and A gives the length of the series transmission line from the transistor after which the stub needs to be connected.

Straight lines are drawn from the center of the chart to yS and A. This gives the value of 0.2125λ and 0.159λ respectively, read from the outer most circle of the Smith chart. The difference between the two gives the distance of the stub from the source.

Figure 5.9: Single stub source impedance matching on the Smith chart.

Length of the transmission line = 0.2125λ - 0.159λ = 0.0535λ

The left most side on the admittance chart refers to the open circuit point and the right most side refers to the short circuit point. The open circuit point has an admittance of y = 0 whereas short circuit point has an infinite admittance y = ∞. Then to reach the center of the Smith chart from point A, an open circuit stub is used to match it to the 50 Ω impedance of the feedline. Susceptance at A is +j0.9. Then using an open circuit stub of length 0.117λ the center of the Smith chart is reached. The length of the stub is found by travelling on the wavelength toward generator circle (outer most circle) on the Smith chart. With this, the source matching network using the single stub tuning is complete which looks like Figure 5.10 [9].

Figure 5.10: Single stub source matching network.

Then, the load matching network needs to be designed. The load reflection coefficient ΓL 0.5809∠98.452° is plotted on Smith chart. A straight line is drawn from the center of the Smith chart at an angle of 98.452° and the magnitude of 0.5809 is plotted. Then with ΓL as the radius from the center of the chart the SWR circle is drawn. From ΓL, the point on the admittance chart yL is reached by drawing a straight line from ΓL passing through the center of the Smith chart and reaching the opposite end of the SWR circle. yL now on the admittance chart touches the 1+jb circle at B as seen in Figure 5.11. The length of the series line is the distance between yL and B. These values are achieved by drawing a straight line from the center of the Smith chart to the points yL and B respectively. The point of intersection of these straight lines with the outermost wavelength toward generator circles reads the value of 0.365λ and 0.174λ.

Figure 5.11: Single stub load impedance matching on the Smith chart.

Length of the transmission line = 0.365λ - 0.174λ = 0.191λ

Then the susceptance of 1.4j at B is achieved by an open circuit shunt stub of length 0.152λ. This length of the stub moves from B to the center of the chart to achieve impedance matching. Load impedance matching circuit using single stub is seen in Figure 5.12. Thus, source and load impedance matching using single stub technique is done.

Figure 5.12: Single stub load matching network.

Chapter 6: Design Simulation on ADS

Once the impedance matching is completed then the design was implemented on Keysight ADS to check for its performance. Keysight ADS is the software tool used for RF/Microwave circuit design. Both the L-section design as well as the single stub matching were implemented on ADS. Figure 6.1 shows the schematic of L-section followed by its output in Figure 6.2. It has a gain of 16.8 dB and a noise figure of 1.33 dB at 5.8 GHz. When a transistor is selected it comes in with an s2p file containing S-parameters and data values that provide information of the transistor’s behavior at various frequencies. The s2p file of the BFU725F is inputted to the transistor two-port network as seen in Figure 6.1 with reactive capacitors and inductors connected based of the values derived from the Smith chart.

Figure 6.1: L-section source and load matching networks.

Figure 6.2: Output of the L-section matching networks.

The single stub matching network is seen in Figure 6.3. Stubs connected at a distance d from the transistor are transmission lines themselves. TLIN is the two terminal ideal transmission line component used to represent stubs [10]. Figure 6.3 shows the design in an ideal loss less medium with no losses taken into account. The E value for each transmission line is the electrical length in degrees. It is calculated by multiplying length of each transmission line which is in terms of λ with 360°. For all the lengths of stubs and transmission lines from chapter 5, their respective electrical lengths E is given by,

At the source, the distance of the transmission line dS = 0.0535λ × 360°= 19.26°

Length of open circuit stub = 0.117λ × 360° = 42.12°

At the load, the distance of the transmission line dL = 0.191λ × 360° = 68.74°

Length of the open circuit stub = 0.152λ × 360° = 54.72°

S-parameters model is used as the design is being simulated for S-parameters. The input and output terminations are 50 Ω as that is the source and load impedances used.

Figure 6.3: Schematic of single stub source and load matching network.

The output S-parameters of this design along with the noise figure at 5.8 GHz are seen in Figure 6.4. Since, there are no losses, the performance is as expected based on the design values obtained from the Smith chart. It can be observed from the output that the gain S21 is 0.2 dB less than the design specification of 17.1 dB gain and the noise figure is 0.01 dB less than the design target 1.3

43 dB noise figure. The minor deviations when reading the values from Smith chart could have caused this. However, the performance is close giving the results as expected. In this project, single stub technique was used for LNA design as stubs can be fabricated as transmission lines and it avoids the usage of lumped components. Even though lumped components can be used up to microwave frequencies, they tend to be unstable at higher frequencies causing spurious resonances, perturbations, parasitic capacitance, and inductance.

Figure 6.4: Output of matching networks using single stub technique.

To be more realistic, the design procedure must take into account transmission lines with losses as there are no lossless ideal transmission lines. MLIN is the microstrip transmission line for the practical design purpose. To fabricate the design on printed circuit board (PCB) a substrate needs to be chosen. FR-4 was the substrate chosen for this project to minimize costs. In order to determine the length and width of a microstrip transmission line, the tool LineCalc was used in ADS [11]. LineCalc is a built-in ADS tool for calculating physical parameters of transmission line. The following are the values taken for microstrip substrate. There are various substrate parameters used to calculate the dimensions of transmission line like substrate thickness (H) gives the thickness of the PCB. There are multiple thicknesses available ranging from 0.05 mm to 3.5 mm and 0.8 mm was used for this design. The amount of electric flux the material can hold when exposed to electric field is given by dielectric constant (εr). Copper is the conduction material used whose conducitvity is given by 5.96×107 S/m. There are various thicknesses of copper cladding

44 available from FR-4. One of them, 35 휇m was chosen which is very common. Electric energy dissipation is given by tanδ, dielectric loss factor, which was set to 0.019 based on the FR-4 datasheet.

Parameter Value Substrate thickness (H) 0.8 mm

Relative Dielectric constant (εr) 4.5 Relative permeability (Mur) 1 Conductor conductivity (Cond) 5.96e + 7 S/m Cover height (Hu) 3.9e+34 mil Conductor thickness (T) 35 μm Dielectric loss tangent (tanδ) 0.019 Table 6.1 Parameters of the microstrip substrate.

The values of Table 6.1 remain constant along with the frequency of 5.8 GHz and characteristic impedance of 50 Ω but the effective electrical length E_Eff of each MLIN varies. This value is taken from electrical length of ideal transmission line TLIN. Then, the microstrip transmission line was synthesized for its length and width using LineCalc as seen in Figure 6.5.

Figure 6.5: LineCalc tool in ADS for MLIN.

The length and width values of MLIN so generated using LineCalc are used to design the low noise amplifier as seen in Figure 6.6. ADS uses the standard temperature of 290K (16.85 ℃) to measure noise following the IEEE standards. Hence, the temperature is set to 16.85℃ in options section. As losses are considered in this schematic, gain as expected is lower from ideal transmission line design. It has a gain of 16.62 dB and a noise figure of 1.33 dB at 5.8 GHz. An increase in noise figure can also be observed in Figure 6.7 compared with the ideal transmission lines output in Figure 6.4.

Figure 6.6: Single stage LNA using MLIN.

Figure 6.7: Output of single stage LNA using MLIN.

The input and output impedance matched single stage LNA design using MLIN was cascaded with itself for the design of the two-stage low noise amplifier. This gives more gain combining both the stages whereas it will not have significant effect on noise figure because for cascaded design, noise figure of second stage is divided over the gain of previous stage. So, its effect is less. Repeating the design again on the schematic the two stage LNA is seen in Figure 6.8. It has a gain of 32.96 dB and a noise figure of 1.35 dB at 5.8 GHz. The gain is observed to be almost twice the single stage and a fractional increase in noise figure is also noticed in Figure 6.9. The noise figure of two- stage design is same as the theoretically calculated noise figure in Chapter 3 section 3.8.

Figure 6.8: Two-stage LNA with MLIN.

Figure 6.9: Output of the two-stage LNA.

6.1 DC Biasing

For an amplifier to amplify the signal, transistor must be turned on and remain in active region. There are three regions of bipolar junction transistor operation, namely, active region, cut off region, and saturation region. The transistor does not conduct any currents in cut off region and acts as a shorted switch in the saturation region, both of which are not desired. It is required to operate the transistor in the active region. Biasing a transistor provides the required DC voltage for it to operate in the active region so that it can amplify the signal when an RF input is applied.

DC biasing voltages are taken from transistor data sheet as VCE = 2V and IC = 25 mA. From the design aspect, when applying biasing conditions to the transistor it must be ensured that the RF signal does not travel through the path of the DC circuit. Knowing that the RF signal tends to travel through the path of low impedance helps to design the DC network.

Figure 6.10: DC biasing network.

The open circuit microstrip transmission line MLOC seen in Figure 6.10 acts as an RF choke by allowing DC signals but blocking the AC signals. It offers high impedance to the RF signals. The quarter wave microstrip transmission line MLIN is used to transform the RF short circuit to open circuit so that it does not load the DC arm [12]. That is the advantage of quarter wave transmission line as it converts open circuit to short circuit and vice versa. This is better understood through a Smith chart by how travelling 180° will move from the short circuit point on the left to the open circuit point on the right. Even though the quarter wave point is at 90° the value 180° comes from the signal travelling towards the input (90°) and suffering from reflections and travelling another 90° on return path. This value remains as 90° for transmission coefficients. Using this technique,

DC biasing is done for the circuit as seen in Figure 6.11. The length of quarter wave transmission line was found by taking the effective electrical length as 90° in LineCalc.

Figure 6.11: Two-stage LNA with DC biasing circuit.

MTEE is the microstrip tee component used to connect intersecting transmission lines i.e., transmission lines connected at T-junction to one another. Its placement makes more sense when visualizing layout as it helps in neat transition from one transmission line component to the other without irregularities. Modelling the layout becomes easier with MTEE insertion. It uses the same substrate properties as that of the transmission lines.

6.2 Final Schematic

To transition the schematic to a layout there are few more additional steps. All of the T-junctions were joined with an MTEE throughout the design for the ease of layout implementation. Near all the input, output, and DC ports an extra MLIN is connected. This is done so that once fabricated and connector pins are soldered on PCB it leaves enough room for connector pins without interfering with design.

Between the transistor pin and transmission line near it an MTAPER is used. It is an ADS component with two widths as seen in Figure 6.12. The larger width W1 is given the width of

49 transmission line whereas W2 takes the pin width of transistor. This component offers smooth merging of transmission line design and transistor pin on layout.

Figure 6.12: MTAPER in ADS.

The final schematic is seen in Figure 6.13. Lengths of transmission lines were tuned slightly for optimal results. Figure 6.14 shows the final cascaded two-stage LNA output. The addition of more microstrip components like MLINs, MTAPERs, and MTEEs has introduced more losses in the design. However, even with losses included the final schematic output has a gain of 30.16 dB and a noise figure of 1.46 dB meeting the design goal of 30 dB gain and a noise figure of less than 2 dB at 5.8 GHz.

Figure 6.13: Final schematic of the two-stage cascaded low noise amplifier.

Figure 6.14: Output of two-stage cascaded low noise amplifier.

Chapter 7: Layout and EM Simulations

7.1 Layout The layout is the physical model of the schematic to prepare it to be fabricated on a printed circuit board (PCB). While the schematic is for the designer’s understanding of each component and its performance, the layout is for the physical implementation of that design to be fabricated and tested. ADS has a built-in option of generating a layout from a schematic. Once the layout is generated it needs some modifications and few components added.

The initial layout generated was modified to space the tapers as per the pin dimensions of transistor BFU725F taken from data sheet. MTAPERs with transistor pin dimensions already given to its narrower widths were spaced from one another to allow 4-pin transistor to sit right on the pads when soldered. For the two emitter pads a conductor layer with vias was inserted to ground them as seen in Figure 7.1. Vias are used to connect the top conductor layer to the bottom ground layer. For any two or more layered substrates vias are required for establishing connectivity between them.

Figure 7.1: Final layout of the two-stage.

The yellow outline in Figure 7.1 shows the bottom ground layer. The upper conductor layer, bottom ground layer, substrate and vias need to be defined in the substrate editor widow to use that substrate properties for layout EM simulations. Using the same values defined for MSUB in schematic for the dielectric thickness and the conductor thickness, the substrate values are seen in Figure 7.2. ADS provides three dimensional view of the set up to ensure connectivity between top and bottom layer as seen in Figure 7.3. This helps to double check the design in case of a missing or wrong via connection, ground layer not defined correctly.

Figure 7.2: Substrate properties for EM simulations.

Figure 7.3: 3D view of the layout.

Electromagnetic simulations were then conducted for the layout. This simulates the layout for EM fields and provides the most realistic results prior to fabrication. It takes into account substrate properties, frequency plan, ports defined and gives the passive layout laid on a dielectric substrate. The symbol generated from the EM model is seen in Figure 7.4 where it is connected to RF ports and DC ports [14]. The output of this gives the performance that can be expected from testing the PCB. When running the simulation on the layout there will be radiations produced which cause undesired effects such as parasitic inductance or capacitance, displacement currents, coupling effect, etc. The electrical conductors in close proximity to each other cause parasitic effects. Displacement current is caused due to varying electrical field between conductors [15]. These inevitable and undesired effects can be reduced by inserting more vias so that they can be grounded. Hence, more vias were inserted near the emitter pins. The output of the EM cosimulation is seen in Figure 7.5. It has a gain of 30.06 dB, noise figure of 1.36 dB, and reflection coefficient of -15.70 dB at 5.8 GHz. Comparing these results with the schematic results in Figure 6.14 where it has a gain of 30.16 dB, noise figure of 1.46 dB, and reflection coefficient of -11.54 dB, it can be observed that EM cosimulation results are better with the refection coefficient improved by 4.1 dB and noise figure improved by 0.1 dB. The minor variation in gain from 30.16 dB in schematic output to 30.06 dB in EM cosimulation is tolerable considering the improvements in noise figure and reflection coefficient.

Figure 7.4: Schematic with EM symbol for cosimulation.

Figure 7.5: EM cosimulation output.

For PCB fabrication, gerber files were generated from the layout which contains the design information. The final design for PCB fabrication is seen in Figure 7.6 and a photograph of the fabricated PCB is seen in Figure 7.7. Unfortunately, the LNA PCB could not be tested due to COVID-19.

Figure 7.6: Final layout for fabrication.

Figure 7.7: PCB of the two-stage LNA.

Chapter 8: Conclusion

A two-stage low noise amplifier operating at 5.8 GHz with a noise figure of 1.36 dB and a gain of 30.06 dB was designed in this project. Low noise amplifiers are used in communication systems in the receiver. Understanding the importance of LNAs with low noise figure, in early chapters the fundamental concepts of noise, noise figure, stability, and gain were discussed as a means of providing rationale to design decisions. The project walks through the step by step procedure of designing the two-stage LNA, discussing each component used to complete the design. The transistor BFU725F by NXP semiconductors was chosen to operate at the design frequency of 5.8 GHz and was verified for stability and unilateral performance. Using the specific gain approach for the source and the maximum gain approach for the load, the source and load matching were done using the single stub technique.

The design was then implemented on ADS for simulation. Adhering to a practical design procedure, performance constraints like dielectric loss tangent, relative dielectric constant and conductivity of the conductor were taken into consideration. These parameters along with substrate thickness was used in calculating the dimensions of microstrip transmission line. The final schematic resulted in a gain of 30.16 dB, noise figure of 1.46 dB, and input reflection coefficient of -11.54 dB. Then, a layout of the schematic was generated. The layout was spaced as per the dimensions of the transistor pins and the grounding components i.e., vias were inserted. An EM symbol was then generated from the layout. The EM symbol was connected to RF ports and DC ports replacing the whole schematic and was simulated for EM cosimulation. EM simulations help determine the results that can be expected from testing the fabricated PCB. EM cosimulation resulted in a gain of 30.06 dB, noise figure of 1.36 dB, and input reflection coefficient of -15.70 dB. Hence, meeting the design specifications, a two-stage LNA was designed at 5.8 GHz and a PCB was fabricated, but it could not be tested due to COVID-19.

References

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