Digital Design Through Verilog Lecture Notes B.Tech (Iii Year – I Sem)
DIGITAL DESIGN THROUGH VERILOG LECTURE NOTES B.TECH (III YEAR – I SEM) (2019-2020) Prepared by: Mrs. P. ANITHA, Associate Professor Mr. K. SURESH, Assistant Professor Department of Electronics and Communication Engineering MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY (Autonomous Institution – UGC, Govt. of India) Recognized under 2(f) and 12 (B) of UGC ACT 1956 (Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified) Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India MALLA REDDY COLLEGE OF ENGINEERING AND TECHNOLOGY III Year B.Tech. ECE-I Sem L T/P/D C 4 1/ - /- 3 (R15A0410) DIGITAL DESIGN THROUGH VERILOG OBJECTIVE: This course teaches designing digital circuits, behavior and RTL modeling of digital circuits using Verilog HDL, verifying these Models and synthesizing RTL models to standard cell libraries and FPGAs. Students aim practical experience by designing, modeling, implementing and verifying several digital circuits. This course aims to provide students with the understanding of the different technologies related to HDLs, construct, compile and execute Verilog HDL programs using provided Software Tools: Design digital components and circuits that is testable, reusable, and synthesizable. UNIT - I: Introduction to Verilog HDL: Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Programming Language Interface, Module. Language Constructs and Conventions: Introduction, Keywords, Identifiers, White Space, Characters, Comments, Numbers, Strings, Logic Values, Data Types, Scalars and Vectors, Operators. UNIT - II: Gate Level Modeling: Introduction, AND Gate Primitive, Module Structure, Other Gate Primitives, Illustrative Examples, Tristate Gates, Array of Instances of Primitives, Design of Flip-Flops with Gate Primitives, Gate Delay, Strengths and Contention Resolution, Net Types.
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