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Verilog Gate Types

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Verilog Gate Types Tutorial Questions A and Discussion This appendix contains questions, answers, and discussion to accompany Chapter 1, the tutorial introduction. The goal of this appendix is to provide far more help and guidance than we could in Chapter 1. This appendix contains tutorial help for the beginning student and questions appropriate for use with an introductory course in digital systems design or computer architecture. The sections here are referenced from the sections of Chapter 1. Some of the questions assume that the reader has access to a Verilog simulator­ the one included on the book's CD will suffice. A few of the questions assume access to a synthesis tool; limited access to one is available through the CD. Finally, the book's CD includes copies of the books examples; retrieve them from there to avoid retyping. A.l Structural Descriptions The questions in this section accompany Section 1.1.2. The first two include a detailed presentation of how to develop a simple Verilog description, including a dis­ cussion of common mistakes. The questions following assume more familiarity with a hardware description language and simulator. 284 The Verilog Hardware Description Language A.1 Write a Verilog description of the logic AB diagram shown in Figure A.l. This 00 01 II 10 logic circuit im_plements the Boolean c function F=(AB)+C which you can 0 0 0 0 I probably see by inspection of the K­ map. Since this is the first from-scratch I I I I I description, the discussion section has far more help. Do This - Write a module specification for this logic circuit. The module will not have inputs or outputs. Use primitives gates Figure A.l F=(AB)+C (AND, OR, and NOT), connect them with wires, and include an initial statement to fully test your circuit. To produce B from B, add a NOT gate (inverter) to the above dia­ gram. Specify that NOT gates have a delay of 1 time unit and the others have delays of 2 time units. Oh, and try not to look at the answer below! If you're not sure what to do, read on. Discussion: The first thing to write is the module header and name - give it any name you wish. Next, break the description down into the individual gates, assigning distinct names to the wires connecting the gates. Now write the gate instantiations and specify the ports for interconnecting them. A gate is instantiated as shown here: and #5 myFirstAnd (q, r, s); Here an AND gate with delay five, instance name myFirstAnd, and ports q, r, and s is defined. Which connection is first in the list? The output; q it the output and the oth­ ers are inputs. Finish instantiating the gates. In answering the question, you might have written the following module descrip­ tion. Clearly, you probably used a different name for the module (it's top here) and also for the gate instance names (e.g., gl). The delay specification, which is optional when specifying gate instantiations, is required in the description because the problem statement asked for it. There are other ways to start writing this problem. module top; not #1 gl (d, b); and #2 g2 (e, d, a); or #2 g3 (f, c, d); endmodule This description will not parse; some of the identifiers have not been declared. Some? 285 Do This - Explain which ones? Why not the others? There are no declarations in this description, so why don't all of the identifiers produce an error? The reason is that an output of a primitive gate is declared as a wire by default. Thus, identifiers d, e, and f are all defaulted to be of type wire. a, b, and c are not declared and will thus cause errors. Why is the output of a primitive gate defaulted to be a wire? Real combinational logic gates are connected to wires. In the Verilog lan­ guage, new values are either driven on nets {wires are the default type of net) or loaded into registers. Primitive gates always drive wires. Now continue the example by declaring the gate inputs {a, b, and c) to be registers. This will allow us to assign values to them in an initial statement and to test the out­ put of our logic function. We could add the following declarations. wire d, e, f; reg a, b, c; But remember that the wire declaration is not needed because gate outputs default to wire declarations. The following description would parse without errors. module top; reg a,b,c; not #1 g1 (d, b); and #2 g2 (e, d, a); or #2 g3 (f, c, d); endmodule But, this description wouldn't do much except parse correctly. The goal is to simu­ late the design and convince yourself that the specification performs the logic function that you expect. Now we need to specify a set of inputs {called test vectors) so that we can simulate the circuit and observe its output. Do This- write an initial block that will provide several different inputs to these gates and display all values in the circuit. The block should be part of the top module. The ordered series of inputs that we will put into our design will be {a, b, c): 100, 110, 010, 011. This is a fairly extensive test set, even though it does not test every input combination. Discussion: To use the registers that we put in the description for the gate inputs, we need to write an initial block- registers can only be loaded by assignment state­ ments in initial and always blocks. We'll use an initial block since these are often used to provide test vector inputs. Here's our first try. Following the statements, the first three put 100 on the inputs {a, b, c). The next assignment changes b to make the input 110. The fifth assignment 286 The Verilog Hardware Description language changes a to make the input 010, and the last assignment makes the input 011. That is the sequence of inputs we want, but alas this specification will not work. initial begin a= 1; b = 0; c = 0; b = 1; a = 0; c = 1; end Do This- Explain why this initial block will not work. Discussion: There are two errors here. One error is there is no means of displaying the output when the inputs change. Let's add a $monitor statement to display the data to the screen whenever any value changes. Additionally, we will have the simula­ tion time reported. In our case we will use the statement: $monitor($time,"a=%b, b=%b, c=%b, d=%b, e=%b, f=%b", a, b, c, d, e, f); The monitor statement is not just a print statement. It will cause a printing of the quoted string when executed but then it will continue to monitor for changes on any of the input identifiers (a, b, c, d, e, and f here), printing the quoted string when any one changes. Only one of these $monitor statements can be active at the same time. If one is reached while another is active, the new one cancels the old. The second error is more fundamental. The error is that the only input value the gates will see is the last one: 011. The simulation didn't stop to let the intermediate values flow through the gates. Here's how to think about how the simulator works. At the start of the simulation, all values in the system (both nets and registers) have the value x (i.e., unknown). The initial and always blocks start executing in an arbitrary order. In this system, we only have one initial block; it runs, making all of the assign­ ments, and then it stops with a= 0, b = 1, and c = 1. When the initial block stops, the gates notice that their inputs have changed and they calculate their output values. The other input combinations are never seen by the gates. Indeed, if we simulated our current version of the module shown below we would get the simulation trace showing only the final inputs and output. Not cool. 287 module top; wrre d, e, f; reg a, b, c; not #1 g1(d, b); and #2 g2{e, a, d); or #2 g3{f, e, c); II (AB)+C initial begin $monitor{$time, "a=%b, b=%b, c=%b, d=%b, e=%b, f=%b\n", a, b,c,d,e,f); a = 1; I I initialization b = 0; c = 0; b = 1; I I first change of input a= 0; I I second change of input c = 1; I I third change of input #20 $finish; I I this tells the simulator to stop end endmodule Here is the simulated output showing the values in the circuit. The first value on the line is the time at which the values occur. The first line shows the inputs valid at time 0, the output of the not gate (d) changes one time unit later, and the output of g2 {e) and g3 (f) change at time 2. Note that the value of 1 on c causes f to change at time 2. We don't have to wait for the output of the not gate to propagate through gate g2 and g3. 0 a=O, b=1, c=1, d=x, e=x, f=x 1 a=O, b=1, c=1, d=O, e=x, f=x 2 a=O, b=1, c=1, d=O, e=O, f=1 Back to our problem: no delay was used in the assignment of the registers, and they were all assigned {in order, from top to bottom) during the same time.
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