INVITED PAPER Graphene Growth and Device Integration This paper describes one of the emerging methods for growing grapheneVthe chemical vapor deposition methodVwhich is based on a catalytic reaction between a carbon precursor and a metal substrate such as Ni, Cu, and Ru, to name a few.

By Luigi Colombo, Fellow IEEE, Robert M. Wallace, Fellow IEEE,andRodneyS.Ruoff

ABSTRACT | Graphene has been introduced to the electronics devices in order to exceed the performance characteristics community as a potentially useful material for scaling elec- of current device applications as well as developing new tronic devices to meet low-power and high-performance devices, especially for flexible electronics, transparent targets set by the semiconductor industry international road- electrodes for displays and touch screens, photonic map, radio-frequency (RF) devices, and many more applica- applications, energy generation, and batteries [3], [12], tions. Growth and integration of graphene for any device is [13]. The first graphene films were only a few tens of challenging and will require significant effort and innovation to micrometers on the side and so the principal first issue in address the many issues associated with integrating the making graphene devices a reality is the development of a monolayer, chemically inert surface with metals and dielec- graphene of sufficient quality and size to meet the basic trics. In this paper, we review the growth and integration of physical and electronic properties. Since the isolation of graphene for simple field-effect transistors and present graphene from natural graphite, a number of techniques physical and electrical data on the integrated graphene with and processes have been studied and are in development to metals and dielectrics. form graphene materials for a variety of applications; an extensive and complete review of these processes has KEYWORDS | Chemical vapor deposition (CVD); electrochemical recently been summarized by Bonaccorso et al. [22] and a transfer; graphene; mobility; Raman spectroscopy; X-ray concise history of graphene is presented by Dreyer et al. photoelectron spectroscopy [23]. It is still too early to select the final graphene growth process for high-performance electronic devices since none of the processes meets all of the basic requirements. I. INTRODUCTION Today, there are a few sourcesofhigh-qualitygraphene Over the past seven years or so there has been a lot of films: 1) exfoliated graphene from natural graphite or excitement in using graphene for many electronic various other sources of graphite [24]; 2) graphene films applications among others [3]–[6]. Researchers have on SiC single crystals formed by the evaporation of silicon looked to graphene as a material with which to fabricate from either the carbon- or silicon-rich surfaces of SiC [25]; and 3) graphene grown on metal substrates by chemical vapor deposition (CVD) [11], [26]–[29]. The latter two graphene growth techniques have emerged as having the Manuscript received June 4, 2012; revised April 1, 2013; accepted April 17, 2013. Date highest potential for high-performance electronic applica- of publication May 24, 2013; date of current version June 14, 2013. This work was supported in part by the Nanoelectronic Research Initiative and the Southwest tions. There are other sources of ‘‘graphene,’’ for example, Academy of Nanoelectronics (SWAN–NRI) program. The work of R. M. Wallace was reduced graphene oxide or growth on various other metal also supported by an IBM Faculty award. The work of R. S. Ruoff was also supported by the W. M. Keck Foundation, the National Science Foundation, surfaces. However, these are either discontinuous, and the U.S. Office of Naval Research. ‘‘doped’’ with oxygen, or multilayered, as in the case of L. Colombo is with Texas Instruments Incorporated, Dallas, TX 75243 USA (e-mail: [email protected]). growth on metals with high carbon solubility, but these R. M. Wallace is with the University of Texas at Dallas, Richardson, TX 75080 USA may be suited for applications having less stringent (e-mail: [email protected]). R. S. Ruoff is with the University of Texas at Austin, Austin, TX 78712-0292 USA requirements [23], [30], [31]. (e-mail: [email protected]). Each of the graphene sources has its advantages and Digital Object Identifier: 10.1109/JPROC.2013.2260114 disadvantages: Graphene exfoliated from natural graphite

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is of very high quality, as established by carrier transport After the introduction of CVD graphene on Cu there properties, but the area of these films (flakes) is limited to has been a renewed focus in trying to grow large single hundreds of micrometers squared and is thus not scalable graphene layers on Pt, Ni, Co, and Ru among others [21], to meet high-volume manufacturing (HVM) requirements. [26], [29]. However, because of the higher C solubility in Multilayer graphene grown on SiC single crystals has been these metals and difficulty in etching for some of them, the shown to have excellent transport properties [32]–[34]. processes are not yet commonplace, even though there are Further, these films have the advantage of having definite thermal stability advantages in comparison to Cu. exceptional surface flatness, and it is for this reason that The quality of graphene grown by CVD, as determined by this material is preferred by many surface scientists to transport measurements, is now nearly equivalent to that study the basic physical properties of graphene. However, of graphene exfoliated from natural graphite on both SiO2 in order to satisfy the requirements of many electronic [44] substrates as well as on hexagonal boron nitride applications, from nanoelectronics to flexible electronics (hBN) [45]. The availability of large-area graphene grown and transparent conductive electrodes, it is necessary to on Cu affords the ability to form multilevel stacked 3-D form large individual single layers of graphene. At this devices that cannot be easily fabricated using traditional time, exfoliation of the full graphene films from SiC semiconductor materials with a low thermal budget. This substrates has not been achieved yet, and even if it could is all due to the ambipolar nature of graphene and the be achieved, as Hashimoto et al. suggest [35], it might be ability to grow and transfer to any substrate. impractical for many applications because of the SiC In order to take full advantage of graphene grown on substrate size limitations and, to a lesser extent, cost. The any electrically conductive substrate, it is critical to introduction of 450-mm silicon integrated circuit devel- developatransferprocessaswellasthesubsequent opment and production in the next decade or so will make cleaning and integration processes to ensure minimum the use of SiC as a source of graphene even more difficult graphene degradation so as to take advantage of the as- unless SiC graphene can be grown directly on these very grown material properties. Alternative growth methods on large Si wafers. nonconductive substrates are being explored [43], [46], The most challenging aspect of the use of graphene for [47] and may offer the prospect of high-quality material electronicdevicesistheabsenceofabandgap.Itiswell without the need for transfer methods. known that graphene develops a bandgap as its width Fabrication of electronic devices will require the narrows [36], and it would thus be desirable to be able to development of low defect density, highly ordered large- grow graphene nanoribbons (GNRs) in place. There are area graphene films, thin dielectric deposition processes several reports on the chemical synthesis of atomically that do not disturb the band structure of graphene, to precise GNRs [37]–[40], but there are no reports, to our select and develop contact materials and processes that knowledge, of GNR deterministicplacement.Thisisakey provide low contact resistance, and to develop associated research area that requires much more attention. integration processes such as etching and surface cleaning. Traditionally, processes such as CVD and atomic layer While thin dielectric deposition on Si is well developed deposition (ALD) have been a preferred method of film and understood, growth of scaled dielectrics on clean growth/deposition for many types of materials, and it graphene is facing some challenges. For example, because would be desirable if such growth techniques could be clean graphene is chemically inert, uniformly thin di- used for graphene. There have been several recent electrics, at the nanometer scale, have been difficult to attempts at the growth of graphene on Ni by CVD, but deposit. The chemical inertness of the graphene surface the films were mostly multilayers with only small patches requires some functionalizationVeither intentional or of monolayer graphite [41], [42]. Recently, bilayer unintentional (i.e., contamination). Growth of uniformly graphene synthesis at the underlying Ni/SiO2 interface deposited high-k dielectrics on hydrogen terminated Si has been reported with arbitrary carbon sources to the met a similar problem, and fortunately a thin oxide and/or exposed Ni surface [43]. an O–H terminated surface were found to fix the problem. Li et al. [11] on the other hand developed a CVD process Unfortunately graphene does not have a natural oxide and of graphene on Cu substrates where one can grow a so we have to look for different solutions. In addition, low- monolayer of graphene on arbitrarily large Cu substrates. resistance metal contacts, necessary for operation of high- This CVD process has now been adopted by many because of performance devices, have also shown to be challenging, the ease of implementation, and it is simplifying graphene and so many researchers are dedicating significant device development, in comparison to exfoliated graphene. resources to solve and understand this problem. The advantage of graphene on Cu by CVD over graphene An additional significant complication that faces on SiC for HVM is that the CVD process is scalable to sizes graphene is that it does not have a bandgap, thus leading limited only by the size of the CVD system. For example, to devices that do not turn off. It has been found that as the Bae et al. [12] used the CVD graphene on Cu process to scale width of graphene is decreased below a certain value the the growth to square meter copper substrates for display and confined carriers give rise to opening of a bandgap [36], touch screen applications. [48]. Bernal stacked bilayers of graphene have also been

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found to show a bandgap under a transverse electric field A number of scanning probe microscopy techniques [49], [50]. Other than developing non-field-effect-transistor have been applied to graphene metrology, including (FET)-based devices, there are a number of groups trying to scanning tunneling and atomic force microscopy. The introduce a bandgap in graphene to increase the performance former has revealed atomic resolution details of graphene of graphene FETs [51]–[59]. growth [72] and impurity effects [73], while the latter is In this paper, we will review the state-of-the-art typically used for high-resolution profilometry, establish- graphene growth and electronic device integration devel- ing that single- or few-layer graphene growth is present, opment. It is not the intent of this paper, however, to for example [74]. perform an exhaustive review of GNRs and bilayer FET Raman spectroscopy, widely employed for graphene devices and related issues. Rather, we seek to provide the research due to the sensitivity to the bonding structure of reader with an introduction to graphene synthesis from an carbon allotropes [75], is used to establish the level of electronicsmaterialintegrationperspective,asthisisthe perfection of sp2 bonding in a graphene sheet [76]. This key step to HVM. nondestructive technique typically uses coherent light that results in inelastic scattering leading to potentially resonant interactions that enable the study of electronic II. GRAPHENE METROLOGY AND and vibrational properties of molecules and crystals [77]. CHARACTERIZATION The technique can use a focused analysis spot and enable Several techniques have been used in the study of the mapping of 50 50 m2 regions in typical graphene and the associated integration issues, and so a applications. few words on these techniques are appropriate. The reader Finally, X-ray photoelectron spectroscopy (XPS) has will find numerous results in the graphene research also been used in the characterization of graphene and literature employing these techniques, many of which graphite. The technique relies on the photoelectric effect provide the complementary information needed to enable [78], where electrons are generated through the illumina- the integration of graphene and other materials required tion of the sample by (typically) soft (1.4 keV) X-rays, for device fabrication. Examples of such characterization often with a monochromatic source for superior resolu- techniques are presented in what follows, but since a tion. As a result, the energy of the generated electrons detailed discussion is beyond the scope of this review, a limits their origin to less than 10 nm of the surface and, brief survey of these methods is offered here, with as a result, the technique is quite surface sensitive. The references offered to the reader for further in-depth energy spectrum of the electrons is analyzed, and is details. Recent reviews of graphene metrology have sensitive to the local carbon bonding environment [79]. become available as well [60]–[62]. In this review we The C1s lineshape for graphitic materials is complex, and focus on those techniques that primarily impact integra- requires careful analysis to establish the presence of tion for device fabrication. detectable impurities (for example, C–O) on the surface Since ‘‘seeing is believing,’’ a number of microscopy compared to more complicated relaxation phenomenon techniques have been employed in graphene research. associated with the photoelectron generation [80], [81]. Optical microscopy is a first choice in this regard, where a The analytical spot size is typically on the order of number of optical methods to enhance the image contrast squared millimeters and thus requires relatively large can be employed to get a sense of the graphene samples. macroscopic quality. The placement of exfoliated graphene on a suitably thick SiO2 layer to enable contrast through interference is now well known and convenient [63], [64]. III. GRAPHENE GROWTH It is also noted that recent work has extended the Graphite growth on metals has been observed by many application of the spectroscopic ellipsometry technique researchers, especially by the catalysis community over at to graphene, where the phase change of the incident and least the past 50 years [82]. Karu and Beer [83] reported reflected light is used [65]. on the pyrolitic growth of many layers of graphene in 1966, Of course, higher resolution studies require alternative where they exposed the surface of nickel to methane, probes such as electron beams, and both scanning electron dissociating it, diffusing the resulting carbon into the microscopy (SEM), and high-resolution transmission elec- nickel, and then precipitating multilayers of graphene on tron microscopy techniques are used [66]. Recent studies the nickel surface upon cooling. Blakely and students in have employed powerful aberration-corrected TEMs for the 1970s described the details of the C precipitation superior resolution [67]. In this case, care must be exercised process from metals (Ni, Pt, Pd, Co) as deduced by surface in controlling the beam power so as to avoid damaging analytical techniques and stated that monolayer graphite graphene. Alternatively, such beams can be used to etch was the first material to segregate to the surface of the graphene for device fabrication. Low-energy electron metal surface before full graphite precipitation upon microscopy [68] has also been employed to observe the cooling to room temperature [84]–[88]. This pioneering growth process of graphene in a number of studies [69]–[71]. work provided the basic ideas on how to grow multilayer

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graphene on metals and was recently reviewed by and the eutectic temperature, the solubility of C is as high Wintterlin and Bocquet [89]. as a few percent and it is still soluble at a temperature of Thenumberoflayersofgrapheneonmetalsistofirst about 500 C. On the other hand, the Cu–C system is a order dependent upon the solubility of C in the metal and particularly interesting system because the solubility is thecoolingrate.Ahighersolubilityatagiventemperature extremely low. The Ir–C system is an equally attractive results in a higher number of graphene layers precipitating system because of the low carbon solubility at at the surface of the metal. Transition metal substrate temperatures below 1000 C as well as a high catalytic selection for graphene growth depends principally on the activity. solubility of C in the metal and the propensity for the Carbon also has a low reactivity and bond strength with metal–C solution not to form a metal carbide compound. Cu [90], which makes it easy to remove the graphene Before selecting a metal, one must thus first establish that through chemical etching of the Cu substrate. The removal there are no stable or metastable metal carbide phases that has been accomplished by chemical etching of the metal by form during any of the process steps. Second, it is several typical Cu etching chemistries such as aqueous important to select a material that has a low C solubility in FeCl3 solutions, ammonium persulfate, or nitric acid, and order to provide sufficient control of the number of more recently by electrochemical etching to dissociate the graphene layers. Fortunately, there is already an estab- graphene from the substrate. The transfer process will be lished compendium of equilibrium phase diagrams avail- reviewed in greater detail in Section IV-A. able online through the American Society of Metals of the As noted earlier, it would certainly be desirable if metal–carbon systems. The Co–C, Ni–C, Cu–C, Pd–C, graphene could be grown directly on a dielectric surface, Ru–C, Rh–C, Pd–Cu, Ag–C, Ir–C, Pt–C, Au–C, Ge–C, and without a metal intermediary. Growth of graphene has perhaps others, are a few binary systems where a stable been reported on hBN, magnesium oxide, cobalt oxide carbide phase does not seem to form under equilibrium (Co3O4)andperhapsothers[91]–[94].However,atthis conditions; however, one must also pay attention to time, there are no reports of high-quality, large-area metastable phases as in the case of Ni2C [26], [90]. continuous single-layer graphene growth on any dielectric Fig. 1(a) and (b) shows the phase diagram of Ni–C and surface. Cu–C, respectively, where it is very clear for the Ni–C In the case of metals, there are other criteria for system that, at temperatures less than the melting point substrate selection other than C solubility, such as substrate etchability, availability or cost, purity, grain size, orientation control, etc. Therefore, given these basic requirements, it is desirable to have a metal–carbon system that satisfies the aforementioned characteristics. Unfortunately, at this time, there is no single metal that fulfills all of the requirements but the metals being used are providing a sufficient quantity and quality of graphene to enable device development. Currently, the research community has basically overcome the challenge of the growth of monolayer graphene by using CVD. However, because graphene does not have a bandgap, it would be desirable for simple FETs to have a channel material with a bandgap. Two approaches have been used to introduce a bandgap in graphene: one is to form GNRs, which have been shown to have bandgaps and the second is to form bilayer graphene. GNRs have been found to show width-dependent ‘‘band- gap,’’ while the bilayers show a bandgap when a trans- verse electric field is applied. The formation of GNRs at the few nanometer dimension has the added challenge of controlling the graphene edge structure and dimen- sionsorlineedgeroughness(LER)asitiscommonly referred to for Si transistors [95]–[97]. Growth of bilayer graphene on the other hand has been demonstrated on both metals and dielectrics, but it is difficult to control thenumberoflayersatthistime[43],[98],[99].Some advantages and disadvantages of the various graphene Fig. 1. (a) Ni–C phase diagram. (b) Cu–C phase diagram. preparation and growth techniques are summarized in (Adapted from [1].) Table 1.

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Table 1 Graphene Film Growth Techniques Comparison

A. Chemical Vapor Deposition of graphene growth on Cu to very large areas. Since the graphite growth process on Ni takes place by a precipita- 1) Monolayer Graphene: CVD is one of the most tion process, even for very thin Ni films, graphene is only extensively used processes in the semiconductor industry observed in small regions [41], small grains, where perhaps because of its flexibility, composition control, conform- the grains are depleted of the carbon through heavy ality, efficient material usage, etc. It would be advanta- precipitation at grain boundaries. Recently, however, geous if we could use this process technology to grow Addou et al. [26] have reported on the growth of graphene graphene films. As with most materials, thickness and on Ni(111) at a relatively low temperature range, 500 C– composition control are critical and in the case of 650 C. These results are encouraging, but even at such graphene, as a single element material, composition low temperatures, it is difficult to completely prevent control is not an issue, however thickness control, precipitation upon cooling. Additionally, another set of impurities, and surface flatness are extremely critical. very interesting results of graphene growth on single- Graphene grown on Cu was found to grow by a surface crystal Co [29] and Ru [112] on sapphire has also been mediated process and can now be grown routinely and can recently reported, suggesting that the elimination of grain be transferred to any substrate for further evaluation and boundaries leads to improved control of graphene growth. use, while still maintaining the overall properties of the as- These results are important since they demonstrate the grownfilm[2].Fig.2(a)and(b)showsSEMimagesof ability to grow high-quality graphene and perhaps even graphene on Cu and graphene transferred to SiO2, hetero-epitaxial graphene on nearly lattice matched respectively, showing the uniform nature of the film substrates such as Ni and Co. However, there could be across a large area [11]. Fig. 2(c) further shows the scaling some technological limitations such as the unavailability

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[117]. Such methods result in a high density of hexagonal graphene regions upon further exposure to the CVD process. Recently, there have been some advances in the growth of large single-crystal graphene with grain sizes up to 0.5 mm on Cu substrates [118], as shown in Fig. 3(a), and up to 1 mm on Pt substrates [21], as shown in Fig. 3(b). Fig. 3(a) shows a single crystal of graphene grown on Cu where the average growth rate is about 3 m/min, and it is of high quality as determined by Raman spectroscopy as well as transport properties [118]. Recently, Petrone et al. [45] also reported on the mobility of CVD large-area domain, probably single crystal, graphene grown by the same process as that reported by Li et al. [118]. They found 4 2 the mobility to be as high as 2.5 10 cm /VsonSiO2 and 4.5 104 cm2/Vs on hBN for carrier-density- independent mobility and a residual carrier concentration at the Dirac point of much less than 1 1011 cm2 indicative of a good transfer process. These films show high mobility despite the fact that the growth front is dendritic, i.e., ‘‘rough.’’ The growth rate of the films Fig. 2. (a) SEM of graphene on copper and (b) optical image of grownonPtisalsoaboutthesameasthefilmsreported graphene transferred onto a quartz substrate. Adopted from [11]. (c) Large-area graphene grown by CVD on Cu and transferred to by Li et al. [118] on Cu. On the other hand, the graphene polymethylmethacrylate (PMMA) by a roll-to-roll process. grown on Pt and removed from the substrate by an Adapted from [12]. electrochemical process clearly shows a nearly flat growth front, as indicated by the nearly hexagonal shape, of large-area sapphire single crystals. The results of graphene growth on single-crystal Co [29] and Ru [112] on sapphire have also been recently reported, suggesting that the elimination of grain boundaries leads to improved control of graphene growth. These results are important since they demonstrate the ability to grow high-quality graphene and perhaps even hetero-epitaxial graphene on nearly lattice matched substrates such as Ni and Co. However, there could be some technological limitations such as the unavailability of large-area sapphire single crystals. These results could have a positive impact on the fabrication of high-quality electronic devices on graphene if the resulting graphene on lattice matched substrates has a final lower defect density. Growth of large-area graphene is critically important, not only for nanoelectronic devices but even more so for plastic substrate electronics and transparent conductive electrodes, as well as energy generation applications. The principal difference between these applications is that transparent conductive elec- trodes may tolerate defects in the graphene films such as grain boundaries that other devices may not. Higher per- formance thin-film electronic devices on flexible sub- strates are promising since graphene would provide much higher mobilities than other materials under evaluation [113]–[115].

There have also been reports of CVD graphene Fig. 3. Single crystals of graphene grown by CVD using methane on synthesis using patterned nucleation sites such as Ni polycrystalline (a) Cu (adopted from [9]) and on (b) Pt (adopted from metal dots [116] or even patterned graphene seed regions [21]) substrates.

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120 corners of the crystal. With this faceted graphene mediated synthesis [40], [108], [121] as well as longitudi- single crystal, one would expect exceptional transport nal chemical unzipping of carbon nanotubes (CNTs) [110]. properties, but at this time, while the density-independent GNRs have also been formed by a templating growth mobility is very good, > 7.1 103 cm2/Vs with a residual process on SiC [101]. This would certainly be an elegant carrier concentration of about 2 1011 cm2,attheDirac approach to address the many issues of forming GNRs, point, it is lower than the best reported for graphene however, at this time, this can only be achieved directly on grown on Cu or exfoliated graphene. However, this lo- SiC crystals and this can be an intermediate approach for wer mobility could be a result of unoptimized device device evaluation. The continued development of GNR for processing. any device will be critical to the scaling of graphene-based devices regardless of whether a large bandgap is needed. In 2) Bilayer Graphene: Bilayer graphene has been observed addition, as already mentioned above, graphene scaling during the growth of CVD graphene layers in most reports. will need precise LER control in order to yield uniform The density of the bilayer regions has been decreasing as device performance across a wafer [107]. It is unlikely that the CVD process is improving. The principal reason for the traditional etching will meet the required uniform GNRs, successful growth of monolayer graphene is the low C thus the development of deterministic atomically precise solubility in the Cu substrate and the absence of catalytic formation approaches may be necessary. Graphene and activity of graphene. It is this very reason that makes it GNRs are being considered for interconnect applications difficult to grow uniform controlled multilayer graphene as well but the effort for its implementation has been fairly layers. The need for demonstration of bigraphene devices low in comparison to other applications [122], [123]. has spurred many to investigate the growth of bilayer graphene by CVD. There are a few reports on the C. CVD Graphene Characterization intentional growth of large-area Bernal stacked bilayer Raman spectroscopy is one of the most effective graphene [98], [99]. The results seem promising and, at characterization tools for graphene. Ferrari et al. [124] this time, there are potentially two mechanisms for and Casiraghi et al. [125] have performed extensive studies growing these films: 1) growth of the second layer by the to establish the relationship between Raman spectral use of graphene fragments formed on a source metal characteristics and the number of graphite layers and surface (Cu in [99]); and 2) growth under the first transport properties. There are three principal Raman growing graphene films, as reported by Nie et al. [119]. spectral characteristics that are used to evaluate the There are also cases where the films are not uniformly presence and quality of graphene: the D-band (peak) at Bernal stacked, perhaps due to the presence of multiple 1350 cm1,theG-band at 1590 cm1, and the 2-D-band grains and thus poor registration of the first and second at 2700 cm1.TheD-peak is representative of defects in films. graphene or graphite, while the G and 2-D-peaks, indicative Progress is being made deliberately in the basic of the sp2 bonding, are very sensitive to the doping levels in understanding of bilayer graphene growth [43], [119], the films. Additionally, the 2-D-peak is made up of two [120]. Sun et al. [120] studied the structure of graphene distinct peaks 2-D1 and 2-D2 in natural graphite, and as the and multilayer graphene on Ni by in situ low-energy graphite tends toward a monolayer, the higher wave number electron microscopy (LEEM) and found that single layers peak 2-D2 decreases to merge into a sharp 2-D-peak at the of graphene are strongly bound to the Ni substrate and lower wave number, and it is this signature that enables the -band structure characteristic of graphene is absent, one to distinguish graphene from multilayer graphene whileitispresentforbilayergraphene.Thiscouldbean [124]–[126]. issue in the growth of either monolayers of graphene or Fig. 4 shows the Raman spectrum of graphene grown bilayers; however, Peng et al. [43] using a similar process on Cu foils and transferred onto SiO2/Si substrate in find that the bilayers are well behaved according to comparison to that of highly oriented pyrolitic graphite Raman spectroscopy. At this point though there are no (HOPG). The spectrum clearly shows a narrow 2-D reports yet on the electrical behavior of these films. spectral band indicating that the film is a monolayer of graphite, and the absence of a significant D-band shows B. Graphene Nanoribbons that the films have a negligible defect density. GNRs have been extensively studied with the intent of The growth of graphene on copper can be controlled by introducing a bandgap in graphene as well as trying to changing the processing conditions such as substrate evaluate the limits of graphene physical scaling. The first surface conditions, temperature, pressure, precursor and reports have been on chemically derived GNRs from hydrogen partial pressure, and precursor type. At first, a natural graphite with widths below 10 nm. These films few bilayer regions in graphene on Cu were reported [11], showed semiconducting behavior with carrier mobilities presumably as a result of defects on the Cu surface, long below 200 cm2/Vs. The need to form graphene with a growth times, and higher precursor pressures. The growth bandgap has spurred other groups to form GNRs by direct of bilayer regions was studied by Nie et al. [119], and they chemical methods, a bottom–up approach and surface showed that the bilayer regions are a result of carbon

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Fig. 4. Raman spectrum of CVD graphene on SiO2 and that of HOPG.

diffusion under the first graphene film rather than on top of the graphene. The bilayer and sometimes trilayer regions are always small and do not grow even after extended growth periods suggesting that as the Cu surface is covered with graphene, theCsourceforthebilayer growth disappears. What distinguishes the growth of graphene on Cu from growth on other metals is that the growth process is surface limited; that is, the growth ceases as the metal surface is covered with graphene. The 2-D surface-limited growth process of graphene on Cu was identified using a carbon isotope labeling technique, as reported by Li et al. [127]. In this experiment, the surface of Cu is exposed sequentially to 12 ‘‘normal’’ methane, primarily CH4, and then to methane Fig. 5. (a) Raman spectroscopic map of graphene grown on Cu using 13 containing C. Because of the mass difference between isotopically labeled carbon in methane (12CVstandard graphene and 12Cand13C, the Raman peak positions shift, and this shift 13C). (b) Raman spectroscopic map of graphene grown on Ni using was used to monitor the location of the two carbon isotopically labeled carbon in methane (12CVstandard graphene and 13 isotopes on the Cu surface. Fig. 5(b) shows the Raman map C). (Reprinted with permission, Ó2010 American Chemical Society; adapted from [8].) 12 of graphene grown on Cu by sequential exposure to CH4 13 and CH4 at about 1035 C and the corresponding Raman spectra [Fig. 5(a)]; it is clear from the banding, yellow and black, that graphene is growing by a 2-D, i.e., surface mediated, process. A similar experiment was performed A. Transfer of CVD Graphene using thin-film Ni as the substrate, and it was found that The utilization of CVD graphene grown on metals for graphene does not grow by the same process on the Ni as device applications currently requires a transfer process exhibited by the uniform shift of the G-peak, as shown in from the metal substrate to a more suitable substrate, a Fig. 5(c) and (d).

IV. MATERIALS INTEGRATION In order to create graphene-based electronic devices, it is necessary to integrate graphene with a dielectrics, metal contacts, and electrodes. Fig. 6 shows a cross section of a simple four-terminal device with a source and drain, gate dielectric, top gate electrode, and bottom gate contact or body contact. In this section, we will review graphene transfer from metals to dielectrics, dielectric deposition and chemical analysis on graphene, and the effect of Fig. 6. Schematic diagram of a dual-gated graphene FET structure. dielectrics on electronic transport and contact materials. (Reprinted with permission, Ó2009 American Institute of Physics [14].)

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dielectric layer on the surface. The transfer process, although far from ideal, enables reasonable quality graphene for device research and development, with the potential for large-area substrates. In contrast, Si sublima- tion from SiC renders graphene layers on a wafer surface outright, and thus does not require a transfer process to fabricate research devices [128]. In this case, however, the available wafer area size limits the economics of the process and, thus, the potential applications, specifically those requiring integration with Si or those requiring very large areas such as display applications in an HVM environment. The transfer process, first reported by Yu et al. [129], entails a number of wet chemical processes; these can include exposure of the graphene/metal substrate to polymers, solvents, etchants, water rinses, as well as assorted thermal anneals. From a semiconductor manu- facturing point of view, it is clear that such processes would be expected to introduce organic contaminants or defects at some level, and thus a systematic understanding of the impact of the processes is desirable. For example, spin-on poly(methyl methacrylate) (PMMA) [11], [41] or polydimethylsiloxane (PDMS) [129] have been used as a protective coating over the graphene permitting the etching and removal of the underlying metal substrate used for growth, as shown in Fig. 7(a). At the conclusion of the metal etching process, a ‘‘raft’’ of PMMA/ graphene remains, which can be essentially ‘‘fished’’ out of the solution and placed onto a desired substrate, such as a SiO2/Si wafer. The PMMA is then often dissolved away using a suitable solvent, such as acetone. Figs. 8 and 9 show the effect of PMMA residues on graphene device behavior and the resulting surface charac- teristic as determined by XPS [18]. Fig. 8(a) shows the XPS spectra of CVD graphene on Cu, followed by Fig. 8(c) after transfer to a SiO2/Si substrate and PMMA removal using acetone, and finally the film is annealed under ultrahigh vacuum [Fig. 8(c)]. It is seen that the typical PMMA solvent removal process is incomplete, resulting in detectable residuals in the C1s spectra. The subsequent vacuum anneal reduces these residuals to levels near the limit of detection for XPS, and is consistent with prior scanning tunneling microscopy (STM) studies using a reducing atmosphere [73] as well as more recent studies [133]. It is interesting that XPS data performed on the same films after transfer do not show any detectable metal; however, while XPS can provide initial indications on the metal (Cu for example) concentration on Fig. 7. Graphene transfer process from the Cu substrate. (a) Chemical dissolution of the Cu, (adapted from [2]. the graphene surface, more sensitive techniques such as (b) Electrochemical separation [20] of Cu and graphene. inductively coupled plasma mass spectrometry (ICPMS) (Reprinted with permission, Ó2011 American Chemical Society.) will have to be used before such films can be introduced in a Si line. Another method of transferring the graphene is to use a ‘‘dry’’ process where the graphene is covered with the usual dielectric. Following the original work on device measure- polymer, for example, PMMA, but rather than placing the ments using exfoliated graphene, a majority of the studies substrate in the ‘‘wash water’’ and transferring the with CVD graphene entail transfer to Si wafers with a SiO2 graphene/PMMA stack over water, it is removed from on

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Fig. 8. XPS C1s spectrum for (a) CVD graphene on Cu, (b) graphene after transfer to SiO2 and removal of PMMA using acetone, and (c) after Fig. 9. (a) Rtotal versus VGS for the as-prepared devices, annealed at 300 C/3 h ultra high vacuum (UHV) anneal. Curve fits to spectral 300 C in UHV, annealed at 300 CinUHV,plusinsituannealedat80C components attributed to graphene sp2 C–C bonds (d) and PMMA and measured at room temperature, compared to the same device residue (e)–(i) are shown. (Reprinted with permission, measured at 77 K after 300 C UHV anneal followed by an 80 Cinsitu Ó2010 American Institute of Physics [18].) anneal. (b) Mobility as a function of the different graphene and gFET treatments. (Adapted from [15].)

top of the etchant/water solution using a carrier and then placed onto the desired substrate after drying [45], [131]. by the transfer process. Further systematic studies have Yet another similar dry process is the use of a roll-to-roll also been performed at other stages of the transfer process, process, as described by Bae et al. [12], for very large areas. including the effect of water exposure and in situ annealing Recently, there have also been reports on the transfer of to remove physisorbed species prior to electrical measure- graphene by an electrochemical process for both Cu [20] ments [15]. Mobility measurements on CVD graphene substrates and Pt substrates [21], as shown in Fig. 7(b). comparable to exfoliated graphene on SiO2/Si have been The clear advantage of this process is that the substrate can obtained by controlling these processes, and through the be reused many times, and perhaps it may simplify the minimization of extrinsic impurities or defects. handling of the graphene with the transfer polymer from CVD graphene has also been transferred onto alterna- the solution. This type of process could have significant tive dielectrics such as hBN and ideal substrate for advantages since it minimizes metal waste, a potential graphene since they are nearly lattice matched to each environmental problem; further the graphene–polymer other and are both layered materials. The use of exfoliated stack can be transferred ‘‘dry’’ to the desired substrate. hBN as a substrate for exfoliated graphene has resulted in There are advantages and disadvantages to any of the superior device performance due to several factors, current transfer processes, and it is important to optimize including chemical inertness and flatness [134], [135]. As each one, with particular attention to surface cleaning so for large-area studies, work on CVD hBN has recently been as to render the graphene surface as close to the as-grown reported [136]. Single-layer hBN and multilayer hBN have surface as possible. been grown; however, at this time, the electrical The fabrication of back-gated graphene transistors performance of the CVD grown hBN is still inferior to (Fig. 9) enables the study of any correlated conductivity exfoliated hBN from bulk grown crystals [137]. Table 2 (typically measured under a modest vacuum) and the shows a summary of the most common transfer process extracted mobility behavior. It is seen that the reduction of used. There is still much work to be performed in such residues impacts the mobility substantially, pointing optimizing each of the processes, and process selection to the need for careful control of contaminants introduced will depend to the particular application.

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Table 2 Graphene Transfer Process Comparison

B. Dielectrics on Graphene properties of graphene transferred to SiO2/Si wafer One of the basic properties of graphite, and thus substrate [4]. The application of a ‘‘top-gate’’ dielectric graphene, is that the surface is inert to surface oxidation on such structures enables the study of FET saturation and other reactions at typical process temperatures (less characteristics for high-performance analog applications than about 500 C) in comparison to other FET materials, such as radio-frequency (RF) circuits [138]. A review of the such as Si, Ge, and III–V semiconductors. Although recent developments in graphene transistor designs and graphene is quite resistive to oxidation, at the current their potential utility has been recently published [139]. typical device processing temperatures, there are some A number of strategies have been employed to enable materials that readily react with the graphene surface the deposition of dielectrics on graphene, including metal under certain chemical conditions. The resultant disrup- evaporation and ALD. The challenges of nucleating thin tion of the sp2 bonding due to such reactions results in dielectric films on the surface of graphene have been defect sites, which impact transport properties. However, recognized for some time, particularly in view of prior the oxidation behavior also makes integration of graphene work on CNT surfaces [140]. in a conventional device flow challenging. This section For high-k dielectrics such as HfO2 or ZrO2,ALD summarizes the issues and progress on dielectric integra- methods were employed on CNT transistor structures so tion for graphene FETs. that the CNT channel was essentially encased within the Dielectrics in contact with graphene are required to high-k layer [141]. As the ALD process generally requires enable field-effect control of electron and hole transport reaction with the available surface bonds for film through the graphene layer by means of an electrically nucleation and subsequent growth [142], it was later isolated external gate. Typical in many of the earlier shown that defects in the nanotubes can result in such graphene-FET (gFET) devices utilizing exfoliated gra- nucleation sites [140]. Alternative methods for nucleation phene, a dielectric such as SiO2 was employed to serve as a sites entailed the concepts of functionalizing the CNT ‘‘back-gate dielectric’’ in order to probe the transport surface sufficiently to enable subsequent ALD of dielectrics

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[143], based in part on earlier observations of CNT resistivity changes upon exposure to species such as NH3 and NO2 that were apparently physisorbed to the CNT surface [144], [145]. Using a combination of NO2 and trimethyl–aluminum (TMA), a well-known ALD precursor for Al2O3 deposition, Farmer and Gordon [143] demon- strated that a thin, uniform Al2O3 dielectric can be formed on the single-wall CNT surface by ALD. Without such functionalization of clean graphene, nonuniform film deposition occurs largely at defect sites, as seen in Fig. 10 for the HOPG surface, which is thought Fig. 11. (a) Raman spectrum of a pristine single graphene layer to be representative of the graphene surface [146]. It can (bottom) and graphene treated with O3 at 25 C for 20 s. (b) The same as be seen that the ALD process decorates the step edges of (a) except with O3 exposure at 200 C. (Reprinted with permission, the surface, while the relatively inert terraces remain free Ó2010 American Institute of Physics [17].) of detectable deposition under these conditions. The NO2- functionalization strategy was subsequently adapted for top- gate Al2O3 dielectric growth on the exfoliated graphene been reported upon exposure to O2/Ar mixtures as well as to surface for quantum Hall effect measurements of ambipolar ultraviolet light, for example, [150]. transport [147]. Later work on gFETs demonstrated, The O3 process can be optimized for an exfoliated however, that such NO2 functionalization can degrade graphene layer by conducting the O3 pretreatment at room gFET mobility presumably through charge impurity scatter- temperature, followed by an elevated temperature TMA/ ing as well as interface phonons with the Al2O3 [148]. water ALD process, as reported by Lee et al. [17] As seen in Another challenge for adopting NO2 in standard device pro- Fig. 11(a), the Raman spectra of the 25 CO3 exposure for cessing lies in the corrosive properties of the gas in 20 s results in no detectable defect band (‘‘D’’ 1350 cm1), deposition tools where residual water may be present and while the elevated temperature clearly results in etch safety considerations due to the strong reactivity. As a result, damage and thus a detectable ‘‘D’’-band [Fig. 11(b)]. The alternative functionalization methods are being explored. resultant Al2O3 film was then grown with a TMA/water A common point-of-use oxidizer, well established in chemistry at 200 C and incorporated as a top gate on a semiconductor fabrication technology, is ozone, and this has dual-gated gFET device using exfoliated graphene. Electri- been recently explored for surface functionalization of cal characterization shows ambipolar behavior with an 2 graphene [16], [17], [149]. The effect of an O3 pre-treatment extracted mobility [14], [151] as high as 5000 cm /s [17]. to the HOPG surface on Al2O3 ALD is shown in Fig. 10(c). In The mechanism associated with functionalization by this work, the HOPG surface was exposed to O3 at 200 C O3 on clean graphene has been considered using first- resulting in substantial C–O bonding thus rendering the principles computational methods and in situ electrical surface active for subsequent Al2O3 ALD growth with a characterization [152], [153]. It is found that the short time TMA/water chemistry. Of course, the formation of detect- 25 CO3 exposure is predicted to weakly chemisorb on the able C–O bonding implies some disruption of the HOPG surface, resulting in an epoxide species with submonolayer surface, and thus damage to a graphene specimen with this surface coverage. This species then serves as a nucleation process would clearly be anticipated. Such elevated site for subsequent ALD dielectric growth. Additionally, temperature etch damage (and chemical doping) has also the effect of extrinsic contamination with the O3 process is also a consideration for film nucleation [154]. Organic species have also been shown to facilitate nucleation for subsequent ALD dielectric film growth, such as perylene tetracarboxylic acid (PTCA) [155] or perylene- 3,4,9,10-tetracarboxylic dianhydride (PTCDA) [156], but transport measurements of gFETs using these organic layers have not yet been reported. Polymer-based nucleation layers have also been employed and include photoresist materials such as hydrogen silsesquioxane (HSQ) [157] as well as a planarization polymer that performs as a low-k dielectric buffer layer [158], [159]. In the latter case, an extracted mobility up to 7700 cm2/s was reported for top-gated gFETs Fig. 10. Atomic force microscope images of the HOPG surface after with an HfO2 layer deposited on the buffer layer [159]. The (a) exfoliation and (b) exposure to an ALD process of TMA and water at 250 C, and (c) after exposure to an ALD process and ozone at use of such ‘‘seed’’ layers for functionalization and subse- 200 C. (Reprinted with permission, Ó2008 American Institute of quent high-k dielectric deposition has also been proposed to Physics [16].) decouple the surface phonon interaction associated with

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such oxides and the graphene interface, potentially enhanc- There are limited reports on the effect of the deposited ing the resultant mobility. dielectrics on the Raman signature. The limited data show Given the ability of organic species to result in that there are no significant deleterious effects as established nucleation and growth of ALD dielectric films by ALD, by the absence of the Raman D-band for processes that yield one may also ponder the effects of spurious surface good electrical data [17], [171]. contamination from, for example, atmospheric exposure. Scaling of deposited oxides has been extensively Such contamination is well documented in the Si studied with some nucleation–functionalization ap- integrated circuit fabrication community, and contains proaches better than others as described above, but scaling organic species as well as physisorbed species such as downtomonolayerlevelswithoutpinholesandlowgate water [160]. Estimates of the formation of a monolayer on leakage has been difficult to achieve. The introduction of a typically reactive surface have been less than 30 min hBN [134] and transition metal dichalcogenides (TMD) [161]. Enhanced surface contamination from B during [172] as potential dielectrics has changed the landscape of exposure of a surface under clean-room conditions has also dielectric scaling approaches and is now attracting a lot of been reported [162]. The concentration of such species on attention [173], [174]. Graphene, exfoliated and CVD on freshly exfoliated graphene may be anticipated to be Cu, transfer to hBN flakes has yielded excellent carrier somewhat less than that on active surfaces such as the mobilities as a result of lower substrate induced disorder. native oxides of Si or III–V compounds, but their effect on Deposition and growth of these materials is now being nucleation in an ALD process cannot be ruled out. extensively investigated because of the promising electri- Residues from processing also surely play a role in this cal results using exfoliated films. However, the deposition context. The impact of such contamination on ALD high-k of the same materials on metal substrates and on graphene dielectric growth has been recently reported [149]. at the monolayer level has not yielded the same transport An alternative method to ALD of gate dielectrics on properties, to our knowledge, yet. graphene includes the physical vapor deposition (PVD) of While ALD, perhaps in this case atomic layer epitaxy metals and metal oxides. Early work on high-k gate (ALE), can still be a desired approach for the growth of dielectric deposition on Si employed this concept [163]. these ‘‘new’’ 2-D materials, there are other techniques such Examples include sputtered Zr [164] as well as evaporated as molecular beam epitaxy that could be equivalently LaandAl[165].andsubsequentoxidationtoformthin attractive. The advantage of processes like MBE is that one (2–5 nm) ZrO2,La2O3,andAl2O3, respectively. In the could avoid the use of precursors that tend to introduce context of graphene, Kim et al. [14] utilized this approach unwanted hydrocarbons and perhaps metallic impurities to produce a ‘‘seed layer’’ for subsequent Al2O3 ALD because of the difficulty in procuring very high purity growth. A 1–2-nm Al metal film was deposited by e-beam precursors, and thus provide purer films. At this time, evaporation on exfoliated graphene, followed by exposure there are no reported data on the effect of specific to the clean-room ambient resulting in extensive oxidation impurities in gate dielectrics on device performance. of the thin Al layer [166]. This surface was then submitted to a water/TMA ALD process to produce a 15-nm Al2O3 C. Graphene-Dielectric Interface Characterization dielectric film incorporated into a top-gated structure. A The characterization of the graphene-dielectric inter- dielectric constant of k ¼ 6:0 was reported for the face is also a topic of intense interest. An important resultant Ni/Al2O3/AlOx/graphene gate stack, and an method in this work is X-ray photoelectron spectroscopy extracted mobility as high as 8600 cm2/s was reported. [175], which enables the detailed understanding of the This work was recently extended by comparing Ti and Al as interfacial bonding present. Particularly when coupled nucleation layers. The data indicate that the Ti is a more with in situ treatments of the graphene surface, one can effective and uniform metal as an adhesion layer yielding obtain a fundamental understanding of reaction pathways an improved capacitance scaling for the Al2O3 top-gate during the dielectric growth process. Another important dielectric on exfoliated graphene [167]. technique is scanning tunneling microscopy/spectroscopy. Lemme et al. [168], [169] studied the use of an electron- An example of in situ analysis of 1 nm of Al deposited beam evaporated SiO2 layer (20 nm) as a gate dielectric on an on HOPG is shown in Fig. 12 [7]. In this work, the effect of exfoliated graphene gFET and observed that the mobility is annealing of the exfoliated HOPG sample, prior to Al reduced from 4800 cm2/Vs for electrons and holes to metal deposition was conducted, to remove physorbed 700 and 500 cm2/Vs, respectively, after deposition of the species on the surface, such as hydroxyls from (brief) top-gate stack. An interaction of the -orbitals of the under- atmospheric exposure. It is seen in Fig. 12(a) that the post- lying graphene with the SiO2 resulting in van der Waals anneal surface reveals a characteristic C1s line shape for bonding [170] was proposed as the source of mobility de- sp2 carbon, and that the Al2p spectra is consistent with gradation for this gFET. There are limited reports utilizing unoxidized Al on the clean HOPG surface. Upon exposure such PVD methods to seed ALD on CVD graphene, and to O2 at 200 C, the aluminum is not completely oxidized, mobilities greater than 4000 cm2/Vs have been extracted as seen by the small remnant Al0 metal feature at 72.6 eV. from electrical measurements of Al2O3 top-gated films [11]. In contrast, if the exfoliated HOPG surface is not annealed

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Fig. 12. O1s, C1s, and Al2p spectra for graphite sample with predeposition anneal at 500 C to remove physisorbed interfacial hydroxyls (a) Al as-deposited and (b) Al oxidized in 1000 mbar O2 at 200 C for 10 min. Sample without predeposition anneal (c) Al as-deposited and (d) oxidized under the same conditions as (b). (Reprinted with permission, Ó 2009 American Institute of Physics [7].)

prior to deposition, the surface has remnant oxygen-related physisorbed species (likely hydroxyls), and the deposited Al reacts with these species to consume them forming AlOx at the interface [Fig. 12(c)]. It is clear that subsequent Fig. 13. 1-nm Hf deposited on (a) exfoliated graphite with oxidation then results in complete oxidation of the deposition chamber walls at 25 CandP ¼ 1 108 mbar, (b) annealed deposited Al. In contrast to the behavior of Al, a 1-nm Hf (500 C/30 min) graphite with chamber walls cooled by liquid N2 10 and P ¼ 4 10 mbar, (c) Hf oxidized in 1000 mbar O2 at 25 C, layer deposited at room temperature can result in Hf–C 6 (d) HfO2 deposited by reactive e-beam deposition with 1 10 mbar formation on HOPG, as seen in Fig. 13. Fig. 13(a) shows the partial pressure of O2. A difference spectrum between the two XPS spectra of Hf/graphene after Hf deposition; where a graphite+HfO2 C1s peaks is shown in (e); the peak for sample (c) C1s feature at 282 eV is clearly evident and indicative of is broader than (d) by 0.13 eV. (Reprinted with permission, Hf–C bonding. Perhaps the formation of Hf–C reaction is Ó 2009 American Institute of Physics [19].) aided by the presence of adsorbates on the graphite surface; graphite–titanium reactions have been reported after annealing at high temperatures, and at T G 600 K subsequent oxidation of this film results in the formation of interfacial reactions have been observed. It is therefore HfO2 [Fig. 13(c) and (d)]. A comparison of the topography not surprising that Hf also reacts with graphite at room of these metal–oxide films using ex situ AFM (not shown) temperature. In the case of Al, Al4C3 can also be formed, reveals that the AlOx is clustered while the HfOx is but it readily reacts with water and is thus unstable [176]. In relatively smooth, presumably due to a lower surface thepresenceofoxygenaswasthecasefortheTi,Hf,andAl diffusion rate of Hf relative to Al, and is consistent with the interfacial layers reported by Fallahazad et al. [167], [177] interfacial chemical behavior observed. Taken together, and Kim et al. [178], the graphene seems to be very stable these results point to the importance of controlling the against carburization. Such bonding would be anticipated interfacial reactions through careful control of the depo- to be catastrophic for a monolayer graphene sheet. A sition tool conditions, and thus substantial optimization substantialamountofoxidizedHfisalsonotedonthis can be achieved for device development. In situ studies of surface from the companion O1s and Hf4f spectra. the HfO2/graphene (derived from SiC) have also been However, if one performs an anneal prior to deposition recently reported [179]. and utilizes a liquid N2 cooled shroud in the e-beam As noted previously, improvements in the capacitance deposition process, thereby improving the vacuum during scaling by engineering the interface are necessary. deposition through the cryo-adsorption of residual gas Fallahazad et al. [167]usedTiasanucleationlayerto species such as hydroxyls, carbide formation is suppressed improve the uniformity of the top dielectric as well as an and the Hf metal getters the remaining oxygen to form increase in the dielectric constant. The increase in HfOx on the HOPG surface, as shown in Fig. 13(b). Again, dielectric constant of the Al2O3/TiO2 stack was associated

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with a partial crystallinity of the Al2O3. It is interesting to contact resistance of the following metals on graphene/ note that no interdiffusion of the Al and Ti took place as SiC: Ti/Au, Cr/Au, Ni/Au, Pt/Au, Cu/Au, and Pd/Au after perhaps expected given the low processing temperature. It various oxygen plasma treatments and found that while the was also noted that the roughness of the oxidized Ti layer graphene quality degraded according to Raman measure- (0.24nm)isabouthalfofthatfortheoxidizedAllayer, ments, i.e., the D-band intensity increased significantly, the consistent with a reduced surface diffusion rate for Ti specific contact resistance decreased to about 107 W cm2. relative to Al. The extracted dielectric constant of the A summary of the process conditions and the effect on the Al2O3/TiO2 stack is larger than that for the Al2O3-only contactresistanceisshowninFig.14.Thisisamajor stack, and that the extracted mobility is also impacted by advancement, but even though there was a large work the higher dielectric capacitance density obtained through function difference between the various metals, there was the incorporation of Ti-based nucleation layer. The falloff no correlation to the contact resistance. The reasons for the in the mobility with increasing (Al2O3) gate stack thickness high contact resistance vary and the lack of correlation to was attributed to Coulomb scattering from charged point the specific metal may be associated with the lack of precise defects (e.g., oxygen vacancies) in the dielectric [167]. understanding of the graphene–metal interface chemistry, Recent studies have also examined the placement of Al2O3 an area still to be carefully investigated. nanoribbons on exfoliated graphene, where top-gate mobi- Certainly, graphene on SiC maybe the best source of lities as high as 23 600 cm2/Vs were reported for the thin- ‘‘clean’’ graphene since exposure to hydrocarbons and other nest top dielectric, 38 nm and a residual carrier concentration at the Dirac point of about 4.1 1011 cm2 [180]. Recently, in situ electrical measurements of ALD Al2O3 deposited on exfoliated graphene utilizing the ozone functionalization methods described previously indicate a back-gated mobility as high as 19 000 cm2/Vshavealso been reported [153]. Finally, extensions to deposited low-k dielectrics on exfoliated graphene have been reported for parylene-C, a dielectric normally employed for organic thin-film transistor development [181]. Further work using such dielectric deposition methods applied to large-area CVD graphene is anticipated in the near term.

V. METAL CONTACTS Successful device fabrication and operation requires low contact resistance for the source and drain regions since this can limit device performance. There has been a significant amount of effort in decreasing the metal contact resistance in silicon devices. The contact resis- tanceofmetalstographeneortoCNTsisstillveryhigh compared to state-of-the-art contacts in silicon devices. There have been some advancements in the contact resistance of metals on graphene, but it is still about an order of magnitude too high. There are several issues at this time, metal selection, graphene surface cleaning, and metal–graphene bonding type and understanding. Metal selection involves ensuring that the metal does not fully carburize thus destroying the graphene or dissolving the graphene, and must have the desired work function. With the exception of Cu, Ir, Au, and Ag, most metals either react or can significantly dissolve the carbon under appropriate thermodynamic and chemical conditions. A few studies have been carried out to extract the contact resistance of metals on graphene [10], [182]–[184]. The contact resistance of metals on graphene was measured by the traditional transfer length Fig. 14. Process showing that surface preparation has a significant method (TLM) for a several metals and the graphene effect on the specific contact resistance of Ti to graphenen. (Reprinted carefully characterized. Robinson et al. [10] measured the with permission, Ó 2011 American Institute of Physics [10].)

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chemicals used in the processing and transfer of CVD ment of many different applications, from displays to RF graphene is much lower. However, the multilayer nature of devices. In addition, the community is learning how to graphene on SiC may introduce aspects in the understanding grow relatively large single crystals of graphene on metal and controlling the contact resistance in single-layer surfaces that will hopefully help identify the material graphene that have not been comprehended so far. Recently, requirements for the most demanding devices. Xia et al. [185] also reported on the reduction of the contact Because of the physical size demands and manufactur- resistance of Pd to graphene down to about 170 W-cm, but ability, it is likely that CVD processes, in general, will win this is still too high for most device applications. Therefore, it out over other graphene production means for HVM of is important to continue to develop a basic understanding of graphene-based high-performance devices. Growth of the metal–graphene interface chemistry. graphene on SiC can provide very high-quality material In addition to the basic understanding of the interface but many applications require large substrate areas that chemistry, it is also important to select the appropriate this technique cannot currently provide. CVD of graphene metal deposition technique in addition to graphene surface on dielectrics would be a preferred process; however, cleaning and preparation. Nagashio et al. [186] have there are still many challenges that face this approach, and recently reported that sputtered Ti led to extremely high more work needs to be done. The contact resistance also resistivity in comparison to evaporated Ti. requires a significant amount of work in understanding metal–graphene interface, and the effect of extrinsic factors of which at this stage of development there are VI. SUMMARY many. Finally, an equivalently challenging problem is the Significant advancements have been made in the growth scaling of gate dielectrics on graphene with a desired and integration of large-area graphene films over the past dielectric constant. While dielectrics have been scaled on eight years or so. Freestanding extremely large graphene Si down to about 1 nm in products and dielectrics of films can be grown using CVD on weakly interacting thicknesses much lower than 1 nm can de deposited or substrates like Cu with transport properties equivalent to grown on Si, the deposition details of dielectrics on graphene exfoliated from natural graphite. Because of the graphene still need more work. The use and development ability to grow very large-area and high-quality graphene of2-DcrystalssuchashBNandTMDcouldhelpaddress films, the CVD growth process is enabling the develop- the need for scaled dielectrics. h

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ABOUT THE AUTHORS Luigi Colombo (Fellow, IEEE) received the B.S. Development Group at TI, where he is responsible for the development of degree in physics from the Iona College, New new materials such as graphene and its integration in new device flows for Rochelle, NY, USA, in 1975 and the Ph.D. degree in beyond complementary metal–oxide–semiconductor (CMOS) device materials science from the University of Rochester, technology as part of the Nanoelectronics Research Initiative. He is also Rochester, NY, USA, in 1980. an Adjunct Professor in the Department of Materials Science and From 1980 to 1981, he was a Postdoctoral Engineering, University of Texas at Dallas. He is the author or coauthor Fellow at the Mechanical and Aerospace Science of more than 140 publications in peer-reviewed journals and proceedings, Department, University of Rochester, Rochester, more than 100 contributed and 60 invited talks at international meetings NY,USA.In1981,hejoinedTexasInstruments(TI) and symposia, has written three chapters in edited books, and holds a Incorporated, Dallas, TX, USA, where he first total of 107 U.S. and international patents. He is on the European worked on infrared detector materials until 1995. Over this period, he Community Graphene Flagship Advisory Board, the AIP Corporate developed a HgCdZnTe liquid phase epitaxy process, which he also put in Associates Advisory Committee, Cambridge University Graphene Centre production in 1991, and it is still in production today. Since then, he has Advisory Board, and the Solid State Electronics Editorial Board. been responsible for the development of high-k capacitor metal– Dr. Colombo is a member of the American Physical Society, the insulator–metal structures for dynamic random access memories, Material Research Society, the American Vacuum Society, and the development of high-k gate/metal gate transistor gate stack using Electrochemical Society. In 2012, he was elected to IEEE Fellow for his Hf-based dielectrics, and low-leakage SiON-based 45-nm transistor gate contributions to infrared detector materials and devices and high-k stack development. He is currently a TI Fellow in the External Research dielectrics in integrated circuits.

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Robert M. Wallace (Fellow, IEEE) received the Rodney S. Ruoff received the Ph.D. degree in Ph.D. degree in physics from the University of chemical physics from the University of Illinois at Pittsburgh, Pittsburgh, PA, USA, in 1982, 1984, Urbana-Champaign,Urbana,IL,USA,in1988. and 1988, respectively. He joined the University of Texas at Austin He was then a Postdoctoral Research Associate (UT-Austin), Austin, TX, USA, as a Cockrell Family in Chemistry with the Pittsburgh Surface Science Regents endowed chair in September 2007. He was Center, Pittsburgh, PA, USA. In 1990, he joined as a a Fulbright Fellow in 1988–1989 at the Max Planck Member of Technical Staff (MTS) with the Texas Institute fuer Stroemungsforschung, Goettingen, Instruments Central Research Laboratories, Dallas, Germany. Prior to joining UT-Austin, he was the TX, USA, where he was elected Senior MTS in 1996. John Evans Professor of Nanoengineering in the In 1997, he was appointed to manage the Advanced Technology Branch Department of Mechanical Engineering at Northwestern University, that focused on advanced device concepts and the associated material Evanston, IL, USA, and Director of NU’s Biologically Inspired Materials integration issues. In May 1999, he joined as Professor of Materials Institute from 2002 to 2007. He has coauthored over 300 peer-reviewed Science and Director of the new Laboratory for Electronic Materials and publications devoted to chemistry, physics, materials science, mechanics, Devices with the University of North Texas, Denton, TX, USA. In 2003, he engineering, and biomedical science; cofounded Graphene Energy, Inc.; joined as Professor of Electrical Engineering and Physics with the and is the founder of Graphene Materials, LLC. and Nanode, Inc. University of Texas at Dallas (UT-Dallas), Richardson, TX, USA. He has Dr. Ruoff is on the editorial board of Composites, Science, and authored or coauthored over 225 publications in peer-reviewed journals Technology; Carbon; Journal of Nanoengineering and Nanosystems;and and proceedings and 70 U.S. and international patents. His research is a Managing Editor and Editorial Board Member of NANO. He is a Fellow interests include materials and integration issues for advanced logic and of the Materials Research Society (MRS), the American Physical Society memory technologies. (APS), and the American Association for the Advancement of Science Dr. Wallace serves on the editorial board of the Journal of Materials (AAAS). He was a Distinguished Chair Visiting Professor at Sungkyukwan Science: Materials in Electronics and Applied Surface Science.Hewas University’s Advanced Institute of NanoTechnology (SAINT) for several named Fellow of the American Vacuum Society (AVS) in 2007 and an IEEE years and has been recently named that again. He is a Fellow of the APS; Fellow in 2009 for his contributions to the field of high-k dielectrics in was a Lee Hsun Lecture Award recipient, 2009, Institute of Metal integrated circuits. He holds the Erik Jonsson Distinguished Chair in the Research, Chinese Academy of Sciences, Shenyang, China; and was listed Erik Jonsson School of Engineering and Computer Science at UT-Dallas. as the 16th most cited materials scientist of among the top 100 most cited He is also a member of the AVS, the Materials Research Society, the for the decade 2000–2010 (http://bucky-central.me.utexas.edu/ American Chemical Society, and the Electrochemical Society. RuoffsPDFs/THE%20Top%20100%20Materials%20Scientists).

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