DOCSLIB.ORG

Prace-3Ip D8.3.4

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Prace-3Ip D8.3.4 SEVENTH FRAMEWORK PROGRAMME Research Infrastructures INFRA-2012-2.3.1 – Third Implementation Phase of the European High Performance Computing (HPC) service PRACE PRACE-3IP PRACE Third Implementation Phase Project Grant Agreement Number: RI-312763 D8.3.4 Technical lessons learnt from the implementation of the joint PCP for PRACE-3IP Final Version: 1.5 Author(s): Stephen Booth, EPCC Date: 10.01.2018 D8.3.4 Technical lessons learnt from the implementation of the joint PCP for PRACE-3IP Project and Deliverable Information Sheet PRACE Project Project Ref. №: RI-312763 Project Title: PRACE Third Implementation Phase Project Project Web Site: http://www.prace-project.eu Deliverable ID: D8.3.4 Deliverable Nature: <Report> Deliverable Level: Contractual Date of Delivery: PU 31 / 12 / 2017 Actual Date of Delivery: 15 / 01 / 2018 EC Project Officer: Leonardo Flores Añover * - The dissemination level are indicated as follows: PU – Public, PP – Restricted to other participants (including the Commission Services), RE – Restricted to a group specified by the consortium (including the Commission Services). CO – Confidential, only for members of the consortium (including the Commission Services). Document Control Sheet Title: Technical lessons learnt from the implementation of the joint Document PCP for PRACE-3IP ID: D8.3.4 Version: 1.5 Status: Final Available at: http://www.prace-project.eu Software Tool: Microsoft Word 2010 File(s): D8.3.4.docx Written by: Stephen Booth, EPCC Authorship Contributors: Fabio Affinito, CINECA Eric Boyer, GENCI Carlo Cavazzoni, CINECA Pekka Manninen, CSC Dirk Pleiter, JUELICH Philippe Segers, GENCI Reviewed by: Stéphane Requena, GENCI Florian Berberich, JUELICH Approved by: MB/TB Document Status Sheet Version Date Status Comments 0.1 19/10/2017 Draft Initial outline 0.2 20/10/2017 Draft 0.3 27/10/2017 Draft PCP section 0.4 10/11/2017 Draft General lessons 0.5 28/11/2017 Draft Technical background 0.6 11/12/2017 Draft E4 sections PRACE-3IP - RI-312763 i 10.01.2018 D8.3.4 Technical lessons learnt from the implementation of the joint PCP for PRACE-3IP 0.7 11/12/2017 Draft ATOS-BULL sections 0.8 12/12/2017 Draft User experiences 0.9 14/12/2017 Draft Formatting 1.0 14/12/2017 Draft User experience section 1.1 16/12/2017 Draft Commits & corrections 1.2 22/12/2017 Draft Editorial updates 1.3 09/01/2017 Pre-Final Updates based on internal review reports 1.4 10/01/2017 Pre-Final Error in Table 19 fixed 1.5 10/01/2018 Last corrections Document Keywords Keywords: PRACE, HPC, Research Infrastructure, Joint Pre Commercial Procurement, Energy Efficiency Disclaimer This deliverable has been prepared by the responsible Work Package of the Project in accordance with the Consortium Agreement and the Grant Agreement n° RI-312763. It solely reflects the opinion of the parties to such agreements on a collective basis in the context of the Project and to the extent foreseen in such agreements. Please note that even though all participants to the Project are members of PRACE AISBL, this deliverable has not been approved by the Council of PRACE AISBL and therefore does not emanate from it nor should it be considered to reflect PRACE AISBL’s individual opinion. Copyright notices 2018 PRACE Consortium Partners. All rights reserved. This document is a project document of the PRACE project. All contents are reserved by default and may not be disclosed to third parties without the written consent of the PRACE partners, except as mandated by the European Commission contract RI-312763 for reviewing and dissemination purposes. All trademarks and other rights on third party products mentioned in this document are acknowledged as own by the respective holders. PRACE-3IP - RI-312763 ii 10.01.2018 D8.3.4 Technical lessons learnt from the implementation of the joint PCP for PRACE-3IP Table of Contents Project and Deliverable Information Sheet ......................................................................................... i Document Control Sheet ........................................................................................................................ i Document Status Sheet .......................................................................................................................... i Document Keywords ............................................................................................................................. ii Table of Contents ................................................................................................................................. iii List of Figures ........................................................................................................................................ v List of Tables .......................................................................................................................................... v References and Applicable Documents .............................................................................................. vi List of Acronyms and Abbreviations ................................................................................................. vii Executive Summary ............................................................................................................................ 12 1 Introduction ........................................................................................................................................13 2 Overview of the PRACE PCP ............................................................................................................13 3 Technical Background .......................................................................................................................14 4 Lessons learned from the Atos-Bull KNL pilot system ............................................................ 17 4.1 Description of the system ...................................................................................................................17 4.1.1 System description ..............................................................................................................................17 4.1.2 Software environment ........................................................................................................................18 4.1.3 Energy efficiency aspects of the design .............................................................................................19 Technology related ....................................................................................................... 19 Infrastructure for Energy monitoring and optimization ............................................... 22 4.2 Suitability for general purpose HPC.................................................................................................28 4.2.1 Ease of code development and porting .............................................................................................28 4.2.2 Energy monitoring/prediction ...........................................................................................................29 4.2.3 System usability .......................................................................................................................... 29 4.3 Impact on energy efficiency ...............................................................................................................29 4.3.1 Final results for HPL..........................................................................................................................30 4.3.2 Final results for NEMO .....................................................................................................................31 4.3.3 Final results for SPECFEM3D ..........................................................................................................32 Small test case .............................................................................................................. 32 Large test case .............................................................................................................. 34 4.3.4 Final results for BQCD ......................................................................................................................34 4.3.5 Final results for Quantum Espresso .................................................................................................35 4.4 Schedule and timing ...........................................................................................................................39 4.5 Impact on Atos-Bull roadmap ...........................................................................................................40 4.6 Summary of lessons learned from the Atos-Bull KNL pilot system ...............................................40 5 Lessons learned from the Maxeler data-flow pilot system ...................................................... 41 5.1 Description of the Maxeler data-flow pilot system ..........................................................................41 5.1.1 System description ..............................................................................................................................41 5.1.2 Software environment ........................................................................................................................43 5.1.3 Energy efficiency aspects of the design .............................................................................................43 5.2 Suitability for general purpose HPC.................................................................................................44
Load more

Recommended publications
  • SEVENTH FRAMEWORK PROGRAMME Research Infrastructures
    SEVENTH FRAMEWORK PROGRAMME Research Infrastructures INFRA-2007-2.2.2.1 - Preparatory phase for 'Computer and Data Treat- ment' research infrastructures in the 2006 ESFRI Roadmap PRACE Partnership for Advanced Computing in Europe Grant Agreement Number: RI-211528 D8.3.2 Final technical report and architecture proposal Final Version: 1.0 Author(s): Ramnath Sai Sagar (BSC), Jesus Labarta (BSC), Aad van der Steen (NCF), Iris Christadler (LRZ), Herbert Huber (LRZ) Date: 25.06.2010 D8.3.2 Final technical report and architecture proposal Project and Deliverable Information Sheet PRACE Project Project Ref. №: RI-211528 Project Title: Final technical report and architecture proposal Project Web Site: http://www.prace-project.eu Deliverable ID: : <D8.3.2> Deliverable Nature: Report Deliverable Level: Contractual Date of Delivery: PU * 30 / 06 / 2010 Actual Date of Delivery: 30 / 06 / 2010 EC Project Officer: Bernhard Fabianek * - The dissemination level are indicated as follows: PU – Public, PP – Restricted to other participants (including the Commission Services), RE – Restricted to a group specified by the consortium (including the Commission Services). CO – Confidential, only for members of the consortium (including the Commission Services). PRACE - RI-211528 i 25.06.2010 D8.3.2 Final technical report and architecture proposal Document Control Sheet Title: : Final technical report and architecture proposal Document ID: D8.3.2 Version: 1.0 Status: Final Available at: http://www.prace-project.eu Software Tool: Microsoft Word 2003 File(s): D8.3.2_addn_v0.3.doc
    [Show full text]
  • Recent Developments in Supercomputing
    John von Neumann Institute for Computing Recent Developments in Supercomputing Th. Lippert published in NIC Symposium 2008, G. M¨unster, D. Wolf, M. Kremer (Editors), John von Neumann Institute for Computing, J¨ulich, NIC Series, Vol. 39, ISBN 978-3-9810843-5-1, pp. 1-8, 2008. c 2008 by John von Neumann Institute for Computing Permission to make digital or hard copies of portions of this work for personal or classroom use is granted provided that the copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise requires prior specific permission by the publisher mentioned above. http://www.fz-juelich.de/nic-series/volume39 Recent Developments in Supercomputing Thomas Lippert J¨ulich Supercomputing Centre, Forschungszentrum J¨ulich 52425 J¨ulich, Germany E-mail: [email protected] Status and recent developments in the field of supercomputing on the European and German level as well as at the Forschungszentrum J¨ulich are presented. Encouraged by the ESFRI committee, the European PRACE Initiative is going to create a world-leading European tier-0 supercomputer infrastructure. In Germany, the BMBF formed the Gauss Centre for Supercom- puting, the largest national association for supercomputing in Europe. The Gauss Centre is the German partner in PRACE. With its new Blue Gene/P system, the J¨ulich supercomputing centre has realized its vision of a dual system complex and is heading for Petaflop/s already in 2009. In the framework of the JuRoPA-Project, in cooperation with German and European industrial partners, the JSC will build a next generation general purpose system with very good price-performance ratio and energy efficiency.
    [Show full text]
  • The QPACE Supercomputer Applications of Random Matrix Theory in Two-Colour Quantum Chromodynamics Dissertation
    The QPACE Supercomputer Applications of Random Matrix Theory in Two-Colour Quantum Chromodynamics Dissertation zur Erlangung des Doktorgrades der Naturwissenschaften (Dr. rer. nat.) der Fakult¨atf¨urPhysik der Universit¨atRegensburg vorgelegt von Nils Meyer aus Kempten im Allg¨au Mai 2013 Die Arbeit wurde angeleitet von: Prof. Dr. T. Wettig Das Promotionsgesuch wurde eingereicht am: 07.05.2013 Datum des Promotionskolloquiums: 14.06.2016 Pr¨ufungsausschuss: Vorsitzender: Prof. Dr. C. Strunk Erstgutachter: Prof. Dr. T. Wettig Zweitgutachter: Prof. Dr. G. Bali weiterer Pr¨ufer: Prof. Dr. F. Evers F¨urDenise. Contents List of Figures v List of Tables vii List of Acronyms ix Outline xiii I The QPACE Supercomputer 1 1 Introduction 3 1.1 Supercomputers . .3 1.2 Contributions to QPACE . .5 2 Design Overview 7 2.1 Architecture . .7 2.2 Node-card . .9 2.3 Cooling . 10 2.4 Communication networks . 10 2.4.1 Torus network . 10 2.4.1.1 Characteristics . 10 2.4.1.2 Communication concept . 11 2.4.1.3 Partitioning . 12 2.4.2 Ethernet network . 13 2.4.3 Global signals network . 13 2.5 System setup . 14 2.5.1 Front-end system . 14 2.5.2 Ethernet networks . 14 2.6 Other system components . 15 2.6.1 Root-card . 15 2.6.2 Superroot-card . 17 i ii CONTENTS 3 The IBM Cell Broadband Engine 19 3.1 The Cell Broadband Engine and the supercomputer league . 19 3.2 PowerXCell 8i overview . 19 3.3 Lattice QCD on the Cell BE . 20 3.3.1 Performance model .
    [Show full text]
  • Measuring Power Consumption on IBM Blue Gene/P
    View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Springer - Publisher Connector Comput Sci Res Dev DOI 10.1007/s00450-011-0192-y SPECIAL ISSUE PAPER Measuring power consumption on IBM Blue Gene/P Michael Hennecke · Wolfgang Frings · Willi Homberg · Anke Zitz · Michael Knobloch · Hans Böttiger © The Author(s) 2011. This article is published with open access at Springerlink.com Abstract Energy efficiency is a key design principle of the Top10 supercomputers on the November 2010 Top500 list IBM Blue Gene series of supercomputers, and Blue Gene [1] alone (which coincidentally are also the 10 systems with systems have consistently gained top GFlops/Watt rankings an Rpeak of at least one PFlops) are consuming a total power on the Green500 list. The Blue Gene hardware and man- of 33.4 MW [2]. These levels of power consumption are al- agement software provide built-in features to monitor power ready a concern for today’s Petascale supercomputers (with consumption at all levels of the machine’s power distribu- operational expenses becoming comparable to the capital tion network. This paper presents the Blue Gene/P power expenses for procuring the machine), and addressing the measurement infrastructure and discusses the operational energy challenge clearly is one of the key issues when ap- aspects of using this infrastructure on Petascale machines. proaching Exascale. We also describe the integration of Blue Gene power moni- While the Flops/Watt metric is useful, its emphasis on toring capabilities into system-level tools like LLview, and LINPACK performance and thus computational load ne- highlight some results of analyzing the production workload glects the fact that the energy costs of memory references at Research Center Jülich (FZJ).
    [Show full text]
  • QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine
    N OVEL A RCHITECTURES QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor’s multicore structure and from implementing the network processor on a field- programmable gate array. 1521-9615/08/$25.00 © 2008 IEEE uantum chromodynamics (QCD) is COPUBLISHED BY THE IEEE CS AND THE AIP a well-established theoretical frame- Gottfried Goldrian, Thomas Huth, Benjamin Krill, work to describe the properties and Jack Lauritsen, and Heiko Schick Q interactions of quarks and gluons, which are the building blocks of protons, neutrons, IBM Research and Development Lab, Böblingen, Germany and other particles. In some physically interesting Ibrahim Ouda dynamical regions, researchers can study QCD IBM Systems and Technology Group, Rochester, Minnesota perturbatively—that is, they can work out physi- Simon Heybrock, Dieter Hierl, Thilo Maurer, Nils Meyer, cal observables as a systematic expansion in the Andreas Schäfer, Stefan Solbrig, Thomas Streuer, strong coupling constant. In other (often more and Tilo Wettig interesting) regions, such an expansion isn’t pos- sible, so researchers must find other approaches. University of Regensburg, Germany The most systematic and widely used nonper- Dirk Pleiter, Karl-Heinz Sulanke, and Frank Winter turbative approach is lattice QCD (LQCD), a Deutsches Elektronen Synchrotron, Zeuthen, Germany discretized, computer-friendly version of the Hubert Simma theory Kenneth Wilson proposed more than 1 University of Milano-Bicocca, Italy 30 years ago.
    [Show full text]
  • Download Presentation
    Computer architecture in the past and next quarter century CNNA 2010 Berkeley, Feb 3, 2010 H. Peter Hofstee Cell/B.E. Chief Scientist IBM Systems and Technology Group CMOS Microprocessor Trends, The First ~25 Years ( Good old days ) Log(Performance) Single Thread More active transistors, higher frequency 2005 Page 2 SPECINT 10000 3X From Hennessy and Patterson, Computer Architecture: A ??%/year 1000 Quantitative Approach , 4th edition, 2006 52%/year 100 Performance (vs. VAX-11/780) VAX-11/780) (vs. Performance 10 25%/year 1 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 • VAX : 25%/year 1978 to 1986 RISC + x86: 52%/year 1986 to 2002 Page 3 CMOS Devices hit a scaling wall 1000 Air Cooling limit ) 100 2 Active 10 Power Passive Power 1 0.1 Power Density (W/cm Power Density 0.01 1994 2004 0.001 1 0.1 0.01 Gate Length (microns) Isaac e.a. IBM Page 4 Microprocessor Trends More active transistors, higher frequency Log(Performance) Single Thread More active transistors, higher frequency 2005 Page 5 Microprocessor Trends Multi-Core More active transistors, higher frequency Log(Performance) Single Thread More active transistors, higher frequency 2005 2015(?) Page 6 Multicore Power Server Processors Power 4 Power 5 Power 7 2001 2004 2009 Introduces Dual core Dual Core – 4 threads 8 cores – 32 threads Page 7 Why are (shared memory) CMPs dominant? A new system delivers nearly twice the throughput performance of the previous one without application-level changes. Applications do not degrade in performance when ported (to a next-generation processor).
    [Show full text]
  • HPC Hardware & Software Development At
    Heiko J Schick – IBM Deutschland R&D GmbH August 2010 HPC HW & SW Development at IBM Research & Development Lab © 2010 IBM Corporation Agenda . Section 1: Hardware and Software Development Process . Section 2: Hardware and Firmware Development . Section 3: Operating System and Device Driver Development . Section 4: Performance Tuning . Section 5: Cluster Management . Section 6: Project Examples 2 © 2010 IBM Corporation IBM Deutschland Research & Development GmbH Overview Focus Areas . One of IBM‘s largest Research & Text. Skills: Hardware, Firmware, Development sites Operating Systems, Software . Founded: and Services 1953 . More than 60 Hard- . Employees: and Software projects Berlin ~2.000 . Technology consulting . Headquarter: . Cooperation with Mainz Böblingen research institutes Walldorf and universities Böblingen . Managing Director: München Dirk Wittkopp 3 3 © 2010 IBM Corporation Research Zürich Watson Almaden China Tokio Haifa Austin India 4 © Copyright IBM Corporation 2009 Research Hardware Development Greenock Rochester Boulder Böblingen Toronto Fujisawa Endicott Burlington La Gaude San Jose East Fishkill Poughkeepsie Yasu Tucson Haifa Yamato Austin Raleigh Bangalore 5 © Copyright IBM Corporation 2009 Research Hardware Development Software Development Krakau Moskau Vancouver Dublin Hursley Minsk Rochester Böblingen Beaverton Toronto Paris Endicott Santa Foster Rom City Lenexa Littleton Beijing Teresa Poughkeepsie Haifa Yamato Austin Raleigh Costa Kairo Schanghai Mesa Taipei Pune Bangalore São Paolo Golden Coast Perth Sydney
    [Show full text]
  • Presentación De Powerpoint
    Towards Exaflop Supercomputers Prof. Mateo Valero Director of BSC, Barcelona National U. of Defense Technology (NUDT) Tianhe-1A • Hybrid architecture: • Main node: • Two Intel Xeon X5670 2.93 GHz 6-core Westmere, 12 MB cache • One Nvidia Tesla M2050 448-ALU (16 SIMD units) 1150 MHz Fermi GPU: • 32 GB memory per node • 2048 Galaxy "FT-1000" 1 GHz 8-core processors • Number of nodes and cores: • 7168 main nodes * (2 sockets * 6 CPU cores + 14 SIMD units) = 186368 cores (not including 16384 Galaxy cores) • Peak performance (DP): • 7168 nodes * (11.72 GFLOPS per core * 6 CPU cores * 2 sockets + 36.8 GFLOPS per SIMD unit * 14 SIMD units per GPU) = 4701.61 TFLOPS • Linpack performance: 2.507 PF 53% efficiency • Power consumption 4.04 MWatt Source http://blog.zorinaq.com/?e=36 Cartagena, Colombia, May 18-20 Top10 Rank Site Computer Procs Rmax Rpeak 1 Tianjin, China XeonX5670+NVIDIA 186368 2566000 4701000 2 Oak Ridge Nat. Lab. Cray XT5,6 cores 224162 1759000 2331000 3 Shenzhen, China XeonX5670+NVIDIA 120640 1271000 2984300 4 GSIC Center, Tokyo XeonX5670+NVIDIA 73278 1192000 2287630 5 DOE/SC/LBNL/NERSC Cray XE6 12 cores 153408 1054000 1288630 Commissariat a l'Energie Bull bullx super-node 6 138368 1050000 1254550 Atomique (CEA) S6010/S6030 QS22/LS21 Cluster, 7 DOE/NNSA/LANL PowerXCell 8i / Opteron 122400 1042000 1375780 Infiniband National Institute for 8 Computational Cray XT5-HE 6 cores 98928 831700 1028850 Sciences/University of Tennessee 9 Forschungszentrum Juelich (FZJ) Blue Gene/P Solution 294912 825500 825500 10 DOE/NNSA/LANL/SNL Cray XE6 8-core 107152 816600 1028660 Cartagena, Colombia, May 18-20 Looking at the Gordon Bell Prize • 1 GFlop/s; 1988; Cray Y-MP; 8 Processors • Static finite element analysis • 1 TFlop/s; 1998; Cray T3E; 1024 Processors • Modeling of metallic magnet atoms, using a variation of the locally self-consistent multiple scattering method.
    [Show full text]
  • Multigrid Algorithms on QPACE
    FRIEDRICH-ALEXANDER-UNIVERSITAT¨ ERLANGEN-NURNBERG¨ INSTITUT FUR¨ INFORMATIK (MATHEMATISCHE MASCHINEN UND DATENVERARBEITUNG) Lehrstuhl f¨urInformatik 10 (Systemsimulation) Multigrid algorithms on QPACE Daniel Brinkers Diploma Thesis Multigrid algorithms on QPACE Daniel Brinkers Diploma Thesis Aufgabensteller: Prof. Dr. U. R¨ude Betreuer: Dipl.-Inf. M. St¨urmer Bearbeitungszeitraum: 01.09.2009 { 01.03.2010 Erkl¨arung: Ich versichere, daß ich die Arbeit ohne fremde Hilfe und ohne Benutzung anderer als der angege- benen Quellen angefertigt habe und daß die Arbeit in gleicher oder ¨ahnlicher Form noch keiner anderen Prufungsbeh¨ ¨orde vorgelegen hat und von dieser als Teil einer Prufungsleistung¨ angenom- men wurde. Alle Ausfuhrungen,¨ die w¨ortlich oder sinngem¨aß ubernommen¨ wurden, sind als solche gekennzeichnet. Erlangen, den 1. M¨arz 2010 . Abstract QPACE is a cluster computer developed for lattice QCD calculations. The computing nodes consists of IBM PowerXCell 8i processors. The interconnect is a custom three dimensional torus network. The application dependent design goals were a latency smaller then 1µs and a band- width about 1 GiB/s. The cluster is very energy efficient and reached the 1st place on the Green500 list of November 2009. With this work a multigrid solver should be implemented and investigated on this hardware. It was concluded, that it is possible to use this hardware for multigrid calculations. Another important result is the conclusion that the analysis of commu- nication patterns is important to understand the performance of programs on this hardware. Methods and parameters for this analysis are introduced. Zusammenfassung QPACE ist ein Cluster, der fur¨ Gitter QCD Berechnungen entwickelt wurde. Die Cluster- knoten bestehen aus IBM PowerXCell 8i Prozessoren.
    [Show full text]
  • QPACE 2 and Domain Decomposition on the Intel Xeon Phi∗
    QPACE 2 and Domain Decomposition on the Intel Xeon Phi∗ Paul Artsa, Jacques Blochb, Peter Georgb, Benjamin Glässleb, Simon Heybrockb, Yu Komatsubarac, Robert Lohmayerb, Simon Magesb, Bernhard Mendlb, Nils Meyerb, Alessio Parcianelloa, Dirk Pleiterb;d, Florian Rapplb, Mauro Rossia, Stefan Solbrigb, Giampietro Tecchiollia, Tilo Wettig†b, Gianpaolo Zaniera aEurotech HPC, Via F. Solari 3/A, 33020 Amaro, Italy bDepartment of Physics, University of Regensburg, 93040 Regensburg, Germany cAdvanet Inc., 616-4 Tanaka, Kita-ku, Okayama 700-0951, Japan dJSC, Jülich Research Centre, 52425 Jülich, Germany E-mail: [email protected] We give an overview of QPACE 2, which is a custom-designed supercomputer based on Intel Xeon Phi processors, developed in a collaboration of Regensburg University and Eurotech. We give some general recommendations for how to write high-performance code for the Xeon Phi and then discuss our implementation of a domain-decomposition-based solver and present a number of benchmarks. arXiv:1502.04025v1 [cs.DC] 13 Feb 2015 The 32nd International Symposium on Lattice Field Theory, 23-28 June, 2014 Columbia University, New York, NY ∗Work supported by DFG in the framework of SFB/TRR-55. †Speaker. c Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike Licence. http://pos.sissa.it/ QPACE 2 and Domain Decomposition on the Intel Xeon Phi Tilo Wettig 1. Introduction After the invention of lattice QCD in 1974 [1] it quickly became clear that (i) it had great potential to yield physically relevant nonperturbative results and (ii) enormous computational re- sources would be required to obtain them.
    [Show full text]
  • Than Powerful: German Research Computer QPACE Is the Most Energy Efficient in the World 20 November 2009
    More than powerful: German research computer QPACE is the most energy efficient in the world 20 November 2009 At the 2009 Supercomputing Conference in For a long time, in the world of supercomputers Portland, Oregon, the high-performance computer performance was solely associated with speed. QPACE (QCD Parallel Computing on the Cell) was This notion led to the development of computers recognized today as the most energy-efficient that use enormous amounts of energy. Energy supercomputer in the world. efficiency usually was ignored. Not until the advent of increased discussions about the scarcity of QPACE is at the head of the Green500 list, which natural resources and energy over the past years provides a global ranking of energy-efficient did this aspect gain in importance for the supercomputers. QPACE was developed by an development of supercomputers. Along with the academic consortium of universities and research Top500 list of the fastest computers, the Green500 centers as well as the German IBM research and list of supercomputers with the least energy use development center in Böblingen within the emerged as criterion for the rating and ranking of framework of a state-sponsored research computer performance. Both lists are updated and association. Within the consortium, the presented twice a year at the international development effort was led by the University of Supercomputing conference. The QPACE Regensburg, while the research centers DESY and supercomputer comes in at place 110 on the Jülich also assumed central responsibilities. TOP500 list and has a computing power of 55 Additional members included the University of teraflop/s. Wuppertal, the University of Ferrara (Italy), the University of Milan-Bicocca (Italy) as well as the The heart of QPACE is the IBM PowerXCell 8i companies Eurotech, Knürr, Zollner and Xilinx.
    [Show full text]
  • Deep Learning ▪ Healthcare: Diagnostics and IT Systems Break Tasks Into Artificial Neural Treatment Networks ▪ Supply Chain and Logistics
    Cognitive, AI and Analytics examples, trends and directions Ulrich Walter Cognitive Systems HPC & Cloud Sales Leader Hanover, 22.12.2017 The world is changing Past Present Processes Future Collecting, Islands Intelligent, Assistants Social Media explosion User genereated Social feedback Collaborative loop buying Mobile Batch oriented revolution Location based Palm sized Digital money And wearable Power of analytics Entire Predictive Integration Manual Processes Analytics Cognitive AI SaaS Cloud enablement IT Centralized System Autonomous Boundary less Living in a smart, intelligent and cognitive world Smart Facilities Intelligent traffic systems Smart Farming Smart Grid Autonomous Driving Intelligent Light System Smart Health Smart Watch Emotionally Intelligent Robots Smart GPS Intelligent Image Recogniton Smart TV Intelligent Response System Smart Phone Intelligent vehicle Smart Refrigerator Intelligent POS and payments Smart Ordnance Smart Camera Intelligent Assistants Smart Surface Intelligent Social Media Analytics Cognitive Fraud Detection Intelligent Museum Cognitive Robotics IBM Systems Two principles of conciousness Cogito, Ergo Sum Γνῶθι σεαυτόν Rene Descartes, 1637 Chilon of Sparta, 555 B.C Overall Artificial Intelligence (AI) Space New class of applications Cognitive / Machine Learing & Training ML/DL ▪ Pattern matching Human Intelligence Exhibited by Machines ▪ Image ▪ Real-time decision support ▪ Complex workflows Machine Learning ▪ Data Lakes New Data “Human Trained” using large amounts of data & ability to learn how to perform
    [Show full text]