A Commodore PET-2001 clone

Built in 2018 using current-production parts.

Glen Kleinschmidt www.glensstuff.com November 2018 Introduction

This project had its genesis in 2017 when, reading on-line about old computers, I stumbled upon the fact that a variant of the PET-2001’s original brain, now more than 40 years old, is still being produced.

The venerable MOS Technology 6502 , in its modern guise, is the W65C02S, supplied by fabless semiconductor company Western Design Center, Inc and distributed by Mouser Electronics. WDC specialise in 65xx-brand microprocessor technology and additionally supply the W65C21N and W65C22N, which are, for all practical purposes here, current production, drop-in replacements for the PET’s original 6520 “PIA” and 6522 “VIA” chips.

This clone is therefore not another FPGA port or an emulator running on a Raspberry Pi, but a functional replica of the original computer in the traditional hardware sense. Nor is it a part- for-part duplication of the original circuitry, but a complete re-design using contemporary discrete CMOS logic and memory devices, with some additional features thrown in for good measure. At the time or writing every component used in this project is a current-production part.

74HC(T) CMOS family logic almost entirely displaces the original LS TTL logic and great simplifications were made by using modern memory devices. Additionally, although for all practical purposes here the W65C02 is, functionally, entirely equivalent to the original 6502, it is not a direct drop-in replacement. It has slightly different pin functions, different, more stringent timing requirements due to its ability to run several times faster than the original NMOS 6502 and it is a CMOS part with CMOS-level, rather than TTL-level compatible I/O thresholds.

The potential timing incompatibility mostly relates to memory write operations and how briefly (only 10 ns) valid data is guaranteed to remain on the data bus upon the falling edge of the system clock (time THW ). If your memory write strobe decoding doesn’t have time to react before the data disappears from the data bus you’re going to have trouble with memory write operations! If you peruse my circuit diagrams you’ll notice that a pair of 74HCT244 driver chips directly buffer the W65C02S’s data I/O pins to the systems data bus. These chips provide CMOS-level to TTL-level threshold conversion and add critical, delayed time extension to THW . To doubly ensure that the memory write strobe is available well ahead of schedule, it is decoded by a super-fast 74AC family device.

The PET-2001 was originally offered with as little as 4 kilobytes of random access memory, but the BASIC is capable of recognising an expandable maximum of 32 kilobytes. A single modern static RAM chip, part # AS7C256, provides the full 32 kilobytes of system RAM and dispenses with a great deal of address decoding logic. There isn’t a need for arrays of 4096-bit memory chips like the old MOS 6550 in this day and age! The scenario is the same for the systems read only memory which stores the operating system. A single AT27C256 chip serves as the system ROM and is in fact large enough to contain both the early and the later revised versions of the BASIC operating system; more about this later.

Back in the day if you wanted sound effects for games (or any other purpose) you would typically connect the CB2 pin at the parallel port of your PET-2001 to the input of an external audio amplifier via an attenuator of some sort. Later models of the PET gained an internal CB2 logic-level-driven speaker, but that I think is a bit rudimentary – for one the volume can’t be controlled. My clone design incorporates an LM386 audio amplifier with volume control and a source-select function giving the additional handy utility of letting the user listen in on the read and write signals from or to the external data cassette storage devices.

I also designed a universal “PS/2 keyboard and RS-232 interface”, which is accommodated on a separate, self-contained circuit board and is compatible with any PET-2001, not just my clone design. Via a length of ribbon cable it plugs into the keyboard interface connector and permits the connection of a PS/2 keyboard to the PET and, if desired, communication to the PET via an RS-232 port. The latter function permits you to type to your PET via an ASCII terminal program.

Compete schematic diagrams, bills of material and further technical descriptions follow in this document.

A complete set of Gerber files for the PCBs, ROM image binary files and firmware for the PS/2 keyboard and RS-232 interface unit are available for downloading on my website:

www.glensstuff.com

You can view a Youtube video of my competed PET-2001 clone loading and running a version of the computer game here:

https://youtu.be/e4uILTKAoj8

The motherboard

The video generator board

The PS/2 & RS-232 interface board

Muscovy ducks! Hardware Overview

With the exception of a few power supply components, all of the circuitry in the original PET-2001 was accommodated on one large PCB. In my clone design I have split the video generation circuitry onto a separate PCB. There are thus two PCBs, designated the “motherboard” and the “video generator board”.

The motherboard contains:

The power supply circuitry, CPU, System RAM & ROM, VIA and PIA chips, All peripheral I/O interface circuitry, Audio amplifier and associated circuitry, A 60 Hz reference “jiffy” clock/timebase (more about this oddity in a little bit).

Video generator board

The video generator board contains all of the circuity required to generate the PET’s 40 column by 25 row, character-based video display. This includes the screen, or video, display RAM, the character ROM and a 16 MHz master oscillator module from which the 1MHz CPU/system clock, as well as all video timing signals, are derived.

Note that in the PET the video RAM and ROM space is in addition to and separate from the system RAM and ROM space. There are 40 x 25 = 1000 bytes of system-accessible video RAM to define each individual character location. The video ROM simply contains the data defining the PET’s unique alpha-numeric and graphical character set and is continuously and exclusively accessed by the circuitry concerned with producing the video display. The video character ROM is not hardware accessible to the CPU.

A significant departure in the video generation circuitry of my clone design, from the PET’s original specification, is that, for compatibility with the traditional television displays that we use in this part of the word, I designed for raster refresh rate of 50 Hz (50.08 Hz to be precise, with 312 non-interlaced horizontal lines). The original PET-2001 had its own internal video display monitor that rescanned at a frame rate of 60 Hz, with 260 non-interlaced, horizontal lines. As far as I know, as so far I have not found any evidence to the contrary, Commodore never made a version of the ‘2001 with an internal video frame rate of 50 Hz.

The first implication of having a video frame rate of 50 Hz rather than 60 Hz is totally inconsequential as far as the actual video display generation is concerned, but as some operations of the CPU are synchronised to the video refresh rate, some functions thus operate at a proportionally slower rate. A video game program, for example, which synchronises writing to the video RAM during the vertical blanking intervals only, to produce a clean, “snow free” graphical display, will update at the reduced rate. “Snow” was a term given to what was visually produced on the display when the PET is programmed to access the video RAM asynchronously - while the video generation circuitry is busy scribing a visible portion of the display. The PET’s snow- free and non snow-free modes of video RAM access were called “slow” and “fast” respectively. The latter was naturally faster because a video RAM read or write didn’t have to wait around for the next vertical blanking interval. In reality, however, as far as the 50 Hz vs. 60 Hz difference goes, unless you’re sitting next to a 60 Hz PET running the exact same video game at the same time, you’d never be aware of the subtle difference in speed. The 60 Hz Jiffy clock generator

The second implication of having a video frame rate of 50 Hz rather than 60 Hz, is that the PET’s BASIC operating system won’t keep accurate time. Now this, obviously, only has an impact upon applications that make use of the PET’s internal software real-time clock. The PET measures time in units of 1/60 th of a second, dubbed “jiffies”. In other words there are 60 jiffies in each second and the video frame rate serves as the timebase. With a timebase of 50 Hz the PET’s clock will run about 17% slow.

This is the reason why I have included an accurate and alternative 60 Hz timebase clock source on the motherboard. With a flick, one way or the other, of the “Jiffy” switch, CPU synchronisation is derived from either the video vertical refresh rate or from this alternative 60 Hz source. However there is a catch – when switched to the 60 Hz source, the functions of the CPU will no longer be synchronised to the video display and the snow-free modes of video RAM access will cease to be snow-free.

One last issue, which at the time of writing this document I have not had time to fully investigate, is that in the original PET the 60 Hz vertical frame rate, being derived from an 8 MHz master clock by integer division, wasn’t therefore precisely 60 Hz. I am led to believe that the PET’s OS was programmed with a correction factor to account for this, so that the HH-MM-SS software counter would continue to keep accurate time in the long term. My alternative jiffy hardware clock, however, is an accurate 60 Hz, so any correction factor applied would accumulate error rather than remove it. I have implemented the accurate alternative jiffy clock this way so as to set myself the challenge of eventually reverse engineering and modifying the operating system ROM to disable any correction factor that may be employed. I am likely not to get around to this for some time though, so if anyone else is up for the challenge or can provide knowledgeable insight, I’d appreciate the feedback.

Referring to sheet 3 of the motherboard schematic set, the 60 Hz jiffy clock is derived from a 3.93216 MHz crystal oscillator divided by 2 16 . U303 is serves as a 2-input data selector, providing system synchronisation to either the 50 Hz video frame rate or the 60 Hz jiffy clock as commanded by the “Jiffy” frequency selector switch.

IEEE-488 Interface port.

The long-obsolete Motorola IEEE-488 interface chips (MC3446) originally used in the PET were unusual in that a separate receive output pin and transmit input pin were provided for each I/O pin, as opposed to a less cumbersome arrangement utilising a common directional control input.

All I/O, as per the original IEEE-488 standard, was open-collector with resistive (voltage divider) pull-ups to approx. 3.5V. Logic low = true. In these Motorola chips a receive data output pin simply reflected the logic state of its respective I/O pin regardless of whether said I/O pin was asserted true (low) by either an external device or by the respective transmit data input pin being asserted low.

Consequently in the PET there isn't a direction control register of any sort for IEEE-488 communications, but separate output and input register bits for all of the CPU-controlled I/O pins, with the exception of control line SQR, which is an input only and therefore doesn't have an output register address. There are also two control pins which have no register addresses at all as they have no hardware provision for CPU control. These are control lines RET and IFC. The RET line is electrically tied to ground. This asserts the PET as a permanent host. IFC is asserted by the power-on system reset timer only. There are a total of 16 lines in the IEEE-488 standard - 8 data lines and 8 control lines.

To implement the IEEE-488 interface in a manner functionally equivalent to the original PET hardware configuration using current production parts, rather than the obsolete Motorola MC3446, I used a pair of SN75ALS160 IEEE-488 Bus Transceiver chips as the output line drivers and a pair of 74LS245 buffers as the input line receivers. The 74ALS160s chips are wired in uni-directional mode with the active pull-ups disabled. In this mode all I/O pins operate as open-collector outputs with an internal resistive pull-up to ~3.5V. The 74LS245s are perfect in this application as line receivers as they have the necessary TTL- level input switching thresholds with hysteresis for noise immunity. They also have special high-impedance inputs courtesy of emitter-follower input buffers, so they will not load the internal resistive pull-ups of the SN74ALS160 operating in open-collector mode.

Finally, the receiver outputs of the two 74LS245 chips are connected to PIA#2 and VIA#1 via current-limiting resistors RP401 and RP402. These resistors are necessary because although the PET’s BASIC operating system ostensibly configures all PIA and VIA I/O pins connected to the IEEE-488 receiver outputs to be inputs only, there are certain potential scenarios which can cause these pins to be misconfigured as outputs instead, possibly causing contention. While the VIA and PIA chips internally current-limit their I/O pins in the driven high state, the 74LS245 does not. Note that the receiver outputs of the originally-utilised Motorola MC3446 were internally current-limited in the high state by a ~440-ohm resistor in series with the collector of the upper transistor of each output totem-pole. Audio line-out and power amplifier

The audio circuitry located on the motherboard is quite simple. Referring to page 6 of the motherboard schematic set, U601 is wired as a 1-of 4 data selector under the command of the “Audio source” select switch, which has the following four positions:

Off Read Write CB2

In the off position no data source is selected and the audio is muted. The “Read” position permits the serial data stream received from either data cassette storage unit to be monitored. The “Write” position permits the serial data stream sent to either data cassette storage unit to be monitored. Note that there are separate “read” data lines for each data cassette port, but a common “write” line for both. The two read lines are logically ORed by U601 parts A and B of the audio source data selector.

Op-amp U602 serves as a line-level output buffer. The line-level output connects to an RCA jack mounted on the front panel of my clone and serves as an audio output which can handily drive the audio input of a video monitor, if desired. Alternatively the internal amplifier and speaker can be utilised by turning up the volume control. A good old LM386 audio power amplifier, U603, is utilised for speaker-driving duties.

Memory, address decode and BASIC

Referring to page 2 of the motherboard schematic set, U202 is the system ROM. This 32 kilobyte memory contains both versions of the BASIC operating system originally produced for the PET-2001. Confusingly, the “original” and “upgraded” versions of BASIC are arbitrarily called BASIC 1 and BASIC 2 respectively by some authorities and BASIC 2 and BASIC 3 respectively by others. The former was preferred by Commodore, but others, for example, Donahue & Enger, PET/CBM Guide , used the latter:

Another thing of note is that at some stage along the line Commodore modified the character ROM:

The character ROM contains 256 individual characters and the PET’s video generation hardware splits the ROM into two separate 128 character pages. These pages are called the “Graphics” and “Business” character sets respectively. When switched on the PET boots up using the graphics character set by default. The business page is mostly a duplicate of the graphics page, but substitutes 26 graphics characters with lower case letters of the alphabet. Both versions of the character ROM are identical, but the updated version swaps around the upper and lower case letters in the business page.

The system ROM, U202, is programmed with the “original” BASIC in the first 16 kilobyte page and “upgraded” BASIC in the other. Page selection is decided by the “BASIC” selector switch which connects to the motherboard via header P201. When the “BASIC” selector switch is open, R202 keeps address pin A14 of U202 low, selecting the lower 16 kilobyte page and thus causing the PET to run “original” BASIC. Closing the “BASIC” selector switch pulls A14 high and selects “upgraded” BASIC.

The “BASIC” selector switch control line also asserts the most significant address bit of the character ROM, U13, of the video generator board. The character ROM is programmed with both character set versions, so that when “original” BASIC is selected the “original” character set will be utilised and when “upgraded” BASIC is selected the “upgraded” character set will be utilised.

Flicking the “BASIC” selector switch while the computer is running will cause the system to crash, but a complete system re-boot can be initiated at any time, without having to cycle the power off and then on again, simply by pressing the “Reset” push button.

Like in the original PET, I used an LM555 Timer I.C. wired as a monostable to generate the power-on system hardware reset. The “Reset” button simply re-triggers the ‘555. The original PET wasn’t provided with a reset button, but many owners back in the day added one themselves, simply to avoid the annoyance of having to reach for the mains power switch each and every time the computer locked up!

All of the computers memory address decoding logic has been simplified to a ROM look-up table stored in U204. There are six separate memory areas accessible to the CPU. These are:

System RAM Video RAM System ROM PIA#1 registers PIA#2 registers VIA#1 registers

Power supply

The power supply circuitry is so simple it barely rates a mention. The most important thing of note is that there are two separate regulated supply rails. A +6.3 V rail is produced and used exclusively for powering the motors of the data cassette units and the LM386 audio power amplifier. A +5V logic supply rail is generated to power everything else.

PS/2 keyboard and RS-232 interface.

As the name suggests, this little interface board has two modes of operation. In PS/2 mode (pin RB0 of U2 = high) any PS/2–standard PC keyboard can be used with the PET. It was only a little bit of a challenge to logically and efficiently map all of the PET’s functions and unique characters to a modern keyboard layout.

In the page following this written description is a graphical keyboard legend which I produced as a typing aide. I printed this legend out and laminated it, to serve as a handy look- up card when typing. The function keys are easily memorised and after that the card is only really needed when looking for a shifted graphics character. In the PS/2 mode all make and break codes received from the keyboard are echoed out of the RS-232 port at 38400 baud. The mode control switch connects between pins 3 and 4 of header P5.

The second mode of operation (pin RB0 of U2 = low) lets you type to your PET via an RS- 232 terminal by receiving standard ASCII character and control codes via the RS-232 port, rather than communicating with a PS/2 keyboard. The ASCII codes are received and immediately echoed back to the terminal at 38400 baud. The only limitation in this mode of operation is that, with the exception of the "pi" character, the PET's shifted graphics characters are otherwise not supported.

The supported keys and respective ASCII codes are as follows:

Received character ASCII code (decimal) PET key / function

H 72 Home cursor W 87 Cursor up Z 90 Cursor down A 65 Cursor left S 83 Cursor right C 67 Clear screen B 66 Stop N 78 Run R 82 Reverse on T 84 Reverse off I 73 Insert a 97 A b 98 B c 99 C d 100 D e 101 E f 102 F g 103 G h 104 H i 105 I j 106 J k 107 K l 108 L m 109 M n 110 N o 111 O p 112 P q 113 Q r 114 R s 115 S t 116 T u 117 U v 118 V w 119 W x 120 X y 121 Y z 122 Z 0 48 0 1 49 1 2 50 2 3 51 3 4 52 4 5 53 5 6 54 6 7 55 7 8 56 8 9 57 9 + 43 + - 45 - = 61 = [ 91 [ ] 93 ] < 60 < > 62 > ! 33 ! @ 64 @ # 35 # $ 36 $ % 37 % ^ 94 ^ & 38 & * 42 * ( 40 ( ) 41 ) _ 95 Left arrow symbol P 80 pi symbol \ 92 \ / 47 / ; 59 ; : 58 : ' 39 ' " 34 " , 44 , . 46 . Enter 13 Return Backspace 8 Delete

VIDEO GENERATOR BOARD

U4B 74HC08 4 6 C29 5 47uF +5V U1 U12 U14A +5V U14B 16V +5V 16MHz 74HCT165 +5V +5V 74HCT74 +5V 74HCT74 U2 1 14 74HC161 +5V 3 1 16 4 14 10 9 VCC SH/LD VCC S1 VCC S2 Q2 C30 2 2 9 1 13 R4 CLK QH R1 R2 470uF 8 2 16 U4A 15 7 6 220R R6 OUT CLK VCC CLK_INH QH Q1 16V P1 1 74HC08 U5A 10 8 3 11 68R

RST SER A B C D E F G H GND CLK1 CLK2 7 9 1 74HC00 2 5 12 7 GND LOAD D1 Q1 D2 GND 4 7 3 ENP 3 COMPOSITE

3 10 2 3 4 5 6 U15A

P0 ENT 11 12 13 14 2 VIDEO OUTPUT 4 74HC10 U15C U3C Q1 R5 P1 1 5 14 +5V 1 74HC10 U5D 74HC10 BC860C 10k P2 Q0 6 13 1 2 12 9 74HC00 9 P3 Q1 12 2 12 1 2 13 10 8 12 10 8 Q2 8 11 13 11 11 11 28 1 22 GND Q3 11 12 13 15 16 17 18 19 20 13 R1 U3A U6A U15B 2k2

74HC10 74HC04 U13 FIELD REV. 74HC10 CE OE

AT27C256 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 3 VCC VPP CHARACTER 4 6 1 4 +5V P2 ROM U4D 5 3 6 74HC08 2 5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 1 12 R2 2 11 U16A U16B 5k1 R3 3

9 8 7 6 5 4 3 2 13 74HC00 74HC00 1k 10 25 24 21 23 26 27 14 4

CHARACTER ROM PAGE SELECT - MSB

U7 HR1 HR2 HR4 HR8 HR16 HR32 U8A U8B CHARACTER ROM PAGE SELECT - LSB +5V 74HC4040 +5V 74HC74 +5V +5V 74HC74 CLOCK 1 MHz 16 9 4 14 10 8 HORIZONTAL BLANKING VCC Q1 S1 VCC S2 Q2 7 1 13 HORIZONTAL SYNC Q2 R1 R2 10 6 VERTICAL BLANKING CLK Q3 5 3 11 VERTICAL SYNC Q4 CLK1 CLK2 11 3 2 5 12 7 MR Q5 D1 Q1 D2 GND 8 2 GND Q6 DV0 DV1 DV2 DV3 DV4 DV5 DV6 DV7 VR1 VR2 VR4 U23 74HCT244 +5V 9 10 R7 +5V 20 10k U4C DV0 2 18 D0 74HC08 U9A +5V 74HC74 +5V 3 17 R8 U19 10k DV1 D1

8 4 14 U17 74HCT157 +5V U22 4 16 S1 VCC 3 4 1 AT27C256 +5V AS7C256 R1 HR1 2 16 SCREEN 5 15 R9 A0 VCC 3 A0 10 28 HR2 5 MEMORY +5V 10k CLK1 A0 VCC A1 U6B 2 6 A1 9 HR4 11 DV2 6 14 D2 D1 Q1 A1 A2 74HC04 A2 8 1 HR8 14 4 10 28 A2 VPP A3 Y0 A0 VCC A3 7 7 9 7 13 A3 Y1 A1 A4 6 11 3 9 8 11 DV0 A4 IO0 B0 Y2 A2 IO0 A5 5 12 6 12 7 12 DV1 DV3 8 12 D3 A5 IO1 B1 Y3 A3 IO1 A6 4 13 10 6 13 DV2 A6 IO2 B2 A4 IO2 A7 3 15 13 5 15 DV3 9 11 A7 IO3 B3 A5 IO3 A8 25 16 15 4 16 DV4 10 A8 IO4 OE A6 IO4 A9 24 17 1 8 3 17 DV5 A9 IO5 SEL GND A7 IO5 21 18 25 18 DV6 A10 IO6 A8 IO6 DV7

23 19 24 19 1

A11 IO7 A9 IO7 19 2 21 A12 A10

U10 VR1 VR2 VR4 26 22 23 27 A13 OE A11 WE +5V 74HC4040 U6C U9B 27 U20 2 A14 A12 74HC04 74HC74 14 20 74HCT157 +5V 26 20 GND CE A13 CE 16 9 1 VCC Q1 A14 7 5 6 10 9 HR16 2 16 14 22 U24 Q2 S2 Q2 A0 VCC GND OE 10 6 13 HR32 5 74HCT244 +5V CLK Q3 R2 A1 5 VR8 11 Q4 A2 3 4 11 U18 VR16 14 4 20 Q5 CLK2 A3 Y0 2 6 12 7 AT27C256 +5V 7 DV4 2 18 D4 Q6 D2 GND Y1 11 4 5 3 9 MR Q7 B0 Y2 13 A0 10 28 6 12 3 17 Q8 A0 VCC B1 Y3 8 12 U5B A1 9 10 GND Q9 A1 B2 74HC00 A2 8 1 13 DV5 4 16 D5 A2 VPP B3 A3 7 15 A3 OE A4 6 11 1 8 5 15 A4 IO0 SEL GND U6D U11A A5 5 12 1 2 A5 IO1 (1) GRAPHICS/BUSINESS (2) BASIC 2/3 74HC04 74HC74 +5V A6 4 13 DV6 6 14 D6 3 4 A6 IO2 (3) BLANK SCREEN A7 3 15 5 6 A7 IO3 (5) PROCESSOR SYNC 9 8 4 14 A8 25 7 13 7 8 S1 VCC A8 (7) CLOCK 1 MHz 1 A9 24 U21 9 10 R1 A9 (9) WRITE VIDEO RAM 21 74HCT157 +5V DV7 8 12 D7 11 12 A10 (11) READ VIDEO RAM

VR256 VR128 VR64 VR32 VR16 VR8 3 23 13 14 CLK1 A11 (13) SELECT VIDEO RAM 2 5 2 VR32 2 16 9 11 D0 15 16 D1 Q1 A12 A0 VCC 26 22 VR64 5 10 D1 17 18 LSB A13 OE A1 27 VR128 11 D2 19 20 A14 A2 14 20 VR256 14 4 D3 21 22 GND CE A3 Y0 D4

7 +5V 1 23 24 DATA

Y1 19 3 9 D5 25 26 B0 Y2 6 12 D6 27 28 B1 Y3 10 D7 29 30 MSB B2 13 R10 A0 31 32 B3 U5C U11B 15 10k A1 33 34 LSB OE U3B U6E 74HC00 74HC74 1 8 A2 35 36 SEL GND 74HC10 74HC04 9 A3 37 38 3 8 10 9 9 A4 39 40 S2 Q2 4 6 11 10 10 13 8 A5 41 42 ADDRESS R2 5 8 10 A6 43 44 Q2 11 A7 45 46 CLK2 U6F 12 7 U16C A8 47 48 D2 GND 74HC04 74HC00 R11 R12 A9 49 50 MSB 10k 10k 13 12 P3 IDC50

+5V

+5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V 12 14 14 14 14 14 14 11 C25 C26 C27 C28 13

+ + + + + + U16E U16D

G G G G G G 74HC00 74HC00 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 1uF 1uF 1uF 1uF

100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 16V 16V 16V 16V 7 7 7 7 7 7

U3D U4E U5E U6G U15D 74HC10 74HC08 74HC00 74HC04 74HC10

PET 2001 CLONE

Sheet_1 Sheet_4 1) CPU.Sch 4) IEEE-488.Sch

IEEE-488 DATA BUS IN PIA#2_PA[0..7] PIA#2_PA[0..7]

IEEE-488 DATA BUS OUT PIA#2_PB[0..7] PIA#2_PB[0..7] ATN_IN PIA#2_CA1 PIA#2_CA1 NDAC_OUT PIA#2_CA2 PIA#2_CA2

SRQ_IN PIA#2_CB1 PIA#2_CB1 DAV_OUT PIA#2_CB2 PIA#2_CB2 NDAC_IN VIA#1_PB0 VIA#1_PB0 NRFD_OUT VIA#1_PB1 VIA#1_PB1

ATN_OUT VIA#1_PB2 VIA#1_PB2 NFRD_IN VIA#1_PB6 VIA#1_PB6 DAV_IN VIA#1_PB7 VIA#1_PB7

EOI_IN PIA#1_PA6 PIA#1_PA6

BLANK_TV/EOI_OUT PIA#1_CA2 PIA#1_CA2 SRQ IFC_OUT POR POR EOI

Sheet_5 5) IO.Sch

DATA BUS PARALLEL PORT VIA#1_PA[0..7] VIA#1_PA[0..7] EOI

CA1 VIA#1_CA1 VIA#1_CA1 SRQ

CB2/SOUND_FX VIA#1_CB2 VIA#1_CB2 DIAG_JUMP PIA#1_PA7 PIA#1_PA7 #2_CASS_READ VIA#1_CB1 VIA#1_CB1

CASS_WRITE VIA#1_PB3 VIA#1_PB3 #1_CASS_SWITCH PIA#1_PA4 PIA#1_PA4 #2_CASS_SWITCH PIA#1_PA5 PIA#1_PA5

#1_CASS_READ PIA#1_CA1 PIA#1_CA1

#2_CASS_MOTOR VIA#1_PB4 VIA#1_PB4 #1_CASS_MOTOR PIA#1_CB2 PIA#1_CB2

PIA#1_PA[0..3] PIA#1_PA[0..3]

PIA#1_PB[0..7] PIA#1_PB[0..7]

Sheet_6 6) Sound.Sch

CB2/SOUND_FX VIA#1_CB2 VIA#1_CB2 CASS_WRITE VIA#1_PB3 VIA#1_PB3 #2_CASS_READ VIA#1_CB1 VIA#1_CB1

#1_CASS_READ PIA#1_CA1 PIA#1_CA1

Sheet_2 2) Memory and address decode.Sch

SYSTEM ADDRESS BUS A[0..15] A[0..15] SYSTEM DATA BUS DATA[0..7] DATA[0..7]

POWER-ON RESET POR POR

R/W R/W

READ_STROBE READ_STROBE

READ_STROBE READ_STROBE

WRITE_STROBE WRITE_STROBE

PIA#2_SELECT PIA#2_CS2B PIA#2_CS2B VIA#1_SELECT VIA#1_CS2B VIA#1_CS2B PIA#1_SELECT PIA#1_CS2B PIA#1_CS2B

BLANK_TV/EOI_OUT PIA#1_CA2 PIA#1_CA2

GRAPHIC/BUSINESS VIA#1_CA2 VIA#1_CA2 1_MHz SYSTEM_CLOCK SYSTEM_CLOCK

PROC_SYNC

Sheet_7 7) Power.Sch

Sheet_3 3) 60 Hz jiffy clock.Sch

PROC_SYNC

50_Hz_FRAME 50_Hz_FRAME 1) CPU

IFC_OUT 2 POR POR 4

PIA#2_PA[0..7] 2 SYSTEM_CLOCK PIA#2_PA[0..7] 4

PIA#2_PB[0..7] PIA#2_PB[0..7] 4

U105 ATN_IN PIA#2_CA1 4 U101 W65C21N W65C02S PIA#2 +5V NDAC_OUT PIA#2_CA2 4 +5V C.P.U. U102 DATA0 33 20 SRQ_IN D0 VDD PIA#2_CB1 4 8 40 74HCT244 +5V DATA1 32 VDD RESB D1 37 DATA2 31 2 PIA#2_PA0 DAV_OUT PHI2 D2 PA0 PIA#2_CB2 4 34 20 DATA3 30 3 PIA#2_PA1 RWB D3 PA1 IEEE-488 4 IO0 2 18 DATA0 DATA4 29 4 PIA#2_PA2 NDAC_IN IRQB D4 PA2 VIA#1_PB0 4 DATA5 28 5 PIA#2_PA3 D5 PA3 +5V 3 17 DATA6 27 6 PIA#2_PA4 NRFD_OUT D6 PA4 VIA#1_PB1 4 DATA7 26 7 PIA#2_PA5 D7 PA5 6 IO1 4 16 DATA1 8 PIA#2_PA6 ATN_OUT NMIB PA6 VIA#1_PB2 4 25 9 PIA#2_PA7 PHI2 PA7 2 R101 5 15 NFRD_IN RDY VIA#1_PB6 4 3k3 A0 36 10 PIA#2_PB0 RS0 PB0 38 IO2 6 14 DATA2 A1 35 11 PIA#2_PB1 DAV_IN SOB RS1 PB1 VIA#1_PB7 4 12 PIA#2_PB2 PB2 36 7 13 21 13 PIA#2_PB3 EOI_IN BE RWB PB3 PIA#1_PA6 4 14 PIA#2_PB4 PB4 IO3 8 12 DATA3 38 15 PIA#2_PB5 BLANK_TV/EOI_OUT IRQAB PB5 PIA#1_CA2 4 37 16 PIA#2_PB6 IRQBB PB6 33 IO0 9 11 +5V 17 PIA#2_PB7 D0 PB7 32 IO1 10 22 D1 CS0 31 IO2 24 40 ATN_IN D2 CS1 CA1 30 IO3 23 39 NDAC_OUT D3 CS2B CA2

29 IO4 1

D4 19 28 IO5 34 18 SRQ_IN D5 RESB CB1 27 IO6 1 19 DAV_OUT D6 VSS CB2 26 IO7 D7 VIA#1_PA[0..7] VIA#1_PA[0..7] 5

9 A0 U103 U106 CA1 A0 VIA#1_CA1 5 10 A1 74HCT244 +5V W65C22N A1 PARALLEL PORT 11 A2 VIA#1 +5V CB2/SOUND_FX A2 VIA#1_CB2 5 12 A3 20 A3 13 A4 IO4 2 18 DATA4 DATA0 33 20 DIAG_JUMP A4 D0 VDD PIA#1_PA7 5 14 A5 DATA1 32 A5 D1 15 A6 3 17 DATA2 31 2 VIA#1_PA0 A6 D2 PA0 16 A7 DATA3 30 3 VIA#1_PA1 A7 D3 PA1 17 A8 IO5 4 16 DATA5 DATA4 29 4 VIA#1_PA2 A8 D4 PA2 18 A9 DATA5 28 5 VIA#1_PA3 A9 D5 PA3 19 A10 5 15 DATA6 27 6 VIA#1_PA4 A10 D6 PA4 20 A11 DATA7 26 7 VIA#1_PA5 A11 D7 PA5 22 A12 IO6 6 14 DATA6 8 VIA#1_PA6 A12 PA6 23 A13 25 9 VIA#1_PA7 A13 PHI2 PA7 24 A14 7 13 A14 21 25 A15 A0 38 10 NDAC_IN VSS A15 RS0 PB0 IO7 8 12 DATA7 A1 37 11 NRFD_OUT CB2/SOUND_FX RS1 PB1 VIA#1_CB2 6 A2 36 12 ATN_OUT RS2 PB2 9 11 A3 35 13 CASS_WRITE CASS_WRITE RS3 PB3 VIA#1_PB3 6 10 14 #2_CASS_MOTOR PB4 SOUND 22 15 SYNC #2_CASS_READ RWB PB5 VIA#1_CB1 6 +5V +5V +5V +5V 16 NRFD_IN PB6

1 +5V 21 17 DAV_IN #1_CASS_READ

19 IRQB PB7 PIA#1_CA1 6

24 40 CA1 CS1 CA1 U104A 23 39 GRAPHIC/BUSINESS CS2B CA2 74AC00 C101 C102 C103 C104 1 34 18 #2_CASS_READ RESB CB1 100nF 100nF 100nF 100nF 3 1 19 CB2/SOUND_FX VSS CB2 2 PIA#1_PA[0..3] PIA#1_PA[0..3] 5 KEYBOARD +5V U107 PIA#1_PB[0..7] PIA#1_PB[0..7] 5 +5V +5V +5V +5V W65C21N 12 13 14 PIA#1 +5V

U104D U104E DATA0 33 20 + D0 VDD 74AC00 74AC00 DATA1 32

G D1 C108 DATA2 31 2 PIA#1_PA0 #2_CASS_READ D2 PA0 VIA#1_CB1 5 C105 C106 C107 1uF DATA3 30 3 PIA#1_PA1 D3 PA1

100nF 100nF 100nF 16V 7 DATA4 29 4 PIA#1_PA2 CASS_WRITE

11 D4 PA2 VIA#1_PB3 5 DATA5 28 5 PIA#1_PA3 D5 PA3 U104C DATA6 27 6 #1_CASS_SWITCH #1_CASS_SWITCH D6 PA4 PIA#1_PA4 5 74AC00 DATA7 26 7 #2_CASS_SWITCH D7 PA5 9 8 EOI_IN #2_CASS_SWITCH PA6 PIA#1_PA5 5 CASSETTE 8 25 9 DIAG_JUMP PHI2 PA7 10 #1_CASS_READ PIA#1_CA1 5 U104B A0 36 10 PIA#1_PB0 RS0 PB0 74AC00 A1 35 11 PIA#1_PB1 #2_CASS_MOTOR 2 R/W RS1 PB1 VIA#1_PB4 5 4 12 PIA#1_PB2 PB2 6 21 13 PIA#1_PB3 #1_CASS_MOTOR 2 READ_STROBE RWB PB3 PIA#1_CB2 5 5 14 PIA#1_PB4 PB4 38 15 PIA#1_PB5 2 READ_STROBE IRQAB PB5 37 16 PIA#1_PB6 IRQBB PB6 +5V R102 17 PIA#1_PB7 2 WRITE_STROBE PB7 3k3 22 CS0 24 40 #1_CASS_READ CS1 CA1 23 39 BLANK_TV/EOI_OUT CS2B CA2 A[0..15] 2 A[0..15] 34 18 SYNC RESB CB1 DATA[0..7] 1 19 #1_CASS_MOTOR 2 DATA[0..7] VSS CB2

PIA#2_SELECT 2 PIA#2_CS2B PROC_SYNC 3 SYNC CLOCK

VIA#1_SELECT BLANK_TV/EOI_OUT 2 VIA#1_CS2B PIA#1_CA2 2 VIDEO PIA#1_SELECT GRAPHIC/BUSINESS 2 PIA#1_CS2B VIA#1_CA2 2 2) MEMORY AND ADDRESS DECODE

GRAPHIC/BUSINESS 1 VIA#1_CA2

BLANK_TV / EOI_OUT 1 PIA#1_CA2

VERTICAL_SYNC 3 50_Hz_FRAME

DATA[0..7] 1 DATA[0..7]

A[0..15] 1 A[0..15] +5V U203 U202 AS7C256 AT27C256 SYSTEM R.A.M. R201 +5V SYSTEM R.O.M. +5V 32kbyte +5V R213 560R 10k A0 10 28 A0 10 28 1 A0 VCC A0 VCC BASIC2/3 A1 9 A1 9 2 A1 A1 A2 8 1 A2 8 11 DATA0 8 9 3 A2 VPP A2 IO0 RESET A3 7 A3 7 12 DATA1 4 A3 A3 IO1 R202 A4 6 11 DATA0 A4 6 13 DATA2 A4 IO0 A4 IO2 +5V 10k A5 5 12 DATA1 A5 5 15 DATA3 U205D A5 IO1 A5 IO3 P201 A6 4 13 DATA2 A6 4 16 DATA4 74HCT04 A6 IO2 A6 IO4 O/S SELECT A7 3 15 DATA3 A7 3 17 DATA5 A7 IO3 A7 IO5 & RESET R203 R204 A8 25 16 DATA4 A8 25 18 DATA6 10 11 D201 A8 IO4 A8 IO6 100R 10k A9 24 17 DATA5 A9 24 19 DATA7 LL4148 A9 IO5 A9 IO7 A10 21 18 DATA6 A10 21 A10 IO6 A10 A11 23 19 DATA7 A11 23 27 U205E A11 IO7 A11 WE A12 2 A12 2 74HCT04 A12 A12 A13 26 22 A13 26 20 A13 OE A13 CE 27 A14 1 12 13 A14 A14 14 20 14 22 GND CE GND OE U201 LM555 U205F U205C POWER-ON 74HCT04 74HCT04 RESET +5V

6 5 3 8 1 POR OUT VCC U204 P202 4 R205 R206 AT27C256 IDC50 RST 100k 1M ADDRESS VIDEO 5 6 DECODER +5V +5V GENERATOR CV THRES

C211 7 A4 10 28 R210 1 2 DISC A0 VCC (1) GRAPHICS/BUSINESS (2) BASIC 2/3 100nF A5 9 10k R211 3 4 A1 (3) BLANK SCREEN 1 2 A6 8 1 10k 5 6 GND TRIG A2 VPP (5) PROCESSOR SYNC A7 7 7 8 A3 (7) CLOCK 1 MHz A8 6 11 9 10 C212 A4 IO0 (9) WRITE VIDEO R.A.M. C213 A9 5 12 11 12 10uF A5 IO1 (11) READ VIDEO R.A.M. 100nF A10 4 13 13 14 16V A6 IO2 (13) SELECT VIDEO R.A.M. A11 3 15 DATA0 15 16 A7 IO3 A12 25 16 1 R212 DATA1 17 18 LSB A8 IO4 A13 24 17 10k DATA2 19 20 A9 IO5 A14 21 U205A DATA3 21 22 A10 A15 23 74HCT04 DATA4 23 24 DATA A11 +5V 2 DATA5 25 26 A12 26 22 DATA6 27 28 A13 OE 27 DATA7 29 30 MSB A14 2 14 20 A0 31 32 GND CE A1 33 34 LSB

R207 R208 R209 3 A2 35 36 10k 10k 10k A3 37 38 U205B A4 39 40 VIA#1_SELECT 74HCT04 A5 41 42 ADDRESS 1 VIA#1_CS2B A6 43 44 PIA#2_SELECT A7 45 46 1 PIA#2_CS2B A8 47 48 4 PIA#1_SELECT A9 49 50 MSB 1 PIA#1_CS2B

1 READ_STROBE

1 WRITE_STROBE

1 READ_STROBE

U206A U206B 74HC00 74HC00 U206C 2 4 74HC00 3 6 9 1 5 8 1 R/W 10

1 SYSTEM_CLOCK

+5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V 14 14 U206D C207 C208 C209 C210 74HC00 U205G U206E + + 12 74HCT04 74HC00 11 G G 13 C201 C202 C203 C204 C205 C206 10uF 1uF 1uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF 16V 16V 16V 16V 7 7 3) 60 Hz JIFFY CLOCK

U301 U302A U302B +5V 74HC4060 +5V 74HC74 +5V 74HC74 U303B XTAL301 74HC00 U303D 3.93216 MHz 16 4 14 10 9 60_Hz 4 74HC00 R303 VCC S1 VCC S2 Q2 12 pF PARALLEL 1 13 6 12 220R R1 R2 C304 11 5 8 5 11 OSC_IN Q1 Q2 PROC_SYNC 1 22pF 3 11 13

CLK1 CLK2 3 R301 2 6 12 7 D1 Q1 D2 GND 4M7 C305 10 OSC_OUT1 22pF U303A R302 74HC00 1k5

12 1 2 RST 8 3 U303C GND Q14 74HC00 9 8 10 2 50_Hz_FRAME

+5V +5V

R304 10k P301

1 60 Hz JIFFY CLOCK SWITCH 2 VIDEO BOARD POWER 3 GND 4 GND

+5V +5V +5V +5V 14

U303E + 74HC00 G

C301 C302 C303

7 100nF 100nF 100nF 4) IEEE-488 INTERFACE PORT

U401 +5V SN75ALS160

PIA#2_PB[0..7] 20 1 PIA#2_PB[0..7] VCC 1 TE

PIA#2_PB0 19 2 DIO-1 D1 B1 PIA#2_PB1 18 3 DIO-2 D2 B2 PIA#2_PB2 17 4 DIO-3 D3 B3 PIA#2_PB3 16 5 DIO-4 P401 D4 B4 PIA#2_PB4 15 6 DIO-5 IDC26 D5 B5 PIA#2_PB5 14 7 DIO-6 IEEE-488 D6 B6 PIA#2_PB6 13 8 DIO-7 PORT D7 B7 PIA#2_PB7 12 9 DIO-8 D8 B8 DIO-1 1 2 DIO-5 11 DIO-2 3 4 DIO-6 PE 10 DIO-3 5 6 DIO-7 GND DIO-4 7 8 DIO-8 9 10 EOI 11 12 DAV 13 14 NRFD 15 16 U402 +5V NDAC 17 18 74LS245 IFC 19 20 PIA#2_PA[0..7] 20 SRQ 21 22 1 PIA#2_PA[0..7] RP401 VCC 1 ATN 23 24 4816P-1-221LF DIR 25 26 PIA#2_PA0 16 1 18 2 DIO-1 B1 A1 PIA#2_PA1 15 2 17 3 DIO-2 B2 A2 PIA#2_PA2 14 3 16 4 DIO-3 B3 A3 PIA#2_PA3 13 4 15 5 DIO-4 B4 A4 PIA#2_PA4 12 5 14 6 DIO-5 B5 A5 PIA#2_PA5 11 6 13 7 DIO-6 B6 A6 PIA#2_PA6 10 7 12 8 DIO-7 B7 A7 PIA#2_PA7 9 8 11 9 DIO-8 B8 A8

19 SRQ OE SRQ 5 10 GND EOI EOI 5

U403 +5V SN75ALS160

20 VCC 1 TE

DAV_OUT 19 2 DAV 1 PIA#2_CB2 D1 B1 18 3 NRFD D2 B2 NRFD_OUT 17 4 NDAC 1 VIA#1_PB1 D3 B3 16 5 ATN D4 B4 NDAC_OUT 15 6 EOI 1 PIA#2_CA2 D5 B5 14 7 IFC D6 B6 ATN_OUT 13 1 VIA#1_PB2 D7 12 D8 BLANK_TV / EOI_OUT 1 PIA#1_CA2 11 PE IFC_OUT 10 1 POR GND

U404 +5V 74LS245

20 RP402 VCC 1 4816P-1-221LF DIR

DAV_IN 16 1 18 2 DAV 1 VIA#1_PB7 B1 A1 15 2 17 3 NRFD B2 A2 NRFD_IN 14 3 16 4 NDAC 1 VIA#1_PB6 B3 A3 13 4 15 5 ATN B4 A4 NDAC_IN 12 5 14 6 EOI +5V +5V +5V +5V 1 VIA#1_PB0 B5 A5 11 6 13 7 SRQ B6 A6 ATN_IN 10 7 8 1 PIA#2_CA1 A7 9 8 9 A8 EOI_IN 1 PIA#1_PA6 19 OE SRQ_IN 10 C401 C402 C403 C404 1 PIA#2_CB1 GND 100nF 100nF 100nF 100nF 5) I/O

VIA#1_PA[0..7] 1 VIA#1_PA[0..7]

CB2 / SOUND_FX 1 VIA#1_CB2 CA1 1 VIA#1_CA1 P501 IDC26 PARALLEL PORT 4 SRQ

1 2 4 EOI 3 4 5 6 VIA#1_PA0 7 8 VIA#1_PA1 DIAG_JUMP 9 10 VIA#1_PA2 1 PIA#1_PA7 11 12 VIA#1_PA3 CASS_WRITE 13 14 VIA#1_PA4 1 VIA#1_PB3 15 16 VIA#1_PA5 #1_CASS_SWITCH 17 18 VIA#1_PA6 1 PIA#1_PA4 19 20 VIA#1_PA7 #2_CASS_SWITCH 21 22 1 PIA#1_PA5 23 24 #1_CASS_READ 25 26 1 PIA#1_CA1

#2_CASS_READ 1 VIA#1_CB1

+6V3 +5V

R504 1k P502 Q503 #1 CASSETTE +6V3 FZT1149A C502 R505 100nF 1 GND 560R 2 +5V R503 3 MOTOR 10k 4 READ 5 WRITE Q502 6 SWITCH R501 BC850C 10k #1_CASS_MOTOR Q501 1 PIA#1_CB2 BC850C #2_CASS_MOTOR R502 1 VIA#1_PB4 10k +6V3

R509 1k P503 Q506 #2 CASSETTE +6V3 FZT1149A C503 R510 100nF 1 GND 560R 2 +5V R508 3 MOTOR 10k 4 READ 5 WRITE +5V Q505 6 SWITCH R506 BC850C 10k Q504 C501 BC850C 100nF R507 10k

P504 IDC26 U501 +5V KEYBOARD 74LS145

16 1 KEY_SCAN_0 KEY_SCAN_0 1 2 KEY_SCAN_1 VCC 0 2 KEY_SCAN_1 KEY_SCAN_2 3 4 KEY_SCAN_3 1 3 KEY_SCAN_2 KEY_SCAN_4 5 6 KEY_SCAN_5 2 PIA#1_PA0 15 4 KEY_SCAN_3 KEY_SCAN_6 7 8 KEY_SCAN_7 A 3 PIA#1_PA1 14 5 KEY_SCAN_4 KEY_SCAN_8 9 10 KEY_SCAN_9 B 4 PIA#1_PA2 13 6 KEY_SCAN_5 11 12 C 5 PIA#1_PA3 12 7 KEY_SCAN_6 13 14 +5V D 6 9 KEY_SCAN_7 15 16 7 10 KEY_SCAN_8 17 18 8 8 11 KEY_SCAN_9 PIA#1_PB0 19 20 PIA#1_PB1 GND 9 PIA#1_PB2 21 22 PIA#1_PB3 PIA#1_PA[0..3] PIA#1_PB4 23 24 PIA#1_PB5 1 PIA#1_PA[0..3] PIA#1_PB6 25 26 PIA#1_PB7 +5V

PIA#1_PB0 16 1 PIA#1_PB1 15 2 PIA#1_PB2 14 3 PIA#1_PB3 13 4 PIA#1_PB4 12 5 PIA#1_PB5 11 6 PIA#1_PB6 10 7 PIA#1_PB7 9 8

RP501 4816P-1-103LF PIA#1_PB[0..7] 1 PIA#1_PB[0..7] 6) SOUND

P601 AUDIO SOURCE SELECT R601 +5V SWITCH 560R +6V3 1 2 3 4

C608 P602 R611 7 10uF AUDIO U601A 1M R613 C607 16V OUTPUT 74HCT08 R605 R610 2 560R 100nF #1 CASS READ 1 10k 10k 6 1 PIA#1_CA1 1 3 3 LINE 2 2 3 U602 SPEAKER 4 C605 C606 R612

4 TL071 U601B 10nF 1nF 1M 74HCT08 R606 #2 CASS READ 4 10k 1 VIA#1_CB1 P603 6 VOLUME 5 CONTROL

1 U601C 2 74HCT08 R607 3 CASS WRITE 9 10k 1 VIA#1_PB3 4 8 10 +6V3 R614 U601D 10k 74HCT08 R608 6 CB2/SOUND_FX 12 10k 1 VIA#1_CB2 11 3 13 5 2 R615 U603 R616 C611 R602 R604 R609 2k7 LM386 100R 470uF

10k 10k 10k 4 7 16V C609 C610 10uF 10nF R603 16V 10k

+5V +5V +6V3 +6V3 +6V3 14

U601E + 74HCT08 G C604 C601 C602 C603 10uF

7 100nF 100nF 100nF 16V 7) POWER

P701 9VAC

1 B701 2 REG701 WO4 +6V3 3 LM317 4 ~ 3 2 IN OUT

~ ADJ C701 C702 R701 C703 R704 4700uF 100nF 220R 100nF 470R 25V 1

R702 P702 68R

1 2 POWER-ON 1 R703 3 L.E.D. 820R 4 HS1 HSE-B20254-040H 2

REG702 +5V LM7805

1 1 3 IN OUT

HS2 COM HSE-B20254-040H C704 C705 2 100nF 100nF 2

PS/2 KEYBOARD AND RS-232 INTERFACE BOARD

P2 ICSP P3 U1 U2 ICSP PIC18F874A PIC18F874A MATRIX +5V 1 2 3 4 SERIAL +5V ENCODER COMMUNICATOR 1 2 3 4 R1 R2 P1 KEY_SCAN_1 19 11 4k7 11 4k7 RD0 VDD VDD IDC26 KEY_SCAN_2 20 32 32 RD1 VDD VDD KEYBOARD KEY_SCAN_3 21 RD2 KEY_SCAN_4 22 1 1 RD3 MCLR MCLR 1 2 KEY_SCAN_1 KEY_SCAN_5 27 +5V +5V +5V RD4 KEY_SCAN_2 3 4 KEY_SCAN_3 KEY_SCAN_6 28 40 40 RD5 PGD PGD KEY_SCAN_4 5 6 KEY_SCAN_5 KEY_SCAN_7 29 39 39 RD6 PGC PGC KEY_SCAN_6 7 8 KEY_SCAN_7 KEY_SCAN_9 30 RD7 KEY_SCAN_8 9 10 KEY_SCAN_9 2 KEY_CODE_D0 19 R3 R4 R5 P4 RA0 RD0 11 12 3 KEY_CODE_D1 20 4k7 4k7 4k7 +5V PS/2 RA1 RD1 13 14 +5V 4 KEY_CODE_D2 21 RA2 RD2 15 16 5 KEY_CODE_D3 22 RA3 RD3 1 +5V VCC (5) 17 18 6 KEY_CODE_D4 27 35 RA4 RD4 RB2 2 KBD_CLOCK (1) PIA#1_PB0 19 20 PIA#1_PB1 7 KEY_CODE_D5 28 34 RA5 RD5 RB1 3 KBD_DATA (3) PIA#1_PB2 21 22 PIA#1_PB3 8 KEY_CODE_D6 29 33 RE0 RD6 RB0 4 GND (2) PIA#1_PB4 23 24 PIA#1_PB5 PIA#1_PB6 25 26 PIA#1_PB7 9 EXTENDED 2 RE1 RA0 PIA#1_PB0 15 10 SHIFT 3 () = PIN NUMBERING RC0 RE2 RA1 PIA#1_PB1 16 FOR 6-PIN MINATURE RC1 PIA#1_PB2 17 33 BUSY 4 D.I.N. CONNECTOR RC2 RB0 RA2 PIA#1_PB3 18 25 RC3 RC6 PIA#1_PB4 23 13 13 26 RC4 CLKI CLKI RC7 PIA#1_PB5 24 RC5 PIA#1_PB6 25 12 12 U3 RC6 VSS VSS PIA#1_PB7 26 31 31 MAX202 +5V RC7 VSS VSS

1 16 C1+ VCC

C6 C8 100nF 100nF 3 2 C1- V+ +5V C9 4 C2+ 100nF KEY_SCAN_1 16 1 KEY_SCAN_2 15 2 C7 6 V- KEY_SCAN_3 14 3 100nF P5 KEY_SCAN_4 13 4 U4 5 RS-232 C2- KEY_SCAN_5 12 5 +5V 16MHz KEY_SCAN_6 11 6 11 14 T1IN T1OUT 1 T.X. (3) KEY_SCAN_7 10 7 14 10 VCC T2IN 2 R.X. (2) KEY_SCAN_9 9 8 3 MODE 8 12 13 OUT R1OUT R1IN 4 GND (5) 8 R2IN RP1 7 GND 4816P-1-472LF () = PIN NUMBERING FOR DE9/M CONNECTOR KEY_SCAN_8

D1 D2 BAS85 BAS85

+5V +5V +5V +5V +5V

C1 47uF 16V C2 C3 C4 C5 100nF 100nF 100nF 100nF

Parts for Motherboard PCB

Designator Component type Value Part # Manufacturer Package Description Quantity

R206, R611, R612 Resistor 1M Various 1206 Chip, thin film 3 R302 Resistor 1k5 Various 1206 Chip, thin film 1 R504, R509 Resistor 1k Various 1206 Chip, thin film 2 R102, R102 Resistor 3k3 Various 1206 Chip, thin film 2 R301 Resistor 4M7 Various 1206 Chip, thin film 1 R202, R204, R207, R208, Resistor 10k Various 1206 Chip, thin film 26 R209, R210, R211, R212, R213, R304, R501, R502, R503, R506, R507, R508, R602, R603, R604, R605, R606, R607, R608, R609, R610, R614 R615 Resistor 2k7 Various 1206 Chip, thin film 1 R702 Resistor 68R Various 1206 Chip, thin film 1 R203, R616 Resistor 100R Various 1206 Chip, thin film 2 R205 Resistor 100k Various 1206 Chip, thin film 1 R303, R701 Resistor 220R Various 1206 Chip, thin film 2 R704 Resistor 470R Various 1206 Chip, thin film 1 R201, R505, R510, R601, R613 Resistor 560R Various 1206 Chip, thin film 5 R703 Resistor 820R Various 1206 Chip, thin film 1 RP401, RP402 Resistor array 220R x 8 4816P-1-221LF Bournes 16 pin SMT 2 RP501 Resistor array 10k x 8 4816P-1-103LF Bournes 16 pin SMT 1

C304, C305 Capacitor 22pF Various 1206 Ceramic 2 C606 Capacitor 1nF Various 1206 Ceramic 1 C605, C610 Capacitor 10nF Various 1206 Ceramic 2 C101, C102, C103, C104, Capacitor 100nF Various 1206 Ceramic 33 C105, C106, C107, C201, C202, C203, C204, C205, C206, C211, C213, C301, C302, C303, C401, C402, C403, C404, C501, C502, C503, C601, C602, C603, C607, C702, C703, C704, C705 C108, C208, C209, C210 Capacitor 1uF / 16V Various 1206 Tantalum 4 C207, C212, C604, C608, Capacitor 10uF / 16V EEE-1CA100SR Panasonic SMT Electrolytic 5 C609 C611 Capacitor 470uF / 16V EEE-1CA471UP Panasonic SMT Electrolytic 1 C701 Capacitor 4700uF / 25V Various Through hole. Pitch = Electrolytic 1 7.5mm. Diameter = 16mm.

U104 I.C. 74AC00 Various SOIC Quad NAND gate 1 U206, U303 I.C. 74HC00 Various SOIC Quad NAND gate 2 U302 I.C. 74HC74 Various SOIC Dual flip-flop 1 U301 I.C. 74HC4060 Various SOIC 14-stage binary counter 1 U205 I.C. 74HCT04 Various SOIC Hex inverter 1 U601 I.C. 74HCT08 Various SOIC Quad AND gate 1 U102, U103 I.C. 74HCT244 Various SOIC - WIDE Octal buffer / driver 2 U501 I.C. 74LS145 Various SOIC 1-of-10 decoder. OC-outputs 1 U402, U404 I.C. 74LS245 Various SOIC - WIDE Octal line driver / receiver 2 U401, U403 I.C. SN75ALS160 SOIC - WIDE GPIB driver / receiver 2 U201 I.C. LM555 Various SOIC Timer 1 U203 I.C. AS7C256 Alliance Memory SOJ 32k x 8 SRAM 1 U202, U204 I.C. AT27C256 Atmel DIP 32k x 8 OTP ROM 2 U101 I.C. W65C02S WDC DIP Microprocessor 1 U105, U107 I.C. W65C21 N WDC DIP PIA. DO NOT sub. with W65C21 S 2 U106 I.C. W65C22 N WDC DIP VIA. DO NOT sub. with W65C22 S 1 U602 I.C. TL071 Various SOIC JFET-input op-amp 1 U603 I.C. LM386 Texas Instruments DIP Audio power amplifier 1 REG701 I.C. LM317 Various TO-220 Adjustable positive regulator 1 REG702 I.C. LM7805 Various TO-220 +5V fixed regulator 1

B701 Bridge rectifier W04 Various TH 1 D201 Diode LL4148 Various SOD-80 1 Q501, Q502, Q504, Q505 Transistor BC850C Various SOT-23 NPN 4 Q503, Q506 Transistor FZT1149A Diodes Inc. SOT-223 PNP 2

XTAL301 Crystal 3.93216 MHz Various HC-49 12 pF Parallel res. 1 " Insulator 700-TFL-9001 ECS Crystal insulator HC-49U/US 1

P201, P301, P601, P602, Connector 0022272041 Molex TH KK-254 vertical header, 4-way 7 P603, P701, P702 P502, P503 Connector 0022272061 Molex TH KK-254 vertical header, 6-way 2 P401, P501, P504 Connector Various TH 26-way IDC boxed header 3 P202 Connector Various TH 50-way IDC boxed header 1

HS1, HS2 Heatsink HSE-B20254-040H CUI Inc. TH 25.4x32x20mm w/pin extrusion 2

TO-220 Insulator kit required to isolate REG701 tab from heatsink HS1. REG701 and REG702 mounted with M3 hardware. Sockets recommended for all DIP integrated circuits. Parts for Video Generator PCB

Designator Component type Value Part # Manufacturer Package Description Quantity

R3 Resistor 1k Various 1206 Chip, thin film 1 R1 Resistor 2k2 Various 1206 Chip, thin film 1 R2 Resistor 5k1 Various 1206 Chip, thin film 1 R5, R7, R8, R9, R10, R11, Resistor 10k Various 1206 Chip, thin film 7 R12 R6 Resistor 68R Various 1206 Chip, thin film 1 R4 Resistor 220R Various 1206 Chip, thin film 1

C1, C2, C3, C4, C5, C6, C7, Capacitor 100nF Various 1206 Ceramic 24 C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24 C25, C26, C27, C28 Capacitor 1uF / 16V Various 1206 Tantalum 4 C29 Capacitor 47uF / 16V EEE-1CA471UP Panasonic SMT Electrolytic 1 C30 Capacitor 470uF / 16V EEE-1CA471UP Panasonic SMT Electrolytic 1

U5, U16 I.C. 74HC00 Various SOIC Quad NAND gate 2 U6 I.C. 74HC04 Various SOIC Hex inverter 1 U4 I.C. 74HC08 Various SOIC Quad AND gate 1 U3, U15 I.C. 74HC10 Various SOIC Triple 3-input NAND gate 2 U8, U9, U11 I.C. 74HC74 Various SOIC Dual flip-flop 3 U2 I.C. 74HC161 Various SOIC 4-bit binary counter 1 U7, U10 I.C. 74HC4040 Various SOIC 12-stage binary counter 2 U14 I.C. 74HCT74 Various SOIC Dual flip-flop 1 U19, U20, U21 I.C. 74HCT157 Various SOIC Multiplexer 3 U12 I.C. 74HCT165 Various SOIC Shift register 1 U23, U24 I.C. 74HCT244 Various SOIC - WIDE Octal buffer / driver 2 U22 I.C. AS7C256 Alliance Memory SOJ 32k x 8 SRAM 1 U13, U17, U18 I.C. AT27C256 Atmel DIP 32k x 8 OTP ROM 3 U1 I.C. MX045-3C-16M0000 CTS Elec. Comp. DIP 16 MHz oscillator, 14 pin DIP 1

Q1 Transistor BC860C Various SOT-23 PNP 1

P1, P2 Connector 0022272041 Molex TH KK-254 vertical header, 4-way 2 P3 Connector Various TH 50-way IDC boxed header 1

Parts for Keyboard Interface PCB

Designator Component type Value Part # Manufacturer Package Description Quantity

R1, R2, R3, R4, R5 Resistor 4k7 Various 1206 Chip, thin film 5 RP1 Resistor array 4k7 x 8 4816P-1-472LF Bournes 16 pin SMT 1

C2, C3, C4, C5, C6, C7, C8, Capacitor 100nF Various 1206 Ceramic 8 C9 C1 Capacitor 47uF / 16V EEE-1CA471UP Panasonic SMT Electrolytic 1

U1, U2 I.C. PIC16F874A Microchip DIP Microcontroller 2 U3 I.C. MAX202 Various SOIC RS-232 transceiver 1 U4 I.C. MX045-3C-16M0000 CTS Elec. Comp. DIP 16 MHz oscillator, 14 pin DIP 1

D1, D2 Diode BAS85 Various SOD-80 2

P1 Connector Various TH 26-way IDC boxed header 1 P2, P3, P4, P5 Connector 0022272041 Molex TH KK-254 vertical header, 4-way 4