Visual Debugger for the i281 CPU Iowa State University Department of Electrical & Computer Engineering Team 38 - Spring 2021 Client & Advisor: Alexander Stoytchev Email:
[email protected] Website: http://sdmay21-38.sd.ece.iastate.edu/ Eric Marcanio Colby McKinley Computer Engineering Software Engineering
[email protected] [email protected] Aiman Priester Bryce Snell Computer Engineering Computer Engineering
[email protected] [email protected] Brady Kolosik Jacob Betsworth Computer Engineering Computer Engineering
[email protected] [email protected] Final Report SDMAY21-38 Executive Summary _________________________________________________________________ Development Standards & Practices Used Standard industry convention was used in all software designs. These include: ● ISO/IEC/IEEE 23026:2015 ○ Systems and software engineering — Engineering and management of websites for systems, software, and services information ● ISO/IEC/IEEE 15026:2019 ○ International Standard - Systems and software engineering ● IEEE 1008-1987 ○ IEEE Standard for Software Unit Testing ● IEEE 1284-2000 ○ IEEE Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers Summary of Requirements ● Create a lightweight Javascript Web client which simulates the i281 Processor ○ Have a Visualiser that is able to propagate through generated machine code ○ GUI that simulates the switches and seven-segment display from an FPGA ● Develop an assembler to output machine code to the CPU ○ The ability to upload an assembly file or choose from a list of examples ○ A visual component that allows students to understand the conversion between assembly and binary ○ The ability to download generate verilog and machine code ● Create a Verilog model of the i281 processor ○ Have a one-to-one copy in Verilog to allow the students to understand the nuances of Quartus BDF designs and Verilog ○ Provides a framework to build on for their potential CprE281 projects.