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Design of Discrete-Time Chaos-Based Systems for Hardware Security Applications

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Design of Discrete-Time Chaos-Based Systems for Hardware Security Applications University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Doctoral Dissertations Graduate School 8-2020 Design of Discrete-time Chaos-Based Systems for Hardware Security Applications Aysha Shanta University of Tennessee, [email protected] Follow this and additional works at: https://trace.tennessee.edu/utk_graddiss Recommended Citation Shanta, Aysha, "Design of Discrete-time Chaos-Based Systems for Hardware Security Applications. " PhD diss., University of Tennessee, 2020. https://trace.tennessee.edu/utk_graddiss/6823 This Dissertation is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Doctoral Dissertations by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a dissertation written by Aysha Shanta entitled "Design of Discrete- time Chaos-Based Systems for Hardware Security Applications." I have examined the final electronic copy of this dissertation for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Doctor of Philosophy, with a major in Electrical Engineering. Garrett Rose, Major Professor We have read this dissertation and recommend its acceptance: Jayne Wu, Hoon Hwangbo, Jinyuan Stella Sun Accepted for the Council: Dixie L. Thompson Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) Design and Implementation of Discrete-Time Chaos-Based Systems for Hardware Security Applications A Dissertation Presented for the Doctor of Philosophy Degree The University of Tennessee, Knoxville Aysha Siddique Shanta August 2020 © by Aysha Siddique Shanta, 2020 All Rights Reserved. ii I dedicate this work to my beloved father, Md Siddique Hossain, without whom this day would not have been possible and to my wonderful husband, Md Arifur Rahman, who stood by me through thick and thin. iii Acknowledgments I would like to thank my advisor Dr. Garrett S. Rose for giving me the opportunity to work in his research group and for providing guidance throughout my PhD career at University of Tennessee, Knoxville (UTK). I will always be indebted to him for believing in me when I was going through a rough patch in life. I am thankful to Dr. Jayne Wu, Dr. Jinyuan Stella Sun and Dr. Hoon Hwangbo for serving on my PhD committee and dedicating their valuable time in helping and guiding me through the process. I am extremely grateful to Dr. Hairong Qi and Dr. Leon Tolbert for their support and help during my time as a student at UTK. I would also like to thank Dr. Syed Kamrul Islam for giving me the opportunity to come to UTK for higher studies. I would like to thank the Department of Electrical Engineering and Computer Science at University of Tennessee, Knoxville for their excellent service throughout the course of my degree. I would especially like to thank Dana Bryson, Linda Robinson and Melanie Kelley for helping me with useful information and reimbursement procedures. I am grateful to have had the opportunity to work with wonderful people during my graduate studies. I would like to extend my gratitude to Md Sakib Hasan, Md. Badruddoja Majumder, Samira Shamsir, Mohammad Habib Ullah Habib, Khandaker Abdullah Al Mamun, Ava Hedayatipour, Shaghayegh Aslanzadeh, George Niemela, Sagarvarma Sayya- paraju, Mohammad Aminul Haque and Sherif Amer. Finally, I would like to thank my family and friends for their support throughout different phases in life. These people made me the person I am today. This work would not have been possible without their endless love, support and kindness. iv Abstract Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions in order to meet the area, power and performance specifications of the systems. The additional circuitry required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete- time chaos-based systems to address multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo- random numbers (PRN) for cryptographic applications. The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator or analog-to-digital converter in order to build logic gates or generate PRNs. The chaos- based logic gate is reconfigurable since parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are iteration number, control input, bifurcation parameter and threshold voltage of the comparator. The proposed PURCS system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication v mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a physical unclonable function (PUF). The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices. vi Table of Contents 1 Introduction1 1.1 Motivation and Research Goals.........................1 1.1.1 Chaos-based Logic Gates and Functionality Space...........1 1.1.2 Random Number Generation......................3 1.1.3 IC Counterfeiting.............................3 1.1.4 Authentication..............................5 1.1.5 Physically Unclonable and Reconfigurable System...........6 1.2 Dissertation Overview..............................6 2 Background7 2.1 Introduction to Chaos Theory..........................7 2.1.1 Classification of Chaotic Map......................8 2.1.2 Study of Chua's Circuit.........................8 2.2 Introduction to Chaos Computing........................ 11 2.2.1 Continuous-time Nonlinear System................... 13 2.2.2 Discrete-time Nonlinear System..................... 16 2.2.3 Digital Logic Obtained by Varying Iteration Number......... 19 2.2.4 Distinguishing Between (0,1) and (1,0) Input Pairs.......... 20 2.2.5 Design of Multi-Input Multi-Output Logic Functions......... 21 2.3 Concluding Remarks............................... 22 3 Design of Chaotic Oscillator and Chaos-Based Logic Gate Using Three Transistor Chaotic Map 24 vii 3.1 Design of Chaotic Map.............................. 25 3.1.1 DC Transfer Characteristics of the Map................ 26 3.2 Design of Chaotic Oscillator........................... 27 3.2.1 Iterating through the Map........................ 30 3.2.2 Sensitivity to Initial Condition...................... 30 3.2.3 Ergodicity of the Chaotic Map...................... 30 3.2.4 Bifurcation Diagram........................... 31 3.2.5 Lyapunov Exponent........................... 31 3.3 Reconfigurable Chaos-based Logic Gates.................... 33 3.3.1 Introduction................................ 33 3.3.2 Design of Reconfigurable Chaos-based Gates.............. 35 3.3.3 Complex Functions Obtained Using Single Chaotic Element..... 40 4 Expansion of Functionality Space Using Three Transistor Chaotic Map 45 4.1 Introduction.................................... 45 4.2 Expansion of Design Space............................ 46 4.2.1 Comparison of Area and Power Overhead................ 47 4.2.2 Design Space Enhancement....................... 49 4.3 Application.................................... 52 5 Four Gate Transistor Negative Differential Resistance (NDR) Based Discrete-Time Chaotic Map 53 5.1 Background.................................... 53 5.2 Four Terminal Transistor (G4FET)....................... 54 5.2.1 G4FET Operation............................ 56 5.3 G4FET Based Negative Differential Resistance................. 59 5.4 G4NDR Based Chaotic Map........................... 61 5.4.1 Design of Chaotic Oscillator Using G4NDR Based Map........ 62 5.4.2 Bifurcation Diagram and Lyapunov Exponent............. 62 5.5 Design of Logic Gates Using G4NDR Based Map................ 63 5.6 Expansion of Design Space Using G4NDR Map................ 63 viii 6 Pseudo-Random Number Generation (PRNG) Using Three Transistor Chaotic Map 71 6.1 Introduction.................................... 71 6.2 True Random Number Generator (TRNG)................... 72 6.3 Pseudo-Random Number Generator (PRNG).................. 73 6.3.1 Linear PRNG............................... 74 6.3.2 Nonlinear PRNG............................. 74 6.4 Proposed Lightweight and Reconfigurable PRNG............... 75 6.4.1 Chaotic Oscillator for PRNG Design.................
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