Electrical and Thermal Design of High Efficiency and High Power Density Power Converters

Home , Power rating

Andrew Yurek

A thesis submitted to the Department of Electrical and Computer Engineering

In conformity with the requirements for

the degree of Master of Applied Science

Queen’s University

Kingston, Ontario, Canada

(January 2020)

Abstract

This thesis investigates high power density power converters from two approaches: electrical circuit and module design, and thermal management and mitigation. Three specific topics are studied in this thesis: Point-of-Load (POL) power module packaging, thermomechanical structures for high power density power converters, and single-stage resonant converters with Power Factor

Correction (PFC) for the Electric Vehicle (EV) On-Board Charging (OBC) application.

A new POL power module packaging structure called Power-System-in-Inductor (PSI2) is analyzed against traditional plastic packaging. PSI2 promises lower loss and higher package thermal conductivity by replacing a traditional plastic casing with the magnetic inductor core.

Thermal analysis and FEA thermal simulation are conducted to verify the new packaging technology. Identical buck power modules are developed and tested experimentally. Simulation and experimentation show the PSI2 package achieves 2.68% greater efficiency, 0.51W less loss, and 26˚C lower top temperature compared to the traditionally plastic packaged module. Thermal conductivity of the PSI2 package accounts for about 33% of the improved thermal performance.

A new thermomechanical structure is proposed named Integrated Multi-Layer Cooling (IMLC).

The IMLC structure uses multiple-PCB layers, integrated active liquid cooling, and component sorting to achieve increased power density while maintaining thermal performance compared to a traditional single-PCB liquid cooled structure. FEA thermal simulation and experimentation with an EV Low-Voltage DC converter (LDC) show the IMLC structure achieves a 46°C peak temperature rise decrease and 0.6% improved efficiency over air cooled designs. Additionally, power density is improved by 31% compared to a single-PCB liquid cooled design.

A single-stage LLC converter with PFC is designed for use in the EV OBC application. This topology promises improved power density, lower loss, and less complexity compared to traditional two-stage PFC designs by removing one switching converter stage. The circuit schematic and PCB layout are designed to achieve maximum power density and minimum loss.

Simulation and experimental verification are conducted to verify the electrical performance and high-power density of 2.3kW/L of this topology. A high-power density, 1.65kW single-stage LLC

OBC experimental prototype is designed which achieves 99.1% power factor and 96.9% efficiency at 1.47kW operation.

Acknowledgements

I am eternally grateful to have had the opportunity to study under Dr. Yan-Fei Liu. His supervision has been nothing short of excellent. He has always provided support and guidance in my studies and has pushed me to become a better student and person. I have greatly appreciated his generosity, compassion, and humor and aspire to possess these qualities myself. I will always look back fondly on the time I have spent under his guidance.

I am additionally grateful for the colleagues I have had the opportunity to work with. My colleagues Dr. Yang Chen, Dr. Xiang Zhou, Wenbo Liu, Sam Webb, Bo Sheng, Mojtaba

Forouzesh, Binghui He, and Richard Sun have been a pleasure to work with and have helped to teach and guide me in my research. I have appreciated their friendships and the time I have spent with them in the lab and at conferences.

I am finally grateful for my family and friends for providing so much for me and supporting me along the way. I am very privileged to have had the opportunity to study at Queen’s University and acquire a higher education. I could not have achieved any of my success by myself. I am forever grateful for the family I have.

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Table of Contents

Abstract ...... i Acknowledgements ...... iii List of Figures ...... vii List of Tables ...... x Introduction and Purpose of Research ...... 1 1.1 Introduction ...... 1 1.1.1 Power Modules and Packaging ...... 1 1.1.2 Thermomechanical Design of Power Converters ...... 3 1.1.3 Power Converters in Electric Vehicle Applications ...... 4 1.2 Thesis Objective ...... 6 1.3 Thesis Outline ...... 7 Thermal and Electrical Analysis of Power-System-in-Inductor (PSI2) Technology ...... 9 2.1 Introduction ...... 9 2.2 Literature Review ...... 10 2.2.1 Power-Supply-in-Inductor and Integrated Power Modules ...... 10 2.2.2 Principles of Thermal Modeling ...... 13 2.3 Structure of Integrated PSI2 Technology ...... 18 2.3.1 Power Module Design and Fabrication ...... 18 2.4 Thermal Equivalent Circuit (TEC) Modeling ...... 21 2.4.1 Loss Analysis ...... 21 2.4.2 Thermal Equivalent Circuit Model Analysis ...... 23 2.5 FEA Thermal Simulation ...... 26 2.5.1 FEA Simulation, 8A Load Test ...... 27 2.5.2 FEA Simulation, 3W Constant Loss Test ...... 28 2.5.3 Summary of Simulated Results ...... 30 2.6 Experimental Results ...... 31 2.6.1 Test Setup and Conditions ...... 31 2.6.2 Constant Current Tests ...... 31 2.6.3 Constant Loss Tests ...... 36 2.6.4 Analytical Versus Experimental Results ...... 40 2.7 Conclusion ...... 40 Integrated Multi-Layer Cooling (IMLC) Structure for High Power Density Converters ...... 42

3.1 Introduction ...... 42 3.2 Literature Review ...... 43 3.3 Structure of IMLC ...... 47 3.3.1 Power Converter for Testing ...... 47 3.3.2 IMLC Structure ...... 49 3.4 Loss Analysis and Thermal Modeling ...... 54 3.4.1 Loss Analysis ...... 54 3.4.2 PCB Thermal Modeling ...... 59 3.5 FEA Thermal Simulation ...... 64 3.6 Experimental Results ...... 70 3.6.1 Test Setup and Conditions ...... 70 3.6.2 Single Phase Thermal Comparison ...... 72 3.7 Conclusion ...... 78 Single-Stage AC-DC Converter with Power Factor Correction Using LLC Resonant Converter for EV Applications ...... 79 4.1 Introduction ...... 79 4.2 Literature Review ...... 81 4.3 Design and Analysis of Single-Stage LLC for PFC Operation ...... 85 4.3.1 Single-Stage Mathematical Design ...... 86 4.3.2 LLC Parameters and Component Selection ...... 90 4.4 Simulation of Topology ...... 90 4.4.1 DC-DC LLC Stage Simulation ...... 91 4.4.2 AC-DC PFC Simulation...... 95 4.5 Prototype Circuit Design and Fabrication ...... 98 4.5.1 LLC Control Block Diagram ...... 98 4.5.2 Input Current Sensing Design ...... 99 4.5.3 Input Voltage Sensing Design ...... 103 4.5.4 PCB Layout Design of AC Power Loop ...... 105 4.5.5 Double Line Frequency Output Capacitor Design ...... 108 4.6 Experimental Results ...... 112 4.6.1 Experimental Prototype...... 112 4.6.2 DC-DC LLC Test ...... 112 4.6.3 AC-DC PFC Testing ...... 117 4.7 Conclusion ...... 121

Conclusion and Future Work ...... 123 5.1 Conclusion ...... 123 5.2 Future Work ...... 125

List of Figures

Fig. 1.1. Power module using integrated NextFET MOSFET integration [4]...... 2 Fig. 1.2. Air cooled solution for a power converter [7]...... 3 Fig. 1.3. A block diagram of a typical liquid cooling system [8]...... 4 Fig. 1.4. Electric vehicle electrical architecture...... 5 Fig. 1.5. Block diagram of two stage AC-DC converter...... 6 Fig. 2.1. Power module using integrated LTCC magnetics [26]...... 11 Fig. 2.2. Structure of power module using traditional plastic packaging [2]...... 12 Fig. 2.3. Structure of power module using PSI2 packaging [2]...... 13 Fig. 2.4. Continued fraction thermal circuit model [41] [42]...... 15 Fig. 2.5. Partial fraction thermal circuit model [41] [42] [43]...... 16 Fig. 2.6. Simplified thermal circuit model [44]...... 17 Fig. 2.7. PCB structure of power modules with cases removed...... 19 Fig. 2.8. PSI2 (top) and Plastic (bottom) PCB modules, not populated...... 20 Fig. 2.9. Fabricated power modules with PSI2 and plastic package inductor...... 20 Fig. 2.10. Testing board with PSI2 package mounted...... 21 Fig. 2.11. Thermal equivalent circuit models...... 25 Fig. 2.12. Surface temperatures in FEA thermal simulation, constant 8A load...... 28 Fig. 2.13. Junction temperatures in FEA thermal simulation, constant 8A load...... 28 Fig. 2.14. Surface temperatures in FEA thermal simulation, constant 3W loss...... 29 Fig. 2.15. Junction temperatures in FEA thermal simulation, constant 3W loss...... 30 Fig. 2.16. Comparing efficiency at different load currents...... 32 Fig. 2.17. Comparing loss at different load conditions...... 33 Fig. 2.18. Comparing top temperatures at varying load conditions...... 34 Fig. 2.19. Comparing bottom temperatures at varying load conditions...... 34 Fig. 2.20. PSI2 thermal image, 8A load...... 35 Fig. 2.21. Plastic thermal image, 8A load...... 35 Fig. 2.22. Top temperatures at different loss conditions...... 38 Fig. 2.23. Bottom temperatures at different loss conditions...... 38 Fig. 2.24. PSI2 thermal image, constant 3W loss...... 39 Fig. 2.25. Plastic thermal image, constant 3W loss...... 39 Fig. 3.1. Circuit diagrams of discrete OBC and LDC topologies [23]...... 44

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Fig. 3.2. Circuit diagram of a proposed integrated OBC and LDC topology [23]...... 44 Fig. 3.3. On-board charger for EV with integrated liquid cooling package...... 46 Fig. 3.4. A comparison of cooling methods studied in [60]...... 47 Fig. 3.5. Circuit diagram of the proposed 1.3kW LLC LDC converter...... 48 Fig. 3.6. Top view of a conventional single-PCB converter for an LLC power converter...... 49 Fig. 3.7. Front view of the IMLC structure...... 50 Fig. 3.8. Side view of the IMLC structure...... 52 Fig. 3.9. Top view of IMLC bottom PCB layer with high loss components...... 53 Fig. 3.10. Front view of IMLC structure ...... 54 Fig. 3.11. Horizontal thermal resistance of PCB...... 61 Fig. 3.12. Vertical thermal resistance of PCB...... 62 Fig. 3.13. Vertical thermal resistance of thermal vias and PCB...... 63 Fig. 3.14. Three-dimensional mechanical model for single-PCB air cooled...... 65 Fig. 3.15. Three-dimensional mechanical model for single-PCB liquid cooled...... 65 Fig. 3.16. Three-dimensional mechanical model for two-PCB IMLC...... 66 Fig. 3.17. Loss distribution for the proposed 1.3kW LLC resonant converter...... 67 Fig. 3.18. Thermal simulation of single PCB air cooled layout...... 68 Fig. 3.19. Thermal simulation of single PCB liquid cooled layout...... 69 Fig. 3.20. Thermal simulation of IMLC liquid cooled layout...... 70 Fig. 3.21. Single-PCB liquid cooled prototype...... 71 Fig. 3.22. Two-PCB IMLC prototype...... 71 Fig. 3.23. Temperature of SR MOSFETs with air cooling, 70A load...... 72 Fig. 3.24. Temperature of transformer secondary winding with air cooling, 70A load...... 72 Fig. 3.25. Temperature of SR MOSFET with air cooling, 95A load...... 73 Fig. 3.26. Temperature of SR MOSFETs with liquid cooling, 95A load...... 74 Fig. 3.27. Temperature of GaN with liquid cooling, 95A load...... 75

Fig. 3.28. Temperature of transformers (Tx) with IMLC structure, 95A load...... 76

Fig. 3.29. Temperature of resonant inductor (Lres) with IMLC structure, 95A load...... 76 Fig. 3.30. Efficiency comparison of different thermomechanical designs...... 77 Fig. 4.1. A Boost PFC converter with CLLC resonant stage for EV On-Board Charger...... 82 Fig. 4.2. A dual-boost bridgeless PFC converter with CLLC stage for EV On-Board Charger...... 82 Fig. 4.3. A half-bridge LLC resonant PFC converter for EV On-Board Charger...... 85

Fig. 4.4. A plot of the input voltage (Vin), required gain (Greq), and output power (Pout) for input voltage phase angle, θ [68]...... 87

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Fig. 4.5. Waveforms for maximum gain requirement confirming ZVS and ZCS at Vin(ac) = 200V,

Vin(θ=10°) = 49V, Vout = 430V...... 94

Fig. 4.6. Waveforms for minimum gain condition confirming ZVS and ZCS at Vin(ac) = 240V, Vin(θ=90°)

= 339V, Vout = 250V...... 95

Fig. 4.7. Vin = 200Vac, Vout = 430V, Iin(rms) = 8.46A, PF = 99.3%, THD = 4.7%...... 96

Fig. 4.8. Vin = 220Vac, Vout = 330V, Iin(rms) = 7.77A, PF = 98.9%, THD = 3.53% ...... 97 Fig. 4.9. Single-stage LLC PFC converter control block diagram...... 98 Fig. 4.10. Circuit diagram showing the location of the Hall sensor for input current sensing...... 100 Fig. 4.11. Signal waveform of Hall sensor...... 100 Fig. 4.12. Circuit diagram of the hall sensor for current sensing...... 102 Fig. 4.13. Current sensing waveform after RC filter circuit...... 102 Fig. 4.14. Sensed current signal waveform...... 103

Fig. 4.15. Sensing location of input voltage Vrec...... 104 Fig. 4.16. Input voltage sensing circuitry...... 104 Fig. 4.17. PCB layout design for the LLC converter operating in the positive half cycle...... 106 Fig. 4.18. PCB layout design for the LLC converter operating in the negative half cycle...... 107 Fig. 4.19. LLC PFC prototype power loop PCB design...... 108

Fig. 4.20. Signal waveforms of the output power and resulting Cout voltage...... 109 Fig. 4.21. Prototype with the electrolytic capacitor bank highlighted...... 111 Fig. 4.22. Full experimental prototype of the single-stage AC-DC LLC resonant converter with PFC for the EV OBC application...... 112

Fig. 4.23. Waveforms for Vin(θ=45°) = 200VDC, Vout = 250V, Iout = 5A, Pout = 1.25kW...... 114

Fig. 4.24. Waveforms for Vin(θ=45°) = 200VDC, Vout = 330V, Iout = 5A, Pout = 1.65kW...... 115

Fig. 4.25. Waveforms for Vin(θ=10°) = 49VDC, Vout = 250V, Pout = 75W...... 116

Fig. 4.26. Waveforms for Vin(θ=10°) = 49VDC, Vout = 380V, Pout = 100W...... 117

Fig. 4.27. Waveforms for Vin = 220Vac, Vout = 250V, Iout = 4.604A, Pout = 1.15kW, PF = 99.3%, Efficiency = 96.9%...... 118

Fig. 4.28. Waveforms for Vin = 225Vac, Vout = 320V, Iout = 4.69A, Pout = 1.474kW, PF = 99.1%, Efficiency = 96.9%...... 119

Fig. 4.29. Thermal image of GaN devices at Vin = 225Vac, Vout = 320V, Pout = 1.474kW...... 120

Fig. 4.30. Waveforms for Vin = 230Vac, Vout = 375V, Iout = 4.04A, Pout = 1.515kW, PF = 98.6%, Efficiency = 96.6%...... 121

List of Tables

Table 2.1. Electrical circuit properties used to represent thermal properties...... 14 Table 2.2. Device specifications for the tested POL converters...... 19 Table 2.3. Thermal equivalent circuit model parameters...... 24 Table 2.4. Loss data for thermal equivalent circuit model...... 24 Table 2.5. Material thermal conductivity...... 27 Table 2.6: Analytical TEC and FEA simulation results for 3W constant loss...... 30 Table 2.7: Experimental results of PSI2 versus plastic power modules...... 36

Table 2.8: Module temperatures at 3W loss, Vin=24V, Vout=1.5V...... 40 Table 3.1: LLC Power converter operating parameters...... 48 Table 3.2. A summary of the 1.3kW LLC estimated losses ...... 59 Table 3.3. Horizontal and vertical thermal conductivities for FEA thermal simulation...... 64 Table 4.1. Parameters designed for the single-stage LLC converter...... 90

Table 4.2. Fixed DC-DC operating conditions at maximum gain condition. Vin = 200Vac, Vout = 430V, Pout = 1.65kW...... 92

Table 4.3. Fixed DC-DC operating conditions at minimum gain condition. Vin = 200Vac, Vout = 250V, Pout = 1.25kW...... 93

List of Symbols

A Effective area of magnetic core

Bpk Magnetic flux density – peak

Cm Magnetic temperature coefficient

Cout Output capacitor

Cres Resonant capacitor

Cth Thermal capacitance

d Heat path length

Ediss Capacitor discharge energy

Fr1 Series resonant frequency

Fr2 Parallel resonant frequency

Fsw Switching frequency

g Effective contact area

Greq Required gain

Iac AC current

Ic Capacitor current

Iout Output Current

Ipk Peak current

Iref Current reference signal

Ires Resonant current

Isec Secondary side current

Isense_LF Filtered current sensing signal

K Ratio of magnetizing inductance to resonant inductance

Kac AC winding resistance coefficient

Keq Equivalent thermal conductivity

Keq_horizontal Equivalent horizontal thermal conductivity

Keq_vertical Equivalent vertical thermal conductivity

Keq_via Equivalent vertical thermal conductivity with thermal vias

Kisns Input current sensing gain coefficient

Kvsns Voltage sensing signal gain

L Inductance

Le Core length

Lp Parallel inductor

Lres Resonant inductor

N Number of turns n Transformer turns ratio

Pciss Input capacitance switching loss

Pcore Core loss

Pcoss Output capacitance switching loss

PIC IC loss

Pin Input power

Pout Output power

Ptotal Total loss

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Pv Core loss character

Pwinding Magnetic winding loss q Heat generated

Q Quality factor

Qrated Rated quality factor

Rac FHA output resistance

Ramb PCB to ambient resistivity

Rchip Chip junction to case resistivity

Rconduction Conductive thermal resistance

Rdson Resistance of device when turned ON

Req_horizontal Equivalent horizontal thermal resistance

Req_vertical Equivalent vertical thermal resistance

RPCB PCB resistivity

Rth Thermal resistance

Rwinding Winding resistance t Material thickness

Tamb Ambient temperature

Tcase Case temperature

Tjunc Junction temperature

Tx Transformer

Vac AC voltage

VDS Drain-to-source voltage of switch

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Verr Output voltage error signal

VGS Gate-to-source voltage of switch

VH_bias Hall sensor bias voltage

VHall Hall sensor output signal

Vin Input voltage

Vout Output voltage

Vrec Rectified voltage signal

Vrec_sense Filtered voltage sensing signal

θ Phase angle

휆 Output voltage ratio

∆E Extra energy stored in capacitor

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List of Abbreviations

AC Alternating current

CAD Computer aided design

CLLC Resonant converter with series inductor and capacitor, one parallel

inductor on primary and secondary side

CPU Central processing unit

Cuk A type of DC-DC switching converter

DC Direct current

DCR DC resistance

DSC Dual-sided cooling

EV Electric Vehicle

FEA Finite element analysis

FHA Fundamental harmonic approximation

GaN Gallium Nitride

HEMT High-electron-mobility transistor

HV High voltage

IC Integrated circuit

IGBT Insulated-gate bipolar transistor

IMLC Integrated multi-layer cooling

LDC Low-voltage DC converter

LLC Resonant converter with series inductor and capacitor, one parallel

inductor

LTCC Low temperature co-fired ceramic

MCU Micro-controller unit

MOSFET Metal-oxide-semiconductor field-effect transistor

OBC On-board charger

PCB Printed circuit board

PEV Plug-in electric vehicle

PF Power factor

PFC Power factor correction

PHEV Plug-in hybrid electric vehicle

PI Proportional-integral controller

POL Point-of-load

PSI2 Power-supply-in-inductor

PSIM Circuit simulation tool

PWM Pulse width modulation

RC Resistor-capacitor

RMS Root mean squared

SEPIC A type of DC-DC converter

SiC Silicon carbide

SR Synchronous rectifier

TEC Thermal equivalent circuit

THD Total harmonic distortion

V2H Vehicle to home

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WBG Wide bandgap

ZCS Zero current switching

ZVS Zero voltage switching

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Introduction and Purpose of Research

This chapter introduces the research topics studied in this thesis. Current literature focusing on the thesis topics is discussed to provide context and a basis of comparison. Current power module designs, structures, and analyses in literature are introduced. Thermomechanical designs and structures are discussed for electric vehicle applications. Current electric vehicle On-Board

Charger topologies in industry and academia are discussed.

1.1 Introduction

1.1.1 Power Modules and Packaging

Integrated power modules are desired for their high-power density, small size, and simple functionality. Industry and academic efforts have been focused on increasing power density of power converters by increasing power ratings and decreasing size. Specific attention has been given to Point-of-Load (POL) devices used in consumer electronics, data centers, server applications, and other applications with high power density demands and difficult thermal challenges. Power modules are critical in industries such as aerospace and automotive to handle power conversion and control [1]. Power modules offer simple DC-DC conversion for a designer without the additional complexity that accompanies discrete DC-DC converter design.

Additionally, power modules offer reliable and robust performance [2].

To achieve the desired power density objectives, integration techniques have been developed to reduce size and increase power density. Active and passive integration methods are studied in literature [3]. Active integration methods include interconnection modifications, packaging

material changes, and module integration. Passive methods include magnetic integration and studies into Low Temperature Co-fired Ceramic (LTCC) devices. An example of an active integration method is shown in Fig. 1.1 below. This technology is known as NextFET, which integrates the discrete MOSFET with the controller IC to reduce package volume by roughly 50% compared to a traditional power module [4].

Fig. 1.1. Power module using integrated NextFET MOSFET integration [4].

Further study has been conducted on new POL topologies to achieve smaller size and lower loss. To achieve smaller size, switching frequency must be increased to overcome the size limitation of the power magnetic devices. Typical POL converters today use non-isolated DC-DC converters in step-down configurations to accommodate the low voltage application of most POL devices. Such devices include CPU or server applications, which can demand power above 100W and therefore require advanced cooling techniques [5]. Research into new wide bandgap devices

(WBG) such as GaN and SiC devices has been conducted to increase switching frequency and reduce switching loss in power modules [6].

1.1.2 Thermomechanical Design of Power Converters

The thermomechanical design of power converters is critical in achieving reduced size while managing thermal dissipation. Most research has focused on developing heat transfer methods to improve cooling to allow for higher loss components. Such designs include active air and liquid cooling methods to achieve improved heat transfer. Typical air-cooling designs incorporate finned air cooling to increase conductive heat transfer surface area. An example air cooling solution with finned heat sinks and fan cooling is shown in Fig. 1.2 below based on work in [7].

Fig. 1.2. Air cooled solution for a power converter [7].

To improve heat transfer further, liquid cooling solutions are developed. These solutions provide direct contact liquid cooling, typically through surface contact of cold plate heatsinks. For

Electric Vehicle (EV) applications, liquid cooling is preferred as the radiation in automobiles

already are incorporated into the mechanical design of the vehicle. A block diagram of a typical liquid cooling system is shown below in Fig. 1.3 based on work in [8].

Fig. 1.3. A block diagram of a typical liquid cooling system [8].

1.1.3 Power Converters in Electric Vehicle Applications

Industry and academic research have placed emphasis on developing high-power density power converters for medium power applications. A significant motivation for this focus is the recent development of electric vehicles in consumer transportation. Within this field, research has been conducted to design new On-Board Charger (OBC) power converters for charging vehicles in the level 1 and level 2 charging standards [9]. OBCs are converters built into the vehicle which convert standard AC grid power to high power DC voltage for electric vehicle high voltage battery charging. Level 1 and 2 charging typically operate between 1.9kW to 19.2kW power levels and are designed for use in public or private settings [10]. Off-board charging is available typically in commercial settings due to large capital investment and demand for fast charging. A typical electric vehicle architecture is shown in Fig. 1.4 below. The AC OBC and off-board DC fast 4

charger are shown as two different grid-based charging methods. Research has also focused on the on-board Low-Voltage DC-DC charger (LDC) for charging the auxiliary battery from the high- voltage battery pack. The LDC is responsible for converting 400VDC voltage of the high voltage battery pack to the 14VDC auxiliary battery pack. This converter is shown in Fig. 1.4 below.

LDC

OBC

Off-Board

Fig. 1.4. Electric vehicle electrical architecture.

The electrical design of OBC and LDC converters has focused on topology design to improve efficiency, lower component count, and increase switching frequency to thereby decrease size.

Different topologies have been studied to achieve these objectives. A typical OBC topology consists of two distinct switching stages: an AC-DC PFC stage to convert the AC voltage to a loosely regulated DC voltage and achieve PFC at the grid side, and a second stage DC-DC converter to provide regulated DC voltage to the load. A block diagram of a two-stage PFC converter is shown in Fig. 1.5 below. A typical two-stage topology is the bridgeless totem pole

PFC CLLC converter, which uses a bridgeless boost converter for the AC-DC stage, and a CLLC converter for the DC-DC stage [11] [12] [13]. Some of these designs use Silicon Carbide devices 5

to improve efficiency [14] [15] [16]. Some research has been conducted on a single-stage PFC design to reduce switching components and therefore significantly reduce size and loss [17] [18]

[19].

+ Clink Stage 1 Stage 2 Cout Vac EMI Filter Rectifier Vout Converter Converter -

AC-DC Stage DC-DC Stage

Fig. 1.5. Block diagram of two stage AC-DC converter.

Research has also been conducted on the LDC power converter to improve the power conversion from the high voltage battery pack to the low voltage auxiliary battery. Research has focused on improving the size, efficiency, and loss of the LDC converters to increase power density. Proposed solutions include integrating the LDC with the OBC to share switching devices and reduce size [20] [21] [22] [23]. Various topologies are proposed to improve the device performance or achieve integration. One proposed solution proposes utilizing a flyback and boost converter to achieve LDC conversion [24]. Improving the OBC and LDC topologies allow for reduction in size, cost, and weight for the competitive electric vehicle market.

1.2 Thesis Objective

This thesis is written to explore new high-power density power converters based on electrical and thermal design improvements. Firstly, a detailed electrical and thermal investigation into integrated power module packaging technologies for high power density POL applications is studied. Secondly, a novel multi-PCB, liquid cooled thermomechanical structure is proposed for high power DC-DC converter applications. Finally, design, simulation, fabrication, and

experimentation with a single-stage LLC converter with PFC is conducted for EV OBC applications. This thesis focuses on detailed electrical and thermal design and analysis of high- power density power converters.

1.3 Thesis Outline

This thesis is organized into five chapters. The chapters are outlined as follows.

Chapter 1 introduces the purpose of the thesis and related research and study pertaining to the thesis. This chapter also states the objective of the thesis and outlines the structure of the thesis.

Chapter 2 analyses a new POL packaging structure for integrated power modules called Power-

System-in-Inductor (PSI2) technology. This design is proposed to replace traditional plastic packaged POL modules by replacing the plastic with the magnetic inductor core of the power module power inductor. The objective of this design is to reduce power inductor loss and improve thermal dissipation through the metal module packaging. Identical power modules are designed in plastic and PSI2 packages. FEA thermal simulation is conducted to compare the thermal performance of both packages. Experimental testing is conducted to examine the efficiency, loss, and thermal performance of the PSI2 package.

Chapter 3 proposes a new thermomechanical power converter structure called Integrated Multi-

Layer Cooling (IMLC). This structure is proposed for medium power, high power density DC-DC power converters for electric vehicle applications which require active liquid cooling while maintaining minimal package size. The IMLC structure is designed with multiple PCBs, component sorting by loss, and bottom side active liquid cooling to improve the electrical PCB layout and mechanical power converter structure. Thermal modeling and FEA thermal simulation are performed on a traditional single-PCB LDC power converter with air-cooling and liquid

cooling versus the new IMLC structure. A prototype power converter is constructed using a single

PCB design and the IMLC structure to verify thermal and electrical performance.

Chapter 4 discusses the application of a single-stage AC-DC LLC resonant converter with PFC for use in EV OBC applications. Design and analysis of the single-stage LLC converter for PFC is conducted based on past research. Simulation is conducted for fixed DC-DC and closed loop

AC-DC PFC operation to verify the feasibility of the topology. A circuit schematic and PCB layout are designed including critical power loop and control loop design considerations. Experimental testing is conducted on the LLC prototype to verify feasibility of the topology for the OBC application.

Chapter 5 concludes the contributions and accomplishments presented in this thesis and outlines future research goals.

Thermal and Electrical Analysis of Power-System-in-Inductor (PSI2)

Technology

2.1 Introduction

Thermal management and loss mitigation are primary design considerations for high density power modules such as Point-of-Load (POL) converters. Module package size is increasingly reduced which poses a challenge to reduce and mitigate thermal generation. Studying POL converters offers insight into the mechanical and thermal design of power converters applicable to any power rating or device application.

The primary challenge in designing POL converters is removing heat from the device package to ambient. Heat is generated in POL converters through DC and AC losses. DC losses are primarily attributed to conduction loss of power components. AC losses are primarily attributed switching losses in MOSFETs and magnetic components. These losses become more dominant as switching frequency increases in pursuit of reducing magnetic device size. For high power density converters, switching frequency is increased to decrease magnetic component size and therefore overall package size. Consequently, package surface area decreases, thereby reducing module thermal conductivity to ambient. Additionally, traditional plastic packaging of power modules suffers from low thermal conductivity which traps heat within the package. The loss must be reduced to minimize module size, lower component cost, and decrease the required thermal dissipation. The remaining heat generated by the loss must be dissipated through the POL package to avoid damaging the device.

The PSI2 package is designed to address the loss and thermal challenges faced by POL converters. The PSI2 package accomplishes these objectives by replacing the traditional plastic packaging with the magnetic core of the converter power inductor. This design allows for the size of both the winding and core of the inductor to increase, thereby decreasing winding and core losses. Additionally, the magnetic core improves the package thermal conductivity compared to plastic, thereby improving thermal dissipation.

This chapter is organized into the following three sections: Section 2.2 reviews current academic literature, Section 2.3 describes the structure the PSI2 technology including design and device fabrication, Section 2.4 presents the loss estimation and thermal equivalent circuit (TEC) model used to predict and compare the thermal performance of the plastic and PSI2 packages,

Section 2.5 presents the FEA thermal analysis of both package types, Section 2.6 presents the experimental loss and thermal results for both fabricated modules, and Section 2.7 concludes the chapter.

2.2 Literature Review

This section describes current integrated power module designs for high power density applications with thermal management challenges.

2.2.1 Power-Supply-in-Inductor and Integrated Power Modules

POL converters are used today in spatially and thermally constrained applications due to their high-power density and versatile design. Academic and industry have focused on developing high power density packages that utilize the 3D space of a power module through package integration and new passive component technology [4] [25] [26]. Such methods include passive component integration into PCB substrates [27] [28] and Power-Supply-in-Inductor [2] [29]. At very low

power, the inductor has been integrated into the substrate of the PCB to achieve integrated power delivery [30]. Low Temperature Co-fired Ceramic (LTCC) is used to integrate power supplies and inductors at high power [31]. An example integrated power module with LTCC is shown in Fig.

2.1 below based on work in [26].

Fig. 2.1. Power module using integrated LTCC magnetics [26].

A critical consideration in designing high power density POL converters is thermal management and heat transfer [32]. To design such packages, research has focused on different thermal modelling and analysis methods to predict the performance of module packages. Such methods include accurately estimating loss values considering switching loss, gate driving loss, conduction losses which are studied in [33] [34]. Additionally, significant research has focused on simulating device performance through analytical or FEA methods. In [35] [36], thermal impedance networks are developed for multi-layer IGBT converters. In [37] [38], FEA and thermal tests are performed and compared for accuracy.

Recent research has focused on developing a new packaging method called Power-System-in-

Inductor (PSI2). The PSI2 design integrates a POL power module by using the core of the power inductor to encapsulate the power module [2] [29] [39]. This package is designed to increase power

density, improve converter loss, and manage thermal challenges faced by POL converters. Under the PSI2 design, the plastic packaging that traditionally packages the power module is replaced with the magnetic inductor core. The structure of a traditional plastic packaged power module is show below in Fig. 2.2.

Fig. 2.2. Structure of power module using traditional plastic packaging [2].

The PSI2 package allows for the core and winding of the power inductor to increase. This allows for larger inductor windings which reduces winding resistance through decreased DC resistance

(DCR). The increase in inductor size also offers a higher attainable inductance value with the same module volume. Additionally, the thermal conductivity of the package casing is increased due to the conductivity of ferrite material versus plastic. Therefore, the PSI2 package offers reduced heat generation while improving heat transfer. Finally, PSI2 maintains package size compared to its plastic counterpart. The structure of the PSI2 package is shown below in Fig. 2.3.

Fig. 2.3. Structure of power module using PSI2 packaging [2].

The PSI2 package in Fig. 2.3 shows the larger inductor winding and core compared to the plastic package in Fig. 2.2.

2.2.2 Principles of Thermal Modeling

Thermal modeling provides critical prediction of power module thermal performance.

Temperature in power electronic devices plays a critical role in device performance and reliability.

Many properties of the power converter are influenced by temperature. The maximum junction temperature of most silicon devices is 125°C, above which the device will be damaged.

Additionally, temperature fluctuations in devices reduces device lifespan due to increased mechanical stress of fluctuating temperature. The ON resistance of devices, particularly power switches, increases significantly with temperature which increases both loss and device temperature. Finally, increasing temperature can decrease the threshold voltage of power switches.

This affects the reliable operation of the switch and can lead to device failure. Therefore, predicting and analyzing thermal performance are critical tools to improve device reliability, reduce loss, and manage heat generation. Various research focuses on thermal modelling to predict module performance, including work on buck power modules in [40]. The following section reviews

various Thermal Equivalent Circuit (TEC) models used to predict thermal behavior of power electronic devices.

There are several thermal equivalent circuit models to represent a power converter. Such models rely on the thermal capacities and thermal resistances of the physical materials of the power converter including PCB layers, components, solder, substrate solder, and the base plate. Thermal equivalent circuit models are created to represent thermal properties as electric circuit properties for familiarity and simplicity. A list of electrical properties for circuit modeling and the thermal properties which they represent is shown in Table 2.1 below based on work in [41].

Table 2.1. Electrical circuit properties used to represent thermal properties.

Type Electrical Property Thermal Property Represented

Particle Flow Current (A) Heat Flow (W)

Potential Voltage (V) Temperature (°C)

Resistance Resistance (Ω) Thermal Resistivity (°C/W)

Capacitance Capacitance (F) Thermal Capacitance (W•s/°C)

These parameters allow for derivation of thermal equivalent circuit models to predict power module thermal behavior. There are several thermal equivalent circuit models to represent a power module: the continued fraction circuit [41] [42], the partial fraction circuit [41] [42] [43], and a simplified circuit model [44].

The continued fraction circuit model is based on the real power module thermal resistances and capacitances. This model allows for the real properties of the PCB and components to be directly implemented into the thermal equivalent circuit on a per layer basis. Consequently, individual layer temperatures may be observed on the network nodes of the partial fraction circuit. The

structure of the continued fraction circuit model is shown in Fig. 2.4 below based on work in [41] and [42].

Tjunc Tcase

Pin Rchip Rsolder RPCB

Cchip Csolder RPCB

Tamb

Fig. 2.4. Continued fraction thermal circuit model [41] [42].

Fig. 2.4 above shows the thermal resistance (Rth) and thermal capacitance (Cth) for each layer of the device between the junction (Tjunc) and the case (Tcase). For the heat flow of a power converter heat generating device, the typical layers include the chip IC layer, solder layer, and

PCB layer which are represented above. The heat is generated through device loss. This loss is represented as current input by the current source, Pin. A constant ambient temperature is applied to the ground of the continued fraction model as Tamb. This temperature is constant for all layers of the device; therefore, it is applied as a bias to the common ground.

This model is beneficial in simulation due to the ease of assigning the material properties to the respective circuit properties. However, to mathematically analyze the transient response of the continued fraction model requires high order functions proportional to the number of RC branches.

Therefore, this model is limited to simulation only for steady-state response.

The partial fraction circuit model is the series analog to the parallel structured continued fraction model studied in [41] [42] [43]. This model incorporates parallel RC branches in series with the

junction and case temperatures instead of representing individual layers. The advantage of this model is the ability to implement the model using data collected from cooling curve testing. The resistivity (°C/W) can be observed from the temperature rise using a thermal camera or thermocouples. Similarly, the capacitance (W•s/°C) can be obtained by observing a specified temperature rise over a fixed time period. This data is also available in datasheets as cooling curves.

The derived resistance and capacitance yields equation (2.1).

푛 1 −( ) 휏 (2.1) 푍푡ℎ(푡) = ∑ 푟푖 (1 − 푒 푖 ) 푖=1

Where ri is resistivity and τi is the time constant equal to the product of resistivity and capacitance. Using equation (2.2), the junction temperature can be derived provided the power loss and case (ambient) temperature are known. The expression for junction temperature is given in equation (2.2)

푇푗(푡) = 푃(푡) ∗ 푍푡ℎ(푡) + 푇푐푎푠푒(푡) (2.2)

Based on equation (2.2). The partial fraction circuit is shown in Fig. 2.5 below. The junction temperature can be derived using equation (2.2).

Rchip Rsolder RPCB Tjunc

Pin Cchip Csolder CPCB Tcase

Tamb

Fig. 2.5. Partial fraction thermal circuit model [41] [42] [43].

The partial fraction model is advantageous to power electronic engineers for the mathematical simplicity of transient response cases. Additionally, this model provides simpler calculation when the physical properties and materials of the module is unknown and curve fitting is the best option.

For simplification of thermal analysis, a simpler model is desired. Under steady-state thermal testing, capacitance can be ignored as it will not play a role in static testing. Using the continued fraction circuit, a resistor-only model can be derived based on work in [44]. The simplified model is shown in Fig. 2.6 below.

Rchip Ramb Case

Tjunc Tcase

RPCB Ramb Pin Tamb PCB

Fig. 2.6. Simplified thermal circuit model [44].

Using the simplified model shown in Fig. 2.6, steady state thermal analysis can be achieved.

The resistivity of the chip junction to PCB (RPCB), chip junction to case (Rchip), PCB to ambient

(Ramb), and case to ambient (Ramb) are required to analyze the temperature data. These values can be estimated based on the material of the device, or by estimating the resistivity experimentally based on equation (2.3).

(푇 − 푇 ) 푅 = 퐽 퐴 (2.3) 퐽 푃

The temperature difference between the junction (Tj) and ambient (TA) and the power loss (Pin) are required to calculate resistivity. For the simplified model, the total power loss is required as the heat flow source, and the ambient temperature is required for the constant voltage potential.

2.3 Structure of Integrated PSI2 Technology

This section introduces the PSI2 power module structure and introduces the fabricated modules for both traditional plastic packaging and PSI2 packaging.

2.3.1 Power Module Design and Fabrication

Power module packaging typically consists of fixed components encapsulated in plastic epoxy packaging to provide uniform heatsinking and durability. Fig. 2.7 (a) shows the PSI2 module with the inductor core semi-transparent. Fig. 2.7 (b) shows the plastic module with the plastic package semi-transparent. The new PSI2 packaging method replaces the traditional plastic packaging with the magnetic inductor core. The remaining components of the power module are contained within the cavity of the PSI2 package magnetic core opposite the inductor winding. To thermally connect the components to the core cavity, thermal paste is applied with the same conductivity as the plastic package.

(a) Structure of PSI2 module

(b) Structure of plastic module

Fig. 2.7. PCB structure of power modules with cases removed.

Synchronous buck power modules with constant on-time are used for testing the packaging design. Additional module components consist of two synchronous MOSFETs, an inductor, and passive components. The fixed inductor of the plastic package is selected based on the parameters defined by the PSI2 inductor. The same size restrictions are made for both packages. The dimensions of the PSI2 package are defined as 15mm x 9mm x 3mm. The plastic package must use a fixed inductor with a 2mm maximum height to achieve the same package volume after epoxy coating is complete. The electrical parameters of the fixed inductor are also selected to be the same as the PSI2 inductor. The maximum current saturation rating is selected at 9.6A. The inductance for both packages is selected at 1uH. The selected fixed inductor has 17.2 mΩ DCR and meets the spatial constraints defined by the PSI2 package. Table 2.2 shows the testing parameters for simulation and experimentation.

Table 2.2. Device specifications for the tested POL converters.

Topology Input (V) Output (V) Full Load (A) Tambient (˚C)

Synchronous 12, 24 1.5 8 22 Buck Converter

The fabricated PCB’s of both packages are identical, except for larger inductor footprints of the plastic package on the top side to accommodate the fixed inductor. Power planes contain thermal vias to transfer heat to the bottom side of the board more effectively. The PSI2 inductor is soldered on last to encapsulate the components. Fig. 2.8 shows the fabricated power modules PCBs. This highlights the increased inductor footprint size of the plastic package. Fig. 2.9 (a) shows the populated plastic power module with the plastic cover removed for visibility. In Fig. 2.9 (b) the

PSI2 cavity inductor is shown which encapsulates the module shown in (a) with the fixed inductor replaced by the cavity inductor.

Fig. 2.8. PSI2 (top) and Plastic (bottom) PCB modules, not populated.

(a) Plastic module with fixed inductor (b) PSI2 cavity inductor

Fig. 2.9. Fabricated power modules with PSI2 and plastic package inductor.

Testing boards are used to mount both modules. These boards provide an interface for the modules to accommodate larger passive components such as large capacitors and lower tolerance resistors. Additionally, the mounting board acts as a heatsink for the bottom side surface of the power modules. The testing board with the PSI2 module highlighted in red is shown in Fig. 2.10 below.

Fig. 2.10. Testing board with PSI2 package mounted.

Once the modules are mounted to the testing board, the epoxy is poured onto the plastic package using a small plastic mold to encapsulate the plastic module.

2.4 Thermal Equivalent Circuit (TEC) Modeling

This section introduces the loss analysis and TEC modeling of both the PSI2 and plastic modules to estimate thermal performance.

2.4.1 Loss Analysis

The power loss of the modules must be calculated to model the thermal performance of each package. To ensure fair results, the loss of both converters is fixed at 3W. The distribution of loss is not equal for both packages, however, as the winding losses and operating frequency are not

equal for both converters at the same total loss. For the buck power modules, the primary loss generating components are the core loss, winding loss, and IC loss. ANSYS Maxwell electromagnetic simulation is used to calculate core loss. The inductance, turns, core area, and the waveform of the winding current are required to simulate core loss. The waveforms of the B field and core loss of the inductor are obtained using electromagnetic simulation. The winding current is obtained by applying the inductor voltage waveform to the winding input terminals. The core loss character, Pv, is calculated using the Steinmetz equation shown in equation (2.4) below.

푥 푦 푃푣 = 퐶푚퐵푝푘푓 (2.4)

The Steinmetz coefficients are estimated from the core material, where Cm is the temperature coefficient, B is magnetic flux density, and f is frequency. The exponentials x and y are estimated by curve fitting from the core material datasheet. The final core loss for the given inductor volume is calculated using equation (2.5), where A is core area and Le is the core length. The calculated core loss for both packages is shown in Table 2.4. Since core loss is relatively small and close to the same for both packages, the calculated core loss is the same for both inductors.

푃푐표푟푒 = 푃푣퐴퐿푒 (2.5)

The winding loss is an additional primary loss generator. Winding loss is a conduction loss calculated using equation (2.6).

2 푃푤푖푛푑푖푛𝑔 = 퐼표푢푡푅푤푖푛푑푖푛𝑔 (2.6)

The output current, Iout, is obtained experimentally for each package to achieve 3W loss. The winding resistance (DCR) is defined for each inductor. The DCR for the PSI2 package is 12mΩ.

The DCR of the plastic package fixed inductor is 17mΩ. Skin effect is an AC factor that effects winding resistance. Additionally, temperature also effects winding resistance. The DCR is

measured at full load switching frequency to estimate real resistance using impedance measuring equipment. The PSI2 resistance is measured at 15mΩ and plastic is 21mΩ under these conditions.

The temperature coefficient is estimated at 1.5 for both inductors. The calculated winding loss of both packages are shown in Table 2.4 below.

The final key loss contributor is due to the power modules’ IC. The key contributor to thermal generation in the IC is the integrated switching MOSFETs. MOSFET loss consists of switching and conduction loss. Since the power modules operate with hard switching, switching loss is dominant and dependent on operating frequency. The same IC is used in both converters, therefore differences in IC loss only depends on the frequency dependent switching loss. The loss of IC was estimated as the remaining amount of total loss after accounting for core and winding loss. The estimated IC loss of both packages is shown in Table 2.4 below.

2.4.2 Thermal Equivalent Circuit Model Analysis

To analytically estimate the thermal performance of PSI2 and plastic package, a thermal equivalent circuit model is developed. The model is based on previous research studied in [44]. A thermal equivalent circuit model allows for an accurate estimation of desired node temperatures based on input power loss and the thermal resistivities of the module materials. The objective of this model is to determine the junction, coil, top surface, and bottom surface temperatures of the modules to compare to FEA and experimental results. FEA simulation is used to calculate constant thermal resistance values using room temperature data input. Table 2.3 shows the thermal equivalent circuit parameters determined using FEA simulation.

Table 2.3. Thermal equivalent circuit model parameters.

Value (˚C /W) Designator Equivalent Thermal Resistance PSI2 Plastic

R1 Case to ambient 28 30

R2 Internal packaging 12 8

R3 Internal packaging 12 50

R4 IC to packaging 6 6

R5 IC to module PCB 10 10

R6 Coil to packaging 2 6

R7 Coil to module PCB 10 10

R8 Module PCB to mounting PCB 1 1

R9 Mounting PCB to ambient 24 24

The power loss input to the thermal equivalent model consists of the three primary loss sources of the power module: winding loss, inductor core loss, and IC loss. The loss is fixed at 3W for this test which is near full load condition for both devices. The load current is recorded for both PSI2 and plastic modules to achieve 3W of loss. The power loss data is shown in Table 2.4 below.

Table 2.4. Loss data for thermal equivalent circuit model.

Equivalent Thermal Value (W) Loss Parameter Resistance PSI2 Plastic

Pwinding Inductor winding loss 1.193 1.433

Pcore Inductor core loss 0.032 0.032

PIC IC loss 1.775 1.535

PTotal Total loss 3 3

Tamb1 22°C

69.3°C Ramb1 67.7°C Package Top IC Package Top Inductor

Core Pcore Rcase1 Rcase2

RCase_IC Rcase_ind 0.032W

73.4°C 68.8°C IC Winding PIC Pwinding

Rjunc_IC Rjunc_ind 1.775W 1.193W

PCB Bottom RPCB 62.9°C

Ramb2

Tamb2 22°C

(a) PSI2

Tamb1 22°C

66.6°C Ramb1 75.6°C Package Top IC Package Top Inductor

Core Rcase1 Rcase2 Pcore

Rcase_IC Rcase_ind 0.032W

72.1°C 77.5°C IC Winding P PIC winding Rjunc_ic Rjunc_ind 1.433W 1.535W

PCB Bottom

RPCB 65.9°C

Ramb2

Tamb2 22°C

(b) Plastic

Fig. 2.11. Thermal equivalent circuit models.

The thermal equivalent circuit models are shown in Fig. 2.11 above. These models are based on the simplified thermal equivalent circuit model described in Section 2.2.2. The heat flow is applied using current sources. The ambient temperatures are applied to the top and bottom surfaces using voltage sources labelled Tamb1 and Tamb2. The analytical results of the thermal equivalent circuit model show a more uniform temperature gradient on the surface of PSI2 versus plastic packaging with an average temperature decrease of about 7˚C. At the junction level, the IC temperature is nearly the same, while the winding temperature is 8.7˚C cooler for the PSI2 package. The total loss of both devices is the same which suggests the thermal performance of the

PSI2 package is superior to traditional plastic packaging. These results will be verified in the FEA simulation and experimental testing.

2.5 FEA Thermal Simulation

Thermal performance of both converters is simulated using Finite Element Analysis (FEA) through ANSYS Computer Aided Design (CAD) software [45]. A boundary condition is set fixing the ambient temperature at a fixed 25°C. The input losses are shown in Table 2.4 above. The loss is applied as heat generation to the inductor core, windings, and the modules’ IC. The materials are defined based on the corresponding thermal conductivities listed in Table 2.5. The thermal conductivity of the PSI2 package is 10x better than the plastic packaging material. Testing is conducted at constant 8A load condition and constant 3W loss condition. The objective of the constant load test is to observe the electrical and thermal performance of the PSI2 package over traditional plastic packaging. The objective of the constant loss test is to isolate the thermal performance of the PSI2 package compared to plastic packaging.

Table 2.5. Material thermal conductivity.

Material Thermal Conductivity (W/(m·˚C))

PSI2 Package (MP55 core) 3 Plastic Package 0.3 Copper 400 FR-4 Epoxy 0.3 Ferrite 4 Silicon 148 Solder 48

2.5.1 FEA Simulation, 8A Load Test

Thermal performance of both converters is simulated using FEA in ANSYS based on the losses calculated for each package. Fig. 2.12 (a) and (b) show the package surface temperatures at 8A load. The peak surface temperature of the plastic package is 94.6˚C, which is 27.4˚C greater than the PSI2 package which has a peak surface temperature of 67.6˚C. The temperature variation across the plastic package surface ranges from 94.6˚C to 66.6˚C, amounting to a 29.7˚C range. For the PSI2 package, the temperature variation ranges from 67.6˚C to 64.3˚C, amounting to a 4.3˚C range. The surface temperature of the PSI2 package is more uniform than the plastic package due to the improved thermal conductivity of the PSI2 package. Fig. 2.13 (a) and (b) show the junction temperatures of the power modules. The temperature of the plastic package IC is 74.2˚C, which is about 3˚C greater than PSI2 IC temperature of 69.8˚C. For the inductor, the plastic package temperature is 96.3˚C, which is 27.2˚C greater than the PSI2 inductor temperature of 68.1˚C. As expected, the major source of loss is due to winding loss in the inductor. The temperature difference of the IC is small due to identical IC’s and similar switching frequency.

(a) PSI2 surface, 8A Load (b) Plastic surface, 8A Load

Fig. 2.12. Surface temperatures in FEA thermal simulation, constant 8A load.

(a) PSI2 junction, 8A Load (b) Plastic junction, 8A Load

Fig. 2.13. Junction temperatures in FEA thermal simulation, constant 8A load.

2.5.2 FEA Simulation, 3W Constant Loss Test

FEA simulation is also conducted for the constant loss condition. The objective of the constant loss test is to isolate the thermal performance of the PSI2 package compared to plastic packaging by regulating the heat generation in each module to a fixed 3W. Fig. 2.14 and Fig. 2.15 show results for an equal 3W loss in both devices. The peak surface temperatures are shown in Fig. 2.14

(a) and (b). The plastic package is 78˚C, which is 8.7˚C greater than the PSI2 package which has a peak surface temperature of 69.3˚C. The temperature variation across the plastic package surface

ranges from 78˚C to 65.1˚C, amounting to a 12.9˚C range. For the PSI2 package, the temperature variation ranges from 67.1˚C to 69.3˚C, amounting to a 2.2˚C range. Fig. 2.15 (a) and (b) show the junction temperatures of the power modules. The temperature of the plastic package IC is 73.1˚C, which is about 2.5˚C less than PSI2 IC temperature of 75.6˚C. For the inductor, the plastic package temperature is 78.7˚C, which is 10.7˚C greater than the PSI2 inductor temperature of 68˚C.

The surface temperature of the PSI2 package is more uniform and cooler than the plastic package due to the improved thermal conductivity of the PSI2 package. Also, the coil temperature is much lower in PSI2 due to the improved package thermal conductivity. This additionally results in a slightly higher temperature in the PSI2 IC as the heat generated in the inductor coil transfers through the case to the IC more effectively. The PSI2 bottom surface temperature is also slightly higher due to the increase in IC temperature. A summary of the analytical and FEA simulated temperature results are shown in Table 2.6 below. The case and junction temperatures are very similar to the analytically derived temperatures from the thermal equivalent circuit model for both

PSI2 and plastic.

(a) PSI2 surface, 3W Loss (a) Plastic surface, 3W Loss

Fig. 2.14. Surface temperatures in FEA thermal simulation, constant 3W loss.

Fig. 2.15. Junction temperatures in FEA thermal simulation, constant 3W loss.

2.5.3 Summary of Simulated Results

Table 2.6 shows a summary of the simulated temperature data from the TEC model and FEA thermal simulation. The results show agreeability between both thermal approximation methods within a small margin of error. Therefore, the simulated results are expected to agree with experimental results.

Table 2.6: Analytical TEC and FEA simulation results for 3W constant loss.

PSI2 Package Plastic Package Temperature Location Analytical FEA Analytical FEA TEC Simulation TEC Simulation

Package Top IC (˚C) 69.3 69.3 66.6 65.1

Package Top Inductor (˚C) 67.7 67.1 75.6 78

IC Junction (˚C) 73.4 75.6 72.1 73.1

Inductor Winding (˚C) 68.8 68 77.5 78.7

PCB Bottom (˚C) 62.9 66.3 65.9 63.6

2.6 Experimental Results

This section demonstrates and presents the results of the experimental testing using the fabricated PSI2 and plastic packaged power modules. The test setup and conditions, constant current testing, constant loss testing, and a summary of the results is presented.

2.6.1 Test Setup and Conditions

The PSI2 and plastic modules are experimentally tested to determine the thermal performance of the modules. The input voltage and load current are varied using DC power supplies and DC loads. The modules are initially tested with a fixed 12V input and 1.5V output to determine the electrical and thermal benefits of PSI2. Finally, the modules are tested with a fixed loss of 3W at

24V input and 1.5V output to determine the thermal performance of the packages in isolation. The testing board is shown in Section 2.3.1 in with the PSI2 module equipped.

2.6.2 Constant Current Tests

Fig. 2.16 below show the efficiency curves for the 12V nominal input case at 1.5V output. The

PSI2 benefits from the magnetic package by allowing for a larger inductor, and lower DCR in the windings. The result is that the PSI2 package is more efficient and has lower loss. Across all input and output voltage cases, the PSI2 package has a greater efficiency of 1.82% overall, and 2.82% at full load compared to the plastic package.

Efficiency, Vin=12V, Vout=1.5V 90

70 Efficiency (%) Efficiency 65

60 PSI2 55 Plastic 50 0 1 2 3 4 5 6 7 8

Iout (A)

Fig. 2.16. Comparing efficiency at different load currents.

The loss of the power module is also calculated while measuring the efficiency. Fig. 2.17 below shows the loss curves for the 12V nominal input case at 1.5V output. Overall, the PSI2 package has 0.14W less loss than the plastic package across all input and output voltage cases. At full load, the PSI2 module has 0.48W less loss than plastic module. A summary of these results is shown in

Table 2.7. These results show that the PSI2 package offers better electrical performance compared to the traditional plastic packaging. The PSI2 package has the advantage of using package volume more efficiently to allow for larger inductor coil windings and magnetic core to consequently lower

DCR. The PSI2 package therefore achieves less loss and greater efficiency compared to the plastic package.

Loss Comparison, Vin=12V, Vout=1.5V 3.5 0.6

3 0.5

2.5 0.4 2 0.3

1.5 Loss (W) Loss 0.2 1 PSI2 (W) Difference Loss 0.1 0.5 Plastic Difference 0 0 0 2 4 6 8 Iout (A)

Fig. 2.17. Comparing loss at different load conditions.

The top and bottom temperature of the PSI2 and plastic power modules are measured using thermal cameras under different operating conditions. Temperature data is collected from the top of the module and the bottom of the testing board. A small coating of epoxy is put on the top of the PSI2 package to guarantee the same emissivity is observed by the thermal camera for both modules. The first test involves measuring the temperature of the modules under the same load current conditions. The output current is set between 0 and 8A in steps of 2A. Overall, the PSI2 package is on average 8.4˚C cooler than the plastic on top and 0.8˚C cooler on the bottom for both output voltages. At full load, the PSI2 package is 23.9˚C cooler than the plastic on top, and 3.5˚C cooler on the bottom for both input voltages. A full summary of the results is provided in Table

2.7 below. Fig. 2.18 shows the PSI2 and plastic modules top temperatures versus load current. The top temperature disparity can be attributed to poor thermal conductivity of the epoxy and higher

DCR in the fixed inductor than the PSI2. Fig. 2.19 shows the bottom temperatures of the test board for both modules versus load current. The bottom temperatures of both packages are similar due

to the almost identical PCB layouts. Most of the heat being transferred to the bottom of the board is through the footprints of the components of the PCB. The IC is the component with the largest footprint and will therefore transfer the most heat to the bottom of the board. Since both modules use the same IC and operate at a similar switching frequency, it is expected that the bottom temperatures will be similar.

Temperature (Top), Vin=12V, Vout=1.5V 100 90 80 70 60

50 Temperature (˚C) Temperature 40 PSI2 30 Plastic 20 0 1 2 3 4 5 6 7 8 Iout (A)

Fig. 2.18. Comparing top temperatures at varying load conditions.

Temperature (Bottom), Vin=12V, Vout=1.5V 70 65 60 55 50 45 40

35 Temperature (˚C) Temperature 30 PSI2 25 20 Plastic 0 1 2 3 4 5 6 7 8

Iout (A) Fig. 2.19. Comparing bottom temperatures at varying load conditions. 34

Thermal images are captured to show the thermal performance of both packages. The top sides of both packages are coated with a thin layer of epoxy to ensure the same emissivity is observed by the thermal camera. Thermocouple measurements are used to validate the thermal camera results. Fig. 2.20 shows the PSI2 thermal image. Fig. 2.21 shows the plastic thermal image. The

PSI2 module is 69.7˚C, which is 26˚C cooler than the plastic package temperature of 95.7˚C at

1.5V output, 8A load. The performance improvement of the PSI2 package is due to the decreased loss generation and improved thermal conductivity of the package over traditional plastic packaging. This result agrees with the simulated results observed in Section 2.4 and Section 2.5.

Fig. 2.20. PSI2 thermal image, 8A load.

Fig. 2.21. Plastic thermal image, 8A load. 35

A summary of the results is shown in Table 2.7 below. For all tests, the values for the plastic package are compared against the PSI2 package (PSI2-Plastic).

Table 2.7: Experimental results of PSI2 versus plastic power modules.

Test PSI2 Package Plastic Package Difference (PSI2-Plastic)

Efficiency 74.83% 73.19% 1.64 %

Full Load Efficiency 80.84% 78.16% 2.68 %

Loss 0.96 W 1.1 W -0.14 W

Full Load Loss 2.82 W 3.33 W -0.51 W

Average TTop 42.52 ˚C 53.54 ˚C -11 ˚C

Average TBottom 38.64 ˚C 42 ˚C -3.36 ˚C

Full Load TTop 69.7 ˚C 95.7 ˚C -26 ˚C

Full Load TBottom 59.6 ˚C 65.3 ˚C -5.7 ˚C

2.6.3 Constant Loss Tests

A final constant loss test is conducted on both modules. The purpose of this test is to isolate the heatsinking properties from the electrical properties of both packages. The loss of the modules is fixed equally at one, two, and three Watts. This testing method removes any temperature disparity due to increased heat generation. Both modules will generate the same total quantity of heat; therefore, temperature differences will be the result of the package thermal conductivity. The input and output voltages are the same for both modules. To produce three Watts of loss, the input voltage is set to 24V. The load current is then varied for each module until total recorded loss is

3W. The temperatures are then recorded once thermal steady state is achieved. Fig. 2.22 shows the top surface temperatures. The PSI2 top surface package is 44˚C, 59.4˚C, and 80.3˚C at 1W, 2W,

and 3W respectively. The plastic top surface package is 35.8˚C, 52.9˚C, and 67.6˚C at 1W, 2W, and 3W respectively. Therefore, the PSI2 average temperature difference over each operating point is 8.7˚C cooler on average than the plastic package. Fig. 2.23 shows the bottom surface temperatures. The PSI2 top surface package is 36.6˚C, 47.7˚C, and 61.8˚C at 1W, 2W, and 3W respectively. The plastic top surface package is 38.6˚C, 48.8˚C, and 62.6˚C at 1W, 2W, and 3W respectively. Therefore, the PSI2 average temperature difference over each operating point is 1.4˚C cooler on average than the plastic package.

In the previous constant loss testing in which the load current was increased from 0A to 8A, the average top temperature difference at full load was 26˚C. For the constant loss testing in which the total loss of both modules is varied from 1W, 2W, and 3W, the average temperature difference is

8.7˚C. The constant loss test isolates the thermal performance of the PSI2 and plastic modules by ensuring the heat generation of both modules is identical. The constant load test demonstrates the thermal and electrical performance of the PSI2 and plastic modules by operating under the same electrical conditions in which loss generation is unequal. Therefore, the 8.7˚C temperature difference at constant loss accounts for roughly 33% of the total 26˚C difference under constant load testing. Lower loss components and improved thermal conductivity of the PSI2 package improves overall thermal performance against traditional plastic packaging. The average temperature difference on the bottom surface is very small. Both boards have identical layouts and components except for the inductor therefore this result is expected.

Temperature (Top), Vin=24V, Vout=1.5V 90

50 Temperature (˚C) Temperature PSI2 40 Plastic 30 1 1.5 2 2.5 3 Loss (W) Fig. 2.22. Top temperatures at different loss conditions.

Temperature (Bottom), Vin=24V, Vout=1.5V 65

Temperature (˚C) Temperature PSI2 40 Plastic 35 1 1.5 2 2.5 3

Loss (W) Fig. 2.23. Bottom temperatures at different loss conditions.

Thermal images are taken to observe the heat distribution of the power modules. Plastic epoxy is coated on the top sides of both packages to ensure the thermal camera records the same emissivity for both modules. Thermal camera results are verified by thermocouple measurements.

Fig. 2.24 shows the top surface temperature of the PSI2 package and Fig. 2.25 shows the top

surface temperature of the plastic package. The PSI2 package is 68.4˚C, which is 11°C cooler than the plastic package top surface temperature of 79.4˚C at 3W loss, 24V input, and 1.5V output. On the bottom surface, the PSI2 package is 61.8˚C, which is 0.8°C cooler on the bottom surface than the plastic package temperature of 62.6˚C at 3W loss, 24V input, and 1.5V output. These images confirm the results of the analytical TEC values from Section 2.4 and simulated FEA values in

Section 2.5 and show the improved thermal performance of the PSI2 package.

Fig. 2.24. PSI2 thermal image, constant 3W loss.

Fig. 2.25. Plastic thermal image, constant 3W loss.

2.6.4 Analytical Versus Experimental Results

A summary of the analytical, simulated, and experimental results is shown in Table 2.8 below.

The results in this table are for the constant 3W total loss, 24V input, and 1.5V output testing conditions. The experimental results for the junction IC and winding of both the PSI2 and plastic packaged modules is not recorded due to the inability to observe within the package of the modules.

Table 2.8: Module temperatures at 3W loss, Vin=24V, Vout=1.5V.

PSI2 Plastic Temperature Location Analytical FEA Analytical FEA Experimental Experimental TEC Simulation TEC Simulation

Package Top 69.3 69.3 62 66.6 65.1 64 IC (˚C)

Package Top 67.7 67.1 68.4 75.6 78 79.4 Inductor (˚C)

IC Junction 73.4 75.6 - 72.1 73.1 - (˚C)

Inductor 68.8 68 - 77.5 78.7 - Winding (˚C)

PCB Bottom 62.9 66.3 61.6 65.9 63.6 62.6 (˚C)

2.7 Conclusion

A new power module packaging technology called Power-System-in-Inductor (PSI2) is analyzed for high efficiency, high power density power module applications. The PSI2 package performance is tested against traditional plastic packaging through an innovative testing combination of analytical and FEA simulation and accurate experimentation with identical buck power modules. The PSI2 package uses the magnetic inductor core of the power module to replace

traditional plastic epoxy as the power module case. Analytical thermal equivalent circuit (TEC) models and FEA thermal simulations are performed on the PSI2 and plastic power modules to predict the thermal performance of both packages and verify the experimental results.

Experimental testing is conducted on power modules with both packaging types under constant load and constant loss testing. The PSI2 package achieves 2.68% greater efficiency, 0.51W less loss, and 26˚C lower top temperature compared to an identical plastic module. Analytical and experimental testing results suggest that an estimated 33% of the measured temperature difference is attributed to the improved thermal heat transfer of the PSI2 packaging.

Integrated Multi-Layer Cooling (IMLC) Structure for High Power Density

Converters

3.1 Introduction

Electronic devices today are consistently improving through increases in both power density and efficiency. A significant obstacle in achieving these design goals lies in the thermal design of the converter. Heat is generated in high loss components that must be transferred to ambient to prevent device damage [46]. Additionally, the decreasing package size reduces the available surface area for conductive heat transfer which causes further thermal challenges. To address this thermal challenge, methods are proposed to increase heat transfer. Cooling methods such as magnetically integrated power modules exist for lower power applications [2]. For high power applications, typical cooling methods include air and liquid cooled heatsinking.

Present research and industrial design have focused on improving electrical design to reduce size and improve efficiency, or thermal design to improve heat transfer. These solutions do not however address both challenges simultaneously. A unified solution that improves the converter size, power density, and thermal properties while maintaining design and manufacturing simplicity is desired. A new Integrated Multi-Layer Cooling (IMLC) thermomechanical structure is proposed to achieve these design objectives.

This chapter is organized into the following sections: Section 3.2 reviews current academic literature related to this chapter, Section 3.3 describes the IMLC structure; Section 3.4 presents the loss analysis and thermal modeling; Section 3.5 presents the finite element analysis (FEA) thermal

results; Section 3.6 presents the protype with experimental results and two-PCB simulation and experimental verification; Section 3.7 concludes the chapter.

3.2 Literature Review

Industry focus has been pushing for high-power density power converters to serve the growing electric vehicle market. High power is required in small packaging to serve compact vehicles with increasing electrification. The electric vehicle On-Board Charger (OBC) is a critical power converter which converts AC power from the grid to high-voltage DC for the electric vehicle primary battery pack. Research has focused on improving the OBC power converter efficiency and size using resonant converters, such as LLC [47] [48] [49] [50] and CLLC converters [51]

[52], to achieve higher power density and greater efficiency. CLLC converters offer an improvement over LLC designs in EV applications due to their improved bidirectional operation.

Electric vehicles also require a Low-Voltage DC Converter (LDC), which converts the 400V high-voltage DC form the main battery pack to the 14V low-voltage DC required by the auxiliary battery pack. This auxiliary battery powers the instrumentation and helps during vehicle startup.

Research has focused on improving this converter to increase efficiency, increase power density, and reduce size. A popular solution proposed in literature consists of integrating the OBC with the

LDC by combining switching devices [20] [21] [22] [23]. This method allows for fewer switching devices including magnetic devices, which considerably reduces size and increases power density.

Research in [23] proposes an integrated OBC and LDC, where a traditional discrete OBC and LDC are combined into one converter. Fig. 3.1 shows the discrete OBC and LDC devices used in traditional electric vehicle designs. Fig. 3.2 shows the proposed integrated OBC and LDC.

(a) Discrete OBC for high-voltage AC-DC battery charging.

(b) Discrete LDC for low-voltage DC-DC battery charging.

Fig. 3.1. Circuit diagrams of discrete OBC and LDC topologies [23].

Fig. 3.2. Circuit diagram of a proposed integrated OBC and LDC topology [23].

Different topologies are used to achieve conversion, such as LLC resonant converters [20], full- bridge converter [22], phase shift full bridge converter [21] [23], and combined boost and flyback converters [24]. Improving the OBC and LDC topologies allow for reduction in size, cost, and weight for the competitive electric vehicle market. Improving the electrical qualities of a converter has limitations, however, as the need for size reduction and thermal management remain to be addressed. Therefore, further research is focused on the mechanical design of converters.

Significant research has been proposed to improve the heat transfer performance of power converters. In [53], a new thermomechanical structure is proposed for a power converter based on double-sided liquid cooling. In [54], a new direct cooling method is developed with a copper heat spreader and ported aluminum cold plate to improve thermal conductivity of the actively cooled connection. Additionally, various cold plate technologies are examined in [55] to extend beyond the common aluminum design. A new design is proposed in [8] which integrates the cold plate heatsink into the liquid cooling pump system. In [56], different cold plate materials are proposed and tested based on heat transfer for robotic applications. Finally, research in [57] is focused on examining cold plate long term reliability due to exposure to heat stresses.

For EV applications, it is desired to improve both the electrical and thermal performance of the converter to increase efficiency, reduce converter size, and reduce component temperature rise.

The demand for such a converter comes with the relatively high-power requirements of the converter, ranging from 3 to 4kW. Typical power ratings range from 1kW to 19.2kW for level 1 and 2 charging respectively, and up to 60kW and beyond for level 3 charging. High power density is therefore required, further emphasizing the need for effective thermal management solutions.

Current research has focused on integrating water cooling to improve cooling for high power density converters. Research in [58] proposes an integrated liquid cooled module with a liquid

cooling channel to cool through-hole switching devices for an electric vehicle on-board charger.

The structure of the converter and cooling assembly is shown in Fig. 3.3 below.

Fig. 3.3. On-board charger for EV with integrated liquid cooling package.

This design provides a total package reduction in size and achieves 1.4kW/L power density due to the integrated liquid cooling and inclusion of IGBT modules. However, this method has limited liquid cooling for additional surface mount components and does not maximize three-dimensional space usage.

Research in [59] studies a new power module for electric vehicle applications utilizing a Dual-

Sided Cooled (DSC) approach. This thermal design uses two heatsinking mediums attached to the

PCB bottom surface and the top junction of surface mount components. This solution allows for twice the heat transfer surface area and reduces the thermal resistivity between the module and 46

ambient. However, this solution suffers from a more difficult design and a more costly manufacturing process. Additionally, usable PCB surface area remains un-improved.

A final design proposed in [60] uses a similar design to [59], but incorporates direct water cooling of components through direct metal connection. The design improves power density by approximately 70% and reduces thermal resistance by 50%. A comparison of thermomechanical structures is shown in Fig. 3.4 below.

Fig. 3.4. A comparison of cooling methods studied in [60].

This structure also suffers from a complex manufacturing requirement and assembly and no improvement in PCB surface area as compared with [59].

3.3 Structure of IMLC

In this section, the structure of the IMLC thermomechanical design is described. Additionally, the proposed EV LDC used to test the IMLC structure is introduced.

3.3.1 Power Converter for Testing

A 1.3kW LLC power converter is designed using the IMLC structure for high voltage to low voltage DC-DC conversion of 400V to 14V for the LDC electric vehicle application. The operating parameters of the LLC converter are shown in Table 3.1 below.

Table 3.1: LLC Power converter operating parameters.

Input Output Maximum Switching Dimensions, Dimensions, Loss Voltage Voltage Load Current Frequency one PCB (mm) two PCBs (mm)

400V 14V 95A 260~350kHz 39W 70x190x42 45x190x50

For the proposed 1.3kW LLC converter, high output current increases conduction loss of the secondary transformer winding. To reduce this conduction loss, two transformers are arranged in series-parallel connection to reduce the secondary winding conduction loss by 50% [61]. The synchronous rectifiers of the output side are also connected in parallel to reduce the device ON resistance by 50%, thereby reducing loss and increasing efficiency. In addition, GaN HEMT devices are used at the primary side to further increase efficiency at greater switching frequencies.

A circuit diagram of the proposed 1.3kW LLC LDC is shown in Fig. 3.5 below.

TX1 SR1

Q1 Q3 Cout Vout VLV_DC SR2 Lres SR3

VHV_DC Cin Q2 Q4 Lp

GaN Cres TX2 SR4

Fig. 3.5. Circuit diagram of the proposed 1.3kW LLC LDC converter.

The LLC converter components are arranged to minimize the AC current path and economize

PCB surface area. To improve heat transfer for high loss surface mount components, a liquid cooled heatsinking solution is applied. A cold plate heatsink is fixed to the bottom side of the

bottom-most PCB using copper connectors and thermal gap pads. With a single-PCB design, all components are placed on the top surface of the single-PCB layer. A single-PCB design of the proposed LLC resonant converter is shown in Fig. 3.6 below. This figure shows that a significant amount of package volume and PCB surface area is occupied by the magnetic components.

Fig. 3.6. Top view of a conventional single-PCB converter for an LLC power converter.

The conventional single-PCB structure can incorporate liquid cooling via the bottom surface of the PCB, however, only the top PCB surface is available for component placement. Therefore, a trade-off between liquid-cooling heat transfer and PCB dimensions is required to integrate liquid cooling for a power converter.

3.3.2 IMLC Structure

The IMLC structure is proposed to use three-dimensional package volume efficiently while incorporating liquid-cooling thermal performance. Three key design principles are established for the IMLC structure. Firstly, two or more PCB’s are connected vertically through copper connections to make use of three-dimensional space and increase PCB surface area. Secondly, components are sorted and distributed by the heat they generate. High loss components are placed directly to the top surface of the bottom PCB to enable direct heat transfer to the cold plate on the 49

bottom PCB surface. Copper connectors connect the cold plate to the PCB and provide heat transfer to the cold plate. Finally, IMLC achieves active cooling through bottom side liquid cooled cold plate heatsinking. Fig. 3.7 shows a cross sectional diagram of the complete two-layer IMLC structure.

Magnetic Magnetic Component Component Low Loss Circuitry PCB Low Loss Circuitry Copper Connectors High Loss Circuitry PCB Copper Bar Connector

Cold Plate Heatsink Coolant

Fig. 3.7. Front view of the IMLC structure.

IMLC is structured to provide targeted active cooling. Large magnetic components and low loss circuitry are placed on the top-most PCB. Copper connections are used to electrically connect the magnetic components to both PCB layers. The large size and weight of the magnetic components requires that the copper connectors are strong and sturdy enough to physically support the heavy devices. The connectors therefore anchor these components to the bottom PCB layer. In addition, the copper connectors act as thermal vias from the top PCB to the bottom PCB and therefore to the cold plate heatsink. This provides heat transfer for the top PCB magnetic and surface mount components to the heatsink. High loss surface mount components are placed exclusively on the 50

top side of the bottom PCB layer. This connection allows for direct connection to the cold plate heatsink and therefore heat conduction of the highest heat generating components. The heat flow path of the IMLC structure is shown in Fig. 3.8 below. To minimize package volume, the height of the components on the top surface of the bottom PCB should be minimized to reduce the gap between the two PCB’s and thereby minimize package volume.

Multiple PCB layers are used in the IMLC structure to achieve more efficient use of three- dimensional space. This structure allows the length and width of the converter to be reduced significantly while at the same time increasing PCB surface area. The increase in height of the converter is relatively smaller than the decrease in length and width, therefore the converter volume is decreased overall.

The final component of the IMLC structure is the active liquid cooling system. A cold plate heatsink is fixed to the bottom surface of the bottom-most PCB to achieve conductive heat transfer from the high loss bottom-PCB components. To maximize conductive heat transfer to the cold plate, the bottom side of the bottom PCB is used to connect to the heatsink with exceptions for through hole connections. The structure of the cold plate connection consists of the liquid cooled cold plate heatsink, thermal gap pads, copper bar connectors, and the bottom PCB. A diagram of this structure is shown in Fig. 3.8 below.

Magnetic Magnetic Component Component

PCB

High Loss Components PCB Gap Copper Pad Bars Heat

Heat Heat

Coolant

Fig. 3.8. Side view of the IMLC structure.

Copper bars and thermal gap pads are used to connect the heatsink to the PCB with electrical isolation and uniform contact. Copper bars are placed underneath high loss components to provide direct heat transfer. Therefore, the connection between the cold plate and the bottom PCB consists of several copper bars connecting under high loss components. The remaining bottom surface of the bottom PCB is unused and is cooled through passive convection. Thermal gap pads are used to interface between the copper bars and the PCB or cold plate. These pads provide uniform contact, thereby improving thermal conductivity. The pads also provide electric isolation to prevent short circuiting.

Fig. 3.9 shows the top view of the bottom layer PCB for the two PCB IMLC structure of the proposed LLC power converter. This layer contains the high loss surface mount components, while the magnetic components and low loss circuitry are on the top PCB. Fig. 3.10 below shows a model

of the complete IMLC structure in a cross-sectional view. This figure shows the magnetics and circuitry on the top PCB layer, as well as the high loss circuitry on the bottom PCB layer. Fig. 3.10 also shows the liquid cooling cold plate heatsink attached to the bottom of the structure using copper bar connectors. Compared with the traditional single PCB design shown in Fig. 3.6, component sizes, PCB surface area, and cold plate contact area remain unchanged in the IMLC design of the proposed LLC power converter. Therefore, thermal performance is expected to be maintained with the new IMLC structure. The benefit of the IMLC structure, however, is through improved power density. For the proposed conventional single PCB LLC converter, the total size is 0.56L with a power density of 2.33kW/L. For the IMLC LLC converter, the volume is reduced to 0.43L, with 3.15kW/L power density. Converter size is reduced by 31% while maintaining thermal performance by incorporating active liquid cooling and efficiently distributing components with multiple PCB layers.

Lres GaN Lp Tx SR

Fig. 3.9. Top view of IMLC bottom PCB layer with high loss components.

Lres Lp Tx1 Tx2

Fig. 3.10. Front view of IMLC structure

3.4 Loss Analysis and Thermal Modeling

In this section, a proposed 1.3kW LLC power converter will be analyzed by first determining the loss of key components. The converter will then be modeled and simulated using FEA thermal analysis. To determine the benefit of the new IMLC structure, the LLC converter will be analyzed using three PCB structures: single-PCB design with passive cooling, single-PCB design with active liquid cooling, and two-PCB design using the new IMLC structure. Three-dimensional models of each structure are developed. A detailed loss analysis of the proposed LLC resonant converter is also studied.

3.4.1 Loss Analysis

There are six main loss contributors for the proposed 1.3kW LLC power converter. The loss must be characterized to predict, verify, and compare the performance of the three thermomechanical structures: single-PCB air cooled, single-PCB liquid cooled, and two-PCB

IMLC structure. The six loss contributors in the LLC converter are as follows: GaN switching and conduction loss, synchronous rectifier (SR) conduction loss, resonant inductor (Lres) core and

conduction loss, parallel inductor (Lp) core and conduction loss, transformer (Tx) core and conduction loss, and PCB conduction loss.

The switching loss of the GaN device consists of the turn-off discharging loss (Pcoss) which is studied in [62]. The traditional turn-on switching loss (Pciss) is eliminated in this design due to the

ZVS operation of the LLC converter. The Pcoss loss is calculated using equation (3.1) below based on work in [62].

푃푐표푠푠 = 푓푠푤 ∗ 퐸푑푖푠푠 (3.1)

The variable fsw is the converter switching frequency and Ediss is the energy dissipated to charge and discharge the output capacitor per cycle. The Ediss and switching frequency are derived using

PSIM simulation for the proposed 1.3kW LLC converter and from the GaN GS66508B datasheet and estimated values in [62].

The conduction loss of the GaN is calculated using equation (3.2) below based on traditional resistive power loss.

2 푃퐺푎푁_푐표푛푑 = 퐶푡 ∗ 푅푑푠표푛 ∗ 퐼푟푒푠(푟푚푠) (3.2)

Ct is the temperature coefficient of the GaN device estimated at 1.3, Rdson is the ON-resistance of the selected GaN device, and Ires(rms) is the RMS resonant current of the LLC converter.

Synchronous rectifier (SR) loss consists of conduction loss only. Switching loss is eliminated as the LLC converter operates in the Zero Current Switching (ZCS) region and therefore SR turn off loss is eliminated. Conduction loss of the SR is calculated based on traditional resistive power loss using equation (3.3) below.

2 푃푆푅_푐표푛푑 = 퐶푡 ∗ 푅푑푠표푛 ∗ 퐼푠푒푐(푟푚푠) (3.3)

Ct is the temperature coefficient estimated at 1.3, Rdson is the SR ON-resistance, Isec(rms) is the secondary side RMS current.

For loss calculation of the magnetic devices (Lres, Lp, and Tx), the magnetic core loss and winding conduction loss must be calculated. To calculate the core loss of the magnetic devices, equation (3.4) is used based on the Steinmetz equation.

푥 푦 푃푐표푟푒 = 퐶푚 ∗ 퐵푝푘 ∗ 푓푠푤 (3.4)

Cm, x, and y are Steinmetz values derived based on the ferrite core material. Bpk is the peak magnetic flux density of the core, and fsw is the device switching frequency. To calculate the peak magnetic flux density, equation (3.5) is used.

퐿 ∗ 퐼푝푘 퐵 = (3.5) 푝푘 푁 ∗ 퐴

L is the inductance of the magnetic device, Ipk is the peak winding current, N is the number of turns, and A is the area of the magnetic core. The winding conduction loss of the magnetic devices are calculated using equation (3.6) below based on the resistive power loss formula.

2 푃푤푖푛푑푖푛𝑔 = 퐾푎푐 ∗ 퐼푟푚푠 ∗ 푅푤푖푛푑푖푛𝑔 (3.6)

Kac is the AC resistance of the winding based on the AC resistance factors of the winding, Irms is the RMS current through the magnetic windings, and Rwinding is the DC resistance of the winding.

For the proposed LLC converter, Litz wire is used for the magnetic windings to reduce AC resistance factors such as skin effect and proximity effect. The skin effect is studied in [63] and is responsible for reducing the effective cross-sectional area of a conductor as switching frequency increases. This property results in smaller conduction area, and therefore higher effective resistance. Litz wire provides thousands of micro strands within a conductor to increase the area

per conductor and mitigate skin effect losses. In [63], AC proximity effect is also studied.

Proximity effect results from the magnetic field created by current in a nearby conductor to induce circulating current in a conductor and therefore increase resistance. Both skin effect and proximity effect are calculated and included in equation (3.6) using KAC. KAC is estimated for each magnetic device.

The losses for each magnetic device are defined based on equations (3.4) and (3.6). For the resonant inductor (Lres), the core loss is given in equation (3.7) below. The conduction loss is given in equation (3.8) below. KAC_Lres is estimated at 1.2 for Lres at nominal operating conditions.

푥 푦 푃푐표푟푒_퐿푟푒푠 = 퐶푚_퐿푟푒푠 ∗ 퐵푝푘_퐿푟푒푠 ∗ 푓푠푤_퐿푟푒푠 (3.7)

2 푃푤푖푛푑푖푛𝑔_퐿푟푒푠 = 퐾퐴퐶_퐿푟푒푠 ∗ 퐼푟푚푠_퐿푟푒푠 ∗ 푅푤푖푛푑푖푛𝑔_퐿푟푒푠 (3.8)

For the parallel inductor, Lp, the core loss is given in equation (3.9) and the conduction loss is given in equation (3.10) below. KAC_Lp is estimated at 1.5 for Lp at nominal operating conditions.

푥 푦 푃푐표푟푒_퐿푝 = 퐶푚_퐿푝 ∗ 퐵푝푘_퐿푝 ∗ 푓푠푤_퐿푝 (3.9)

2 푃푤푖푛푑푖푛𝑔_퐿푝 = 퐾퐴퐶_퐿푝 ∗ 퐼푟푚푠_퐿푝 ∗ 푅푤푖푛푑푖푛𝑔_퐿푝 (3.10)

For the transformer, Tx, the core loss is given in equation (3.11). For the transformer, the peak magnetic flux density is generated from the clamped output voltage.

푥 푦 푃푐표푟푒_푇푥 = 퐶푚_푇푥 ∗ 퐵푝푘_푇푥 ∗ 푓푠푤_푇푥 (3.11)

1 푉표푢푡 푁푡푥푝푟푖 1 퐵푝푘_푡푥 = 퐼푝푘 ∗ 퐿푚 ∗ = ∗ ∗ (3.12) 푁푡푥푝푟푖 ∗ 퐴푡푥 4 ∗ 푓푠푤 푁푡푥_푠푒푐 푁푡푥_푝푟푖 ∗ 퐴푡푥

For the transformer conduction loss, there is winding loss on the primary and secondary winding. The primary winding loss is given in equation (3.13). KAC_Tx_p is estimated at 1.4 for 57

Tx_primary at nominal operating conditions. The secondary loss is calculated in equation (3.14) based on copper foil resistance estimation described in [64]. KAC_Tx_s is estimated at 4.3 for Tx_secondary at nominal operating conditions.

퐼 2 (3.13) 푃 = 퐾 ∗ ( sec_푟푚푠) ∗ 푅 푤푖푛푑푖푛𝑔_푇푥(푝푟푖) 퐴퐶_푇푥_푝 푛 푤푖푛푑푖푛𝑔_푇푥_푝

2 푃푤푖푛푑푖푛𝑔_푇푥(푠푒푐) = 퐾퐴퐶_푇푥_푠푒푐 ∗ 퐼sec_푟푚푠 ∗ 푅푤푖푛푑푖푛𝑔_푇푥_푝 (3.14)

All magnetic parameters, including inductance, turns, core size, and core material were designed for the LLC converter separately. The electrical parameters, including switching frequency, voltage, and current of the LLC converter are simulated using PSIM simulation to estimate the loss values.

The final loss parameter for the proposed 1.3kW LLC converter is the PCB conduction loss.

This loss is the result of the a purely resistive loss of the 95A secondary side PCB bus bar. The

DC resistance of the bus bar is calculated using the conductivity of copper and the volume of the copper bar. The equation for PCB conduction loss is give in equation (3.15) below.

2 푃푐표푛푑_푃퐶퐵 = 퐶푡 ∗ 퐼sec_RMS ∗ 푅푃퐶퐵 (3.15)

A summary of the total estimated loss of the 1.3kW converter is given in Table 3.2 below.

Table 3.2. A summary of the 1.3kW LLC estimated losses

Conduction Loss Switching Total Loss Device # Devices (W) Loss (W) (W)

4 1.5 GaN 1 2.5 (2 in series for each half cycle) (0.375 per device)

8 6 SR 0 6 (4 in parallel for each half cycle) (1.25 per device)

Lres 1 0.4 0.9 1.3

Lp 1 0.4 0.3 0.7

2 Tx (2 primary windings in series, 2 21 3.8 24.8 secondary windings in parallel)

PCB 1 4.5 0 4.5 Trace

Total 39.8

3.4.2 PCB Thermal Modeling

It is desired to simplify the thermal model of the IMLC structure to create a simpler model for

FEA thermal simulation. An equivalent thermal resistance method is used to simplify the PCB simulation model by approximating orthogonal thermal conductivity based on PCB structure and thermal via distribution. To estimate the thermal conductivity, the expression for heat conduction must also be defined. Equation (3.16) below describes heat conduction inside a path.

푇1 − 푇2 푔 푞 = ∙ (3.16) 푑 푘푒푞 ∙ 퐴

Where q is the heat flow generated by loss in Watts, T1 and T2 are the temperatures of the heat path terminations, d is the heat path length, g is the effective contact area, Keq is the thermal conductivity of the heat carrying material in W/°C•m, and A is cross sectional area the is perpendicular to the direction of heat flow. Equation (3.17) below express the conductive thermal resistance of a material.

푔 ∗ 푑 푅푐표푛푑푢푐푡푖표푛 = (3.17) 푘푒푞 ∗ 퐴

Using equation (3.17), an equivalent thermal conductivity Keq can be expressed by the conduction thermal resistance, Rconduction. The expression for the equivalent conductivity is shown in equation (3.18):

푑 퐾푒푞 = (3.18) (퐴 ∙ 푅푐표푛푑푢푐푡푖표푛)

To calculate the equivalent conductivity in the horizontal and vertical dimensions, the composition of the heat flow material is required. Horizonal resistance derives from the thermal resistance of copper and PCB epoxy material in parallel due to the parallel PCB layers. Fig. 3.11 shows the horizontal thermal resistance acted on by a horizontally applied heat flow. The equivalent thermal resistance and conductivity are estimated based on the parallel thermal resistances. The area, A, is the cross-sectional area of each layer in which heat flow is being applied perpendicularly.

Length d

Heat Flow IN Heat Flow OUT

Copper tcopper FR4 tPCB

RPCB_1_H

Pin Rcopper_1_H

RPCB_n_H

RCopper_n_H

Fig. 3.11. Horizontal thermal resistance of PCB.

The horizonal thermal resistance calculation is expressed in equation (3.19) as a parallel calculation.

푅푃퐶퐵_ℎ표푟푖푧표푛푡푎푙 = 푅퐶표푝푝푒푟_1||푅PCB_1||… 푅퐶표푝푝푒푟푛||푅푃퐶퐵_푛 (3.19)

Equation (3.20) expresses the horizontal equivalent thermal conductivity of PCB Keq_h, derived from equation (3.19), including the total resistance of length d.

푑 푡퐶표푝푝푒푟퐾퐶표푝푝푒푟 + 푡푃퐶퐵퐾푃퐶퐵 퐾푒푞_ℎ표푟푖푧표푛푡푎푙 = = (3.20) 퐴‧푅푃퐶퐵_ℎ표푟푖푧표푛푡푎푙 푡푃퐶퐵

In equation (3.20), the thickness of copper layer and PCB are represented by tcopper and tPCB respectively.

Fig. 3.12 shows vertical thermal resistance due to a vertically applied heat flow. The thermal equivalent circuit model is also shown in Fig. 3.12.

RPCB_1_v Heat Flow IN

RCopper_1_v tcopper tPCB

RPCB_n_v Copper dcopper FR4 dPCB

RCopper_n_v Heat Flow OUT

Fig. 3.12. Vertical thermal resistance of PCB.

Vertical resistance appears as several resistances in series since the heat transfers through these layers continuously. The vertical thermal resistance of the PCB is calculated based on multiple vertically stacked layers of differing thermal resistance. Vertical equivalent resistance is expressed in equation (3.21) below.

푅푃퐶퐵_푣푒푟푡푖푐푎푙 = 푅푃퐶퐵_1 + 푅퐶표푝푝푒푟_1 + ⋯ 푅푃퐶퐵_푛 + 푅퐶표푝푝푒푟_푛 (3.21)

Thermal vias are placed underneath high loss power semiconductor devices to improve thermal conductivity to the cold plate heatsink. Thermal vias affect the vertical thermal resistance as heat transfers vertically across multiple vias and through the PCB material at once. Therefore, the equivalent vertical resistance of the PCB becomes the parallel of the PCB vertical resistance and via thermal resistance, as shown in Fig. 3.13.

Heat Flow IN RPCB_1_v

RCopper_1_v tcopper tPCB

RVia RVia

RPCB_n_v Copper dcopper FR4 dPCB via via RCopper_n_v Heat Flow OUT

Fig. 3.13. Vertical thermal resistance of thermal vias and PCB.

The equivalent vertical thermal resistance of the PCB area with thermal vias is shown in equation (3.22):

푅푣푒푟푡푖푐푎푙 = 푅푣푖푎|| 푅푃퐶퐵_푣푒푟푡푖푐푎푙 (3.22)

In summary, the equivalent vertical thermal conductivity can be expressed with and without thermal vias. Both expressions are shown in equation (3.23), with the via case represented by

Rvertical.

푑 푑 퐾푒푞_푣푒푟푡푖푐푎푙 = , 퐾푒푞_푣푖푎 = (3.23) (퐴 ∗ 푅푃퐶퐵_푣푒푟푡푖푐푎푙) (퐴 ∗ 푅푣푒푟푡푖푐푎푙)

The PCB equivalent thermal conductivity is required for FEA thermal simulation. Due to the uneven distribution of thermal vias, different PCB sections have different equivalent thermal resistances. For the x and y direction, the orthogonal equivalent thermal conductivity is defined by

Keq_horizontal, while the z direction is defined by Keq_vertical. The equivalent horizontal and vertical thermal conductivities are estimated for the SR and GaN PCB area. The remaining PCB thermal conductivity is also estimated. The conductivities are estimated based on the density of vias and adjusted based on thermal observation. These values are used in the thermal model for FEA simulation in Section 3.5. Table 3.3 shows the equivalent thermal conductivities.

Table 3.3. Horizontal and vertical thermal conductivities for FEA thermal simulation.

SR Area GaN Area Remaining PCB

Keq_Horizontal (W/°C•m) 88.9 88.9 88.9

Keq_Vertical (W/°C•m) 7.5 5 0.3

3.5 FEA Thermal Simulation

To predict the performance of the IMLC structure and verify experimental results, a Finite

Element Analysis (FEA) thermal simulation is conducted. Three-dimensional models are created using CAD tools and imported into ANSYS thermal simulation software. For the three structures

under test, single-PCB air cooled, single-PCB liquid cooled, and two-PCB IMLC, a separate three- dimensional model is created. All three models are shown in below Fig 3.14 to Fig 3.16 respectively. For each structure, the PCB incorporates thermal vias to improve thermal conductivity, as discussed in Section 3.4.2.

Fig. 3.14. Three-dimensional mechanical model for single-PCB air cooled.

Fig. 3.15. Three-dimensional mechanical model for single-PCB liquid cooled.

Fig. 3.16. Three-dimensional mechanical model for two-PCB IMLC.

To account for these significant changes in thermal properties, sections of the PCB were partitioned based on the density of vias. Using the equation (3.20) for Keq_Horizontal, and equation

(3.23) for Keq_Vertical, estimated thermal conductivities of sections of the PCB were developed. The conductivities for different sections are listed in Table 3.3 above. The FEA thermal simulations require the loss data calculated in section 3.4.1 as heat generation sources. For the proposed LLC converter, the heat generating loss is the same for all three PCB structures. The loss for the GaN switches (GaN), synchronous rectifier (SR), resonant inductor (Lres), parallel inductor (Lp), transformer (Tx), and PCB are shown in Table 3.2 in section 3.4.1. These losses are assigned to their respective components. A visualization of the loss components is shown in Fig. 3.17 below.

Lres Lp Tx

GaN PCB SR

Fig. 3.17. Loss distribution for the proposed 1.3kW LLC resonant converter.

The FEA thermal testing is conducted at 25°C ambient temperature which functions as a global boundary condition for the ambient. Active air cooling is incorporated into this model to provide some heat transfer. The coefficient of moving air convection is therefore increased to four times that of ambient air to account for this cooling.

Fig. 3.18 below shows the FEA thermal simulation for the single PCB structure with passive air cooling. This model shows the 1.3kW LLC power converter and the local hot spots on the PCB.

The transformers in this structure reach about 80°C. This temperature is acceptable as the magnetic devices are cooled exclusively through conduction across the large, thermally conductive magnetic core and active air cooling is applied. The SR MOSFET temperature on the PCB reaches 125°C which is at the device thermal limit. This simulated temperature shows that a single-PCB, actively air-cooled thermomechanical structure is not suitable for the proposed 1.3kW LLC converter.

Lres Lp Tx1 Tx2

GaN SR

Fig. 3.18. Thermal simulation of single PCB air cooled layout.

Fig. 3.19 below presents the thermal simulation results for the single-PCB converter with active liquid cooling via bottom side cold plate heatsinking. In this case, there is no active air cooling. A boundary condition is set on the liquid cooling cold plate to fix the temperature at 25°C by assuming the cold plate temperature is constant. The results of this test show a 50% decrease in

SR temperature compared to the air-cooled structure in Fig. 3.18 with temperature decreasing from

125°C to 79°C. The transformer temperature in this design is roughly 30°C higher due to the elimination of passive air cooling, however, this temperature is still within a safe operating temperature for a magnetic component. The significant overall decrease in surface mount component temperature suggests that both efficiency and reliability will be improved. There is a considerable temperature difference on the cold plate heatsink between the GaN and SR side. The significantly greater heat generation of the SR results in a roughly 15°C temperature difference on the cold plate, where under the GaN is roughly 55°C and under the SR is roughly 70°C.

Lres Lp Tx1 Tx2

GaN

Fig. 3.19. Thermal simulation of single PCB liquid cooled layout.

Fig. 3.20 shows the FEA thermal simulation of the new two-PCB IMLC structure. The model shows the two layers of PCB with magnetic components fixed above the top-level PCB and connected to the bottom PCB through copper connections. Surface mount components are visible from the side view on the top layer of the bottom PCB. A boundary condition is set on the liquid cooling cold plate to fix the temperature at 25°C by assuming the cold plate temperature is constant. Compared with the single-PCB liquid cooled structure in Fig. 3.19, the temperatures for the IMLC structure are nearly the same with respect to the GaN FETs, SR MOSFETs and magnetic components. Most significantly, overall package volume is reduced by 30% compared to this single-PCB liquid cooled design while maintaining thermal performance. Compared to the air cooled single-PCB design in Fig. 3.18, the SR MOSFETs are still roughly 50% cooler for the

IMLC structure.

Lres Lp Tx1 Tx2

GaN SR

Fig. 3.20. Thermal simulation of IMLC liquid cooled layout.

3.6 Experimental Results

In this section, three thermomechanical structures will be tested experimentally using a 1.3kW

LLC power converter.

3.6.1 Test Setup and Conditions

A prototype of the two-PCB liquid cooled IMLC LLC converter is assembled to verify thermal performance against traditional single-PCB structures. A single-PCB LLC power converter prototype is assembled to compare to the new IMLC structure. Thermal testing is conducted on the single-PCB with air cooling, the single- PCB with liquid cooling, and the two-PCB IMLC power converter with liquid cooling. The liquid cooling loop consists of a pump, reservoir, radiator with fans, and a cold plate heatsink. Distilled water is used as the coolant in all experiments. The pump used has a maximum flow rate of 6L/min and is operated at half speed, therefore liquid flow rate is around 3L/min. Each cooling structure is applied to a 1.3kW power converter as discussed in Table 3.1. All three structures are first tested at 14V output and 70A load current steady-state condition. For the second test operating at 14V output, 95A load current, only the liquid cooled

structures are tested to maintain safe operating temperatures. Fig. 3.21 below shows the single-

PCB structure with attached liquid cooling used in lab testing.

Fig. 3.21. Single-PCB liquid cooled prototype.

Fig. 3.22 below shows the two-PCB IMLC structure used in lab testing.

Fig. 3.22. Two-PCB IMLC prototype. 71

3.6.2 Single Phase Thermal Comparison

Fig. 3.23 shows the results of the air-cooled structure under 70A load. The transformer secondary winding is the highest temperature passive component reaching 59°C. Of the active components, the SR MOSFETs reach the highest temperature of 84.3°C. The passive components reach a maximum temperature of 59°C on the transformer secondary winding shown in Fig. 3.24.

Fig. 3.23. Temperature of SR MOSFETs with air cooling, 70A load.

Fig. 3.24. Temperature of transformer secondary winding with air cooling, 70A load. 72

The load is further increased to the rated condition of 95A output current to test the converter at rated power condition. At this condition, the SR MOSFET temperature quickly rises in temperature to 122°C. The thermal image is shown Fig. 3.25 below. This temperature indicates that active air cooling is an insufficient thermomechanical structure for this LLC converter as the temperature has effectively reached the 125°C thermal limit of the MOSFET semiconductor. This temperature agrees with the simulated 125°C FEA result observed in Fig. 3.18 for 95A load.

Fig. 3.25. Temperature of SR MOSFET with air cooling, 95A load.

Experimentation is conducted on the single-PCB structure and IMLC structure with active liquid cooling. Based on simulation, the expected thermal performance of both structures is relatively the same. The resulting thermal images for both modules are tested at rated 95A load. In

Fig. 3.26 and Fig. 3.27, the single-PCB structure with active liquid cooling is tested. The SR

MOSFETs reach a temperature of 76°C compared to 122°C for the air-cooled structure. Therefore, temperature rise is decreased by roughly 46°C. In simulation, the liquid-cooled structure reaches

78.7°C and the air-cooled structure reaches 125°C. For the passively cooled devices, specifically

the transformer, the temperature rise reaches 110°C for the liquid cooled structure compared to roughly 90°C for the air-cooled structure. This is shown in the thermal image of Fig. 3.26. In simulation, the liquid cooled transformer temperature is about 110°C compared to 79.2°C for the air-cooled structure. The increased temperature for the air-cooled experimental results can be attributed to non-ideal fan cooling. The transformer temperature increase from air to liquid cooling is attributed to the removal of convection which is the primary cooling mechanism of the magnetic devices. The peak temperature of the transformer is less significant than surface mount temperature rise, however, as magnetic device temperature tolerance is greater and temperature rise is isolated within this device.

Fig. 3.26. Temperature of SR MOSFETs with liquid cooling, 95A load.

GaN

Fig. 3.27. Temperature of GaN with liquid cooling, 95A load.

For the IMLC structure, thermal images of the surface mount devices are unavailable due to the visual impairment of the two-PCB structure. The magnetic transformer temperature is observed in

Fig. 3.28 and reaches 111°C which is nearly identical to the single-PCB liquid cooled structure.

Additionally, the 48°C resonant inductor temperature observed in Fig. 3.29 is very close to the observed magnetic temperature in the single-PCB liquid cooled structure. Both structures achieve similar thermal performance in simulation and experimentation due to nearly identical active liquid cooling implementation. Thus, the IMLC surface mount device temperatures, specifically the SR

MOSFET and GaN devices, are assumed to be very close to the single-PCB temperatures observed in Fig. 3.26 and Fig. 3.27.

Fig. 3.28. Temperature of transformers (Tx) with IMLC structure, 95A load.

Fig. 3.29. Temperature of resonant inductor (Lres) with IMLC structure, 95A load.

To verify the thermal performance of the IMLC structure versus the single-PCB structures with air or liquid cooling, efficiency is measured at a fixed operating condition. For the LLC converter, the magnetic devices are not significantly affected by temperature increases. Core loss and

conduction loss of magnetic windings are less sensitive to increases in operating temperature. The conduction loss of surface mount integrated devices, such as the SR MOSFET and GaN devices experience significant increases in device conduction resistance as operating temperature is changed. Therefore, the efficiency is expected to increase for the liquid cooled structures against the air-cooled structure. The measured efficiency versus load current of the air-cooled and liquid- cooled structures is shown in Fig. 3.30 below. Liquid-cooling can reduce peak surface mount temperature rise by 46°C which results in a 0.6% efficiency increase at 70A load. With air cooling, efficiency is increased by 0.7%. This shows that only about 0.1% of the efficiency improvement is due to the decreased magnetic temperature using air cooling, while 0.6% is due to integrated liquid cooling of surface mount devices. The IMLC structure achieves this efficiency improvement while increasing the total package power density by 31% compared to the single PCB structures.

Fig. 3.30. Efficiency comparison of different thermomechanical designs.

3.7 Conclusion

A new Integrated Multi-Layer cooling (IMLC) thermomechanical structure for power converters is developed to significantly improve power density while maintaining optimal liquid cooling thermal performance. The IMLC structure addresses three design principles to achieve higher power density and strong thermal performance: multiple PCB layers stacked vertically to utilize three-dimensional space, arranging components based on heat generation and device footprint for targeted cooling, and integrated liquid cooling for maximum conductive heat transfer.

A 1.3kW power converter is selected and loss characterized to compare power converter structure efficacy. FEA thermal simulations are conducted on three power converter prototypes: single-PCB air cooled, single-PCB liquid cooled, and two-layer IMLC. Experimental testing verifies simulated results and shows a 46°C decrease in SR surface mount temperature and 0.6% efficiency improvement for the liquid-cooled structures versus air-cooled structures at 95A load. The IMLC structure further increases power density by 31% compared to a traditional single-PCB liquid cooled structure while improving on traditional air-cooled design.

Single-Stage AC-DC Converter with Power Factor Correction Using LLC

Resonant Converter for EV Applications

4.1 Introduction

The growing electric vehicle (EV) market, specifically the plug-in electric vehicle (PEV) and plug-in electric hybrid vehicle (PHEV) are increasingly growing in popularity due to energy and environmental concerns. One major barrier to acceptance in the EV market is the charging time of the high voltage battery packs. Major research is focused on reducing charging times by increasing power ratings of the On-Board Charger (OBC) integrated into the vehicle. The OBC is responsible for converting power for the level 1 (slow) and level 2 (semi-fast) charging stations, where level 3 is handled by off-board chargers [9]. Level 1 and 2 are much more common than level 3 stations due to the ease of installation and cost. Current industry leading level-2 OBC designs operate in the 100kHz switching frequency range with efficiencies of approximately 92% to 94% and power densities of approximately 0.2 to 0.75kW/L [9] which leaves significant room for improvement in power density and efficiency. Therefore, a high-performance OBC is crucial in increasing EV acceptance as level 1 and 2 stations are most convenient and ubiquitous for consumers.

Current research is focused on developing the OBC to maximize the potential of the popular level 1 and 2 charging stations. Development has centered around two-stage converter designs which implement discrete AC-DC with Power Factor Correction (PFC) and DC-DC regulating stages to convert the AC mains supply to the 250V-430V DC voltage required by the high-voltage

EV battery packs. Different AC-DC converters have been proposed, including traditional boost converter [11] [14], two-stage bridgeless totem pole converter [14] - [16], and LLC resonant

79 converters [65]. The bridgeless-totem pole topology is most widely adopted today due to the elimination of high loss input diodes to increase efficiency and reduce loss. Further research has been conducted to improve efficiency and power density by replacing silicon devices with wide bandgap devices (WBG) such as GaN [12] [14] and SiC transistors [15] [16]. Some designs have been proposed to combine the two stages using various DC-DC converters [17] [18] [19].

Currently, OBC designs consist of two-stage designs typically incorporating a bridgeless totem pole boost converter to handle the AC-DC conversion, followed by an LLC or CLLC converter to handle DC-DC conversion. While these designs offer tight regulation of output voltage and predictable operation of both stages due to the decoupling of the AC and DC stages, the increase in switching components, especially large magnetic devices, results in higher loss, larger size, and higher cost. Additionally, current designs using silicon switches in the AC-DC stage limit the bidirectional operation due to large reverse recovery losses.

A single-stage design is desired to overcome the limitations of the traditional two-stage designs.

Recent research has been conducted on designing and implementing a single stage AC-DC converter using a single LLC converter [66] [67] [68]. This design has been proven to operate as both the AC-DC PFC stage and the DC-DC regulating stage simultaneously. The PFC inductor and additional switching components can be eliminated which promises higher efficiency, lower cost, and smaller size.

This chapter will introduce a new single stage LLC AC-DC PFC converter for OBC EV application. This topology offers to combine the AC-DC and DC-DC stages of a traditional two- stage design to eliminate magnetic and switching components, increase efficiency, reduce size, and reduce cost. This chapter is organized into the following sections: Section 4.2 presents a review of current academic literature, Section 4.3 describes the design principles and mathematical

80 analysis for the single stage LLC AC-DC converter; Section 4.4 presents the circuit simulation and verification of the topology; Section 4.5 presents the prototype circuit design and fabrication;

Section 4.6 presents the experimental results; Section 4.7 concludes the chapter.

4.2 Literature Review

The growing electrified vehicle (EV) market has exploded in recent years due to increasing demand for efficient and clean transportation. Research and development have focused on developing new high-power density converters to make EV’s a reality. One such converter of chief importance is the EV On-Board Charger (OBC), which is the AC/DC converter that transmits power from an EV wall charger to the main high-voltage (HV) battery packs of the EV. The power rating and power density of the OBC is critical in determining the maximum power and charging time the EV will experience in charging mode from a regular 120Vac or 220Vac mains outlet. This will be the primary charging scenario for most EV users as they plug in their vehicles for charging at their home or workplace. The challenge faced in designing OBCs is achieving high efficiency, high power density, and adequate thermal management to maximize the charging potential of the vehicle while minimizing vehicle weight and size.

Extensive academic and industry effort is focused on improving converter topologies and designs to improve OBC power ratings, power density, efficiency, and size. For a traditional OBC, the converter consists of an AC-DC stage with active PFC to achieve maximum efficiency, power factor, and minimum distortion at the AC mains. Additionally, the OBC must incorporate a second

DC-DC stage to regulate the voltage to the correct voltage desired by the HV battery pack. A conventional design that is based on traditional boost PFC design is the silicon based boost PFC rectifier with an isolated DC-DC stage, commonly an LLC or CLLC converter [14] [11]. This topology is shown in Fig. 4.1 below.

Boost PFC VDC CLLC Resonant Converter Vout 400V 250-450V

L L pri N:1 sec

Vac Clink Cout Vout

Fig. 4.1. A Boost PFC converter with CLLC resonant stage for EV On-Board Charger.

This design is popular due to the ubiquity of Boost PFC designs currently studied, which increases simplicity and reliability. The main drawback to this design is the unidirectional power flow and heavy switching losses generated in the AC-DC boost PFC stage due primarily to hard switching.

One of the most popular configurations used to achieve high performance regulated AC-DC with active PFC is the two-stage bridgeless totem pole PFC with CLLC resonant converter topology. This topology is studied extensively in research [14] - [16]. In [14], 96% peak efficiency is achieved at 2.26kW/L power density which leads academia. The dual-boost bridgeless totem pole PFC converter with CLLC stage topology is shown in Fig. 4.2 below.

Dual-Boost Bridgeless PFC VDC CLLC Resonant Converter Vout 400V 250-450V

L L pri N:1 sec

Vac Clink Cout Vout

Fig. 4.2. A dual-boost bridgeless PFC converter with CLLC stage for EV On-Board Charger.

This converter topology offers many advantages for the OBC application. Firstly, the implementation of the CLLC converter allows for bidirectional power flow. This is especially useful for EV applications as the vehicle may supply power to the home (V2H) when there is a power outage or to supplement electricity costs during peak hours. Secondly, a two-stage topology allows for adequate control for the AC-DC and DC-DC stages. The dual-boost bridgeless PFC

AC-DC stage allows for a fixed 400V DC link voltage to be achieved with near unity power factor.

This DC link capacitor allows for the 120Hz double line frequency and switching frequency noise to be eliminated in the DC-DC stage. The DC-DC CLLC resonant converter stage allows for output voltage regulation and magnetic isolation between the source and load. The limitation of the AC-

DC stage is the significant switching loss and large reverse recovery loss when using silicon switching devices, limiting bidirectional power flow capabilities. Also, the bridgeless design increases EMI at the AC input [9]. For the DC-DC stage, a small zero-voltage switching (ZVS) range and high turn-off losses due to Coss capacitance is experienced. Overall, this design suffers most greatly due to the inherent inefficiency experienced due to a two-stage design. The requirement of two switching converters reduces maximum attainable efficiency due to the increase in semiconductor devices and magnetics compared to a single stage design.

Additional two-stage models have been proposed utilizing different topologies and devices for the first and second stage. In [65], an LLC converter is used in the AC-DC PFC stage and a boost converter in the DC-DC stage. In [15] [16], SiC devices are used to increase DC link voltage and improve efficiency over silicon. In [69], a two-stage converter with a SEPIC converter in the AC-

DC stage is proposed. In [70], a two-stage converter using a Cuk converter in the AC-DC stage is proposed. The inherent problem with all two-stage solutions is the increased complexity and

83 inherent inefficiency of introducing an additional switching stage. This requires more switching and magnetic devices, increasing cost and size while reducing efficiency.

Some research has focused on combining the two-stages of the conventional converter design into one stage to eliminate additional switching components thereby reducing loss, cost, and size.

Such designs have been implemented using various combinations of converters. In [17], a Boost-

Flyback converter is proposed to address the limitations of the two-stage designs. This design uses the primary side of the Flyback converter to control the boost inductor current and transfer power to the load. This design however suffers from low efficiency and constant DC transformer current inherent in the Flyback converter design, further reducing efficiency. In [18] [19], a new single- stage topology is proposed that combines the boost stage of a traditional dual-boost bridgeless PFC converter with the inverter bridge of an LLC converter. The LLC inverter acts to control the interleaved boost inductors, reducing switching stages to one. This design achieves efficiency gains over two-stage designs due to lower component counts, however, the boost inductors are retained thereby increased magnetic loss and substantially increasing device size.

Recently, a new methodology has been studied based on the single-stage LLC converter for

AC-DC PFC applications studied in [66] and [67]. In [68], a mathematical analysis is presented for a single-stage LLC converter for PFC applications. The topology consists of a bridge rectifier followed by an LLC converter with frequency control implemented to track the input current and achieve PFC. A diagram of this topology is shown in Fig. 4.3 below.

LLC Resonant Converter

L L r N:1 sec Vac Lm Cout Vout

Tx Cr

Fig. 4.3. A half-bridge LLC resonant PFC converter for EV On-Board Charger.

This design benefits from the high efficiency of the LLC resonant converter and the improved size, cost, and efficiency achieved when eliminating the second switching stage and switching components. The design of a single stage also improves simplicity in both design and implementation and can sufficiently regulate output voltage [67]. There are several design challenges for this topology. Firstly, large gain requirements near input zero voltage crossing are required to maintain output voltage regulation. As such, magnetic design must be compromised as the switching frequency range must be wide. Secondly, twice the rated power is required to be processed at peak input condition to achieve PFC which increases converter loss. Finally, double line frequency output voltage ripple must be filtered through large electrolytic capacitor banks which increases device size.

4.3 Design and Analysis of Single-Stage LLC for PFC Operation

In this section, the mathematical design of the single-stage LLC converter for PFC operation is described based on work in [68]. The design procedure is applied to the 1.65kW design proposed for the OBC application to derive the final LLC resonant component and operating parameters.

4.3.1 Single-Stage Mathematical Design

There are many different PFC topologies in use today that offer relatively high efficiency and high-power density. However, most designs consist of a two-stages which increase complexity, switching components, and consequently limit size and efficiency. Some research has been conducted on single-stage PFC designs using LLC resonant converters [66] [67] [68]. A 1.65kW single-stage LLC converter with PFC is proposed for the OBC application. In future study, four parallel LLC phases will be assembled to achieve a 6.6kW OBC power rating. Mathematical design studied in [68] is used to select the LLC resonant components and operating frequency range. Firstly, the theoretical design parameters must be established.

An LLC resonant converter must first be designed to operate inductively to achieve Zero-

Voltage Switching (ZVS). This means the switching frequency must always be larger than the parallel resonant frequency, Fr2, which is described in equation (4.1) below and determined by the parallel resonance of Lp with the series resonance of Lres and Cres.

1 퐹푟2 = (4.1) 2휋√(퐿푝 + 퐿푟푒푠) ∗ 퐶푟푒푠

To achieve Zero-Current Switching (ZCS), the resonant converter must also operate below the series resonant frequency, Fr1, which is described in equation (4.11) below.

1 퐹푟1 = (4.2) 2휋√퐿푟푒푠 ∗ 퐶푟푒푠

Therefore, the basic frequency range of the LLC converter is established.

The gain of the converter is the critical design decision for a single-stage LLC converter PFC design. The requirement of the resonant tank gain is such that minimum gain requirement is met

when the converter operates close to Fr1. Conversely, the resonant tank must be designed to achieve maximum gain when the converter is operating close to Fr2. The LLC converter must achieve the required gain at all output voltage levels and different phase angles of the AC input voltage. It is observed that the gain required to achieve PFC at varying input voltage phase angles changes in proportion to the converter output power requirements. A plot of the input voltage, LLC gain requirement, and output power (Pout) requirement is shown in Fig. 4.4 below based on the work studied in [68].

Fig. 4.4. A plot of the input voltage (Vin), required gain (Greq), and output power (Pout) for input

voltage phase angle, θ [68].

The gain required at varying input voltage phase angles, θ, is shown in equation (4.3) below.

푉표푢푡(푚푎푥) 퐺푟푒푞(휃) = 휆 (4.3) √2 ∗ 푉푖푛(푟푚푠) ∗ sin (휃)

Where Vout(max) is the maximum DC output voltage which requires maximum gain, Vin(rms) is the RMS AC input voltage, θ is the phase angle of the input voltage, and 휆 is the ratio of the DC output voltage to the maximum DC output voltage, given in equation (4.4).

푉표푢푡 휆 = (4.4) 푉표푢푡(푚푎푥)

The relationship between the LLC tank gain and Pout is critical. When Pout decreases, output resistance (Rac) increases linearly, which results in increasing converter gain based on the expression for quality factor given in equation (4.5) below.

퐿 √ 푟푒푠 퐶 (4.5) 푄(휃) = 푟푒푠 푅푎푐(휃)

Since the Rac increases proportionately with the phase angle, the Rac can be expressed as the rated Rac times the squared sine wave of the input voltage phase angle. The result is shown in (4.6) below.

퐿 √ 푟푒푠 2 퐶푟푒푠 2 (4.6) 푄(휃) = 2 ∗ (sin 휃) ∗ = 2 ∗ (sin 휃) ∗ 푄푟푎푡푒푑 푅푎푐(푟푎푡푒푑)

Qrated is the quality factor at rated power condition. The expression for Qrated is given in equation

(4.7) below based on the fundamental harmonic approximation (FHA) and rated voltage and current of the output.

휋2 퐼 퐿 표푢푡 푟푒푠 (4.7) 푄푟푎푡푒푑 = 2 ∗ ∗ √ 8푛 푉표푢푡 퐶푟푒푠

Equation (4.6) shows that the maximum Q, and consequently minimum gain occurs when

θ=90°. This means that to design for worst case input/output voltage condition, only the θ=90° case needs to be satisfied.

The worst case requirement is designed at minimum input voltage and maximum output voltage. At this condition, Fsw is at Fr2 to allow the LLC to achieve peak gain, and the input voltage phase angle is at a maximum of θ=90° which is the lowest gain condition of the input voltage. The maximum gain must be designed at these conditions to ensure the gain is met at all other input conditions. Because this converter operates at varying input and output voltage ranges, the maximum gain must vary proportionately to the change in the input and output voltages. Therefore, the required gain is equal to the product of the input and output voltage ratios. The resulting gain requirement is expressed in equation (4.8) below based on work in [68].

1 퐺푎푖푛푟푒푞(푓푠푤 = 퐹푟2, 휃 = 90°) = 푘2 √ ∗ 2 ∗ 푄 1 + 푘 푟푎푡푒푑(푉표푢푡(푚푎푥)) (4.8)

푉 ( )( ) 푉 ( ) ≥ 푖푛 푟푚푠 푚푎푥 ∗ 표푢푡 푚푎푥 푉푖푛(푟푚푠)(푚푖푛) 푉표푢푡(푚푖푛)

The variable k is defined in equation (4.9) below as the ratio of magnetizing inductance to the resonant inductance.

퐿 푘 = 푚 (4.9) 퐿푟푒푠

To design for the minimum gain condition of the converter, the transformer is designed to achieve the required minimum gain at the series resonant frequency Fr1. At Fr1, the LLC gain is unity. The transformer must be designed so the gain at Fr1 is equal to ratio of maximum input voltage to minimum output voltage. The calculation of the transformer turns ratio, n, is given in equation (4.10) below.

푉푖푛(푟푚푠)(max) 푛 = (4.10) √2 ∗ 푉표푢푡(min)

4.3.2 LLC Parameters and Component Selection

Using equation (4.8) and (4.10), the resonant tank can be designed. For the single-stage LLC

PFC converter in this design, the resonant components were selected to operate at the desired electrical conditions. A summary of the electrical parameters and the derived resonant components, Lres, Lp, Cres, and the transformer turns ratio are shown in Table 4.1 below.

Table 4.1. Parameters designed for the single-stage LLC converter.

Input Output Voltage Switching Power Lres Lp Cres Ntx Voltage (Vin) (Vout) Frequency (fsw) Rating

200-240Vac 250-430V 350-650kHz 1.65kW 8.5uH 21uH 7nF 23:17

4.4 Simulation of Topology

In this section, the simulation of the DC-DC and AC-DC PFC operation of the single-stage

LLC converter is described.

4.4.1 DC-DC LLC Stage Simulation

To verify the feasibility of the single-stage LLC converter for PFC operation, the LLC stage must be able to operate in DC-DC condition for the maximum and minimum gain conditions. The

LLC converter must operate at all the phase angles of the input voltage. As described in Section

4.3, the gain of the LLC converter must adjust according to the phase angle of the input voltage.

When the phase angle of the input voltage is low, such as at 10°, the gain of the LLC converter must be high to transfer power to the load. Around line cycle peak, such as at 90° phase angle, the gain of the LLC converter will be close to unity. To modulate the gain of the LLC converter, the switching frequency is adjusted. Increasing switching frequency results in a decrease in gain towards unity which is achieved at the Fr1 series resonant frequency. Decreasing switching frequency increases the gain towards peak gain which is achieved at the Fr2 parallel resonant frequency. The gain required for different input voltage phase angles are calculated based on the equation shown in equation (4.11) below.

푉표푢푡(퐷퐶) 1 퐺푎푖푛푟푒푞 = ∗ (4.11) 푉푖푛(휃) 푛

For this equation, Vout(DC) is the average DC output voltage, Vin(θ) is the input voltage at a discrete phase angle θ, and n is the turns ratio of the transformer. The gain is calculated for the minimum and maximum AC-DC operating conditions. For the maximum gain requirement, Vin is

200Vac and Vout is 430V. For the minimum gain requirement, Vin is 240Vac and Vout is 250V. Table

4.2 below shows the operating parameters for the maximum gain requirement. Switching frequency is determined through DC-DC simulation at fixed DC input conditions representing the

AC input voltage from θ=10° to 90°.

Table 4.2. Fixed DC-DC operating conditions at maximum gain condition. Vin = 200Vac, Vout =

430V, Pout = 1.65kW.

θ (°) Vin(V) Iin (A) P(W) Vout (V) Iout (A) Rload (Ω) Gainreq Fsw (kHz)

90 283 11.7 3300 430 7.7 56.0 2.06 431

80 279 11.5 3200 430 7.4 57.8 2.09 429

70 266 11.0 2913 430 6.8 63.5 2.19 424

60 245 10.1 2474 430 5.8 74.7 2.38 416

50 217 8.9 1936 430 4.5 95.5 2.69 407

40 182 7.5 1363 430 3.2 135.7 3.20 398

30 141 5.8 825 430 1.9 224.2 4.12 389

20 97 4.0 386 430 0.9 479.2 6.02 377

10 49 2.0 99 430 0.2 1859.1 11.9 363

For the minimum gain requirement, the operating parameters are calculated and summarized in

Table 4.3 below. The switching frequency fsw is also obtained from PSIM simulation for a fixed

DC operating condition at each angle θ.

Table 4.3. Fixed DC-DC operating conditions at minimum gain condition. Vin = 200Vac, Vout =

250V, Pout = 1.25kW.

θ (°) Vin(V) Iin (A) P(W) Vout (V) Iout (A) Rload (Ω) Gainreq Fsw (kHz)

90 339 7.4 2500 250 10.0 25.0 1.00 654

80 334 7.3 2424 250 9.7 25.8 1.01 644

70 319 6.9 2207 250 8.8 28.3 1.06 623

60 294 6.4 1874 250 7.5 33.3 1.15 582

50 260 5.6 1467 250 5.9 42.6 1.30 530

40 218 4.7 1033 250 4.1 60.5 1.55 484

30 170 3.7 625 250 2.5 100.0 1.99 445

20 116 2.5 292 250 1.2 213.8 2.92 411

10 59 1.3 75 250 0.3 829.5 5.74 379

For the LLC resonant tank design described in Section 4.3, the switching frequency range is limited from 350kHz to 655kHz, which represents the Fr2 and Fr1 resonant frequencies respectively. These limits force the LLC to operate above the capacitive region left of Fr2 and the within the secondary side zero current crossing (ZCS) region to the left of Fr1. For the maximum gain requirement in Table 4.2, the minimum required frequency at 10° phase angle is 363kHz which is within the LLC operating frequency limits. For the minimum gain requirement in Table

4.3, the minimum gain is required at 90° with a maximum switching frequency of 654kHz. This frequency is also within the LLC operating frequency limits.

Simulation is used to verify that the LLC converter is operating within the specified frequency range and is achieving ZVS and ZCS by operating between Fr1 and Fr2. To verify this condition, the resonant current Ires, GaN LLC inverter voltage VDS, secondary side rectified current Isec, and secondary side bridge rectifier voltage Vsec are monitored. The resulting waveforms for the maximum gain requirement described in Table 4.2 are shown in Fig. 4.5 below. The parameters for this test are Vin(ac) = 200V, Vin(θ=10°) = 49V, Vout = 430V.

ZCS

ZVS

Fig. 4.5. Waveforms for maximum gain requirement confirming ZVS and ZCS at Vin(ac) = 200V,

Vin(θ=10°) = 49V, Vout = 430V.

The waveforms for the minimum gain requirement are shown in Fig. 4.6 below. The parameters for this test are Vin(ac) = 240V, Vin(θ=90°) = 339V, Vout = 250V.

ZCS

ZVS

Fig. 4.6. Waveforms for minimum gain condition confirming ZVS and ZCS at Vin(ac) = 240V,

Vin(θ=90°) = 339V, Vout = 250V.

Both waveforms in Fig. 4.6 show that ZVS and ZCS are achieved which verifies the LLC converter can achieve PFC for all operating conditions.

4.4.2 AC-DC PFC Simulation

A simulation of the complete AC-DC PFC operation of the proposed 1.65kW LLC single-stage converter is completed to validate the theoretical design for the full AC-DC OBC application. The

simulation is conducted at the maximum gain condition of Vin = 200Vac, Vout = 430V, and Pout =

1650W. A second test is conducted at nominal condition, where Vin is 220Vac, Vout is 330V, and

Pout = 1650W. The simulation must verify that the single stage design can achieve suitable power factor (PF), total harmonic distortion (THD), and output voltage double line frequency ripple.

Fig. 4.7 below shows the maximum gain requirement of the LLC converter with Vin = 200Vac,

Vout = 430V, and Pout = 1650W. Waveform Iac is the input current which achieves a PF of 99.3% and THD of 4.7%. The input voltage is shown below as waveform Vac. Waveform Vo below shows the output voltage. The double line frequency ripple is about 11Vpk, about 2.6% of the 430V output.

Fig. 4.7. Vin = 200Vac, Vout = 430V, Iin(rms) = 8.46A, PF = 99.3%, THD = 4.7%.

Fig. 4.8 below shows the nominal operating condition with an input voltage of 220Vac, output voltage of 330V, and output power of 1650W. At this condition, the average load current is the greatest at approximately 5A. At this condition, the PF achieved is 98.9% and input current THD is 3.53%. The double line frequency output voltage ripple is roughly 14Vpk-pk which is around

4.2% of the 330V output voltage.

Fig. 4.8. Vin = 220Vac, Vout = 330V, Iin(rms) = 7.77A, PF = 98.9%, THD = 3.53%

Therefore, the AC-DC PFC simulation verifies the single-stage LLC PFC design for complete

1.65kW PFC operation.

4.5 Prototype Circuit Design and Fabrication

This section introduces the PCB circuit design and fabrication for the single-stage AC-DC converter with PFC using LLC resonant converter for EV OBC applications. The control circuitry, input current sensing, input voltage sensing, AC power loop layout, and double-line frequency output capacitor banks designs are described in this section.

4.5.1 LLC Control Block Diagram

The prototype circuit design of the single-stage LLC PFC converter consists of the power components and control components. For the power components, the primary components are the

AC source, the input bridge synchronous rectifier, DC-DC LLC converter, output diode rectifier, output capacitance, and load. For the control circuitry, the primary components consist of the input current, Iac, sensing circuitry, rectified voltage, Vrec, sensing circuitry, and output voltage, Vout, sensing circuitry. A block diagram of the primary power and control circuitry for the LLC converter design is shown in Fig. 4.9 below.

L + res N:1 Iac

Lm Vac Vrec Cout Vout

Tx - Cres

Synchronous LLC Converter Diode Rectifier PFM Rectifier

PI Vout

Iac Irec Verr - Iac Rectifier - + Optocoupler PI Iref + Kvsns KvsnsVrec Verr Verr Vref Vrec multiplier Fig. 4.9. Single-stage LLC PFC converter control block diagram.

For the experimental testing, the output voltage loop is left in open loop as the primary focus is towards achieving optimal PFC performance through current loop design optimization. Therefore, the voltage error signal, Verr, shown in red above, is set to a fixed value. Synchronous MOSFETs are used for the input bridge rectifier to reduce conduction loss compared to diodes. GaN Wide

Bandgap (WBG) switches are used for the full bridge inverter of the LLC resonant converter to further reduce switching and conduction loss and allow for higher switching frequency. Design of the input current sensing loop, input voltage sensing loop, LLC AC power loop, and output voltage capacitor bank is described in the following sections.

4.5.2 Input Current Sensing Design

To achieve PFC, the input current, Iac, must be sensed as described in section 4.5.1. There are several ways to sense the input current of the converter. The design selected for this converter consists of a magnetic Hall sensor with its output fed into an analog RC filter. The hall sensor passively measures the current through the Hall Effect and does not introduce any impedance into the power loop. The hall sensor outputs a voltage signal with a 2.5V bias, VH_bias. This bias is reduced externally to 2V to prevent MCU ADC saturation. The hall sensor senses the AC input current before the rectifier bridge at the AC-DC stage. The location of the hall sensor is shown in

Fig. 4.10 below.

VHall Iac

VCC

Vac Vrec

Fig. 4.10. Circuit diagram showing the location of the Hall sensor for input current sensing.

The hall sensor senses the AC input current. The sensing signal, VHall, is proportional to the input current by a factor of coefficient, Kisns, in addition to the Hall sensor bias, VH_bias. The sensing bias is given in the Hall sensor device datasheet depending on the device configuration. For this sensor, the sensing sensitivity is 80mV/A. A signal waveform of the AC input current, Iac, and the

Hall sensor output is shown in Fig. 4.11 below.

Iac VHall VHmax

VH_Bias t V Hmin t

Fig. 4.11. Signal waveform of Hall sensor.

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The output of this signal is a voltage signal proportional to the input current and the hall sensing bias, expressed in equation (4.12) below.

푉퐻푎푙푙 = 푉퐻_푏푖푎푠 + 퐼푎푐 ∗ 퐾푖푠푛푠 (4.12)

For the proposed 1.65kW LLC converter, the peak input current is 11.7A with an input voltage of 200Vac(rms). Therefore, the maximum and minimum VHall voltages are calculated in equations

(4.13) and (4.14) respectively.

80푚푉 푉 = 2푉 + (11.7퐴) ∗ ( ) = 2.96푉 (4.13) 퐻푎푙푙(max) 퐴

80푚푉 푉 = 2푉 − (11.7퐴) ∗ ( ) = 1.064푉 (4.14) 퐻푎푙푙(푚푖푛) 퐴

The VHall voltage range must be between 0 and 3.3V to be properly sensed by the 3.3V MCU.

In addition, it is desirable to filter the switching frequency noise in the sensed current signal by limiting the sensing bandwidth. The desired current sensing signal captures the line frequency current, which is a 60Hz low frequency signal, therefore high frequency signals should be filtered.

To condition the gain and filter the VHall current signal, an RC filter is used. The bandwidth of the

RC filter is shown in equation (4.15)

1 퐹퐼_푅퐶 = = 16푘퐻푧 (4.15) 2휋√(10푘훺)(1푛퐹)

The bandwidth is 16kHz, which is more than 200 times greater than the 60Hz input current signal. Additionally, the bandwidth is significantly less than the 350-650kHz switching frequency which makes 16kHz a suitable cutoff frequency to filter switching frequency noise. The circuit

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diagram of the current sensing is shown in Fig. 4.12 below. The hall sensor signal, VHall, and filtered current sensing signal, Isense_LF, are shown.

Fig. 4.12. Circuit diagram of the hall sensor for current sensing.

The resulting waveform of the filtered current signal, VIsense_LF is shown in Fig. 4.13 below compared to the source input current signal, Iac. The VIsense_LF(max) and VIsense_LF(min) are the filtered values of VHall(max) and VHall(min) respectively.

I V ac Isense_LF VIsense_LF(max)

t V Isense_LF(min) t

Fig. 4.13. Current sensing waveform after RC filter circuit.

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The signal sensed by the MCU is converted to a digital signal and rectified using an absolute value calculation. The bias is removed by subtracting the 2V DC bias voltage introduced by the hall sensor. This signal becomes the sensed current signal and is shown in Fig. 4.14 below.

V Isns Isense_LF VIsense_LF(max)

0.5*VIsense_LF(max/min)

V Isense_LF(min) t t

Fig. 4.14. Sensed current signal waveform.

4.5.3 Input Voltage Sensing Design

For PFC, the input voltage Vrec serves as the current reference signal to shape the input current correctly. The switching converter, in this case an LLC converter, is controlled so the input current achieves optimal power factor with respect to input voltage and lowest total harmonic distortion

(THD). Therefore, the input voltage must be sensed to generate this reference signal. Vrec is more suitable as a reference signal compared to Vac as Vrec has a common ground with the sensing circuitry. Vrec can be sensed using voltage sensing on the output of the diode bridge. The location of the sensing terminals is shown in Fig. 4.15 below.

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V ac Vrec Vrec

Vrec_s

Fig. 4.15. Sensing location of input voltage Vrec.

The rectified voltage signal Vrec has a range of 0 to 340Vpk for the 240Vac input case. Therefore, the voltage is step down using a voltage divider of gain Kvsns. The step-down signal is input into an op amp circuit to filter any signal noise. The sensing circuitry is shown in Fig. 4.16 below.

Fig. 4.16. Input voltage sensing circuitry.

The op amp is configured as a non-inverting voltage follower. The gain Kvsns applies a gain of

1/111, which reduces the sensing voltage amplitude to a range of 0V to 3.06V which is within the

3.3V range of the MCU ADC.

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The input capacitor C51 and resistors R18, R19, and R20 form a low pass filter with a bandwidth of 8kHz shown in equation (4.16) below.

1 퐹푉_푖푛 = = 8푘퐻푧 (4.16) 2휋√(2.2푀||20푘) ∗ (1푛퐹)

The output filter is formed by C52 and R21 which has a bandwidth of shown in equation below.

Both filters are designed to be great than 100 times the signal frequency of Vrec, which is a double- line frequency signal of 120Hz.

1 퐹푉_표푢푡 = = 16푘퐻푧 (4.17) 2휋√(10푘훺)(1푛퐹)

The voltage sensing signal, Vrec_s is sensed by the MCU to generate the voltage reference signal used to shape the input current for PFC.

4.5.4 PCB Layout Design of AC Power Loop

The AC power loop of the LLC resonant converter is a critical design consideration in the PCB layout design. The power polygons that carry high current power signals must be designed correctly to achieve the optimal converter performance. From a DC perspective, longer power loops increase copper length and therefore increase DC conduction loss. Long power loops for high power AC signals can create parasitic inductance and capacitances due to path turns and proximity [71]. The parasitic inductance can induce ringing which can appear in the ground path and effect sensing and driving circuitry. In addition, AC loops with asymmetrical power loops for positive and negative cycles can cause parasitic imbalances which can further increase parasitic resonant ringing and lead to loss imbalances. Finally, these parasitic properties increase impedance

105 and therefore converter loss which reduces efficiency and increases heat generation. Thus, the AC power loop must be designed as short and straight as possible to eliminate these problems.

For the LLC resonant converter used in the proposed single-stage 1.65kW AC-DC single-stage

LLC resonant converter, the AC loop is designed to have the shortest and straightest path possible.

The loop length for the positive and negative half cycles of the full-bridge LLC converter are roughly the same length and shape to mitigate parasitic and loss imbalances. Fig. 4.17 below shows the PCB layout design for the LLC converter operating in the positive half cycle.

Vrect Lres -

GaN LLC Bridge

Lp Tx

Fig. 4.17. PCB layout design for the LLC converter operating in the positive half cycle.

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Fig. 4.18 below shows the PCB layout design for the LLC converter operating in the negative half cycle.

Vrect Lres -

GaN LLC Bridge

Lp Tx

Fig. 4.18. PCB layout design for the LLC converter operating in the negative half cycle.

The conduction path for the negative half cycle is slightly longer than the positive half cycle.

There is also one extra 90° turn for the negative cycle to reverse the current flow for the LLC resonant tank negative half cycle. Overall, the current paths are relatively equal, and the resulting positive and negative half cycle waveforms are expected to be comparable. The prototype of the power loop is highlighted in Fig. 4.19 below.

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Fig. 4.19. LLC PFC prototype power loop PCB design.

4.5.5 Double Line Frequency Output Capacitor Design

For the single-stage LLC converter design, a double-line 120Hz ripple will propagate to the output to achieve PFC operation. The LLC converter controls the input current, Irec, by tracking the rectified sinusoidal input voltage, Vrec through frequency modulation. The double line frequency ripple cannot be sufficiently attenuated by the LLC converter due to the extremely low frequency and desire to maintain PFC performance. Therefore, a large output capacitor bank is required to filter the double line frequency ripple.

The selection of the output capacitor bank is critical to reduce the output voltage ripple seen at the load at the cost of increased package size. Due to the low frequency of the double line frequency ripple, the time constant required for the capacitor bank filter is very large. In addition, output voltage for this application reaches a maximum of 430V. Therefore, a physically large electrolytic capacitor bank is required to attenuate this ripple. Therefore, it is critical to select the appropriate capacitor bank to keep device size as small as possible. The selection of the capacitor bank is

108 designed based on the charging and discharging energy the capacitor must store. When the input power is greater than the average power drawn by the load, the output capacitor must store energy.

When the input power is less than the average power, the output capacitor must supply energy to the load. This extra energy, ∆E, creates a double line frequency ripple across the output capacitor

Cout. A waveform showing the output power to the load and corresponding Cout voltage is shown in Fig. 4.20 below.

Pcout

Charging

Pout_avg Discharging t

Vcout

Vout_avg Vout

Fig. 4.20. Signal waveforms of the output power and resulting Cout voltage.

The extra energy stored in the capacitor, ∆E, determines the output voltage ripple. The expression for ∆E is shown in equation (4.18) below.

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135°/푤 ∆퐸 = ∫ (푃푖푛(푤푡) − 푃푖푛(푎푣𝑔))푑푡 (4.18) 45°/푤

Where Pin(wt) is the instantaneous power, and Pin(avg) is the average power drawn by the load.

Assuming the converter is lossless, the average input power is equal to the average output power.

Therefore, the expression for extra energy can be defined in equation (4.19) below.

푃푖푛(푎푣𝑔) 푃표푢푡(푎푣𝑔) ∆퐸 = = (4.19) 푤 푤

This equation can be rearranged based on the relationship between the output power and the load. The resulting expression is given in equation (4.20) below.

푉 ∗ 퐼 ∆퐸 = 표푢푡 표푢푡 (4.20) 푤

The energy expression for a capacitor is based on equation (4.21) below.

1 1 ∆퐸 = 퐶푉2 = 퐶(푉2 − 푉2 ) = 퐶∆푉 ∗ 푉 (4.21) 2 2 표푢푡(푚푎푥) 표푢푡(푚푖푛) 표푢푡 표푢푡

Where Vout(max) and Vout(min) are the maximum and minimum amplitude of the output capacitor voltage, which can also be expressed as ∆Vout. Combining equation (4.20) and (4.21) gives a final expression to calculate the required output capacitance to achieve a desired Vout ripple.

Equation (4.22) below shows the calculation for Crequired.

퐼표푢푡 퐶푟푒푞푢푖푟푒푑 = (4.22) 2휋 ∗ 푓푠푤 ∗ ∆푉표푢푡

For the proposed LLC converter, the maximum average load current is 5A for the 330V output condition and 250V derated condition. The line frequency is 60Hz, and the target output voltage

110

ripple ∆Vout is 20V, less than 10% of the 250V output condition. The required capacitance value is calculated in equation (4.23) below.

5 퐶 = = 663푢퐹 (4.23) 푟푒푞푢푖푟푒푑 2휋(60)(20)

The required capacitance for this design is 663uF. The capacitor rating must be at least 450V to manage the 430V output condition. The selected capacitor bank for this design is two 470uF

450V electrolytic capacitors to ensure enough capacitance and to achieve minimum package volume.

The RMS current through each 470uF capacitor is calculated using equation (4.24) below.

퐼푐(푟푚푠) = ∆푉표푢푡 ∗ 2휋 ∗ 푓푠푤 ∗ 퐶 = 1.77퐴 (4.24)

Therefore, each capacitor experiences an RMS current of 1.77A. The selected capacitors are rated for 2.5A to ensure safe operation. A picture of the prototype capacitor bank is shown in Fig.

4.21 below.

Fig. 4.21. Prototype with the electrolytic capacitor bank highlighted.

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4.6 Experimental Results

This section discusses the experimental prototype and the results for the DC-DC and AC-DC test conditions for the single-stage AC-DC converter with PFC using LLC resonant converter for the EV OBC application.

4.6.1 Experimental Prototype

For the experimental testing, a prototype is developed using a 4-layer PCB. The dimensions of the PCB are 240mm x 75mm x 40mm which results in 2.3kW/L power density for the 1.65kW design. The prototype is shown in Fig. 4.22 below.

Fig. 4.22. Full experimental prototype of the single-stage AC-DC LLC resonant converter with

PFC for the EV OBC application.

4.6.2 DC-DC LLC Test

To verify the feasibility of a single-stage LLC for PFC, experimental testing is conducted at fixed DC operating points to isolate the LLC performance. This testing is the same as the fixed

DC simulation conducted in Section 4.4.1. The conditions for minimum and maximum gain are critical testing points to ensure the converter can achieve the required peak gain and can maintain

ZVS and ZCS by remaining within LLC frequency range.

112

DC-DC testing is conducted at several conditions to verify the feasibility of the AC-DC operation. For the testing, the minimum AC input voltage is 200Vac. During one line-cycle, the

RMS voltage of the AC input voltage is equivalent to the AC voltage at 45° phase angle. This value is the input RMS voltage of 200V. Therefore, the rated voltage for the minimum input condition of 200Vac is used for the DC-DC testing. For the load side, the DC-DC testing is conducted for various output voltage conditions. For the OBC application, the output voltage ranges from 250VDC to 430VDC. From 330VDC to 430VDC, the load draws rated power of 1.65kW.

This corresponds to a peak 5A average load current at 330VDC. At 250VDC, the power is derated to maintain the maximum 5A load current. Therefore, at 250VDC the load draws 5A current corresponding to 1.25kW output power.

The first test is conducted at the 200VDC condition corresponding to the rated voltage of the

200VAC input voltage. The output voltage in this case is 250VDC, which is the minimum output voltage at the 1.25kW derated power. The average load current in this condition is 5A. The waveforms for this condition are shown in Fig. 4.23 below. The green waveform is the VDS voltage of the GaN device of the LLC full bridge. The blue waveform is the GaN gate voltage. The purple waveform is the LLC resonant current. The efficiency achieved in this condition is 97.6%.

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VGS VDS

Ires

Fig. 4.23. Waveforms for Vin(θ=45°) = 200VDC, Vout = 250V, Iout = 5A, Pout = 1.25kW.

The second test is conducted at the 200VDC condition corresponding to the rated voltage of the

200VAC input voltage. The output voltage in this case is 330VDC, which is the minimum output voltage at the 1.65kW rated power. The average load current in this condition is 5A. The waveforms at this condition are shown in Fig. 4.24 below. The efficiency achieved in this condition is 98.2%.

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VGS VDS

Ires

Fig. 4.24. Waveforms for Vin(θ=45°) = 200VDC, Vout = 330V, Iout = 5A, Pout = 1.65kW.

Experimental testing is conducted for light load conditions. For the derated 250VDC output voltage condition, the input voltage phase angle is 10° for the 200VAC input which corresponds to light load, high gain condition. The output power at this condition is 75W. The waveform for this condition is shown in Fig. 4.25 below.

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VGS VDS

Ires

Fig. 4.25. Waveforms for Vin(θ=10°) = 49VDC, Vout = 250V, Pout = 75W.

The second light load test is conducted at 380VDC output. The input voltage remains at 10° for the 200VAC input. At this condition, the output power is 100W. The waveforms for this condition are shown in Fig. 4.26 below.

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VGS VDS

Ires

Fig. 4.26. Waveforms for Vin(θ=10°) = 49VDC, Vout = 380V, Pout = 100W.

4.6.3 AC-DC PFC Testing

Experimental testing is conducted to verify the single-stage LLC design with PFC for the OBC

EV application. The full PFC stage is conducted using a closed current loop design with PI control and an open voltage loop. This design follows the block diagram described in Section 4.5.1.

Testing is conducted at several conditions. The input voltage range is 200VAC to 240VAC. For the testing, the input voltage is operated near the nominal condition of 220VAC from a 60Hz source.

The output voltage is tested at three conditions. The first condition is the derated 250VDC output case. The input current at this condition is 5.435A at a Power Factor (PF) of 99.3%. In this condition, the average load current drawn is 4.604A which corresponds to 1.15kW of output

117 power. The overall efficiency of the LLC converter at this condition is 96.9%. A waveform of the

AC input voltage (blue) and AC input current (purple) is shown in Fig. 4.27 below.

Vin

Iin

Fig. 4.27. Waveforms for Vin = 220Vac, Vout = 250V, Iout = 4.604A, Pout = 1.15kW, PF = 99.3%,

Efficiency = 96.9%.

A second test is conducted close to the minimum full power output voltage of 320VDC. The input voltage for this condition is 225VAC. The input current is 6.811A at a PF of 99.1%. The output power at this condition is 1.474kW with a load current of 4.69A. The overall efficiency of the LLC converter at this condition is 96.9%. A waveform of the input voltage and current are shown in Fig. 4.28 below.

118

Vin

Iin

Fig. 4.28. Waveforms for Vin = 225Vac, Vout = 320V, Iout = 4.69A, Pout = 1.474kW, PF = 99.1%,

Efficiency = 96.9%.

For this condition, a thermal image is taken of the LLC full-bridge inverter GaN devices. The peak temperature of the GaN devices at this operating condition is 74.8°C. A thermal image of the

GaN devices is shown in Fig. 4.29 below.

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Fig. 4.29. Thermal image of GaN devices at Vin = 225Vac, Vout = 320V, Pout = 1.474kW.

A final test is conducted at the rated power condition at an output voltage of 375VDC. The input voltage for this condition is 230VAC. The input current is 6.9A at a PF of 98.6%. The output power at this condition is 1.515kW with a load current of 4.04A. The overall efficiency of the LLC converter at this condition is 96.6%. A waveform of the input voltage and current are shown in

Fig. 4.30 below.

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Vin

Iin

Fig. 4.30. Waveforms for Vin = 230Vac, Vout = 375V, Iout = 4.04A, Pout = 1.515kW, PF =

98.6%, Efficiency = 96.6%.

The single-stage AC-DC converter with PFC using LLC resonant converter is experimentally verified for the EV OBC application. Compared to the academic leading design in [14], the proposed single-stage LLC OBC achieves 96.9% peak efficiency versus 96%, and achieves

2.3kW/L power density versus 2.26kW/L.

4.7 Conclusion

A new 1.65kW single-stage AC-DC LLC resonant converter with PFC for electric vehicle On-

Board Charging (OBC) is proposed using GaN HEMT devices. A single-stage PFC design is

121 proposed to eliminate one switching stage that is used in all other PFC topologies. This topology reduces component count, complexity, size, and increase efficiency. A mathematical analysis is conducted to verify the feasibility of a single-stage LLC converter for PFC operation and to derive resonant converter components and operating parameters. Simulation is performed to verify the performance at nominal and maximum gain conditions in both DC-DC and AC-DC PFC operation.

An experimental high-power density prototype is designed with major circuitry and design decisions described which achieves 2.3kW/L. Experimental testing is conducted on the OBC prototype which achieves 99.1% PF and 96.9% efficiency at 1.474kW for 225VAC input to 320VDC output.

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Conclusion and Future Work

5.1 Conclusion

The power electronics industry today has increasingly focused on researching technologies and methods to improve power density and size for new applications. The contributions of this thesis focus on the electrical and thermal design of high efficiency, high power density power converters.

These topics include studying power converter structure and packaging to improve power density, efficiency, and thermal management. Additionally, this thesis discusses new topologies and control strategies to achieve high power density with simpler design and higher efficiency.

The first contribution involves the analysis of a new integrated power module structure named

Power-System-in-Inductor (PSI2) against traditional plastic packaging. PSI2 is proposed for high efficiency, high power density power module applications. This novel technology integrates the casing of the Point-of-Load (POL) converter with the magnetic core of the power inductor to achieve smaller size, lower inductor winding loss, and improved thermal performance. The inductor encapsulates the remaining components to create a smaller integrated module design. The thermal conductivity of the package improves significantly over traditional plastic packaged modules. Thermal analysis and FEA thermal simulation verify the performance improvement of the PSI2 structure over plastic packaging. Overall, the PSI2 module achieves 2.68% greater efficiency, 0.51W less loss, and 26˚C lower top temperature compared to the traditionally plastic packaged module. Roughly 33% of the improved thermal performance is achieved through the

PSI2 package thermal conductivity.

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The second contribution focuses on a new Integrated Multi-Layer Cooling (IMLC) thermomechanical structure which achieves improved electrical and thermal performance compared to traditional power converter structures. Power electronic designs have primarily focused on improving electrical and thermal design separately to achieve improved designs with higher power density and greater efficiency. In certain applications, such as On-Board Charging

(OBC), significant research has focused on improving power density by reducing size and applying liquid cooling solutions to transfer heat from lossy components. The IMLC structure addresses the desire to improve power density while maintaining thermal performance. The IMLC structure is designed based on three key design principles: multiple PCB layers stacked vertically to utilize three-dimensional space, arranging components based on heat generation and device footprint for targeted cooling, and integrated liquid cooling for maximum conductive heat transfer. Thermal analysis and FEA thermal simulation verify the performance improvement of the IMLC structure.

Compared to a traditional single-PCB air cooled power converter, the liquid cooling performance of the IMLC prototype achieves 46°C peak temperature rise decrease and 0.6% improved efficiency. The IMLC structure additionally improves power density by 31% compared to a single-

PCB liquid cooled design.

The final contribution of this thesis focuses on the LLC resonant converter topology implemented as a single-stage PFC design for electric vehicle (EV) On-Board Charging (OBC).

This topology is proposed to replace the traditional two-stage design with a single LLC stage to decrease topology complexity and switching component count. Additionally, the LLC topology offers high efficiency, high switching frequency operation, and galvanic isolation. Isolation is critical for safe DC battery charging in the OBC system. Simulation and analysis are used to verify the single stage LLC PFC design. Focus is placed on PCB design including input current and

124 voltage sensing, electrolytic capacitor banking, and AC current loop design. A high-power density,

1.65kW experimental prototype is designed using GaN switching devices. In experimentation, the single-stage LLC OBC achieves 99.1% power factor and 96.9% efficiency at 1.47kW operation.

Overall, a single stage LLC converter offers significant potential for OBC applications.

5.2 Future Work

The research conducted in this thesis can be expanded upon in future work for each primary contribution. The desire to constantly improve the efficiency, size, power density, and thermal performance of power converters provides motivation for continued research.

For the PSI2 module, research could be expanded on additional packaging structures that utilize different core shapes to further improve thermal performance. Adding finned structures would allow for increased surface area for convective heat transfer and thereby further improve thermal performance. Additionally, research could be expanded to design a multi-PCB structure that creates a three-dimensional PCB structure to further improve power density.

For the new IMLC structure, significant research could be expanded to improve the performance and feasibility of the structure. Research focused on improving the modularity and ease of assembly and disassembly would allow for scalable design and much simpler prototyping design. Prototyping with the current IMLC design requires significant time for disassembly and increased challenge due to the delicate structure of the assembly. Additional research could also be expanded towards designing a double-sided cooling structure which provides liquid cooling on the top and bottom PCB surfaces. This structure would reduce the required heatsink size while increasing the number of liquid cooled components on the PCB.

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The single-stage LLC resonant converter with PFC for electric vehicle (EV) On-Board

Charging (OBC) applications is a new topology for this application. Therefore, research can be expanded significantly. For the proposed design, synchronous rectifiers could replace the SiC diode of the secondary side bridge rectifier. This will increase efficiency by roughly 0.5% to 0.6% at 5A load. Future work should also be conducted to implement the closed loop operation of the output voltage loop. This requires isolated sensing of the secondary side voltage using optocoupler circuitry. Closed output voltage loop would complete the design and allow for accurate output voltage tracking. Finally, implementing a liquid-cooling solution to the bottom side of the PCB would significantly improve thermal performance and increase efficiency. A liquid cooling solution is also desirable for EV applications where liquid cooled solutions are already standard.

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