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The Sparcenginetw IE CPU Card User's Manual

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The Sparcenginetw IE CPU Card User's Manual The SPARCengineTW IE CPU Card User's Manual Sun Microsystems, Inc. • 2550 Garcia Avenue • Mountain View, CA 94043 • 415-960-1300 Part No: 800-8137-02 Revision A of April 10, 1990 The Sun logo +sun Microsystems, Sun Workstation, NFS, and TOPS are registered trademarks of Sun Microsystems, Inc. Sun, Sun-3, Sun-4, Sun386i, SPARCstation, SPARC, SPARCengine, SunInstall, SunLink, SunOS, SunPro, SunView, NeWS, and NSE are trademarks of Sun Microsystems, Inc. UNIX is a registered trademark of AT&T. OPENLOOK is a trademark of AT&T. All other products or seIVices mentioned in this document are identified by the trademarks or seIVice marks of their respective companies or organizations, and Sun Microsystems, Inc. disclaims any responsibility for specifying which marks are owned by which companies or organizations. Copyright © 1989-90 Sun Microsystems, Inc. - Printed in U.S.A. All rights reserved. No part of this work covered by copyright hereon may be reproduced in any form or by any means - graphic, electronic, or mechanical - including photocopying, recording, taping, or storage in an infonnation retrieval system, without the prior written permission of the copyright owner. Restricted rights legend: use, duplication, or disclosure by the U.S. government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and in similar clauses in the FAR and NASA FAR Supplement. The Sun Graphical User Interface was developed by Sun Microsystems, Inc. for its users and licensees. Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry. Sun holds a non-exclusive license from Xerox to the Xerox Graphical User Interface, which license also covers Sun's licensees. This product is protected by one or more of the following U.S. patents: 4,777,485 4,688,1904,527,2324,745,4074,679,0144,435,792 4,719,569 4,550,368 in addition to foreign patents and applications pending. Contents Chapter 1 Unpacking the CPU Card .......................................................................... 1 Chapter 2 Description of the CPU Card .................................................................. 3 2.1. Main Features .,.................................................................................................................. 3 2.2. Card SllCci fications ......................................................................................................... 4 2.3. Card Landmarks ............................................................................................................... 4 Chapter 3 Bringing Up the SPARCengine IE CPU for the First Time ............................................................................................................................. 9 3.1. Required Refere!lce Materi~ .................................................................................... 9 3.2. Backplane I>efinition ..................................................................................................... 9 3.3. Board Juml>Cl'S ................................................................................................................... 9 3.4. Backplane Slot Configuration Requirements .................................................. 12 3.5. Insertion into a Backplane .......................................................................................... 13 3.6. Power Up .............................................................................................................................. 13 How to Talk to the SPARCengine IE 4MB On-Board Memory ..........................................................................................................; .... ;~.~............. 14 Memory Test Command One ............................................................................ 14 Memory Test Command Two ........................................................................ ;. 14 Memory Test Command Three ....................................................................... l4 3.7. How to Talk to the SPARCengine IE Buses .................................................. ; 15 Step Olle ....................................................................................................................... 15 Step Two ...................................................................................................................... 15 How to Talk to the VMEbus .................................................................................. 15 -iii- Contents - Continued How to Talk to the SBus ........................................................................................... 15 How to Talk to the P-2 Bus ..................................................................................... 15 3.8. Running Extended Selftests ....................................................................................... 16 3.9. Running Functional Tests ........................................................................................... 16 Chapter 4 Board Overview ................................................................................................ 17 4.1. Required Reference Material for the SPARCengine IE ........................... 17 4.2. Introduction ......................................................................................................................... 17 4.3. CPU ......................................................................................................................................... 17 4.4. MMU ...................................................................................................................................... 18 4.5. Cache ...................................................................................................................................... 18 4.6. SBus ........................................................................................................................................ 20 4.7. Direct Virtual Memory Access (DVMA) .......................................................... 21 4.8. Device Space ...................................................................................................................... 21 4.9. Address Spaces ................................................................................................................. 21 4.10. Control Space .................................................................................................................. 21 4.11. Error Registers ................................ ............................................................................... 22 4.12. Memory Maps for the SPARCengine IE ........................................................ 22 Chapter 5 Control Space Registers and Utilities .............................................. 31 5.1. Context Register ............................................................................................................... 31 Programming Example for Sening the Context Register ................. 32 5.2. System Enable Register ............................................................................................... 33 Three Programming Examples for the System Enable Register ........ 33 Turning the Processor Cache ON................................................................... 34 Turning the Cache OFF ....................................................................................... 34 Reseting the CPU with the System Enable Register ........................... 35 5.3. Bus Error Registers ......................................................................................................... 35 Synchronous Errors ..................................................................................................... 35 Programming Example for Using the Synchronous Bus Error Register ............................................................................................................ 36 Programming Example for Using the Synchronous Virtual Register ......................................................................................................................... 37 Asynchronous Errors ................................................................................... ,............ 3g -lY - Contents - Continued Programming Example for Using the Asynchronous B"us Error Register ............................................................................................................ 38 Programming Example for Using the Asynchronous Virtual Regiraer ......................................................................................................................... 39 More on Timeout Errors ........................................................................................... 39 5.4. Direct Accesses to Cache Tags and Data ........................................................... 39 5.5. Serial Port Bypass ........................................................................................................... 39 Chapter 6 Device Space ....................................................................................................... 41 6.1. Req,uired Reference Material .................................................................................... 41 6.2. Main Memory .................................................................................................................... 41 6.3. On-ooard Memory ..........................................................................................................
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