Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters

Spektraler PLL-Selbsttest für integrierte Mobilfunktransmitter

Der technischen Fakultät der Universität Erlangen-Nürnberg

zur Erlangung des akademischen Grades

DOKTOR-INGENIEUR

vorgelegt von

Christian Münker

Erlangen - 2010 ii

Als Dissertation genehmigt von der Technischen Fakultät der Universität Erlangen-Nürnberg

Tag der Einreichung: 30. Oktober 2009 Tag der Promotion: 10. März 2010

Dekan: Prof. Dr.-Ing. Reinhard German Berichterstatter: Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel Prof. Dr.-Ing. Heinrich Klar

Christian Münker March 10, 2010 iii

Die Geburt unseres Sohns Robin, unsere Heirat, zwei Jobwechsel, zwei Umzüge, ein Hauskauf ... ohne die Hilfe meiner geliebten Frau Sylvia Englert und unserer Eltern hätte ich es nie geschafft, meine Arbeit in dieser turbulenten Zeit abzuschließen.

Dafür danke ich Euch von Herzen.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters iv

Acknowledgments

First of all, I’d like to thank my two supervisors Prof. Dr. Dr. Robert Weigel and Prof. Dr. Heinrich Klar for their kind support and motivation over all the years in spite of geographical distance. My interest in PLL topics was triggered by "old PLL rabbit" Edmund Götz. He also played a vital role in our weekly discussions with Markus Scholz, Burkhard Neurauter and Günter Märzinger at Infineon Technologies revolving around Σ∆PLLs and self-calibration strategies. These discussions sparked-off great chips, several patents and, in the end, this thesis. Markus Scholz also designed the excellent multi-modulus divider block that found its way from the Σ∆PLL into the Σ∆FD and shared countless mugs of coffee with me. Manufacturing and evaluation of the test-chips was made possible by the kind support of Infineon Technologies. Frank Demmerle was especially helpful for long discussions on test and self-test issues, motivation and reading the first horrible versions. Guido Retz, Ludger Schneider-Störmann and Stefanie Marek (www.schreibkonzepte.de) gave me valuable ideas for the final structure of this work. Julien Layole’s contributions on PLL modeling using SystemC gave me important insights into modeling issues and spectral estimation.

Parts of this work were funded by the MEDEA+ project A107 "4G-Radio" and the BMBF project 01M3071 "DETAILS".

This work was typeset using the MiKTEX - implementation of LATEX with the TeXnicCenter user interface and the fantastic GhostView / Ghostscript package. Figures were created with XFig / WinFig and references were administrated with the combination of BIBTEX and JabRef. Data was kept secure and up-to-date between many different computers and harddisks by Unison.

A big "THANK YOU" to all of you!!

Christian Münker March 10, 2010 KURZFASSUNG v

Kurzfassung

Bis vor wenigen Jahren war die Komplexität von HF-ICs so gering, dass test- unterstützende Designmaßnahmen (Design-for-Test, DfT) oder gar ein Selbst- test (Built-In Self-Test, BIST) unwirtschaftlich gewesen wären. Da man HF- Parameter zudem nur schwer mit ausreichender Genauigkeit auf dem Chip messen konnte, wurde der Produktionstest auf speziellen automatischen HF- Testsystemen (Automated Test Equipment, ATE) durchgeführt. Der allgemeine Trend der letzten Jahre hin zu drahtlosen Anwendungen schaffte einen Mas- senmarkt für komplexe HF-Systems-On-Chip (SOC) mit rapide sinkenden Pro- duktmargen. Wie zuvor bei digitalen ICs wurde der Produktionstest auch für HF-SOCs zum Flaschenhals; DfT und BIST wurden zur ökonomischen Notwen- digkeit. Sigma-Delta-modulierte Fractional-N Phase-Locked Loops (Σ∆PLLs) gehören zu den Schlüsselkomponenten in heutigen HF-SOCs; sie erzeugen und modu- lieren rauscharme HF-Trägersignale mit kurzer Einschwingzeit. Die enge Ver- zahnung von analogen und digitalen Blöcken in Σ∆PLLs und deren vollständige Kapselung im SOC erschwert jedoch deren Produktionstest und damit den Test des gesamten HF-SOCs. Da erprobte digitale DfT-Methoden ungeeignet sind, um die vielfältigen HF- Spezifikationen abzudecken, wird ein neuer Ansatz für den autonomen, spezifi- kationsgetriebenen Test von Σ∆PLLs in SOCs benötigt. HF-Geräte müssen stren- ge Standards erfüllen, die ganz überwiegend in der Frequenzebene spezifiziert sind, wie z.B. die Sendebandbreite. In dieser Arbeit wurde daher ein spektraler PLL BIST (SP-BIST) entwickelt, um spektrale Eigenschaften von integrierten Σ∆PLLs auf dem Chip ohne externe Messgeräte zu ermitteln und digital auszu- geben. Der SP-BIST beinhaltet einen Stimulusgenerator zur Modulation der PLL und einen Block, der die HF-Antwort der PLL spektral bewertet. Es musste zunächst eine Simulationsmethodik entwickelt werden, um das Zu- sammenspiel der RF- und Digitalblöcke von Σ∆PLL und SP-BIST im Frequenz- und Zeitbereich vorherzusagen. Unter Verwendung eines Standard-VHDL- Simulators konnten damit u.a. die PLL-Schleifenbandbreite und das Phasen- rauschen bei 4 GHz mit einem Noise Floor von -200 dBc/Hz simuliert werden. Der digitale Stimulusgenerator erzeugt Zweitonsignale mit einer Frequenz von 16 . . . 180 kHz und einem Spurious-Free Dynamic Range (SFDR) von 60 dB. Die PLL wird digital über das Fractional-Frequenzwort moduliert. Das Zwei- tonsignal steht sowohl als Sigma-Delta-modulierter Bitstrom zur Verfügung als auch in paralleler Form und ist damit ein vielseitiges Testsignal auch für andere

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters vi KURZFASSUNG analoge und mixed-signal-Blöcke auf dem Chip. Das HF-Signal der PLL wird mit einem digitalen Sigma-Delta-Frequenz-Dis- kriminator (Σ∆FD) gleichzeitig demoduliert und digitalisiert. Der demodulier- te Bitstrom wird in einem Multiraten-Bandpassfilter vierter Ordnung mit einer Bandbreite von 0,8 kHz und einem digitalen Hüllkurvendetektor spektral bewertet. Dabei wird ein SFDR von 45 dB erzielt, der Rauschboden liegt bei L = 80 dBc/Hz. Die Mittenfrequenz des Bandpasses wird mit einem einzigen Para- meter− in Schritten von 300 Hz im Bereich von 10 . . . 200 kHz abgestimmt. Der niedrige Ausschnittsverlust des Filters verursacht einen reproduzierbaren Ampli- tudenfehler von weniger als 0.5 dB für Einzeltöne. Dieser und andere systema- tische Fehler können leicht mit einer Kalibrationsmessung entfernt werden. Die resultierende Standardabweichung des PLL-Frequenzgangs, gemessen mit dem On-Chip Stimulusgenerator, ist 0.05 dB. Die Messdauer beträgt 3 ms pro Frequenzpunkt, Messwerte werden über ein minimales Testinterface als statisches Wort ausgegeben und ermöglichen damit auch einen RF-Test der PLL auf Wafer Level. Mit der Einschränkung des relativ geringen SFDR können auch das In-Band Pha- senrauschen und die Modulationsmaske bewertet werden. Diese On-Chip Extrak- tion der spektralen Parameter stellt eine effiziente Kompression der analogen Da- ten dar und kann direkt mit den Spezifikationen im Frequenzbereich verglichen werden. Durch Messung der PLL-Bandbreite und des Spektrums können funk- tionale und parametrische Ausfälle ermittelt werden. Stimulusgenerator und Bandpassfilter basieren auf verlustlosen Resonatoren, die guten Rauschabstand und Stabilität auch bei kurzen Wortbreiten garantieren. Re- sonanzfrequenz bzw. Bandbreite werden mit einem Parameter mit annähernd li- nearer Abhängigkeit eingestellt. Durch diese einfache Beziehung eignet sich das Verfahren auch für einen Selbstabgleich. Der SP-BIST wurde auf einem hochintegrierten GSM / UMTS-Transceiver-Chip mit zwei 4 GHz Σ∆PLLs in einer 130 nm CMOS-Technologie integriert, ohne die Signalqualität zu beeinträchtigen. Die volldigitale Implementierung ist robust gegen Technologieschwankungen und benötigt eine zusätzliche Fläche von weniger als 0,06 mm2, die durch die Reduktion der Testzeit um 150 ms und die verbesserte Testabdeckung mehr als ausgeglichen wird. Der Transceiver-Chip wurde getestet und zeigt die erwartete SP-BIST Funktionalität.

Christian Münker March 10, 2010 ABSTRACT vii

Abstract

Until a few years ago, RF ICs were low complexity devices that required no Design-for-Test (DfT) or Built-In Self-Test (BIST) features. Additional test blocks would have been uneconomical for these small devices and RF parameters could not be measured with sufficient precision on-chip. Instead, production test was performed on automated test equipment. Since then, a general trend towards wireless applications has turned RF ICs into high volume System-On- Chip (SOC) commodity products with dwindling gross margins. As before with digital ICs, production test has become a bottle-neck for cost sensitive consumer markets, turning DfT and BIST into an economic necessity for RF SOCs as well. Sigma-delta modulated fractional-N Phase-Locked Loops (Σ∆PLLs) are key components of today’s wireless transceivers for the generation and modulation of low-noise RF carrier signals with fast settling times. The tight interaction of analog and digital blocks makes Σ∆PLLs - and as a consequence the whole RF SOC - hard to test, especially as the analog ports of PLLs embedded in SOCs are inaccessible from the outside. As digital DfT methods cannot address the rich analog and RF parameter space, a new approach for the autonomous, specification oriented test of Σ∆PLLs in RF SOCs is needed. RF applications have to fulfill tight spectral requirements, specified by parameters like frequency response or the level of spurious sidebands. In this work, a Spectral PLL BIST (SP-BIST) for on-chip analysis of the spectral properties of Σ∆PLLs is developed that requires no external RF test equipment and does not disturb critical RF paths. The SP-BIST contains a stimulus generator for PLL modulation and a block for spectral response analysis of the PLL RF signal. A simulation methodology had to be developed to predict transient and spectral behavior and the interaction between RF and digital blocks of PLL and SP-BIST. Utilizing a standard VHDL simulator, the PLL bandwidth and phase noise could be simulated down to a noise floor of -200 dBc/Hz at 4 GHz. A digital stimulus generator provides a two-tone sine signal in the range 16 . . . 180 kHz with a spurious-free dynamic range (SFDR) of 60 dB for efficient testing of PLL spectral properties. The PLL is modulated digitally via the fractional frequency word. The two-tone signal is available as an oversampled Sigma- Delta bitstream as well as in parallel form, making it a versatile test signal for other analog and mixed-signal blocks on-chip as well. The PLL RF signal is demodulated and digitized using a first order Sigma-Delta frequency discriminator (Σ∆FD). Spectral estimation of the demodulated bit-

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters viii ABSTRACT stream is performed using a 4th order multi-rate band-pass filter with a resolution bandwidth of 0.8 kHz, achieving an SFDR of 45 dB and a noise floor of L = 80 dBc/Hz. The band-pass center frequency is tuned with a single parameter in− steps of 300 Hz in the range 10 . . . 200 kHz. The low scalloping loss of the filter gives a reproducible amplitude error below 0.5 dB for single tones. This and other systematic errors can be eliminated easily with a calibration run, resulting in a standard deviation of 0.05 dB for the PLL frequency response measured in conjunction with the on-chip multi-tone generator. Using a digital envelope detector, the amplitude of the band-pass output is read out as a static word via the DUT serial data bus. This minimal test interface also enables an RF PLL test on wafer level. Total measurement time is 3 ms per frequency point. Limited by the relatively low SFDR, in-band phase noise and the modulation mask can be measured as well. This on-chip calculation of spectral information is an efficient way for test data compaction and allows direct comparison to specifications in the frequency domain. Functional and many parametric faults can be detected by measuring the PLL bandwidth and spectrum. Both stimulus generator and band-pass filter utilize compact lossless resonators which give good performance in spite of short coefficient and word lengths. Os- cillation and band-pass center frequencies are tuned with a single parameter with nearly linear dependency. This simple relationship enables self-calibration as well. Slow and computation intensive tasks like linearization, smoothing and logarithmic scaling are performed off-chip to save chip area. The SP-BIST has been implemented on an integrated GSM / UMTS transceiver chip with two 4 GHz Σ∆PLLs in a 130 nm CMOS technology. The fully digital implementation is robust against technology deviations, does not degrade the device performance and requires an additional area of less than 0.06 mm2 which is more than compensated by the improved test coverage and a reduction of test time of 150 ms. The transceiver chip has been tested, proving the SP-BIST capabilities and functionalities.

Christian Münker March 10, 2010 Contents

Kurzfassung v

Abstract vii

Table of Contents xii

List of Acronyms and Symbols xiii

1. Introduction 1 1.1. Motivation...... 1 1.2. State-of-the-ArtofDfTandBIST ...... 4 1.2.1. Automated Test Equipment Based Test ...... 6 1.2.2. StructuralTest ...... 6 1.2.3. FunctionalTest ...... 10 1.2.4. Alternate or Translation Test ...... 11 1.2.5. Loop-BackTest...... 11 1.2.6. Built-InSelf-Test ...... 13 1.2.7. PLLBIST...... 16 1.3. Goals ...... 19

2. Fundamentals 21 2.1. Conventions...... 21 2.1.1. Symbols ...... 21 2.1.2. Deﬁnitions ...... 22 2.2. AngleModulation...... 23 2.2.1. Angle Modulation in the Time Domain ...... 23 2.2.2. Sinusoidal Angle Modulation ...... 25 2.2.3. Small-Angle Approximation ...... 27 2.2.4. Bandwidth of Angle Modulation ...... 27 2.3. PhaseNoiseMetrology ...... 28 2.3.1. Double-Sideband Representation ...... 31 2.3.2. Single-Sideband Representation ...... 32 2.3.3. Frequency Modulation and Division ...... 34 2.4. Spectral Estimation of Simulation Data ...... 36

ix x Contents

2.5. Sampling and Quantization ...... 39 2.5.1. Sampling ...... 40 2.5.2. Quantization ...... 40 2.5.3. Oversampling...... 41 2.5.4. Subsampling and Downsampling ...... 42 2.6. Sigma-Delta Modulation ...... 43 2.6.1. Single Bit Quantizer ...... 46 2.6.2. Quantization Noise in Σ∆M ...... 46 2.6.3. Spurious Tones of First Order Σ∆M ...... 49 2.6.4. Higher Order Σ∆M...... 49 2.6.5. Terminology ...... 52 2.7. DigitalResonators ...... 52 2.7.1. BasicProperties ...... 52 2.7.2. Undamped Resonators ...... 55 2.7.3. Resonance Gain and Peak Gain ...... 55 2.7.4. Constant Peak-Gain Digital Resonator ...... 56 2.7.5. Bandwidth and Settling Time of High-Q Resonators . . 58 2.7.6. Resonator Implementations ...... 61 2.8. Fixed-Point Number Format ...... 63 2.9. DigitalFilters ...... 64 2.9.1. Direct Form and Related Filters ...... 64 2.9.2. Passivity and Reference Network Filters ...... 67 2.9.3. Resonator Based Filters ...... 69 2.9.4. Comparison of Filter Structures ...... 72

3. Introduction to the Circuit-Under-Test 73 3.1. BasicPLLTheory...... 75 3.2. Circuit-Under-Test ...... 78 3.3. PLL Speciﬁcations and Test Methods ...... 82

4. Concept and Simulation Methodology for Spectral BIST 87 4.1. RF PLL Test Concept ...... 87 4.2. Measurement Principle ...... 88 4.2.1. PLLBandwidth...... 88 4.2.2. Spectral Analysis with FM Discriminator ...... 89 4.3. From MADBIST to SP-BIST ...... 90 4.4. PartitioningofTestHardware...... 92 4.5. Simulation Methodology ...... 93 4.5.1. Special Requirements for PLLs ...... 94 4.5.2. Discrete Time Modeling of Analog Blocks ...... 95 4.5.3. Limitations of Event-Driven Analog Simulation . . . . . 98

Christian Münker March 10, 2010 Contents xi

4.5.4. Noise/JitterModeling ...... 99 4.5.5. Spectral Estimation of Simulation Results ...... 100 4.5.6. PLL Simulation Results ...... 100

5. Test Tone Generation 103 5.1. Principle of Digital Sine Generator ...... 104 5.1.1. Direct Digital Synthesis ...... 104 5.1.2. Arbitrary Waveform Generation ...... 104 5.1.3. Lossless Digital Resonator ...... 104 5.2. Digital Resonator with Low-Pass Σ∆-Modulation ...... 107 5.2.1. Principle ...... 107 5.2.2. Σ∆-Attenuator ...... 108 5.2.3. Multi-Tone Signal Generation ...... 110 5.2.4. QuantizationNoise ...... 112 5.3. Upconversion in Σ∆PLL ...... 113

6. On-Chip PLL Response Analysis 117 6.1. Spectrum Analysis Overview ...... 117 6.1.1. Direct Spectrum Analysis ...... 117 6.1.2. Indirect Measurement of Angle Modulation ...... 120 6.2. FM Demodulation Using Σ∆ Frequency Discriminator . . . . . 121 6.2.1. Overview of FM Demodulation ...... 121 6.2.2. Principle of First Order Σ∆FD ...... 123 6.2.3. Signal-to-Noise Ratio of Σ∆FD ...... 126 6.2.4. Second Order Σ∆FD ...... 132 6.3. Spectral Analysis of Baseband Signal ...... 133 6.3.1. Overview ...... 133 6.3.2. FilterTopology ...... 134 6.3.3. Downsampling Cascaded-Integrator-Comb Filters . . . . 136 6.3.4. Narrowband Filtering ...... 143 6.3.5. Envelope and Display Detection ...... 151

7. Implementation and Measurement Results 153 7.1. Baseband Test-Tone Generation ...... 153 7.1.1. Oscillation Frequency ...... 153 7.1.2. Amplitude and Amplitude Variation over Frequency . . 154 7.2. Output Response Analysis ...... 156 7.2.1. Sigma-Delta Frequency Discriminator ...... 156 7.2.2. Spectral Analysis of Demodulated Bitstream ...... 159 7.3. Area Estimation and Layout ...... 160 7.4. TestChips...... 162

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters xii Contents

7.5. Measurement Results ...... 164 7.5.1. Disturbances Caused by SP-BIST ...... 164 7.5.2. Spectrum of Test-Tone Generator ...... 165 7.5.3. Measurement Accuracy ...... 165 7.5.4. Measurement of Unmodulated Spectrum ...... 167 7.5.5. Measurement of Modulated Spectrum ...... 169 7.5.6. Measurement of Frequency Response with Calibration . 174 7.6. Programming Examples ...... 174 7.6.1. Programming Registers ...... 176

8. Conclusion and Future Work 179 8.1. ComparisontoGoals ...... 179 8.2. FutureWork...... 182

A. VHDL Behavioral Models 183 A.1. LoopFilter ...... 183 A.2. VoltageControlledOscillator ...... 186 A.3. Random Number Generator ...... 187

Bibliography 189

List of Figures 203

List of Tables 207

Index 209

Christian Münker March 10, 2010 List of Acronyms and Symbols

Acronyms Σ∆M Sigma-Delta Modulation Σ∆PLL Sigma-Delta PLL CP Charge Pump ABIST Analog Built-In Self-Test ACF Auto-Correlation Function ADC Analog-to-Digital Converter ATE Automated Test Equipment ATPG Automatic Test Pattern Generation AWGN Added White Gaussian Noise BE Backward Euler BER Bit-Error Rate BiCMOS Bipolar CMOS BILBO Built-In Logic Block Observer BISC Built-In Self-Calibration BIST Built-In Self-Test BOST Built-Off or Built-Out Self-Test CDF Cumulative Distribution Function CDR Clock-and-Data Recovery CIC Cascaded Integrator-Comb (Filter) CT Continuous-Time CUT Circuit Under Test

xiii xiv LIST OF ACRONYMS AND SYMBOLS

DAC Digital-to-Analog Converter DDS Direct Digital Synthesis DF Direct Form DFT Discrete Fourier Transform DfT Design-for-Test DOT Defect Oriented Test DSB Double Sideband DSM Deep Submicron DT Discrete-Time DUT Device Under Test EVM Error Vector Magnitude FE Forward Euler FFT Fast Fourier Transform FM Frequency Modulation FPGA Field-Programmable Gate Array FSR Full Signal Range GSM Global System for Mobile Communications, originally Groupe Spé- cial Mobile HBIST Hybrid Built-In Self-Test HDL Hardware Description Language IC Integrated Circuit IF Intermediate Frequency LBIST Logic Built-In Self-Test LDI Lossless Digital Integrator LFSR Linear-Feedback Shift-Register LNA Low-Noise Ampliﬁer LO Local Oscillator LTI Linear Time-Invariant

Christian Münker March 10, 2010 List of Acronyms and Symbols xv

MADBIST Mixed Analog-Digital Built-In Self-Test MASH MultistAge noise SHaping MBIST Memory Built-In Self-Test MISR Multiple-Input Signature Register NTF Noise Transfer Function OBIST Oscillation Built-In Self-Test ORA Output Response Analysis OSR Oversampling Ratio OTA Operational Transconductance Ampliﬁer PA Power Ampliﬁer PCB Printed Circuit Board PD Phase Detector PDF Probability Density Function PLL Phase-Locked Loop PM Phase Modulation PRBS Pseudo-Random Binary Sequence PSD Power Spectral Density RBW Resolution Bandwidth RF Radio Frequency RMS Root Mean Square ROM Read-Only Memory RWV Real World Value of binary number representation RX Receiver SC Switched-Capacitor SDM Sigma-Delta Modulation SFDR Spurious-Free Dynamic Range SNR Signal-to-Noise Ratio

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters xvi LIST OF ACRONYMS AND SYMBOLS

SOC System-On-Chip SOS Second-Order Section SP-BIST Spectral PLL BIST SPICE Simulation Program with Integrated Circuit Emphasis SPOT Speciﬁcation Oriented Test SQNR Signal-to-Quantization-Noise Ratio SSB Single Sideband STF Signal Transfer Function TLA Three-Letter Acronym TPG Test Pattern Generation TX Transmitter UMTS Universal Mobile Telecommunications System VCO Voltage Controlled Oscillator VDSM Very Deep Submicron VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language WDF Wave Digital Filter WL Word Length WLAN Wireless Local Area Network

Symbols

β f Frequency modulation index

∆Q Quantization step size ω Angular frequency Ω Normalized angular frequency

ω+ Upper -3 dB frequency of band-pass ω Lower -3 dB frequency of band-pass −

Christian Münker March 10, 2010 List of Acronyms and Symbols xvii

ω0 Nominal or carrier angular frequency

Ωc Center frequency

Ωr Resonance frequency

ωsT Loop gain transit frequency φ Phase deviation from nominal phase

φi(t) Instantaneous phase σ 2 e Variance of quantization error

θp Pole angle A Amplitude

Am Modulation amplitude B Bandwidth

B 3 -3 dB bandwidth − B 60 -60 dB bandwidth − Bm Modulation bandwidth

Bn Noise bandwidth

Brel Relative bandwidth D Frequencies in the discrete time domain en Quantization noise voltage f Frequency F Normalized frequency f0 Nominal or carrier frequency ∆ f Frequency error or deviation ∆ f Peak frequency deviation f Corner or center frequency cc fi(t) Instantaneous frequency fl Lower -3 dB frequency of band-pass fm Modulation frequency or offset frequency from the carrier

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters xviii LIST OF ACRONYMS AND SYMBOLS

fm Modulation frequency fr Resonance frequency fS Sampling frequency fsig Signal frequency fu Upper -3 dB frequency of band-pass FSR Full Signal Range g(t) (Forward) transfer function in the time domain, impulse response G(s) (Forward) transfer function in the frequency domain h(t) Transfer function in the time domain, impulse response H(s) Transfer in the frequency domain

∆Hsc Scalloping loss kBW Coefﬁcient determining the damping in resonator loop k f Coefﬁcient determining the resonance frequency in lossless resonator

∆k f Difference of coefﬁcients determining the resonance frequency in staggered resonator sections kFM Frequency modulation gain kPM Phase modulation gain

L ( fm) Phase noise m(t) Message or modulation signal N Division ratio N Average division ratio

Nq Quantization noise power

Nq′ ( f ) Quantization noise power spectral density Q Quality factor qe Quantization error QF Number of fractional bits (position of binary point) QI Number of integer bits (position of binary point)

Christian Münker March 10, 2010 List of Acronyms and Symbols xix

rp Pole radius RBW Resolution Bandwidth s Complex frequency S Normalized complex frequency; signal power SF Shape factor or selectivity of a band-pass ﬁlter s(t) Signal sFM(t) Angle modulated signal

Sφ ( fm) Phase instability

Sy( fm) Frequency instability t Time T Period T(s) Closed-loop transfer function ∆T Period error or deviation

Tq Quantization time step

Tsym Symbol period, reciprocal of symbol rate WL Word length in bits y(t) Relative frequency deviation y Peak normalized frequency deviation b

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters xx LIST OF ACRONYMS AND SYMBOLS

Christian Münker March 10, 2010 The most exciting phrase to hear in science, the one that heralds new discoveries, is not "Eureka!" (I found it!) but "That’s funny..." Isaac Asimov 1

Introduction

The motivation for improving testability of radio frequency integrated circuits is developed with the main focus on the frequency synthesizer building block. A review of state-of-the-art Design-for-Test techniques for PLLs is given and the goals for this work are deﬁned.

1.1. Motivation

Since its invention in 1958, integrated circuits (ICs) have taken an incredible development. Starting with a few electronic components on a germanium die, the change to silicon enabled the evolution of ICs into full blown Systems-On- Chip (SOC) like one-chip computers, fully integrated Ethernet transceivers or single-chip cellular phones. ICs have become so pervasive in everyday life that Isaac Asimov once called their invention "the most important moment since man emerged as a life form" [Ber05]. The first device breaking the one million transistor barrier was a 1-Mbit dynamic memory in 1986, manufactured in a 1.0-micron complementary metal-oxide- silicon (CMOS) process. In 1989, the Intel 80486 32-bit processor was the first logic device to take this hurdle. It had 1.2 million transistors and operated at 2 1. Introduction up to 50-MHz clock frequency. Only 16 years later in 2005, the first microprocessor featuring more than a billion transistors was Intel’s 64 bit Itanium-2, manufactured in the 90 nm technology node with clock frequencies in the GHz range. Moore’s famous prediction ("Moore’s law") that the number of transistors available for designing an integrated circuit doubles every 18 months has not only been proved correct for the past 40 years, it is also expected to be valid for at least the next 10 years to come [Moo03]. And even when, finally, the limits of physics will prevent a further reduction of feature sizes, new package technologies utilizing the third dimension will enable higher and higher system integration densities [Tum06]. This integration of system functionality onto a chip allowed to decrease the number of components of high technology products. Additionally, shrinking IC feature sizes enabled by advances in manufacturing processes reduced the price of the chips themselves. These two trends created new markets when high technology became affordable for consumers as a central part of entertainment and communication devices like mobile phones, MP3 players or digital cameras. This shift toward high volumes at low prices has significantly increased the percentage of test costs of the total production costs as production test time and costs scale with chip complexity, not with chip area. And despite low prices, the demand for quality became higher and higher as faulty products not only mean increased follow-up costs for the manufacturer, they can also be very damaging to the image of a product and the value of a brand. In the 1980s, this trend forced makers of digital chips to adopt Design-for-Test (DfT) and Built-In Self-Test (BIST) methods. These techniques have proved to be immensely successful to keep test costs down in spite of a few percent area overhead. Two factors had helped this development: (1) Digital signals can be propagated and stored without signal degradation, which eased the design of test logic that does not deteriorate system performance. (2) The boolean nature of digital failures also eases the creation of models and software for fault simulations. About 10 years later, production test became a bottleneck for mixed-signal analog-digital chips, however, the parametric nature of analog failures and the corresponding complexity of fault simulations impeded systematic DfT approaches. Many applications also could not tolerate the system performance degradations brought by DfT enhancements. This is even more problematic for Radio Frequency (RF) ICs which now hit the

Christian Münker March 10, 2010 1.1. Motivation 3 production test wall: Until a few years ago, these devices were low-complexity devices manufactured in special technologies like BiCMOS (Bipolar CMOS) or GaAs requiring no DfT support. The general trend towards wireless devices has fired up fierce competition; the shrinking profit margins and the availability of mainstream CMOS technologies with transit frequencies exceeding 100 GHz made IC designers attempt the seemingly impossible: the integration of RF frontend and digital base-band signal processors on one die. This approach has proved successful for Bluetooth in 2004 [SML+04], WLAN (Wireless Local Area Network) in 2005 [KDZ+05] and GSM (Global System for Mobile Com- munications) in 2006 [BHH+06]. The drawbacks of deep submicron (DSM) CMOS technologies for analog and RF circuits (high parameter spread, low-gain devices) could only be compensated using digital built-in self-calibration (BISC) schemes [MKNM05]. As test costs account for a growing percentage of the total production costs, DfT and BIST have become an economic necessity for RF ICs as well. Increasing signal frequencies aggravate the problem by pushing up the costs per tester channel. This is in contrast to low-performance devices and memories where efficient DfT measures reduce the costs per channel. Chip area overhead, potential degradation of RF performance and yield and increased package cost due to additional pins have made DfT an unpopular option for RF ICs so far [FWM03]. On the other hand, the high integration density of DSM CMOS technologies allows the realization of complex digital signal processing blocks with little area penalty. This also favors the digital implementation of on-chip test circuitry for analog blocks. Besides reducing test time, a second motivation for introducing RF BIST is access to embedded analog blocks. Building blocks with analog interfaces to the outside world like Analog-to-Digital-Converters (ADCs), Digital-to-Analog Converters (DACs) or Low-Noise-Amplifiers (LNAs) can still be tested using the analog capabilities of the Automated Test Equipment (ATE). As a direct consequence of system integration, an increasing number of building blocks is completely embedded in the system. Phase-Locked Loops (PLLs) are a prominent example for a complex mixed-signal building block that is no longer directly observable or controllable from outside. PLLs are core building blocks for RF systems: they are used to generate a clean, stable Local Oscillator (LO) signal with programmable frequency from a fixed reference frequency. Increasingly, Σ∆-modulated PLLs (Σ∆PLLs) are used in RF CMOS transceivers because this highly digital architecture is well adapted to the parameter variations of DSM technologies [MKNM05]. Σ∆PLLs achieve excellent spectral purity and high frequency resolution together with fast settling times. The output

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 4 1. Introduction frequency can be modulated digitally, making Σ∆PLLs well suited for mainly digital RF transmitters or spread spectrum applications. However, the tight interaction between analog and digital sub-blocks makes production test a difﬁcult and time-consuming task even when key analog signals like the tuning voltage or the output of the Voltage Controlled Oscillator (VCO) can be accessed from the tester. In highly integrated SOCs, this is often not the case, restricting test of embedded (Σ∆)PLLs to time-consuming and often inaccurate indirect measurements. For these reasons, DfT support for Σ∆PLLs is a highly desirable feature for speeding up production test and improving testability. The next section gives an overview of the existing approaches to improve testability of integrated circuits, and which of them could be suitable for PLLs.

1.2. State-of-the-Art of DfT and BIST

Production test of complex devices like wired circuits, later of printed circuit boards (PCB) and finally of ICs and systems-in-package has been and is performed using two fundamentally different approaches: specification oriented tests (SPOT) perform a functional test, ensuring that the product performs its specified functions and fulfills the specifications committed to the customer. At the end of the assembly belt of a Ford Model "T", a worker would e.g. trigger the winkers and test the breaks, trying to verify all operating modes. However, full functional test of a complex product takes too long and requires specially skilled workers. Another drawback is that manufacturing defects can cause in-field failures due to untested or unforeseen operation modes. The alternative, structural or defect-oriented test (DOT) targets manufacturing correctness to ensure the product quality. For the example of the Model "T", a worker would check whether all screws are present and tight. Another early, pre-IC example for this kind of test is optical inspection of the solder dots of an printed-circuit board (PCB). This method lends itself to unskilled workers and automated procedures because no knowledge about the product is required. However, it may be difficult to map manufacturing defects to functional failures: functionally good devices may be thrown away because of insignificant defects, reducing yield and gross margin for the manufacturer. The other case is even worse: unmonitored defects may lead to shipping of faulty devices and consequently replacement costs and loss of reputation.

Christian Münker March 10, 2010 1.2. State-of-the-Art of DfT and BIST 5 Spectral PLL BIST (SP-BIST) PLL BIST BIST Jitter Alternate Test BIST Functional Test RF loopback SPeciﬁcation Oriented Test (SPOT) Analog / RF Mixed Analog Digital BIST (MADBIST) Ad-hoc Test Design-for-Test (DfT) Scan Path Next level assembly Digital Figure 1.1.: Overview over DfT techniques Logic BIST (LBIST) Hybrid BIST (HBIST) Structural Test IDDQ Defect Oriented Test (DOT) Chip Level BIST Analog / RF Oscillation BIST (OBIST) Scan Path (ABIST) Analog BIST

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 6 1. Introduction

The deep hierarchies of current integrated circuits prevent the direct control and observation of most components on-chip, giving bad coverage for structural test. Due to the sheer number of operational modes, a pure functional test has also become impractical. Most products are therefore tested using a combination of structural and functional test to minimize the "blind spots". Several techniques are applied during the design phase of an integrated circuit and additional test circuits are integrated to improve its testability. These techniques are subsumed under the label Design-for-Test (DfT): Support for structural IC test (e.g. scan design) • Support for structural test of next level assembly (boundary scan) • Support for functional IC test (built-in self-test, built-out self-test) • Fig. 1.1 gives a graphical overview of the different DfT techniques described in the following.

1.2.1. Automated Test Equipment Based Test

As stated earlier, in production test, typically a combination of structural and functional tests is applied at both wafer level and for packaged devices. After a first basic test to assure proper contacting of the device, scan test vectors are loaded into the chip and the resulting response is analyzed (structural test with DfT). Current consumption for different test vectors and operation modes is mon- itored (IDDQ / alternate test). Especially for analog / RF devices, several critical operating modes are verified (functional test). Although "test coverage" is difficult to define when functional tests are involved, the usual procedure is trying to verify all the critical specifications of the customer data sheet. Further details about economical conditions, tester costs etc. can be found in [Int05] and [FWM03].

1.2.2. Structural Test

In IC manufacturing, basic device structures like wires and vias, transistors and gates are checked for manufacturing correctness with the target of achieving the speciﬁed device behavior. As the terms "defect", "failure" and "fault" are often mixed-up, Box 1.1 contains a short deﬁnition of how these terms are used in this work and in most other publications related to test of integrated circuits:

Christian Münker March 10, 2010 1.2. State-of-the-Art of DfT and BIST 7

A fault is an abstract representation of a defect that can lead to the failure of the device. Every defect should be mapped to a fault, but not every defect or fault results in the failure of the DUT. This is especially true for analog or RF circuits.

Defect: imperfection of a component or structure that violates the technology specifications, e.g. a bridge between a pad and ground or an excessive deviation of a sheet resistance value. Failure: behavior of a DUT that does not conform to customer specifications, be it functional or parametric, e.g. a microprocessor calculating 2 + 2 = 5 or a filter with a corner frequency outside the specification band. Fault: a defect mapped to an abstract, computer-readable representation of the chip which could be a gate level or SPICE netlist of lumped components. Examples for faults are a node stuck at zero level or a resistor with twice the target resistance. Box 1.1: Important Definitions

For defect-oriented testing, a set of input patterns, also called test vectors, is determined that stimulates a high number of the basic devices, the corresponding ideal responses are simulated and recorded. During production test the predetermined stimuli are applied to the DUT and the responses are compared to the predetermined, ideal ones. This only works well when a high percentage of internal nodes is controllable and observable. Finding suitable stimuli is a task well suited for computers as structural test is a brute force approach without knowledge about the function of the circuit. Besides topological information (a netlist or layout), fault models are needed for fault diagnosis techniques. A computer cannot understand the concept of "defects", instead, hypotheses about how the circuit will fail - fault models - have to be formulated. Together with an initial set of test vectors, a fault simulation is started where various faults are inserted into the circuit. The simulator then checks whether the current set of test vectors can detect the difference between faulty and correct circuit behavior and tries to ﬁnd new test vectors if the fault coverage is unsatisfactory.

Digital Structural Test

Due to their complexity, digital ICs were the first to suffer from the loss of ob- servability and controllability of internal nodes. Scan techniques were introduced to improve fault detection during structural test: The basic idea is to implement a scan mode where all the flip-flops in a design are hooked up as a long shift

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 8 1. Introduction

S D D Q out in SE SI Combinational Logic D Q SE SI

D out S D Q en SE S SI in CLK

Figure 1.2.: Scan structure register (Fig. 1.2). An additional test multiplexer at the input of each flip-flop is used to select the scan mode (Fig. 1.3). The first and last flip-flop can be written resp. read via special pins. When switching from normal operation to shift mode, the state information of all flip-flops can be read out sequentially while shifting in a new test vector. When switching back to normal operation, the test vector that has been shifted into the scan chain serially now is applied to the inputs of the combinational logic. The correct behavior of the circuit can now be verified from either the read-out vector or by using current-based techniques like IDDQ test.

Scan insertion together with Automatic Test Pattern Generation (ATPG) is the most common DfT technique for digital ICs in industry: Mature software, well integrated into the design flow, is available for scan insertion and ATPG. As scan techniques are structure based, they work independently of the circuit function and require only little manual intervention of the designer. The additional multiplexer of scan flip-flops and the additional wiring increases the chip area by approx. 5 . . . 20% [PN03]. This overhead is no longer questioned due to lack of alternatives.

Stuck-at fault is the simplest fault model for digital circuits, assuming only simple boolean logic errors caused by nodes stuck at 0 or 1. Stuck-open faults add memory effects to the fault model due to the charge storage of MOS logic. Unfor- tunately, defects in CMOS technologies with feature sizes below 100 nm (very deep submicron, VDSM) are not well modeled by stuck-at or stuck-open faults. An increasing number of failures is caused by bridging defects, i.e. bridges between nodes. The bridging resistance determines the amount of delay variation and quiescent current. Only very low-ohmic bridges cause boolean errors that

Christian Münker March 10, 2010 1.2. State-of-the-Art of DfT and BIST 9

Logic Overhead

Test MUX D D in 0 D−FF out D S in 1 S S en out CLK

Figure 1.3.: Scan flip-flop with test-logic overhead (dashed box) can be detected by static tests. Fault modeling is complex for this class of defects as failures are parametric and so is testing, touching problems of analog test. Additional test methods like at-speed or quiescent current (IDDQ) testing have to be used to find these defects [SCP+99, SH04]. However, the high leakage currents in VDSM technologies reduce the sensitivity of IDDQ tests. At-speed tests are difficult to implement due to lacking automated tool support. For these reasons, functional tests are used increasingly to improve test coverage or for speed binning.

Analog Structural Test

DOT has worked very well for digital circuits for more than 25 years now, and the idea of using a similar approach for analog ICs was and is very appealing. However, the rich parameter space of analog circuit design does not allow a reduction of complexity similar to digital circuits. While simple Boolean logic and register-transfer level abstractions are working fine for digital systems, a state-of- the-art BSIM4 analog transistor model has more than 100 principal parameters (and approx. 300 in total). Hierarchical partitioning of analog circuits is difficult and error prone as the selection of which parameters and constraints have to be passed between abstraction layers is a manual task. Even the concept of "fault coverage" which is a well accepted test quality metric for digital test is difficult to define for analog test. Only simple open/short defects lead to significant performance degradations of the analog DUT that can be detected easily; these faults are classified as catastrophic or hard faults. Analog and especially RF circuits usually try to push the limits of the process technology. Consequently, parametric failures, i.e. a DUT performance slightly outside the specifications, are far more important. Tracking these failures back to individ-

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 10 1. Introduction ual defects is daunting, defining limits for the corresponding parametric or soft faults even more so. DOT approaches are based upon detecting catastrophic and parametric faults due to defects of individual components, however, not every parametric fault or combination of parametric faults causes a parametric failure of the device. A strict application of DOT principles may therefore lead to a loss of yield for analog devices. [Mil98] gives an overview over the challenges involved with defining and finding faults for analog blocks. The effort of simulating catastrophic and parametric faults is high, requiring a large number of analog Monte-Carlo simulations to detect these faults. Hence, analog fault simulation so far is restricted to small circuit blocks like OTAs and low-order filters [GPG01], it has yet to find its way into industry. An automatic RF structural test seems even more unlikely for the near future, given the difficulties of accurate "normal" RF simulations, except for low-complexity devices like LNAs [KDCM04]. A similar procedure for complex mixed-signal building blocks like PLLs or ADCs has not been published yet and does not seem feasible in the near future. A structural PLL test presented in [MCAS05] e.g. only covers some charge-pump related catastrophic defects. In contrast to digital ICs, there is also no solution in sight for monitoring and controlling internal analog nodes without signal deterioration. Analog scan chains were an attempt to adapt the hugely successful digital scan design techniques: [Wey90, SW98] suggest a chain of sample and hold amplifiers as an analog shift register for this purpose. Limited scan chain length due to accumulation of errors, the large area overhead (one opamp and a sampling capacitor per stage) and the restriction to near-static signals have so far limited the practical use of this technique. Analog test buses and multiplexers for controlling and monitoring analog nodes [Wur93] are used to some extent in products, though mainly for quasi-static signals like bias currents. As there is no tool for scan insertion like in the digital domain, a manual selection of the analog nodes of interest is required as well as careful analog design to avoid performance deterioration due to the loading of internal nodes.

1.2.3. Functional Test

On a ﬁrst glance, functional testing seems to be more economical than structural testing because only modes that are important for the customer need to be tested. However, given the multitude of operation modes and input values of SOCs, the duration for an exhaustive functional test would be forbiddingly long. Addition-

Christian Münker March 10, 2010 1.2. State-of-the-Art of DfT and BIST 11 ally, the task of finding a sufficient and not too redundant set of test vectors is very time consuming with little potential for automation. For these reasons, functional test for complex chips is often hierarchical, i.e. the device under test (DUT) is partitioned into several smaller circuits under test (CUT) that are verified individ- ually using functional and / or structural test. Microprocessors are an example where functional test is applied to test the maximum speed of critical blocks, but the overwhelming part of test coverage is achieved by structural test. Analog or RF ICs are a different matter: the lack of a feasible DOT for analog and RF blocks leaves no alternative to specification oriented test (SPOT).

1.2.4. Alternate or Translation Test

Translation test is related to functional test, it translates an on-chip performance parameter like a signal amplitude to a proportional DC-voltage or a frequency [SK93], requiring precise, linear on-chip converters. Alternate test is a more general approach; the translated values do not need to have a direct or linear relationship to the performance parameter. In order to achieve a strong correlation between test response and specification parameter, suitable test stimuli have to be constructed. A single-tone stimulus with a frequency of e.g. 2 f 3dB is much more efficient than a noise signal to characterize the -3 dB frequency− of a lowpass filter. An alternate test for RF frontends has been developed [Gop05] that deploys a wideband current sensor for on-chip signal monitoring. [AC04] deploys subsampling and a noise reference to extract signal features related to harmonic distortions of RF building blocks (hence dubbed "feature extraction"). A strong correlation eases extraction of pass/fail criteria from the test response but still requires substantial on-chip or off-chip computing power, limiting this method to low-complexity, near-linear blocks like an LNA [CLM+07].

1.2.5. Loop-Back Test

Originally, loop back test is a concept for testing ADCs and DACs by reusing analog on-chip resources for BIST purposes. The converters are operated back- to-back in such a way that stimulus generation and response analysis can be performed entirely in the digital domain. Loop-back test is very appealing due to its low hardware overhead and the possibility for a fast system check, how-

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 12 1. Introduction ever, several inherent limitations render a loop-back test impractical for many applications:

Checking two unveriﬁed block against each other may mask errors. Prior • testing of the higher performance block using ATE or additional BIST components [Li04] may be a workaround to this problem but reduces the efﬁ- ciency of the loop-back approach.

"Performance" is a multi-faceted parameter, comprising dynamic range, • sampling speed, differential and integral nonlinearity (DNL / INL), intermodulation distortions etc. One of the converters has to be superior to the other in all aspects which is unlikely for high-performance components.

Inserting analog multiplexers into the signal path to close the loop brings • the risk of performance deterioration.

Loop-back is an integral system test that provides no information about • the cause of the failure which is needed for yield improvement in volume production.

The technique of re-using the on-chip receiver (RX) path to mix down and demodulate the transmitter (TX) signal in RF transceivers is dubbed RF loop back test. Some additional problems make a loop back test at RF even harder to implement:

On- and off-chip crosstalk due to RX and TX running at the same fre- • quency degrades accuracy.

In time-division multiple access (TDMA) systems like GSM or Bluetooth, • RX and TX often cannot operate simultaneously because there is e.g. only one local oscillator shared between RX and TX path or because power consumption would be too high.

RX and TX frequency range in frequency division duplex (FDD) systems • (all major cellular and short-range communication standards) do not overlap. Hence, one of the two blocks has to run outside the standard operation range during test, requiring the design of an extended frequency range. Ad- ditionally, the test results do not reﬂect the real operation case.

Due to these reasons, loop-back test cannot be applied for most RF systems.

Christian Münker March 10, 2010 1.2. State-of-the-Art of DfT and BIST 13

1.2.6. Built-In Self-Test

In order to improve test efﬁciency, built-off self-test1 (BOST) and built-in self- test (BIST) have been developed as DfT techniques for both structural and functional test. The target of BIST / BOST is to minimize ATE requirements by reducing volume and bandwidth of stimulus and circuit response signals. BIST achieves this task by using on-chip test-pattern generation (TPG) and output response analysis (ORA). The ORA usually generates a compact representation of the input data, the so-called signature. Pass / fail information is determined by comparing the signature to the value for the fault-free case. BOST performs the same tasks not within the chip but on the load board. This is achieved e.g. with an RF mixer to reduce the signal frequency or with a ﬁeld- programmable gate array (FPGA) to compress digital data. In many cases, BIST circuitry can be replaced by BOST and vice versa, trading chip area against interface pins and board area. For this reason, BOST is not treated separately in this work. Another application of BIST is not regarded here: Fail-safe systems employ BIST for a continuous on-chip test during operation, switching over to a redundant unit or powering down the system in case of an error. The main drawback of BIST is that it requires more chip area and more effort during the design phase than ATE based test. Circuit partitioning and test pattern generation are mainly performed using ad hoc methods without mathematical un- derpinning and therefore little potential for automation. Design effort and chip area for the additional BIST blocks have to pay-off in terms of reduced test-time and tester resources and / or quality improvement. This is best achieved using digital, synthesizable test blocks which are compact and reusable, minimizing both area and design effort. Like other DfT measures, BIST is usually implemented on a block level to speed-up both test development and the test itself, with highest priority on those blocks that are hard to test otherwise. Observabil- ity and controllability for the individual building blocks is provided via a digital test bus to avoid the routing of sensitive analog signals across the chip.

Logic BIST

In 1979, the ﬁrst logic BIST (LBIST) was presented [KMZ79] using a linear- feedback shift-register (LFSR) to generate pseudo-random binary sequences

1Also called built-out self-test

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 14 1. Introduction

(PRBS) as test-patterns. Output response analysis and compaction was performed with a multiple-input signature register (MISR) (Fig. 1.4), implemented with an LFSR with additional parallel inputs and combined with the scan chain. This structure was named built-in logic block observer (BILBO) [KMZ79]. Test coverage and test times have been further improved since by using more deterministic test generators optimized for individual CUTs [GSHA01, Cha03].

Start Pass / Fail

BIST Logic Signature LFSR MISR Combinational

BIST Clock

Figure 1.4.: Principle of digital BIST

BIST for embedded memory blocks (MBIST) [BCW05] is a very successful vari- ant of LBIST: The regular structure of memories facilitate the development of reusable BIST approaches; the large number of required test vector provide the economic momentum to spend additional chip area for the BIST circuitry. Secu- rity sensitive chips like chip cards are yet another application for LBIST because scan test mode is a potential security vulnerability.

Analog BIST

Fully analog BIST (ABIST) has only limited applications as low-complexity analog chips cannot afford the additional BIST chip area. High complexity devices usually feature digital signal processing which can provide more efﬁcient TPG and ORA. Examples are [RAB97] who investigates analog output compaction for transient signals, and [LMP96] who does the same for test tones. In both cases, a signature is generated by a sampled integrator with threshold detector.

Oscillation BIST

In oscillation BIST, the CUT is reconﬁgured as an oscillator during test mode, requiring no test patterns. Failure to oscillate or a deviation of oscillation frequency indicate a defect. Oscillation test can be an elegant self-test option but

Christian Münker March 10, 2010 1.2. State-of-the-Art of DfT and BIST 15 works only for certain filters and amplifiers [AK97, Won00]. Similar schemes might be feasible for RF blocks like low-noise amplifiers (LNA) but these blocks usually are too sensitive to add parasitic loads and risk unwanted cross-coupling caused by elements not needed for operation.

Hybrid BIST

Hybrid BIST (HBIST) [Ohl91] was the first attempt to perform a built-in self-test of ADC and DAC using simple digital signal processing: An additional LFSR generates transient pseudo-random test patterns for the DAC whose output is sampled by the ADC. A second LFSR compacts the ADC output into a signature. This concept of testing ADC and DAC "back-to-back" is similar to a loop-back test with additional on-chip stimulus generation, response analysis and signature comparison. It also has some additional drawbacks: As small parametric fluctuations of DAC or ADC yield completely different signatures, this approach is problematic for production testing. Similar to LBIST, the pseudo-random test signals do not reflect ADC / DAC specifications, leading to losses in fault or yield coverage and long test times.

Mixed Analog-Digital BIST

The use of multi-tone TPG and ORA is a better choice for analog blocks specified in the frequency domain. It is also easier to define metrics like the maximum amplitude of an intermodulation product for these test signals that are robust against small parametric variations. It is a specification oriented BIST as stimuli can be tailored to the CUT specifications, providing for a more efficient test than pseudo-random signals. With this reasoning, multi-tone Mixed Analog-Digital BIST (MADBIST) concepts for speeding up the time consuming production tests of high-resolution ADCs and DACs were developed in 1993 [TR93b]. Similar to HBIST, both the stimulus and the response analysis are performed in the digital domain; DAC and ADC are also tested back-to-back (Fig. 4.3(a)). However, the authors managed to find a solution to the chicken and egg problem2 of testing two unverified blocks against each other: first, a multi-tone analog stimulus is generated on-chip for a self-test of the ADC. The analog stimulus is extracted with a one-bit auxiliary

2In biology, evolutionary scientists have now proved that the egg came ﬁrst [CNN06].

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 16 1. Introduction

DAC and a low-pass filter from an oversampled digital bit-stream. This leaves the auxiliary DAC and the filter as the only unverified analog circuit block and allows operation in an uncalibrated environment. In the second step, the DAC is characterized using the now verified ADC.

1.2.7. PLL BIST

Due to the complexity of conventional PLL verification, the potential reward of implementing DfT measures is high and many attempts have been made to target functional and performance verification. Some basic self-test features are implemented in most PLLs to detect catastrophic failures [BLBR04, AS07]. Pulse counting with an on-chip frequency counter is such a simple but effective digital BIST method for verifying basic PLL functionality and parameters like center frequency, frequency range and VCO loop gain [KSR00, MSMG02, MS02b, MS03, YL07]. The complex interactions within a PLL make it difficult to establish correlations between complex specification parameters (e.g. RMS jitter, closed-loop bandwidth) and simple PLL quantities (e.g. phase detector pulse width, loop filter voltage) [YL07]. In practice, it is also very difficult to measure e.g. the loop filter voltage with sufficient accuracy without deteriorating PLL performance. Hence, most successful approaches for detecting parametric failures measure the specified parameters directly.

PLL Jitter BIST

In the last years, several BIST approaches have been presented for PLLs used in clock synthesis for microprocessors or in clock-and-data recovery (CDR) for high-speed wire-bound data transmission. These applications are speciﬁed in the time-domain; signal analysis focuses on time-related parameters like timing jitter. The interest in on-chip measurement of PLL timing jitter has increased tremendously with the advent of SOC solutions for high-speed serial transceivers in chip-to-chip [CMJ+03] or Gigabit Ethernet [CKTM02] communication. Com- petitive pressure for communication products and the high costs for fast ATE helped to create the ﬁnancial momentum for developing DfT / BIST solutions. Several methods have been published that determine the cycle-to-cycle jitter from an estimation of the autocorrelation function (ACF) around ∆t = T0. Collecting multiple cycle-to-cycle jitter measurements yields the probability density function (PDF) and the cumulative distribution function (CDF) of the jitter. Subse-

Christian Münker March 10, 2010 1.2. State-of-the-Art of DfT and BIST 17 quently, the RMS cycle-to-cycle jitter can be calculated [Ros92] from the CDF. The main functions of generating and calibrating the delay and determining the auto-correlation have been implemented in different ways:

Figure 1.5.: PLL BIST for measuring cycle-to-cycle jitter [SR99]

The "Fluence PLL BIST" method [SR99, SR02] utilizes a programmable digital delay line and a phase detector for estimating the auto-correlation function (ACF) of the PLL signal (Fig. 1.5). Cycle-to-cycle jitter is measured by counting all events where original and delayed signal differ and slowly sweeping the delay. The digital delay line is calibrated by operating it in a self-oscillating mode and measuring the frequency. This method is applied commercially as it requires only little hardware and no precision components. Variations of this method utilize a coincidence detector [VB03] or a phase detector with programmable dead time [Fet05] instead of the simple phase detector. Vernier delay lines [Kal04] can also be used to measure the instantaneous period or the phase error in a PLL [SOE01, CR04]. However, the long latency of vernier based measurements limits the frequency resolution to relatively low frequencies and requires long measurement times. The solution presented in [HS08] needs more than 3 s to generate an jitter histogram on-chip with a resolution of 1 ps. Measuring k-cycle jitter for many different values of k [Kun05] reveals spectral properties of the jitter at the cost of even longer measurement times. Additionally,

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 18 1. Introduction vernier circuits are large and complex, requiring precision analog components. However, for digital PLLs utilizing vernier based time interval measurements (time-to digital converter, TDC) [MS07], jitter information can be gathered with little overhead [EBSB07]. For testing the bit-error rate (BER), receiver and transmitter are connected in loop-back mode, sent and received bits of a pseudo-random binary sequence (PRBS) are compared for errors. Loop-back test is feasible, because receiver and transmitter of wire-bound systems operate at the same frequency and with similar signal levels. However, veriﬁcation of very low BERs requires excessive measurement times; [SR07] proposed measurement of the PLL RMS jitter instead, using subsampling with a slightly offset frequency.

Frequency Domain PLL BIST

In contrast to time-domain specified PLL Jitter BIST, there are bare to none approaches for a PLL BIST in the frequency domain: PLLs in wireless systems are specified in the frequency domain (frequency response, phase noise, spurious sidebands) and should be tested accordingly. Calculating frequency domain specifications from time-domain measurements is possible but very inefficient with long measurement times due to the required large number of jitter measurements. Several publications try to assess the PLL performance at the output of the phase- frequency detector (PFD) because this is a digital, comparatively low-frequency signal. For high-performance PLLs in wireless systems, this is a dangerous approach: The relative phase error of the VCO signal appears divided by N, making it more difficult to quantify the signal error at this node in practical implementations. The output of the PFD is also a very sensitive node in the PLL; disturbances introduced at this node appear multiplied by N at the VCO output. Due to these reasons, most publications, e.g. [ABM+09] only present simulation results.

Figure 1.6.: Self-calibrated on-chip phase noise measurement circuit [KBK07]

Christian Münker March 10, 2010 1.3. Goals 19

In contrast, [VGKB+07] presents a phase noise BIST based on a tunable delay- line and mixer achieving a measured sensitivity of -75 dBc at 100 kHz offset at the cost of an additional 0.5 mm2 of analog building blocks in a 0.25µm technology. Using the same area in the same technology node, [KBK07] achieves a single-tone sensitivity of -75 db using a self-calibrated delay-line (Fig. 1.6).

1.3. Goals

Today’s RF SOCs require multiple test insertions, i.e. production test on spe- cialized digital, RF and sometimes also mixed-signal automated test equipment. Power and speed of digital testers have to increase with the growing digital complexity of RF SOCs providing ever more features and media support. This means, in the long run, test costs can only be minimized by performing all production tests on a single digital tester, eliminating RF and mixed-signal ATE. However, efﬁcient DfT concepts for RF Systems-On-Chip (SOC) are amiss, as shown in the last section. RF PLLs are among the most troublesome building blocks on RF SOCs as important signals like RF output or tuning voltage are usually unaccessible from outside. The reduced testability slows down production test of the whole device under test (DUT). Consequently, this work starts the improvement of RF SOC testability at the RF PLL. The focus is on Σ∆-modulated RF PLLs (Σ∆PLLs) as they have become the industry standard for RF synthesis and offer convenient digital modulation capabilities. Σ∆PLLs are not only hard to test, the tight interaction between digital blocks (e.g. Σ∆-modulator) and analog blocks (e.g. VCO and loop ﬁlter) is also very hard to simulate, especially when the noise performance is important. Usual mixed- signal, RF or digital simulators do not provide the required simulation performance out-of-the-box, therefore, a new modeling and simulation methodology is needed to complement standard simulators. As the complexity of Σ∆PLLs will not allow structural test in the near future, this work will focus on functional DfT enhancements on block level. In contrast to system level tests, block level tests help to improve yield and the portability of building blocks like the Σ∆PLL. The reuse of e.g. central on-chip DSP resources for computationally intensive test routines would require the routing of high-speed signals across the chip and hinder concurrent testing of function blocks. It also complicates test program development as otherwise unrelated building blocks have to be synchronized. Ideally, the block level tests should be autonomous, require no external mea-

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 20 1. Introduction surement equipment and pass only a few parameters or signatures back to the tester to minimize test program development effort and ATE requirements. A BIST solution is favored over BOST approaches as self-test and self-calibration features of the fully assembled device are getting more and more customer focus. Catastrophic and important parametric faults have to be detected quickly and re- liably. As RF PLLs are specified in the frequency domain, key spectral parameters have to be tested on-chip with the most important PLL parameters being loop bandwidth, in-band noise and modulation mask test. The verification of out-of-band phase noise is not targeted here as a sensitivity better than -129 dBc (TX band) resp. -165 dBc (RX band) requires further work and an optimized RF design. The additional test circuits have to be synthesizable digital blocks with only a minimum of analog circuitry to avoid yield reduction; a digital approach also ben- efits most of the high integration densities of modern technologies and enables an easy reuse path for future chip generations. Only minimal modifications to critical RF and analog paths should be made to avoid performance degradations. PLL BIST has to be implemented during the design phase and may require substantial chip area and design resources. These resources have to be compensated for by reduced test-time or improved testability. Typically, a test time reduction of 200. . . 500 ms for every 0.1 mm2 of additional chip area needs to be achieved with the exact break-even point depending on technology, production volume, tester cost etc. The goal of this work is to develop the next step on the roadmap to RF SOCs that are fully testable on a digital tester, namely, an autonomous RF PLL self-test that is controlled entirely via low-speed digital interfaces. It is organized in the following way: Chap. 2 reviews the underlying theory. Chap. 3 describes the CUT, the Σ∆PLL, and how it is integrated into the DUT, a direct conversion transceiver. Chap. 4 develops test concept and simulation strategy for RF PLLs. Chap. 5 deals with on-chip stimulus generation. Chap. 6 handles the PLL output response analysis. Chap. 7 describes the SP-BIST implementation on a chip together with the CUT and analyzes measurement results.

Christian Münker March 10, 2010 What gets us into trouble is not what we don’t know. It’s what we know for sure that just ain’t so. Mark Twain 2

Fundamentals

Some concepts are reviewed that are used heavily throughout this work, speciﬁ- cally angle modulation, discrete time signal processing, sigma-delta modulation and digital resonators.

2.1. Conventions

2.1.1. Symbols

The following symbols have been adopted throughout this work for denoting continuous-time (CT) / discrete-time (DT) signals and terms: Time is denoted by t, period by T • Frequency is denoted f , angular frequency ω = 2π f and complex fre- • quency s = σ + jω Continuous-time and continuous-value functions have no special prescript • or subscript, e.g. h(t) Capital symbols refer to frequency domain functions, i.e. h(t) vs. H( f ) or • H(z) 22 2. Fundamentals

Symbols referring to DT terms are denoted by the prescript D as in Df = • f TS Normalized frequencies are written in capital letters, i.e. F,Ω,S • In the DT domain, (angular) frequency is normalized w.r.t. the sampling • frequency fS, in the CT domain w.r.t. a center or corner frequency fc

Quantized terms have a subscript Q, e.g. a1 Q • , The DT systems regarded in this work operate at uniform sampling intervals and are shift-invariant1, permitting the use of frequency domain signal-ﬂow diagrams 1 where the unit delay is represented by the symbol z− .

2.1.2. Deﬁnitions

The following deﬁnitions have been taken from [Joi08], terms in round brackets are additions by the author: Accuracy: Closeness of agreement between a measured quantity value and a true quantity value of a measurand Precision: Closeness of agreement between measured quantity values obtained by replicate measurements on the same or similar objects under speciﬁed conditions Uncertainty: Non-negative parameter characterizing the dispersion of the quantity values being attributed to a measurand (usually measured as standard deviation) (Measurement) Error: Measured quantity value minus a reference quantity value Bias: Estimate of a systematic measurement error, i.e. component of measurement error that in replicate measurements remains constant or varies in a predictable manner Resolution: Smallest change in a quantity being measured that causes a percep- tible change in the corresponding indication Reproducibility: Measurement precision under reproducibility conditions of measurement (e.g. repeated measurements on different testers) See also Fig. 4.4 for a visualization of accuracy and precision.

1Similar to LTI systems in the CT domain

Christian Münker March 10, 2010 2.2. Angle Modulation 23

2.2. Angle Modulation

The topic of angle modulation is especially important for this work for two reasons: Signal: The measurement principle described in this work is built upon frequency modulation and demodulation of the device under test. Addition- ally, the DUT utilizes angle modulation for signal transmission. Noise: In a VCO, voltage and current noise in resistive and active elements are converted into phase fluctuations by a combination of additive and non- linear processes [LH00, RA00]. Amplitude deviations are usually suppressed resp. converted to phase or frequency noise by some form of amplitude gain control or limiting in the oscillator. For this reason, the quality of the carrier signal for signal transmission in wireless system is usually specified in terms of phase ("phase noise", "phase instability"), frequency ("frequency instability") or time ("time interval error jitter"), all relating to angle modulation. In the following, phase and frequency modulation are first described in the time domain for general and for sinusoidal signals. Next, a linear approximation for small-angle modulation is derived to allow analysis in the frequency domain and different measures of angle modulation in the frequency domain are given. Fi- nally, the effect of frequency division on angle modulation is explained.

2.2.1. Angle Modulation in the Time Domain

In systems with a ﬁxed frequency and nearly constant amplitude A(t) A like ≈ oscillators or digital blocks, nearly all noise power Pn near the carrier can be contributed to random phase ﬂuctuations φn(t). For this work, it is assumed that amplitude noise contributions Pn,A are suppressed by amplitude control or limiting, i.e. Pn = Pn,A +Pn,φ Pn,φ in the frequency range of interest. The output signal of such a system can be≈ approximated by a purely angle modulated signal s(t) with carrier frequency f0 and a constant amplitude A (2.2.1):

s(t) = A(t)cos(2π f0t + φ(t)) Acos(2π f0t + φ(t)) = Acosφi(t) (2.2.1) ≈ where φ(t) is the phase deviation from the nominal phase 2π f0t. As an angle modulated signal (2.2.1) has a constant envelope, its power is always P = A2/2. The sum of nominal (linear) phase and phase deviation is the instantaneous phase

φi(t) = 2π f0t + φ(t). (2.2.2)

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 24 2. Fundamentals

Its derivative is the instantaneous frequency fi(t) (2.2.3). fi(t) is the sum of nominal frequency f0 and the frequency deviation ∆ f (t). Both φi(t) and fi(t) are hypothetical values that cannot be measured directly. t 1 dφi(t) f (t) = φi(t) = 2π fi(τ)dτ i ∞ 2π dt Z φ − t  1 d (t) ∆ τ τ (2.2.3) = f0 + ⇔ = 2π f0t + 2π f ( )d  2π dt ∞  Z  ∆ − = f0 + f (t) = 2π f0t + φ(t)   Relative frequency deviation y(t) from the nominal frequency f0 is deﬁned by

fi(t) f0 ∆ f (t) 1 dφ(t) y(t) := − = = with [y] = 1. (2.2.4) f0 f0 2π f0 dt

When the message or modulating signal mPM(t) and the phase deviation φPM(t) = kPMmPM(t) have a linear relationship, the modulation is called phase modulation (PM) and kPM phase modulation gain. The resulting instantaneous frequency and phase and frequency deviation are given in (2.2.6). The frequency deviation of PM is proportional to the differential of the modulation signal, hence it is also proportional to the modulation frequency fm (for sinusoidal modulation).

φPM(t) = kPMmPM(t)

1 dφPM(t) kPM dmPM(t) fi,PM(t) = f0 + = f0 +  2π dt 2π dt  (2.2.5)  kPM dmPM(t)  y (t) = PM 2π f dt 0   When modulation signal mFM(t) and the frequency deviation ∆fFM(t) = kFMmFM(t) are linearly related, the modulation is called frequency modulation (FM), yielding the instantaneous frequency and the phase and frequency deviation in (2.2.6). kFM is the frequency modulation gain. Phase deviation of FM is inversely proportional to the modulation frequency for sinusoidal modulation as it is created by the integral of the modulation signal.

fi,FM(t) = f0 + ∆ fFM(t) = f0 + kFMmFM(t) ∆ fFM(t) kFMmFM(t)  yFM(t) = = f0 f0  (2.2.6)  t t  φFM(t) = 2π ∆ fFM(τ)dτ = 2πkFM mFM(τ)dτ ∞ τ= ∞ Z− Z −   A comparison of (2.2.5) and (2.2.6) reveals that FM and PM cannot be distinguished from the modulated signal: A phase modulation with mPM(t) and a frequency modulation with mFM(t) produce the same phase deviation under the

Christian Münker March 10, 2010 2.2. Angle Modulation 25 condition t kFM mPM(t) = 2π mFM(τ)dτ . (2.2.7) kPM τ= ∞ Z − This relationship is utilized in the device-under-test (Sec. 3.2) as indirect PM where the carrier is frequency modulated by the differentiated modulation signal.

2.2.2. Sinusoidal Angle Modulation

In the following, the special case of sinusoidal frequency modulation is described that can be solved in closed form in contrast to most other modulation cases: A carrier, frequency modulated by a sinusoidal modulation signal mFM(t) = Am,FM cosωmt has the phase and frequency deviation shown in (2.2.10) - (2.2.9).

fi,FM(t) = f0 + ∆ fFM(t) with ∆ fFM(t) = kFMAm,FM cosωmt (2.2.8) [ ∆ f (t) ∆ fFM yFM(t) = = cosωmt = ycosωmt (2.2.9) f0 f0 t kFMAm,FM φFM(t) = 2π ∆ fFM(τ)dτ = b sinωmt (2.2.10) τ= ∞ fm Z − :=φ

| {zb } The ratio of peak frequency deviation ∆ f and modulation bandwidth Bm (= fm in this case) for analog modulation signals2 is called frequency modulation in- 3 dex β f (2.2.11) [VDP30]. Another commonc measure is the peak normalized frequency deviation y (2.2.11):

∆ ∆ ∆ f b f f kFMAm,FM y := and β f := = = = φ (2.2.11) f0 Bm fm fm c c c b with β f = 1 and φ = 1 rad, b h i (2.2.11) also shows that the FM modulationb index has the same value as the peak phase deviation measured in rad. As derived in (2.2.7), a PM signal mPM(t) creates the same modulated signal sFM(t) = sPM(t) = s(t) as an FM signal mFM(t)

2The modulation index of digital modulation signals is usually deﬁned as the maximum phase deviation over one symbol period. 3 Phase modulation index βp is deﬁned in a similar way by the ratio of peak phase deviation and modulation signal bandwidth.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 26 2. Fundamentals when

s(t) = Acos(ω0t + φ(t)) = Acos ω0t + φ sinωmt with t kFM mPM(t) = 2π mFM(τ)dτ = Am,PMbsinωmt kPM τ= ∞ Z − Am,FMkFM ∆ f β f φ and Am,PM = = = = . (2.2.12) kPM fm kPM fm kPM kPM c b In general, the spectrum of angle modulated signals cannot be given in closed form. However, sinusoidal and small-angle (see below) phase modulated4 signals can be expanded into an inﬁnite sum of cosine signals, (2.2.13), allowing easy calculation of the spectrum.

s(t) = Acos(ω0t + φ(t)) = Acos ω0t + φ sinωmt ∞ = A ∑ Jn(φ)cos(ω0t + nωmt) b (2.2.13) n= ∞ − b where Jn(φ) are Bessel functions of the ﬁrst kind with integer order n. When the angle modulation consists of multiple tones, results get much more complicated. For the caseb of FM with two sinusoids, Bessel expansion yields (2.2.14) [Sch], containing all kind of intermodulation products between the two modulation frequencies.

mFM(t) = Am1,FM cosωm,1t + Am2,FM cosωm2t

t φFM(t) = 2π kFMmFM(t) ⇒ ∞ Z− kFMAmi,FM = φ1 sinωm1t + φ2 sinωm2t with φi = fmi

sFM(t) = Abcos(ω0t + φbFM(t)) b ⇒ = Acos ω0t + φ1 sinωm1t + φ2 sinωm2t ∞ ∞ = A ∑ Jl(φ1) b∑ Jn(φ2)cosb (ω0t + lωm1t + nωm2t) (2.2.14) l= ∞ n= ∞ − − b b 4FM signals ﬁrst have to be transformed into the PM form using (2.2.7).

Christian Münker March 10, 2010 2.2. Angle Modulation 27

2.2.3. Small-Angle Approximation

Closed-form analysis of most angle modulated signals is either impossible or gives only limited insight as in (2.2.14). However, (2.2.13) can be simpliﬁed for small modulation angles φ < 0.25 rad: The carrier amplitude is attenuated by less than two percent, J0(φ) 1. Only the ﬁrst sidebands have relative amplitudes ≈ exceeding one percent andb can be approximated by J 1(φ) φ/2. Higher ± ≈ ± order sidebands are neglected,b J n >1 0, yielding the small angle approximation | | ≈ (2.2.15): b b φ sFM(t) A cosω0t cos(ω0t ωmt) (2.2.15) ≈ " ± 2 ± # b φ φ jω t jωmt jωmt = Aℜ e 0 1 + e e − (2.2.16) ( 2 − 2 !) b b Its complex phasor form (2.2.16) is visualized in Fig. 2.3. Except for the phase of π of the lower sideband, small-angle approximation takes the same form as amplitude− modulation, i.e. it can also be described as a linear modulation.

2.2.4. Bandwidth of Angle Modulation

(2.2.15) shows that small-angle frequency modulated signals occupy a bandwidth of BFM 2Bm = 2 fm (Fig. 2.1a). Hence, this case is also called narrowband approximation≈ . In contrast, large-angle FM with φ 1 generates many tones around the carrier, ≫ spaced by fm (Fig. 2.1b). Their amplitudes, given by (2.2.13), decrease rapidly for offsets f > ∆ f . The resultingb bandwidth is BFM 2∆ f . ≈ For most practical applications, only the N sidebands required for transmission c 99 c of 99% of the normalized signal power PFM are regarded:

+N99 2 φ ∑ Jn ( ) = 0.99 (2.2.17) n= N − 99 The required number of sidebands directlyb depends on the modulation index, N99 φ + 1, leading to the approximation for FM bandwidth known as Car- son’s≈ bandwidth ⌈ ⌉ rule (2.2.18) that applies for small and large-angle FM [Vid05]. b BFM 2 φ + 1 fm = 2 ∆ f + fm (2.2.18) ≈ ⌈ ⌉ b c

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 28 2. Fundamentals

S (f) S (f) Sy (f) FM B FM FM BFM

(b)

(a) (b) (a) f f f f m f0 +f m f0 +f m

Figure 2.1.: One-sided spectra of frequency deviation Sy,FM( f ) and signal SFM( f ) for small-angle (a) and large-angle (b) sinusoidal FM

2.3. Phase Noise Metrology

In this work, spectra are represented using only positive frequencies (one-sided) as spectra of real-valued signals are symmetric around f = 0 (Fig. 2.2). The power spectral density (PSD) of the one-sided representation has to be twice as large as the two-sided representation to obtain the same total signal power.

This must not be confused with single and double-sideband (SSB / DSB) representation: Spectra of modulated carriers are symmetric around the carrier at f = f0 for real baseband signals and pure amplitude (even symmetry) or phase/frequency modulation (odd symmetry). In contrast, complex baseband signals and combined amplitude / phase modulation schemes produce both odd and even components, yielding asymmetric sidebands. In the following, it is assumed that the signal under analysis is only angle-modulated in the frequency range of interest. In practical VCOs and PLLs, this is achieved by some form of amplitude control or limiting.

The upper sideband contains signal components above the carrier frequency, f0 + fm, signal components below the carrier frequency, f0 fm, constitute the lower − sideband. The frequency variable fm denotes the modulation frequency or offset frequency from the carrier, also called Fourier frequency.

In the frequency domain, signals are usually speciﬁed by power spectral densities (PSD). The PSD S( f ) of a signal resp. process s(t) is obtained by the Fourier

Christian Münker March 10, 2010 2.3. Phase Noise Metrology 29

|S 0 (f)| |S 00 (f)| A 2/2 A2 /4 A2N /8 β2 2 β2 2 0 f A /8 f A /16 2 A N 0 /4

f 0−fm f0 f0 +fm f −f0 −f0 +fm f 0 f 0 +fm f Single sided Double sided

Figure 2.2.: One-sided and two-sided spectra of the signal s(t)

transform of its auto-correlation function (ACF) ρss(τ) [Lük85]

ρss(τ) S( f ) with (2.3.1) ◦−• 1 T ρss(τ) = s(t)s(t + τ) = lim s(t)s(t + τ) dt (2.3.2) T ∞ 2T T → Z− 1 T1 = s(t)s(t + τ) dt for T1 periodic signals and 0 τ T1 . T 0 ≤ ≤ 1 Z ACF and one-sided PSD of a sinusoidal signal s(t) = Am sinωmt are easily derived from (2.3.2): 2 2 Am Am ρss(τ) = cosωmt S( fm) = δ( fm) with 0 fm < ∞ (2.3.3) 2 ◦−• 2 ≤ A similar calculation yields the PSD of the small-angle FM signal (2.2.15): φ sFM(t) A cosω0t cos(ω0t ωmt) ≈ " ± 2 ± # b 2 A2 φ SFM( f ) δ( f0) + δ( f0 fm) (2.3.4) ⇒ | | ≈ 2  2 ! ±  b   A narrowband noise signal can be described by white noise with PSD N0, ﬁltered by a narrow bandpass with center frequency fm, bandwidth B and gain H( fm), ACF and PSD of , [Lük85, p. 193f] are:

ρnn(τ) = 2N0BH( fm)sinc(πBτ)cos(2π fmt) 2N0BH( fm)cos(2π fmt) for πBτ 1 ≈ ≪ Sn( fm) 2N0BH( fm)δ( fm) with 0 fm < ∞ (2.3.5) ◦−• ≈ ≤

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 30 2. Fundamentals

(2.3.3) and (2.3.5) show that a sinusoid with frequency fm and a narrowband noise signal centered at the same frequency have the same ACF and PSD when

A2 P = m = 2N BH( f ) = P . s 2 0 m n On average, the narrowband noise signal can be represented by a sinusoid with the same power. Due to the linearity of small-angle modulation, the spectrum created by general modulation signal with spectrum H( f ) can be calculated using superposition. The FM spectrum of a signal with phase deviation φ(t) can be calculated from its Fourier transform Φ( f ): The spectrum due to each individual frequency component can be approximated by (2.2.15) as long as the (linear) small angle approximation is valid, yielding the complete spectrum by superposition (2.3.7).

t φFM(t) = 2πkFM mFM(τ)dτ τ= ∞ Z − MFM( f ) ΦFM( f ) = for MFM(0) = 0 (2.3.6) ◦−• j f 2 2 SFM( f0 + fm) Φ ( fm) MFM( fm) | | = (2.3.7) ⇒ P ≈ 4 2 f m

S(f) 2 A / 2 2 2 A φ / 8

f0 −f m f0 f0 +f m f

−ω +ω φ / 2 φ m m +ω φ( t ) m φ( t ) A φ / 2 ω ω 0 0 A A ∆A = A φ / 2 (a) (b)

Figure 2.3.: Phasors for small-angle PM/FM, DSB (a) and SSB (b) representation

Phase ﬂuctuations can be measured by two fundamentally different procedures, either by direct spectral analysis of the signal or by prior demodulation, also

Christian Münker March 10, 2010 2.3. Phase Noise Metrology 31 called discrimination. These procedures are related to SSB and DSB representation of the modulation [Pla00, p. 189ff]:

2.3.1. Double-Sideband Representation

Spectra of angle-modulated signals can be obtained from measurements of the phase resp. frequency deviation, requiring demodulation of the signal. Practical measurements use detectors with an output voltage that is proportional to the phase or frequency deviation. The deviation is measured against an external reference or a copy of the signal itself (self-referenced). The amplitude of the carrier is either suppressed (clipping detectors) or needs to be eliminated from the results by calibration [Pla00].

Phase Instability

Phase instability Sφ ( fm) is deﬁned as the one-sided PSD of the phase deviation φ(t) Φ( fm). ◦−• 2 Φ ( fm) Sφ ( f ) = (2.3.8) m 2 2 Sφ ( fm) has the unit rad /Hz. The pseudo-unit dBrad / Hz is deﬁned in this work to express SφdB( fm) in a convenient logarithmic scale:

Sφ ( fm) φ S dB( fm) (dBrad / Hz) := 10log 2 (2.3.9) rad /Hz

Strictly speaking, "per Hz" relates to the argument of the logarithm instead of the logarithm itself - doubling the bandwidth does not give twice the dBrad / Hz value. However, this sloppy use is widely adopted in literature, especially in conjunction with phase noise (see below) and is adopted here as well.

The phase instability Sφ,FM( fm) of a signal sFM(t) frequency modulated by mFM(t) is derived from (2.2.6):

t φFM(t) = 2πkFM mFM(τ)dτ τ= ∞ Z − MFM( fm) Φ( fm) = kFM for M(0) = 0 ⇒ | | fm 2 2 MFM( fm) φ S ,FM( fm) = kFM 2 for M(0) = 0 (2.3.10) ⇒ fm

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 32 2. Fundamentals

The phase instability of sinusoidal FM (2.2.12) is derived in (2.3.11).

kFMAm,FM φFM(t) = sinωmt = φ sinωmt fm 2 β 2 2 Φ ( fm) f b φ Sφ FM( fm) = = δ( fm) = δ( fm) (2.3.11) ⇒ , 2 2 2 b Normalizing the PSD of a small-angle modulated signal (2.3.4) with respect to its power P = A2/2 shows the equivalence to its phase instability (2.3.12):

2 SFM( f0 + fm) φ Sφ,FM( fm) | | = δ( f0) + δ( f0 fm) = δ( f0) + (2.3.12) P 2 ! ± 2 b

Frequency Instability

Frequency instability Sy( fm) is the single-sided PSD of the relative frequency deviation y(t) with the unit rad2/Hz resp. the pseudo-unit dBrad / Hz. The relationship (2.3.13) between phase and frequency instability is derived using (2.2.4) and illustrated in Fig. 2.4 for a typical PLL spectrum: Near the carrier, phase deviation Sφ ( fm) drops with -30 dB/dec, followed by a region of constant in-band noise. Outside the loop bandwidth, phase noise is dominated by the VCO, decreasing with 20 dB/dec. The slope of the Sy( fm) segments in Fig. 2.4 is 2 20 dB/dec larger than the segments of Sφ ( fm) due to the fm term in (2.3.13).

2 fm φ Sy( fm) = 2 S ( fm) (2.3.13) f0

2.3.2. Single-Sideband Representation

A single sideband of an purely angle-modulated signal with carrier frequency f0 can be downconverted to an intermediate frequency with a mixer in one or more stages (Fig. 6.1). Fig. 2.3 shows that this restriction to a single sideband converts half of the phase fluctuations to amplitude fluctuations with ∆A = Aφ/2. This phase-to-amplitude conversion enables measurements in the amplitude domain. The SSB amplitude noise power after conversion is A2φ 2/4. b The ratio of this SSB noise power (due to phase fluctuations only) to the total signal power (carrier and sidebands) in a 1 Hz bandwidthb is called phase noise

Christian Münker March 10, 2010 2.3. Phase Noise Metrology 33

L S(f) (f) Sy (f)

S φ (f)/2 1 Hz

1 Hz 1 Hz

f m f f f

a) f0 f0 +f m f1 b) fm f1 c) fm f1

Figure 2.4.: PSD of signal S( f ) (a), phase noise L ( f ) and phase deviation Sφ ( f ) (b) and frequency deviation Sy( f ) (c)

L ( fm). It is usually speciﬁed in the pseudo-unit dBc / Hz, i.e. dB relative to the carrier. The same caveats apply for the use of this pseudo-unit as explained above for phase instability.

f0+ fm+1Hz S( f )d f Pn,φ ( f0 + fm) f0+ fm L ( fm) = = Z Ptot Ptot S( f0 + fm)/2 1Hz Sφ ( fm) 2 · (2.3.14) ≈ A /2 ≈ 2

Note: Recent standards [IEE08] redeﬁne phase noise via the phase instability as

Lnew( fm) Sφ ( fm)/2 . (2.3.15) ≡ This definition avoids the small angle limitation of the conventional phase noise definition (2.3.14) that is no longer valid near the carrier. Both definitions yield identical values (but not units!) for small phase deviations when the small-angle approximation (2.2.15) is valid, Lnew( fm) L ( fm). ≈ Note: This work does not address the important issue of how the impact of the inevitable amplitude noise in active and passive components upon the oscillator phase fluctuations can be minimized. To some extent, the amplitude noise is independent of the oscillator amplitude (most obvious for additive noise). Hence, one well-known design strategy is to maximize the VCO amplitude in order to minimize the noise-to-carrier ratio. At first glance, there seems to be a contra- diction to (2.3.14) and (2.3.15) which claim that the phase instability does not depend on the carrier amplitude. However, the definition of phase noise contains the single-sideband noise power that is related to the phase instability via the small signal approximation.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 34 2. Fundamentals

The relationship between different measures for phase / frequency stability is demonstrated for the example of the reference spur from Fig. 4.9 with ∆ f = 265Hz, fm = 26 MHz and f0 = 3.434 GHz :

∆ 2 f 8 y y = = 7.72 10− Sy( fm) = = 145.2dBrad/Hz f0 · ⇒ 2 − c ∆ b f yf0 5 βbf = φ = = = 1.02 10− fm fm · c 2 bφ 2 b f0 φ S ( fm) = Sy( fm) 2 = = 102.8dBrad/Hz ⇒ fm 2 − bSφ ( fm) and L ( fm) = = 105.8dBc/Hz (2.3.16) 2 − GSM applies a form of PM where the modulation signal is filtered using Gaus- sian minimum shift keying (GMSK) for high spectral efficiency. The modulation bandwidth Bm is determined by the GSM specifications: The symbol rate is 1/Tsym = 270.833 kbit/s, the ratio of modulation bandwidth and symbol rate is specified as BmTsym = 0.3, resulting in a modulation bandwidth of Bm = 0.3/Tsym = 81.25 kHz. Maximum frequency deviation is derived from the specified modulation index β f = 0.5:

β f = 2∆ f Tsym ∆ f = 1/4Tsym = 67.71kHz ⇔ c c 2.3.3. Frequency Modulation and Division

When the frequency of an FM signal is divided by N, a phenomenon is observed that is well known in PLL and RF design: The carrier frequency is reduced by a factor of N as expected, but the distance of the sidebands from the carrier remains unchanged. This effect is independent from the physical implementation (e.g. a digital divider or an analog mixer) and is best explained in the time domain: The positions of the FM signal edges relative to the unmodulated position (the phase) are modulated in time. Removing e.g. every other edge (division by 2) does not change the "rhythm" of the modulation as long as the removing of the edges does not create aliasing. This condition is fulfilled for narrowband modulation where the spectral components of the sidebands have a much lower frequency than the carrier. The absolute timing fluctuation of the edges is not changed by division. However, as the carrier period is increased by N, the amount of fluctuation relative to the period (phase deviation or relative jitter) is decreased by the same factor.

Christian Münker March 10, 2010 2.3. Phase Noise Metrology 35

These effects can be demonstrated for the case of a carrier with frequency ω0, 5 frequency modulated by a sine wave of frequency ωm , creating a peak frequency deviation ∆ω and a peak phase deviation φ = ∆ω/ωm. ∆ω ω b ω sFM(t) = Acos 0t + ω sin mt m

The signal has an instantaneous phase φi(t): ∆ω φi(t) = ω0t + sinωmt (2.3.17) ωm

After division by N, instantaneous phase φi,N(t) and frequency ωi,N(t) are:

φi(t) ω0t ∆ω φi,N(t) = = + sinωmt (2.3.18) N N Nωm ω (t) dφ (t) ω + ∆ω cosω t ω (t) = i = i,N = 0 m (2.3.19) i,N N dt N

For φ = ∆ω/ωm 1, small-angle approximation (2.2.15) can be used to analyze the effect of division≪ upon the sidebands: b ω t ∆ω s (t) = Acos 0 + sinω t FM,N N Nω m m ω0t ∆ω ω0 A cos cos ωm t (2.3.20) ≈ N ± 2Nωm N ± (2.3.20) shows:

Carrier frequency f0, peak phase and frequency deviation, φ and ∆ f , are • reduced by N b Relative frequency deviation y(t) = ∆ f (t)/ f0 remains unchanged • Sidebands still are a distance of fm from the carrier • ± The level of the sidebands are reduced by N and hence the power of mod- • ulation sidebands and phase noise L ( f ) are reduced by N2 (when the carrier amplitude A remains unchanged) Note: This simple analysis works only for narrowband modulation. In general, the division should be regarded as a subsampling process [Ter05] that folds back wide-band noise into the baseband. 5This could also be a narrowband noise signal.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 36 2. Fundamentals

2.4. Spectral Estimation of Simulation Data

The goal of spectral estimation is to describe the spectral power distribution of a signal, based on a ﬁnite set of data. This section reviews the theory of spectral analysis using periodograms.

Power Spectral Density Estimation

The power spectral density (PSD) of a stochastic process X is deﬁned by the Fourier transform of its auto-correlation function (ACF). A random discrete signal xN with ﬁnite length N can be seen as a realization of X from which its true ACF and PSD can only be estimated. It can be shown that the magnitude squared Fourier transform of xN, a so called periodogram, is an estimation for the true PSD of X [KK06].

Calculating the periodogram of a long sequence xN is very computationally in- i tensive which is avoided by averaging the periodograms of K shorter slices xL of length L < N (Fig. 2.5). An averaged periodogram [PM92] reduces the variance and spectral resolution of the estimate by the factor K at the same time.

0 L-1 L 2L-1 N-1-L N-1 x [k] N

x 0 [k] x 1 [k] K-1 L L x L [k]

Figure 2.5.: Basic slices of the signal xN

The relationship between spectral resolution and variance is improved by Welch’s method [Wel67] of averaging modiﬁed periodograms, calculated from overlap- i ping windowed slices xL (Fig. 2.6)

2 K′ 1 L 1 1 1 π ν Γ (ν) = ∑− ∑− xi [k]w[k]e 2 jk (2.4.1) W L 1 2 L − ∑ − w [k] K′ i 0 k 0 k=0 = =

b window power periodogram of windowed slice i

| {z } | {z } where K′ is the total number of slices. The averaged periodogram is normalized by the power of the window function w[k] for unbiased results [KK06]. This algorithm is used in the Matlab scripts for spectral estimation of the VHDL - simulations.

Christian Münker March 10, 2010 2.4. Spectral Estimation of Simulation Data 37

1 x L * w[k]

x [k] N 0 N-1 0 x L * w[k]

Figure 2.6.: Overlapping windowed slices of the signal xN

Narrowband and Wideband Signals

The power PS of a narrowband signal is concentrated in one spectral line and can be read directly from the display. In contrast, the power PN of a broadband signal like noise is distributed over M frequency bins. The displayed power per bin is therefore given by (2.4.2).

Pbin = PN/M or Pbin [dB] = PN [dB] 10logM (2.4.2) − The relationship between noise power density PN′ (speciﬁed for a bandwidth of 1 Hz) and displayed power per bin depends on the resolution bandwidth RBW of the spectral estimation:

Pbin = PN′ RBW or Pbin [dB] = PN′ [dB] + 10logRBW/1Hz (2.4.3) with RBW = BNB/M where BN is the equivalent noise bandwidth expressed in bins (see next section) and B is the total bandwidth. For an NFFT -point FFT with a rectangular window, BN = 1, B = fS/2 and M = NFFT /2, resulting in RBW = fS/NFFT .

Extracting Noise and Phase Noise from DT Period Data

Spectral estimation of a DT sequence of amplitude values can be performed directly with the periodogram methods described above. When phase noise has to be estimated from a DT sequence of period values, produced e.g. by the simpli- ﬁed DT VCO model described in Sec. 4.5.2, some pre-processing is needed:

The DT period values ck ﬂuctuate around the average period T0. The cumulative sum of the periods, scaled with 2π/T0 gives the DT approximation to the φ ∑N instantaneous phase i[N] = 2π/T0 k ck. φ φ Phase ﬂuctuations [k] = ck′ are estimated from the instantaneous phase i[N] by removing the linear phase 2π f0t (Fig. 2.8). This is achieved in Matlab by spec- ifying the option "detrending" for the PSD which is performed using Welch’s

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 38 2. Fundamentals

Figure 2.7.: Displayed PSD of noise signal [Kes05]

C 2πΣ N Tk / T0

Linear Detrending C 5 C 4 Remove linear phase

C 3 ’ C ’ C ’ C 2 C 4 C ’ C 1 1 5 N k k C ’ C ’ 3 2

Figure 2.8.: Derivation of phase ﬂuctuations from the VCO periods

averaged, modiﬁed periodogram method. By default, Matlab uses a Hamming window with an equivalent noise bandwidth of BN = 1.37 bins [Har78] and scales the PSD with 1/BN to give a correct result for wideband signals. This is reversed in the Matlab routine below for proper display of singles tones. The factor is included in the reported resolution bandwidth to obtain correct noise power densities. Unfortunately, the original Matlab script taken from [Kun05] incorrectly assumes a Hann(ing) window with an equivalent noise bandwidth of BN = 1.5 bins, this value has been used through all simulations in this work. As a consequence, the resolution bandwidth and all simulated values for single tones are too large by 1.5/1.37 = 1.095 or 0.4 dB. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Christian Münker March 10, 2010 2.5. Sampling and Quantization 39

% psd_period .m % % Calculate Power Spectral Density from period data %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%% D e f i n e c o n s t a n t s %%%%%%%%%%%%% nread = 1; % read all samples − % Load Data File generated by VHDL Simulation [periods] = textread(’period_data.txt’,’%f’,nread);

periods = periods / 1.0e15; % scale for fs N_sample = length (periods ); % number of samples

% Calculate average and standard deviation of period data % and phase, find the maximum phase error T_m = mean (periods ); % Calculate average period , J_m = s t d (periods ); % period jitter (StdDev of period), std_dphi = J_m / T_m; % phase error (StdDev of phase) and max_dphi = max( abs (periods T_m ) ) / T_m ; % max. phase error − nfft = floor (N_sample /4); % number of FFT bins winLen = nfft; % Let window length = NFFT overlap = fix (nfft /2); % Let sections overlap by NFFT / 2 winNBW = 1 . 5 ; % equivalent noise bandwidth of Hann window

% Calculate instantaneous phase vector: cum_phi = 2 ∗ pi ∗ cumsum(periods )/T_m;

% Calculate PSD with linear de trending % Data is split into N_sample− / (2 ∗ nfft) sections [Sphi ,f] = psd(cum_phi,nfft ,1/T_m,winLen,overlap ,’lin ear ’);

% Scale PSD with NFFT and winNBW Sphi = winNBW ∗ Sphi / nfft;

N_f = length (f); % number of frequency points = nfft/2 + 1 rbw=winNBW / ( T_m∗ nfft ); % resolution bandwidth in Hz log_rbw = 10∗ log10 (rbw);

% Plot Phase Noise (semilog) figure (1); semilogx (f(2:N_f), 10∗ log10 (Sphi(2:N_f))); xlabel (’Offset Frequency from Carrier (Hz)’); ylabel (’S_{\phi} (dB / Hz)’); title (’VCO Power Spectral Density’);

2.5. Sampling and Quantization

Digital signal processing operates on signals that are discrete-time (sampled) and discrete-valued (quantized):

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 40 2. Fundamentals

2.5.1. Sampling

Sampling creates images of the original signal around multiples of fS that overlap when B > fS/2 (Nyquist frequency), folding back frequency components above fS/2 into the base-band. These components cannot be separated from the original signal. This process is called aliasing and can only be avoided by band-limiting the original signal with an anti-aliasing ﬁlter to B fS/2. ≤ Hence, a sampled signal may be recovered without losses as long as the Nyquist criterion is fulﬁlled:

A signal must be sampled at a rate fS equal to or greater than twice its bandwidth B in order to preserve all the signal information.

2.5.2. Quantization

Quantization reduces the infinite amplitude resolution of the analog signal to a discrete number of levels which inevitably adds distortions that cannot be fully removed. In general, it is very difficult to predict the level of distortion as it depends not only on the quantization step size ∆Q but also on the signal amplitude and statistics. Note: A physical interpretation of the numeric quantizer output is obtained by scaling the output with the quantization step size ∆Q, resulting in a nominal quantizer gain of 1. 6 The quantization error qe(n) is in the range ∆Q/2 for the case of rounding. For ± multi-bit quantizers and sufficiently large signal amplitudes, qe can be approximated by a stochastic process with uniform amplitude probability density 1/∆Q and a constant power spectral density (PSD) Nq′ ( f ) in the interval ( fS/2, fS/2). Outside this interval the noise spectrum repeats due to sampling.− The variance σ 2 e of such a process is given by (2.5.1). σ 2 ∆2 e = Q/12 = Nq(B = fS/2) (2.5.1)

The variance equals the quantization noise power Nq( fS/2) within the Nyquist bandwidth, obtained by integrating the quantization noise PSD Nq′ ( f ) over ( fS/2, fS/2). This allows the calculation of N (2.5.2). − q′ f /2 ∆2 S Q Nq(B = fS/2) = Nq′ ( f )d f = Nq′ ( f ) fS Nq′ ( f ) = (2.5.2) f /2 ⇒ 12 fS Z− S 6 For truncation, ∆Q < qe 0 − ≤

Christian Münker March 10, 2010 2.5. Sampling and Quantization 41

The peak signal-to-quantization-noise ratio (SQNR) is calculated from the power

N’q (f) f −f /2 −B B f /2 S S

Figure 2.9.: Spectral density of quantization noise

S of a signal exercising the full signal range (FSR) of the quantizer and quantization noise power Nq. The SQNR for a sine signal with a peak-to-peak amplitude N App = FSR and a quantizer with 2 quantization levels is given by

∆2 N App Q App = (2 1)∆Q ∆Q = and Nq = (2.5.3) − ⇒ 2N 1 12 2 − A2 2N 1 ∆2 22N∆2 S = pp = − Q Q (2.5.4) ⇒ 8 8 ≈ 8 S 8 SQNR = 10log 10log22N = N 6.02 dB 1.76 dB (2.5.5) ⇒ Nq ≈ 12 · −

In quantizers with only a few bits (N < 5), quantization gain and quantization error are strongly correlated to the signal, creating distortions (harmonics, intermodulation). The resulting degradation of SQNR can be included in (2.5.5) via a reduced maximum input amplitude [vdP94, p. 13]:

N 4 App = 2 2 + ∆Q (2.5.6) − π 2 2 App 3 4 SQNR = 10log dB = 10log 2N 2 + dB (2.5.7) ⇒ 8N 2 − π q

2.5.3. Oversampling

The SQNR of a quantized signal can be improved by reducing the quantization step size ∆Q but this is often more difﬁcult to achieve than oversampling, i.e. sampling a signal with a higher rate than the Nyquist frequency ( fS > 2B). As σ 2 the total quantization noise power Nq = e does not depend on the sampling rate, the quantization noise PSD Nq′ ( f ) is reduced by oversampling (Fig. 2.9). Hence,

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 42 2. Fundamentals the total quantization noise power in the baseband ( B < f < B) depends on the − oversampling ratio OSR = fS/2B. For the optimum case of a brickwall ﬁlter with fc = B (Fig. 2.9), the SQNR is improved by the oversampling ratio OSR = fS/2B (2.5.8).

B ∆2 Q 2B 2B Nq( fS/2) Nq(B) = Nq′ ( f )d f = = Nq( fS/2) = (2.5.8) B 12 fS fS OSR Z−

On a logarithmic scale, this means doubling the OSR improves the SQNR by 10logOSR = 3 db, equivalent to increasing the resolution by half a bit. Another advantage of oversampling is the relaxed requirements for anti-aliasing and reconstruction ﬁlters which remove frequency components above fS/2: In Nyquist rate converters, the signal bandwidth B is just below fS/2, requiring steep analog ﬁlters. This is not needed in an oversampling architecture where B fS/2. Signal and quantization noise between B and fS/2 can be removed later≪ on in the digital domain.

2.5.4. Subsampling and Downsampling

As the Nyquist criterion only requires that the signal bandwidth is lower than the Nyquist frequency fS/2 the signal frequency may be far higher than the sampling frequency. The signal frequency range fsig has to fall into a single Nyquist zone (N 1) fS/2 < fsig < NfS (see Fig. 2.10). If this condition is met, the sampled image− of the signal contains all the information of the original signal. When the original signal lies in an even Nyquist zone, the order of frequency components is reversed which can be reversed easily in digital processing. Using a sampling frequency below the highest signal frequency (i.e. sampling signals above the ﬁrst nyquist zone) is called undersampling or subsampling, independent of whether the Nyquist criterion is fulﬁlled or not. In contrast, the term downsampling is used in this work to denominate the whole process of sampling a signal around fsig with a sampling frequency fS after limiting the signal bandwidth to fS/2 [CT92, pp. 1–25]. Decimation7 by a factor of N operates on a DT signal by keeping 1 out of N samples and discarding the others, yielding an output sampling rate of fS/N. This has the same effect as undersampling a CT signal, consequently, the bandwidth of an DT signal also has to be limited to fS/2N before decimation to avoid aliasing.

7The term has its origins in the Roman method of punishment where a group of men were selected at random and every tenth one was killed.

Christian Münker March 10, 2010 2.6. Sigma-Delta Modulation 43

Figure 2.10.: Subsampling and frequency translation between nyquist zones [Kes05]

Signals with a high ratio between signal frequency and signal bandwidth (as in the case of the response analysis system in Chap. 6) can be processed very efﬁciently by downsampling resp. decimation as the signal processing can be performed at a much lower sampling rate.

2.6. Sigma-Delta Modulation

Originally, Sigma-Delta Modulation (Σ∆M) had been developed to reduce the bandwidth for data transmission by differential predictive coding: When the sampling frequency fS is much higher than the signal bandwidth B, transmission bandwidth can be saved by transmitting only the changes ("delta") between samples of the signal (Fig. 2.11 and Fig. 2.12) [Kes05], requiring only one bit in its simplest form. In this work (with very few exceptions) only one-bit quantization and DACs are used as the inherent monotonicity of a one bit DAC allows implementation in low-cost CMOS technologies. This feature in conjunction with the mainly digital architecture enabled the immense success of Σ∆M in integrated circuits. The signal is demodulated by integrating the delta samples and converting them back to the analog domain. This method, called Delta modulation, is improved by integrating ("sigma") the input signal, yielding Sigma-Delta modulation (SDM,

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 44 2. Fundamentals

d[n] +∆ s(t) δ Q s(t)

−∆ f − Q Quantizer Sampler DAC Integrator LP−Filter Integrator +∆ Q

−∆ DAC Modulator Q Demodulator

Figure 2.11.: Delta modulation and demodulation

(Integrated) Granular Noise Input Signal Slope ∆ Overload Q Distortion

Feedback integrator output

TS (Sigma−) Delta modulated data stream

11 11 1 1 1 1 1 1 1 1 1 0 0 01 01 0 1 0 1 0 0 0

Figure 2.12.: (Sigma)-Delta modulation signal forms

Fig. 2.13). Due to the integration, low-frequency signal components are ampli- ﬁed, improving the correlation between samples. As integration reduces the slew- rate of the signal, slope overload conditions (Fig. 2.12) also become less likely. Additionally, the dynamic speciﬁcations for the quantizer / sampling stage are relaxed as well. When the integrated input signal is regarded instead of the input signal, Fig. 2.12 also shows the Σ∆M principle.

+∆ s(t) δ sd[n] Q s(t)

−∆ f − Q Integrator Quantizer Sampler DAC LP−Filter

+∆ Q

−∆ Modulator IntegratorQ DAC Demodulator

Figure 2.13.: Sigma-Delta modulation and demodulation

Christian Münker March 10, 2010 2.6. Sigma-Delta Modulation 45

The major advantage of Σ∆M over delta modulation is that only a low-pass filter with relaxed specifications instead of an integrator is required for signal reconstruction. Further simplification is obtained by moving both integrators behind the subtractor (Fig. 2.14).

+∆Q s(t) δ sd[n] s(t)

−∆ f − Q Integrator Sampler Quantizer DAC LP−Filter +∆ Q DAC

−∆ Q Modulator Demodulator

Figure 2.14.: Sigma-Delta modulation and demodulation (efﬁcient implementation)

The advantage of exchanging amplitude resolution against oversampling ratio is also frequently applied digital signal processing. In this work, Σ∆M is used in three different forms:

Σ∆PLL: The circuit-under-test (Sec. 3.2) uses an Σ∆PLL to achieve a ﬁne frequency granularity with a high ("coarse") reference frequency.

Σ∆-attenuator: In the digital sine generator (Sec. 5.1), a large N-by-N bit multiplier is replaced by a compact Σ∆M attenuator.

Σ∆-FM discriminator: In the output response analyzer (Sec. 6.2.2), the RF signal is demodulated and quantized with an Sigma-Delta Frequency Discrim- inator (Σ∆FD), yielding an Σ∆M bitstream approximation to the frequency deviation.

s[n] sd[n] z−1 − Quantizer

Accumulator ∆ Q

Figure 2.15.: Digital sigma-delta modulator

In digital Σ∆M, the integrator is replaced by an accumulator, the DAC in the feedback path is implemented by a MUX selecting ∆Q/2 or 0,∆Q. ± As the signal is already DT, the sampler becomes a unit delay that is drawn into

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 46 2. Fundamentals

the accumulator (Fig. 2.15) with a transfer function HA(z) of

1 z− 1 HA(z) = and HA(Ω) = . (2.6.1) 1 z 1 | | √2 2cosΩ − − −

2.6.1. Single Bit Quantizer

For multibit quantizers, the quantizer gain is usually approximated as gQ 1. The output of a single-bit quantizer only depends on the sign of the input value,≈ hence, its "gain" gQ strongly depends on the input signal. Useful approximations for gQ can only be made by regarding the closed loop.

The same is true for the full scale amplitude, which is usually deﬁned as the value where the input signal becomes equal to the DAC output ∆Q as higher input signals overload the converter.

For frequencies well below fS/2, the loop gain is HA( f )gQ 1 and overall gain ≫ is determined by feedback. Correspondingly, the quantization error is ∆Q ∆ 2 ∆ 2 ∆2 − ≤ e[n] < Q with a noise power of en = (2 Q) /12 = Q/3. For the purpose of analysis, the DAC gain factor is absorbed into the quantizer Σ∆-output, yielding a ∆Q instead of a 1 stream. This has the advantage that the low-pass ﬁltered output can directly± be interpreted as an approximation to the original signal.

2.6.2. Quantization Noise in Σ∆M

en [n] s[n] sd[n] z −1 −1 − 1 − z Quantizer Accumulator

Figure 2.16.: Model for quantization noise in Σ∆M bit stream

The model in Fig. 2.16 is used for the analysis of quantization noise in the Σ∆M stream sd[n] where the quantizer action has been replaced by adding the quanti-

Christian Münker March 10, 2010 2.6. Sigma-Delta Modulation 47

zation noise voltage en[n] to the original signal. The digital output stream is 1 z− SD(z) = (S(z) SD(z)) 1 + en(z) − 1 z− − 1 z 1 z 1 − = S(z) − + e (z) 1 + − 1 z 1 n 1 z 1 − − 1− 1 − = S(z) z− +en(z) 1 z− . (2.6.2) − H (z) s Hn(z) |{z} | {z } −1 en [n] (1−z ) s[n] sd[n] z−1

Figure 2.17.: Signal and noise transfer functions in ﬁrst order Σ∆M

The resulting bit stream contains the input signal plus the quantization noise. While the signal is merely delayed by one sample, i.e. the signal transfer function 1 (STF) is Hs(z) = z− , the quantization noise en = ∆Q/√12 fS is shaped with the 1 noise transfer function (NTF) Hn(z) = 1 z (Fig. 2.17). Hn attenuates low − − frequencies of en by taking the difference between two consecutive samples. The frequency response is calculated using sin2 x = 1 (1 cos2x): 2 − jΩ/2 jΩ/2 jΩ jΩ jΩ/2 e e − Hn e = 1 e − = 2je − − − 2j π Ω Ω = 2e j( )/2 sin (2.6.3) − 2 Ω Ω π f H ej = 2sin = 2sin (2.6.4) n 2 f S (2.6.4) shows that the quantization noise at the Σ∆M output is high-pass shaped in the frequency range 0... fS/2, returning to zero at fS. The noise power contained in the bandwidth of interest B is given by (2.6.5): +B +B 2 2 2 π f en Nq(B) = Hn ( f ) Nq′ ( f )d f = 4sin d f B · B fS fS Z− Z− +B 2π f e2 2e2 f 2π f +B = 2 1 cos n d f = n f S sin B − fS fS fS − 2π fS B Z− − e2 2π f 2π f +B 2e2 2πB 2πB = n sin = n sin (2.6.5) π fS − fS B π fS − fS −

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 48 2. Fundamentals

The quantized noise is now concentrated at higher frequencies where it can be ﬁltered out for a small signal bandwidth B fS/2. In this case, it can be approximated using sinx x x3/6: ≪ ≈ − 2 3 2en 2πB 2πB 1 2πB Nq(B fS/2) + ≪ ≈ π f − f 6 f " s s S # π2e2 2B 3 π2e2 π∆ 2 = n = n = Q (2.6.6) 3 f 3OSR3 6OSR3/2 S

A sinusoid with amplitude App = (4/π)∆Q = 1.27∆ that uses the full input range Σ∆ 2 ∆2 2 of the -quantizer without clipping has a signal power of App/8 = 2 Q/π (2.5.6), yielding an SQNR of

2 3/2 √2∆Q 6OSR SQNR = 10log ∆ dB = 6.6 dB + 30logOSR dB (2.6.7) π · π Q ! −

First order Σ∆M improves the SQNR by 30logOSR, compared to only 10logOSR for oversampling without noise shaping (2.5.8). Fig. 2.18 visualizes the differences between Nyquist-rate, oversampled and noise-shaping data converters.

Figure 2.18.: Nyquist rate (a), oversampling (b) and Σ∆M (c) converters [Kes05]

Christian Münker March 10, 2010 2.6. Sigma-Delta Modulation 49

2.6.3. Spurious Tones of First Order Σ∆M

When a constant signal is applied to a ﬁrst order Σ∆M, the internal quantized signal changes between two levels, keeping the mean equal to the input signal. Depending on the level of the input signal x = Qi + b/a∆Q with respect to the two nearest quantization levels Qi and Qi+1, the output pattern can have a short pattern length, concentrating the quantization noise in a few strong spectral lines which are also called "idle tones". The worst kind of input signals are DC signals with a low-valued denominator, i.e. a = 2,3,.... This DC pattern noise is a well- known issue of ﬁrst order SDMs; expressions for the frequency and power of these lines have been derived by [CB81, Gal93] amongst others.

Figure 2.19.: SDM noise for DC inputs [CT92, p. 5]

Fig. 2.19 shows that the peak noise regions are indeed around low-values for a, i.e. around 1/2, 1/3 etc. When a low-frequency ( f fS) signal is present, the SNR is deﬁned by integrating the noise over time while≪ moving along the x-axis in Fig. 2.19. Choosing a bias point around one of the peak noise regions of Fig. 2.19 will therefore lead to a bad SNR.

2.6.4. Higher Order Σ∆M

In first order Σ∆M, the correlation between input signal and quantization error is rather strong, leading to patterns in the output bit stream which show up as spurious lines in the spectrum. Additionally, the noise shaping only has a weak, first order characteristic. One way to improving first-order Σ∆M is to apply the integrated error between

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 50 2. Fundamentals

+∆ z−1 s[n] − − −∆ sd[n]

−1 Quantizer a z a 1 2 First order SDM

Figure 2.20.: Second order multi-loop SDM input signal and quantizer output to its input instead of the original input signal (Fig. 2.20). This topology is called multi-loop Σ∆M. The quantizer output is scaled and fed back into multiple stages of the modulator. The resulting signal and noise transfer functions are given by:

z 1 Hs(z) = 2 = z− for a1 = a2 = 1 (2.6.8) z + (a1 + a2 2)z + 1 a2 − 2 − (z 1) 1 2 Hn(z) = 2 − = 1 z− " (2.6.9) z + (a1 + a2 2)z + 1 a2 − − − 2 π j2π f Ts 2 f Hn ( f ) = 1 e− = 4sin (2.6.10) ⇒ | | − fS

Choosing a1 = a2 = 1 yields an especially simple implementation (Fig. 2.21) that has also been used in the digital sine generator (Sec. 5.1).

s[n] 1 1 +∆ sd[n] z−1 − 1−z −1 − 1−z −1 −∆ Quantizer

Figure 2.21.: Second order multi-loop Σ∆M with a1 = a2 = 1

s[n] 1 1 +1 sd[n] z−1 − 1−z −1 1−z −1 −1 Quantizer

2−z−1

Figure 2.22.: Equivalent second order single-loop Σ∆M for Fig. 2.21

The STF of the second order Σ∆M in Fig. 2.20 is just a delay of one sample (2.6.8) as with a ﬁrst order SDM. The NTF Hn( f ) (2.6.10), however, has a second order

Christian Münker March 10, 2010 2.6. Sigma-Delta Modulation 51 behavior, resulting in a stronger noise shaping. It is calculated exactly as the NTF of the ﬁrst order Σ∆M (2.6.4). The structure in Fig. 2.21 can be rearranged to obtain the second order single-loop Σ∆M in Fig. 2.22 with identical STF and NTF. The quantization model for both version is given in Fig. 2.23

en [n] 1 1 s[n] − 1−z −1 1−z −1 sd[n] Quantizer

2−z−1 z−1

Figure 2.23.: Quantization noise model for Σ∆M in Fig. 2.21 and 2.22

A different architecture for higher-order noise shaping is known under the name of cascaded SDM or MultistAge noise SHaping (MASH). In this topology, single- and second-order loops are cascaded (Fig. 2.24), their single-bit outputs are combined in a noise-cancellation block. The difference between the quantizer output and the output itself of the ﬁrst accumulator is quantization noise which is integrated in the second accumulator. The output of the ﬁrst stage is summed with the differentiated output of the second stage. This way, the quantization noise is high-pass shaped while the signal passes without disturbance.

2 bit

−1 − CO CO z xd(n) x(n)

z−1 z−1

Figure 2.24.: Second order digital Σ∆M with multistage noise shaping

The main advantage of the MASH architecture is that it is unconditionally stable as it is made of ﬁrst order sections without overall feedback. The multi-bit output stream necessitates a multi-bit DAC (Σ∆-ADCs) which may suffer of non- linearities (in contrast to a one-bit converter). In the circuit-under-test, a third- order MASH is used within the Σ∆-PLL to achieve ﬁne frequency granularity

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 52 2. Fundamentals with a high reference frequency. A multi-modulus divider (MMD) converts the multi-bit stream to division ratios, linearity problems (i.e. divider delay depending on the division ratio) can be avoided by proper design techniques [LRP+04]. More in-depth information on various aspects of Σ∆ modulation can be found in [CT92].

2.6.5. Terminology

Historically, the notation Delta-Sigma Modulation was used first in 1962. This terminology describes the causal sequence of operations (difference operation first, followed by integration). In the 1970s, the term Sigma-Delta Modulation was coined to reflect the functional hierarchy: Similar to "Root-Mean-Square" where the actual sequence of operations is "Square-Mean-Root", "Sigma-Delta" describes how a difference is integrated [Kes05]. Nowadays "Sigma-Delta Mod- ulation" is more popular than the original terminology, this terminology is also used throughout this work.

2.7. Digital Resonators

The most important building block of recursive digital filters is the digital resonator, a system with one or two complex poles8. First order resonators with a complex pole require a complex coefficient (i.e. two multipliers) and are most efficient for processing complex input signals. Here, only the magnitude response of real signals is of interest and only second order resonators with real coefficients are regarded. One or two zeros can be included in a separate section.

2.7.1. Basic Properties

A purely recursive second order system with real coefﬁcients a1,a2 is described by the transfer function (2.7.1).

2 g0 g0z H(z) = 1 2 = (2.7.1) 1 + a1z + a2z (z zp 1)(z zp 2) − − − , − , 8Systems with real poles have no resonant behavior (ringing, peaking) and are not regarded here.

Christian Münker March 10, 2010 2.7. Digital Resonators 53

The zeros of the characteristic equation ∆ deﬁne the poles zp,i of the system (2.7.2):

2 1 2 a1 a1 ∆ = 1 + a1z− + a2z− zp,i = a2 (2.7.2) ⇒ − 2 ± s 4 −

2 For the case a2 > a1/4, the system has two conjugate complex poles zp,1 = z∗p,2 = jθp rpe ± that are written in polar form for this analysis, i.e. as pole radius rp (2.7.3) and pole angle θp (2.7.4).

2 2 2 2 2 2 a1 a1 r = r = r = zp i = + a2 = a2 (2.7.3) p p,1 p,2 , 4 − 4

a a2/4 ℑ zp,i 2 1 θp,i = arctan { } = arctan − = θp (2.7.4) ℜ zp i ± q a1/2 ± { , } 2 a1 = ℜ zp i = 2rp cosθp and a2 = r (2.7.5) ⇔ − { , } − p

The system is stable when all poles are inside the unit circle i.e. the pole radius rp is less than one.

a 2 1 complex poles a 1 −2 −1 real poles 1 2 −1

Figure 2.25.: Stability region of a second order system with real coefﬁcients a1,a2

The stability condition (2.7.6) for complex poles is derived directly from (2.7.3) and visualized as the stability triangle in Fig. 2.25.

a2 a < 1 for a > 1 (2.7.6) 2 2 4

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 54 2. Fundamentals

The transfer function in polar form is given in (2.7.7).

g z2 g H z 0 0 (2.7.7) ( ) = = jθ 1 jθ 1 (z zp,1)(z zp,2) 1 rpe p z 1 rpe p z − − − − − − − g0 = 1 2 2 (2.7.8) 1 2rp cosθpz + r z − − p −

ℑ z { }

P1 z L

e jΩ ℜ z Ω { } Z1,2 1

z = 1 | | P2

Figure 2.26.: Poles’ and zeros’ contribution to magnitude frequency response H(Ω)) | |

The frequency response H(Ω) is determined by regarding the system function (2.7.7) along the unit circle9, z = e jΩ. g e 2jΩ g H(Ω) = 0 = 0 (2.7.9) | | (e jΩ z )(e jΩ z ) LP LP p,1 p,2 1 2 − − ·

(2.7.9) can also be interpreted geometrically (Fig. 2.26): The magnitude frequency response H(Ω) is given by the product of the distances between all zeros and the point| L = e| jΩ on the unity circle divided by the product of the distances between all poles and that point L. The length of the individual sections LPi (2.7.10) is calculated from Fig. 2.27 using the cosine formula.

2 LPi = 1 + r 2rp cos(θp i Ω) (2.7.10) p − , − q 9only for a stable system

Christian Münker March 10, 2010 2.7. Digital Resonators 55

ℑ z { }

P1 LP1

θp,1 Ω L rP θ − p,1 1 ℜ z Ω { }

Figure 2.27.: Calculation of distance LP1

Finally, the magnitude response H(Ω) is obtained using θp = θp 1 = θp 2. | | , − , H(Ω) 2 = | | g2 0 (2.7.11) 2 2 1 + r 2rp cos(θp Ω) 1 + r 2rp cos(θp + Ω) p − − p − 2.7.2. Undamped Resonators

2 In the limiting case of a2 = rp = 1, the poles lie on the unit circle, and the system shows undamped oscillation at the resonance frequency Ωr (2.7.12).

1 a2/4 ℑ zp,i 1 a1 Ωr = θp = arctan { } = arctan − = arccos (2.7.12) ± ℜ zp i q a1/2 2 { , }

The resonance frequency is identical to the pole angle Ωr = θp as the normalized frequency Ω = 2ω/ fS has the same values as the corresponding angle in radians, the characteristic equation is given by

1 2 ∆ = 1 2cosΩrz− + z− = 0 . (2.7.13) −

2.7.3. Resonance Gain and Peak Gain

The magnitude transfer function of a resonator with two complex poles has two maxima at the center or peak gain frequency Ωc. As the pole radius rp approaches one, these peaks become more pronounced± and move closer to the resonance frequency Ωr Ωc. ≈

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 56 2. Fundamentals

When the poles are very close to the unit circle (rp 1), there is little mutual ≈ inﬂuence on the resonant behavior in (2.7.9) and the peak gain frequency is Ωc ≈ Ωr = θp (Fig. 2.28). In this case, peak gain at frequency Ωc is nearly identical to the resonance gain at frequency Ωr = θp (Fig. 2.29) which is easier to calculate (2.7.14).

Figure 2.28.: Frequency response of the two-pole resonator (solid line) and contribution of individual poles (dashed lines) [Smi05]

jθp g0 H(e ) = jθ jθ jθ jθ 1 rpe p e p 1 rpe p e p − − − − − g0 = j2θ (2.7.14) (1 rp) 1 rpe p − − − The strong variation of resonance gain with resonance frequency is seen clearly by regarding the special cases of resonance frequencies 0, π/2 and π (2.7.15).

jπ g0 jπ/2 g0 H(0) = H e = 2 > H e = 2 (2.7.15) (1 rp) 1 rp − − The exact value for Ωc can be found by setting the derivative of (2.7.11) to zero (2.7.16): ∂ Ω H( ) Ω Ω |∂Ω | = sin [a1 (1 + a2) + 4a2 cos ] = 0 (2.7.16) Local minima are at Ω = 0 and Ω = π (except for θ = 0), the peak gain frequency Ωc (2.7.17) is found by setting the second part of (2.7.16) to zero. 2 a1 (1 + a2) 1 + rp cosΩc = = cosθp (2.7.17) − 4a2 2rp

2.7.4. Constant Peak-Gain Digital Resonator

The strong variation of peak gain over resonance frequency of the basic resonator can be reduced or avoided altogether by placing zeros at suitable positions, yield-

Christian Münker March 10, 2010 2.7. Digital Resonators 57

Resonator with b = 1, r = 0.99 and θ = 0 ... π 80

)| (dB) 40 Ω |H( 30

0 0 0.2 0.4 0.6 0.8 1 Normalized frequency Ω/π

Figure 2.29.: Frequency response of the two-pole resonator with r = 0.99 for different values of θ ing a biquadratic or biquad transfer function (2.7.18).

1 2 b0 + b1z− + b2z− (z zz,1)(z zz,2) H(z) = 1 2 = g0 − − (2.7.18) 1 + a1z + a2z (z zp 1)(z zp 2) − − − , − , Placing zeros at z = 1 (Ω = 0 and Ω = π) results in a biquad with constant peak-gain over the whole± frequency range that is also very simple to implement θ 2 [Ste94]. The values for the coefﬁcients a1 = 2rp cos p and a2 = rp have been selected as before. −

e jΩ z e jΩ z Ω z,1 z,2 LZ1 LZ2 H( ) = g0 jΩ − jΩ − = g0 · (2.7.19) | | (e zp,1)(e zp,2) LP1 LP2 − − ·

Similar to (2.7.17), the frequency of peak gain can be derived as (2.7.20). Obvi- ously, the zeros at z = 1 prevent setting the peak gain at and near Ω = 0 and ± Ω = π. As the factor for cosθp in (2.7.20) is always less than 1, a value for Ωc exists for every setting of θp. This means, in contrast to (2.7.17), the resonator shows peaking for every value of θp but peak gain frequencies near Ω = 0 and Ω = π cannot be set. Ω θ 2rp cos c = cos p 2 (2.7.20) 1 + rp

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 58 2. Fundamentals

ℑ z { }

P1 z L e jΩ ℜ z Ω { } 1 Z Z 1 − 1 2

z = 1 | | P2

Figure 2.30.: Constant peak gain resonator with zeros at z = 1 ±

The peak gain at Ωc depending on the pole radius is given by [Ste94]. 2 Hc(Ωc) = = f (θ) (2.7.21) 1 r2 6 − p Fig. 2.31 shows the behavior of the constant peak-gain resonator for different θ 1 Ω pole frequencies p. The transfer function has been scaled with Hc− ( c).

2.7.5. Bandwidth and Settling Time of High-Q Resonators

Bandwidth

For a second order band-pass, bandwidth B is usually defined as the half-power bandwidth B 3, i.e. the difference of the upper and lower -3 dB frequencies ω+ and ω where− the magnitude response has dropped by 3 dB compared to the gain − Ac at the center frequency ωc = √ω+ω (Fig. 2.32). − The resolution bandwidth (RBW) of a spectrum analyzer is the -3 dB frequency of the resolution filter, describing the minimum frequency difference of two sine tones with equal amplitude that can be resolved. The shape factor SF or selectivity of a band-pass filter is important for applications where tones need to be separated that are close to each other. It is usually defined by the ratio of the -3 dB and the -60 dB bandwidth B 60 (Fig. 2.32) −

Christian Münker March 10, 2010 2.7. Digital Resonators 59

Resonator with b = z-2 - 1, r = 0.99 and θ = 0 ... π 0

-10

-20 )| (dB) Ω |H( -30

-40

-50 0 0.2 0.4 0.6 0.8 1 Normalized frequency Ω/π

Figure 2.31.: Frequency response of the constant peak-gain resonator with r = 0.99 for different values of θp

0 −3 B 3

A [dB] − 3 dB −20 60 dB −40

−60 B 60 −

ω ω+ − Frequency ωc

Figure 2.32.: Band-pass ﬁlter speciﬁcations

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 60 2. Fundamentals

[Agi06]. Typical values for the selectivity in a spectrum analyzer are 1:5 for a digital and 1:10 . . . 1:15 for an analog ﬁlter implementation.

Normalized bandwidth is deﬁned as ∆Ω = Ω+ Ω , relative bandwidth Brel as the ratio of bandwidth and center frequency. − −

For resonators with rp 1, the normalized center frequency is very close to ≈ the pole angle, Ωc θp and the bandwidth can be estimated graphically from ≈ Fig. 2.33: The -3dB points Ω and Ω+ are √2 farther away from the pole than − the resonance frequency Ωr, yielding

∆Ω fs 1 rp ∆Ω 2(1 rp) B = − . (2.7.22) ≈ − ⇒ π 2 ≈ πTs

ℑ z { } Ω+

1 rP ≈ − Ω 1 1 r c P ≈ P1 − Ω θp 1 rP + − ≈ − r √2(1 rP) P − Ω θ p ℜ− z 1 { }

Figure 2.33.: Estimation of resonator bandwidth

For a second order system, the quality factor Q is approximately the reciprocal of the relative bandwidth Brel (referred to the center frequency fc):

1 f Ω θp Q = c = c (2.7.23) ≈ Brel B ∆Ω ≈ 2(1 rp) −

Settling Time

As the bandwidth of a narrow-band ﬁlter determines its settling time, bandpass speciﬁcations always are a compromise between spectral and temporal resolution.

Christian Münker March 10, 2010 2.7. Digital Resonators 61

For high-Q digital ﬁlters with a dominant pole, the settling time-constant τ can be estimated from the pole radius (2.7.24) [Smi07].

1 T τ = S (2.7.24) ≈ 2πB 2(1 rp) − The other pole has a strong inﬂuence on the frequency response for frequencies near 0 or π, resulting in a large error of the estimations above.

2.7.6. Resonator Implementations

As the poles are mainly responsible for stability and quantization effects, only the differences between recursive structures are regarded here. Various structures have been developed to optimize different aspects of resonator behavior like robustness, signal-to-noise ratio or tunability. An overview over different structures can be found e.g. in [MS86] or [Zöl05], the latter compares different second-order sections with respect to their SNR.

Direct Form Resonator

A rational transfer function in z can be immediately implemented in hardware, yielding the well-known direct form structures. The filter coefficients ai,bi are identical to the polynomial coefficients as shown in Fig. 2.34 for a purely recursive transfer function (2.7.1). Due to this equivalence, the formulas that have been derived for resonance frequency etc. in the last sections, apply directly for the direct form resonators.

x[n] y[n]

−a2 −a1 z −1 z −1

Figure 2.34.: Direct form resonator (second order)

(2.7.5) shows that the pole positions due to a quantized coefﬁcient a2,Q are concentrated near the unit circle. For a2,Q = 1, the pole moves along the unit circle with Ωr = θp = arccos( a1 Q/2). Pole density is high around Ωr = π/2, at low − , frequencies Ωr 1 the reduced pole density leads to large errors due to coefﬁ- cient quantization≪ and degrades the SNR [Zöl05].

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 62 2. Fundamentals

LDI Based Resonator

The structure in Fig. 2.35(a) is known in literature under different names: state- variable biquad [MS86] as it can be derived from analog state-variable ﬁlters or Kingsbury structure after [Kin73]. Here, structures built around a loop of two lossless digital integrators (LDI) are given the more general name LDI based resonator.

xi,BP2 yo,b k2 − z−1 k2 −1 k1 z−1 k3 1 − z 1−z −1 1−z −1 yo,n k1 L2 k3 L1 xi,LP xi,BP1 xi,HP yo

(a) (b)

Figure 2.35.: LDI based resonator (a) and SFG of loops (b)

The LDI based resonator has a good SNR around z = 1 and it can be tuned with either parameter k1 or k2. This is especially simple for the Kingsbury structure where k1 = k2. Setting k3 = 0 places the poles on the unit circle.

Coupled-Form Resonator

The coupled-form resonator, also called Rader-Gould resonator in Fig. 2.36 has the transfer function (2.7.25).

x[n] β −β α α

z −1 z −1 y[n]

Figure 2.36.: Coupled-form resonator

1 H(z) = (2.7.25) 1 2αz 1 + (α2 + β 2)z 2 − − − (2.7.25) shows that one ﬁlter coefﬁcient determines the real part and the other one the imaginary part of the poles. Hence, the density of poles within the unit circle is constant.

Christian Münker March 10, 2010 2.8. Fixed-Point Number Format 63

However, it is obvious that the condition α2 + β 2 = 1 for undamped resonance generally cannot be achieved for quantized coefﬁcients α ,β . It is also unprac- p Q Q tical that both coefﬁcients have to be tuned to modify the resonance frequency.

2.8. Fixed-Point Number Format

When minimum hardware complexity is important, digital signal processing is performed with ﬁxed point arithmetics. In contrast to software and digital signal processor solutions, FPGA and ASIC implementations allow a free choice of number representation (scaling, bias, two’s complement, ...), the number of integer bits QI and fractional bits QF (the position of the binary point) and the total word length WL = QI + QF (Fig. 2.37). In this work, the "Q-notation" is used: QU[QI].[QF] for unsigned and QS[QI].[QF] for signed numbers.

WL QI QF

bWL 1 bWL 2 bWL 3 bQF bQF 1 b2 b1 b0 − − − − MSB LSB

Figure 2.37.: Fixed-point number representation

The same binary word BinWord represents different real-world values (RWV), depending on the number format (Tab. 2.1). For unsigned numbers, this relation is simply: WL 1 WL 1 QF − i − i QF RWV = 2− ∑ bi2 = ∑ bi2 − i=0 i=0

For signed numbers, the MSB bWL 1 represents the sign bit. The corresponding relation is −

WL 2 − i QF ∑ bi2 − for bWL 1 = 0  i=0 − RWV =  WL 2  − i QF QI  ∑ bi2 − 2 for bWL 1 = 1 i=0 − −   

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 64 2. Fundamentals

Encoding QU8.0 QU2.6 QU1.7 QS8.0 QS2.6 QS1.7 2QF 1 64 128 1 64 128 BinWord Real World Value (RWV) 00000000 0 0.000 0.000 0 0.000 0.000 00000001 1 0.016 0.008 1 0.016 0.008 00011000 24 0.375 0.188 24 0.375 0.188 01111111 127 1.984 0.992 127 1.984 0.992 10000000 128 2.000 1.000 -128 -2.000 -1.000 10000001 129 2.016 1.008 -127 -1.984 -0.992 11111111 255 3.984 1.992 -1 -0.016 -0.008

Table 2.1.: Examples for binary encoding with corresponding real world values (rounded to 3 decimal digits)

QF The resolution ε of a fixed-point number is given by ε = 2− . The effect of exceeding the numeric range during an arithmetic operation depends on the hardware implementation: Saturation logic clamps the result to the maximum resp. minimum value when an overflow resp. underflow condition occurs, modulo or wrap-around logic simply drops the overflow bit which has the effect of subtracting 2WL from the result. The latter results in a more unpredictable behavior and possibly oscillations (limit cycles) but needs no additional hardware. For this reason, modulo arithmetics is chosen in this work, overflow conditions are avoided by proper scaling.

2.9. Digital Filters

Many different topologies for DT ﬁlters have been developed with speciﬁc advantages and disadvantages. The overview in Fig. 2.38 only shows the types that are described in this section.

2.9.1. Direct Form and Related Filters

A rational DT transfer function H(z) (2.9.1) (e.g. obtained via bilinear transform from a rational CT transfer function H(s)) can be written in different forms, pro-

Christian Münker March 10, 2010 2.9. Digital Filters 65

digital ﬁlters

recursive non-recursive

direct form reference network resonator based

DF I DF II WDF LDI

Figure 2.38.: Types of digital ﬁlters

viding different "construction plans" for implementation. For real ﬁlter coefﬁ- cients am,bn, poles and zeros are either real or complex-conjugate pairs.

:=H1(z) M m ∑ bmz− Y(z) z }| { H(z) = = m=0 = H (z)H (z); M N (2.9.1) X z N 1 2 ( ) n ≤ 1 + ∑ anz− n=1

:=H2(z) | {z } When the difference equation (2.9.2) is derived directly from H(z) in polynomial form, the corresponding recursive DT ﬁlters (Fig. 2.39) are called direct form (DF) ﬁlters. A common implementation is the so called direct form type II (DF II) shown in Fig. 2.39 with a minimum number of registers (canonical form).

N M n m Y(z) 1 + ∑ anz− = X(z) ∑ bmz− n=1 ! m=0 N M y[k] = ∑ any[k n] + ∑ bmx[k m] (2.9.2) ⇔ − n=1 − m=0 −

It is well-known that DF ﬁlters are very sensitive to coefﬁcient truncation and quantization [Smi05, Mey07], making them impractical for applications with short word length.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 66 2. Fundamentals

−a1 −aN−2 −aN−1 −aN x[k] g[k+N] z −1 z −1 z −1 g[k+N−1] g[k+1] g[k]

b 0 b1 bM−2 bM−1 bM

y[k]

Figure 2.39.: Type II direct form ﬁlter

Cascaded (SOS) ﬁlters

Rearranging the transfer function (2.9.1) into products of ﬁrst and second order (2.9.3) is the starting point for cascaded ﬁlters:

M M m ∑ bmz ∏ z z0 m − − , H(z) = m=0 = m=1 ; M N (2.9.3) N N n ≤ 1 + ∑ anz− ∏ z z∞,n n=1 n=1 −

Individual product terms are implemented as second order sections (SOS), each realizing one or two (complex-conjugate) poles and zeros. The robustness of such a cascade of ﬁrst and second order ﬁlter sections is much higher than a direct implementation.

Parallel form

The transfer function (2.9.1) can also be written as a sum of ﬁrst and/or second order terms (2.9.4), obtained by partial fractional expansion [Smi05]

M ∑ a z m m − NP M r H(z) = m=0 = F(z) + ∑ ∑ i ; M N (2.9.4) N 1 n k=1 m=1 1 piz− ≤ 1 + ∑ bnz− − n=1 where pi are the poles of the transfer function and ri are the residues.

Christian Münker March 10, 2010 2.9. Digital Filters 67

This structure can be implemented as a parallel filter, where the outputs of individual first and second order sections are summed up. Parallel filter structures are preferred when the different sections have disjoint passbands [Smi05] (e.g. for multiple passbands). Parallel filters are also much more robust than a direct implementation; for the same word length, parallel filters have a more ideal passband and worse stopband characteristic than cascaded filters. A serious disadvantage of DF and derived filters is that there is no simple correlation between filter coefficients and frequency response: Tuning e.g. the center frequency of a band-pass requires re-calculation of all coefficients.

2.9.2. Passivity and Reference Network Filters

At the beginning of the 1970’s, analog (LC) ﬁlter topologies like doubly terminated LC ladder networks (Fig. 2.40) [TR86] and design methodologies had been developed for the construction of robust higher order ﬁlters with low sensitivity to component variations.

R0 C2 L2

vin vo

L1 C1 R0

Figure 2.40.: Doubly terminated fourth order ladder LC band-pass ﬁlter

Alfred Fettweis was probably the first to understand that the robustness of those passive filters can be linked to "zero loss". In an interview he pointed out that this is one of the rare cases where engineers get a "free lunch": "Anyhow, I realized that this sensitivity problem was related to basic loss. Zero loss in a passive circuit is something you can never go below, because it would mean you have an active device. [...] So if you have passive devices, at any frequency where the loss reaches zero, that’s rock bottom. [...] If you change a component, if you lower it or make it larger, you cannot get below that value, and therefore the derivative is zero, so you have zero sensitivity. [...] Suppose you have a filter of degree ten, you may have in that filter, let’s say, twenty components. With a filter of degree ten, you can have zero loss at five different frequencies in the pass-band. Now, the sensitivity at any of these five frequencies is zero, and this with respect

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 68 2. Fundamentals

to any of the parameters. You have twenty parameters times five, that is a hundred conditions you impose on the sensitivities to be zero. Now you have only twenty parameters in your circuit; how can you satisfy a hundred conditions? In addition, you don’t want to waste your freedom completely for getting good sensitivity coefficient; you want to use it to get a good filter curve. Now, the amazing thing is you get the good sensitivity free of charge. Just design the filter to be a good filter, and these one hundred conditions are automatically fulfilled. That is a fantastic property of passive circuits." [Fet97]. Once this property of passivity was understood, a lot of research was conducted to derive DT filter structures from these analog reference or prototype networks.

vo 1 vL,1 iin i0 i1 vC,1 vo v C C,1 R 1 R − 1/sL1 vL,1 − 1 1/sC1 L1 iin i0 1 i1 − (a) (b)

y o yo TS/2L1 − R z −1 z −1 R 1 −1 sC1 sL1

x0 x0 z −1 z −1

x1 delay−free loop xin xin TS/2C1 x1

Figure 2.41.: Singly terminated second order LC band-pass (a), its SFG in V/I (b) and abstract form (c) and its unrealizable bilinear DT simulation (d)

One way to maintain passivity of a DT ﬁlter is the operational simulation10 ap-

10"Simulation" in the general meaning of mimicking the behavior of one system with a different system.

Christian Münker March 10, 2010 2.9. Digital Filters 69 proach: The Kirchhoff equations of an analog reference network are transformed in such a way that the transmittances and immitances of all Li and Ci elements 1 1 are mapped to integrators (sLi)− resp. (sCi)− . This is usually performed with the help of a voltage-current (V/I) signal-flow graph (SFG), which can be implemented as an active, inductorless analog filter [MS78] or as an SC filter for full circuit integration without resistors [GMT83]. However, this approach fails for fully digital filters: In Fig. 2.41(a), the example of a second order band-pass is shown with the corresponding V/I SFG (Fig. 2.41(b)) and abstract SFG (Fig. 2.41(c)). Approximating the individual CT integrator blocks by bilinear transform DT integrators results in a DT network with unrealizable delay-free loops (Fig. 2.41), due to the zero latency of the DT integrators.

i0 = iin i1 vout = i0R vL 1 = vout vC 1 (2.9.5) − , − , 1 1 vC,1 = i1 i1 = vL,1 − (2.9.6) − − sC1 − sL1 To overcome the problem of delay-free loops, Alfred Fettweis introduced wave variables - linear transformations of the V/I equations known from microwave and transmission line theory. Constructing the SFG from the wave variable equations and transforming it to the DT domain [Fet86] yields so called wave digital filters (WDF). WDFs maintain the properties of the reference networks, especially their passivity and robustness against quantization and coefficient truncation, making WDFs the most popular filters next to DF filters. Lattice filters are a special case of WDF used in adaptive filtering because their stability can be assessed easily. They are all-pole filters, lattice-ladder-filters also have zeros. While WDF and related structures are much more robust than DF filters, a serious disadvantage remains: There is no simple correlation between filter coefficients and frequency response. This is similar to higher order analog filters which are difficult to tune, requiring the simultaneous variation of multiple elements. As a consequence, WDF battle with the same difficulty, leading to complex structures [ST76, SK97].

2.9.3. Resonator Based Filters

Filters based on undamped DT resonators are less well known than WDFs, although passivity and the same degree of robustness against coefﬁcient truncation

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 70 2. Fundamentals and quantization can be achieved [Pec88]. Similar to parallel ﬁlters derived directly from the transfer function, resonator based ﬁlters consist of a set of parallel digital resonators (Fig. 2.42). However, there are two important differences: The resonators are embedded in a common feedback loop. • The resonators are undamped. •

H (z) H (z) g H1 (z) 2 N

x0 x1 x2 xN xin

Figure 2.42.: Resonator based ﬁlter bank

Due to the parallel structure, these filters have so far mostly been used in the context of adaptive filtering [MS86] with multiple outputs and filter banks for spectral analysis and decomposition [Pec86, PM91]. General transfer functions H(z) can be implemented, using a design procedure described in [Pec89, PM93].

The ﬁlter bank in Fig. 2.43 shows the principle: a common input current iin is divided into currents i1 ...iN into the individual LC-series tanks which are taken as outputs. At the resonance frequency ωi, the impedance of a branch i becomes zero, sinking the complete input current iin. This means, the magnitude of the transfer function becomes one for branch i and zero for all other branches. In an analog implementation of the reference circuit, it would of course be difﬁcult to extract the branch currents without damping the series tanks. As shown in Fig. 2.41(d), bilinear transform of individual integrators in a loop leads to delay free loops that can not be realized. In contrast, replacing the whole loop (Fig. 2.41) by a digital resonator is feasible. [TR95a, TR96] also build upon this approach. Similar structures have been derived in different ways [PM91]:

Observer theory: An input signal is modeled by a hypothetical system of resonators. The states of these resonators (and hence the input signal) is estimated by minimizing the error between the input signal and the output of a set of actual observers [Pec89].

Simulation of singly terminated ladder ﬁlter: In the singly terminated ladder ﬁlter in Fig. 2.43, each CT integrator loop is replaced by an undamped digital resonator [PM91].

Christian Münker March 10, 2010 2.9. Digital Filters 71

i0 i1 i2 iN Iin

C1 C2 CN

L1 L2 LN

(a) Schematic

R 1-11 -1 1 -1 sC1 sL1 sC2 sL2 sCN sLN x0 x x x xin 1 2 N

(b) Abstract SFG

Figure 2.43.: Singly terminated LC ladder ﬁlter bank

The different approaches described above differ in the choice of resonators: Pub- lications based on [Pec89] utilize ﬁrst order complex ﬁlters with transfer functions Hi(z) (2.9.7)

1 ziz− Hi(z) = 1 (2.9.7) 1 ziz − − where zi are complex coefﬁcients.

[PM91, PM93] start with analog LC-ladder filters Fig. 2.43 and arrive at DT resonator based filters built around second order resonators with real coefficients. Under certain restrictions, these resonators can be implemented with very hardware efficient structures requiring only two multipliers.

The above publications utilize a large number of resonators. However, the tunability, simplicity, scalability and robustness of resonator based ﬁlters makes them an attractive choice for BIST applications, even with only one or a few resonators.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 72 2. Fundamentals

2.9.4. Comparison of Filter Structures

Tab. 2.2 summarizes the specific advantages and disadvantages of the DT filters that have been presented in this section (Fig. 2.38). The target application requires tunable narrowband band-pass filters with minimal area, favoring the resonator-based filter structure.

Direct Form WDF Resonator-Based Ease of design + - o Flexibility + + - Robustness - + + Area Consumption - + + Tunability - - +

Table 2.2.: Qualitative comparison of digital ﬁlter families

Christian Münker March 10, 2010 Any sufﬁciently advanced technology is indistinguishable from magic. Arthur C. Clarke 3

Introduction to the Circuit-Under-Test

After some general background on phase-locked loop (PLL) theory, the circuit- under-test (CUT), a sigma-delta modulated radio-frequency PLL as a central part of the DUT is described. A short overview of the device-under-test (DUT) is given as well, a highly integrated wireless transceiver for GSM and EDGE applications. Finally, the critical speciﬁcations that need to be veriﬁed during test are summarized.

Frequency synthesizers belong to the most critical components of modern communication systems. They generate the local oscillator (LO) signal for upconversion and transmission of data over the air or some kind of wire-bound interface and for downconversion of the received signal back down into the baseband domain. In most systems, frequency synthesis is performed with a phase locked loop (PLL) which locks the divided signal of a high frequency oscillator to the signal of a stable reference oscillator.

An ideal carrier signal would have a single spectral line at the oscillation frequency. In reality, random noise and other unwanted signals modulate the carrier. In the time domain, these disturbances can be seen as jitter, reducing e.g. the “data eye” of a clock and data recovery unit. In the frequency domain, the disturbances show as noise skirts as well as discrete lines around the carrier. These lines, created by periodic disturbances are called spurious sidebands. (Fig. 3.1). 74 3. Introduction to the Circuit-Under-Test

|S (f)| Vctrl + ve vco

V ctrl

f t f0−f ref f0 f0+f ref Tref

Figure 3.1.: Disturbance of the VCO control voltage producing phase noise and spurious sidebands on the VCO output

As the limited number of frequency channels has to accommodate more and more network subscribers, bandwidth has become a valuable resource that may not be wasted by spurious emissions. In order to use this resource most effectively, frequency synthesizers have to fulﬁll ever increasing demands:

Fast settling time: GSM and some other communications standards use frequency division duplexing (FDD) / time division multiple access (TDMA) which changes frequencies between every receive and transmit slot. For optimum usage of time and frequency slots, this “frequency hopping” has to be as fast and smooth as possible, requiring tight control of loop bandwidth and phase margin.

Low phase noise and spurious sidebands: Noise and sidebands from the local oscillator can leak into other frequency channels during transmission, disturbing other subscribers. While receiving, local oscillator disturbances can convert signal disturbances down into the target channel, desensitiz- ing the receiver. Noise within the channel bandwidth is also unwanted because it increases the SNR and hence the bit error rate (BER) for both receive and transmit case. As a consequence, in-band and out-of-band PLL noise needs to be tightly controlled to fulﬁll communication standards and system speciﬁcations.

Concepts for on-chip calibration and test help achieving these goals: BISC increases the yield by calibrating the loop parameters under all conditions, avoiding costly calibration routines during production. BIST reduces production test times and cost by running slow tests on-chip and reducing the requirements for external test equipment.

Christian Münker March 10, 2010 3.1. Basic PLL Theory 75

3.1. Basic PLL Theory

Detailed analysis is found in [Bes98, Gar79]; in the following, only some important results are excerpted:

Phase Detector / Charge Pump φ VCO ref Loop Filter φ PD 0 φ φ div = 0 N + F(s) CP

cut here Divider to open loop 1 N

Figure 3.2.: PLL block diagram

Fig. 3.2 shows a block diagram of a PLL, Fig. 3.3 its control theory equivalent.

PD / CP / LF / VCO φ φ φ ref e 0 G(s)

open loop Divider φ div H FB (s)

Figure 3.3.: PLL block diagram - control theory point of view

Usually, the reference phase φre f is regarded as the input and the VCO phase φ0 as the output signal of a PLL (Fig. 3.2). Then, the forward transfer function G(s) (open feedback path) is given by

φ0(s) Kvco G(s) := = Kφ KF0F(s) (3.1.1) φe(s) s where Kφ is the (linearized) gain of the phase detector (PD), deﬁning the ratio

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 76 3. Introduction to the Circuit-Under-Test

of average output voltage and phase error at the input. KF0 is a proportionality factor of the loop filter, including e.g. the current of a charge pump (CP), F(s) is the frequency dependent part. Kvco defines the ratio of frequency change of the VCO and the change of its input voltage. The PLL controls the phase of the (divided) VCO signal, the inherent perfect integration of the VCO frequency always creates one pole at the origin (1/s, Type I PLL). An integrating loop filter or a charge pump (CP) add a second pole at the origin (Type II PLL), requiring a zero for stabilization. The divider divides phase and frequency by N (Sec. 2.3.3).

The product of forward and feedback transfer function is the (open) loop gain G(s)/N (3.1.2).

Φdiv(s) KPDKvcoKF0F(s) KOF(s) As(s) = G(s)/N = = = (3.1.2) Φre f (s) Ns Ns

As the loop ﬁlter is a low-pass, the loop gain also has a low pass characteristic. Its order - which is also the order of the PLL - is the total number of poles of the loop gain G(s)/N. It is larger by one than the order of the low pass due to the integrating behavior of the VCO.

Like most control systems, the behavior of a well-designed PLL can be approximated by a second order system, neglecting the higher order poles of the loop ﬁlter:

1 for type I PLLs 1 + s/ω1 F(s)  (3.1.3) ≈  1 + s/ω1  for type II PLLs sC  

For the loop ﬁlter of a type I PLL, only the dominant loop ﬁlter pole ω1 is taken into account; for a type II CP PLL the main integration capacitor C and the zero 1 at ω2 = (R2C)− are regarded.

Closing the loop in Fig. 3.3 gives the closed loop transfer function T(s) (3.1.5):

Christian Münker March 10, 2010 3.1. Basic PLL Theory 77

Φ (s) G(s) K F(s) T(s) = 0 = = O (3.1.4) Φre f (s) 1 + G(s)/N s + KOF(s)/N ω2 N n 2 2 for type I PLLs s + 2ζωns + ω  n (3.1.5) 2 ≈  N 2ζ/ωns + ω  n for type II PLLs s2 2ζω s ω2 + n + n   where ωn is the natural frequency and ζ the damping, the usual nomenclature for second order systems with

K ω 1 Nω Nω ω = O 1 ζ = 1 = n for type I PLLs and (3.1.6) n N 2 K 2K r r O O ω ω KO ζ R2 KOC n n = = = ω for type II PLLs. (3.1.7) rNC 2 r N 2 2

The loop gain transit frequency ωsT where the loop gain magnitude becomes one, G( jωsT )/N = 1, is an important parameter for the design of PLLs (and other |control systems):|

Type I PLLs: ωc ωn ≈ ζ  for = 0.707 (3.1.8) Type II PLLs: ωc 2ωn  ≈  (3.1.4) shows that the closed loop transfer function of all PLLs can be approximated by (3.1.9), visualized in Fig. 3.4: For frequencies far below the loop gain transit frequency, ω ωsT , the loop gain magnitude G( jω)/N 1 and the closed loop gain T( j≪ω) is only determined by the division| ratio|N ≫in the feedback path. Deviations| of| e.g. the reference phase are multiplied by the divider ratio, PLL phase noise in this in-band region typically has a constant PSD and is dominated by reference, charge pump and phase detector noise.

N for ω ωsT [ GH(ω) 1] T( jω) ≪ | | ≫ (3.1.9) | | ≈  p z G(ω) ∝ (ωsT /ω) − for ω ωsT [ GH(ω) 1]  | | ≫ | | ≪ 

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 78 3. Introduction to the Circuit-Under-Test

At frequencies above the unity gain frequency, ω ωsT , the feedback loop is no longer effective ( G( jω)/N 1) and the transfer≫ function is determined by the forward gain function| G( jω|) ≪. In this frequency range, the PLL behaves like a low-pass of order np nz and the closed loop transfer function drops with (np nz) 20 dB/dec. PLL− phase noise outside the loop bandwidth is dominated by the− VCO· with a PSD that drops with -20 dB/dec. Depending on the phase margin, T( jω) may exhibit peaking at frequencies around ωsT . | | log |T(j ω ) |

log N

−3dB

B Bn f

Figure 3.4.: Closed loop gain T( jω) and noise bandwidth Bn | | The loop gain transit frequency is also approximately equal to the -3dB frequency B of the closed loop (exact for a second order system with phase margin of 45 deg), B[rad/s] ωc. It speciﬁes the maximum change rate of the reference signal the PLL output≈ still can follow. This is also true for changes of the divider ratio which is used to modulate Σ∆PLLs. Hence, the noise bandwidth BN for the reference input and the divide ratio input also directly depends upon the closed loop bandwidth B.

. T( jω) = T(0) /√2 = N/√2 (3.1.10) | | | | B also gives the maximum frequency up to which noise from the VCO is suppressed by the control loop operation - for this noise component, a smaller bandwidth means worse noise performance. This shows that the closed loop bandwidth B is a key performance parameter that has to be veriﬁed during production test.

3.2. Circuit-Under-Test

Only a few years ago, most commercially available GPRS / EDGE transceivers were based on direct conversion architectures. A severe challenge in the design of

Christian Münker March 10, 2010 3.2. Circuit-Under-Test 79 direct modulation transmitters is preventing feedback from the Power Ampliﬁer (PA) output to the unmodulated VCO which creates spurious sidebands [Lee98]. This was achieved with cost-intensive shielding boxes and external ﬁlters for integrated BiCMOS transceivers until commercial pressure forced chip makers to come up with more robust architectures and to migrate to low-cost CMOS technologies.

Figure 3.5.: Principle of Σ∆-modulated PLL with predistortion [GKM+03]

High integration density of modern CMOS technologies enabled the implementation of advanced DSP techniques for digital signal generation. In [GKM+03], a quad-band GSM transceiver is presented in a 130 nm CMOS technology that utilizes a digital sigma-delta modulation transmitter (Fig. 3.5). The integrated VCO is modulated digitally and runs at a multiple of the modulated transmit frequency, making it much less sensitive to PA feedback than a direct conversion architecture. On-chip calibration loops (Built-In Self-Calibration, BISC) were used to overcome one of the main drawbacks of CMOS technologies, the increased parameter spread compared to technologies optimized for analog performance. Speciﬁ- cally, VCO bands and loop gain have to be calibrated before each frequency hop [MSMG02, MS03]. Fig. 3.6 shows a simulation of lock-in, obtained with the simulation methodology described in Sec. 4.5. Despite all digital calibrations, an excellent overall settling time of less than 120µs is achieved. These BISC blocks were also used for a basic Built-In Self-Tests (BIST) of the VCO and the multi-modulus divider to speed up production tests. Due to the combined advantages of ﬁne frequency granularity, fast settling, low

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 80 3. Introduction to the Circuit-Under-Test

Digital Signals Built−In Self−Calibration

∆ f Analog Lock−In

VTune

∆φ

Figure 3.6.: Simulation of PLL lock-in with built-in self-calibration phase noise and digital modulation capabilities [CKHS04, MS02a], most integrated transceiver circuits presented in the last few years utilize Σ∆ fractional-N PLLs (Σ∆PLLs) for frequency synthesis. The device-under-test (DUT) is a wireless transceiver for GSM and EDGE build around a Σ∆PLL for frequency synthesis and digital modulation (Fig. 3.8). Fre- quency modulation is achieved modulating the division ratio of the Σ∆PLL, enabled by the small granularity. Phase modulation for GSM is implemented as indirect PM, i.e. by frequency modulation with the differentiated message signal. The higher device noise level of CMOS technologies compared to bipolar and BiCMOS technologies mandates a narrow PLL loop bandwidth. Typical in- band phase noise levels that can be achieved with Σ∆PLLs with a reference frequency of 13 or 26 MHz are -90 . . . -100 dBc/Hz, requiring a loop bandwidth of 80 . . . 100 kHz to meet the spectral mask requirements at an offset of 400 kHz [Mär00]. This is in contrast to the goal of wide modulation bandwidths: Fig. 3.7 shows the RMS phase error of a typical GSM modulation loop without predistortion as a function of the loop bandwidth, demonstrating that a bandwidth of approx. 500 kHz is needed to meet GSM specs (5◦), neglecting other error sources. Therefore, many Σ∆PLLs apply bandwidth extension techniques to achieve a sig-

Christian Münker March 10, 2010 3.2. Circuit-Under-Test 81 nal bandwidth exceeding the PLL bandwidth: The modulator architecture de- picted in Fig. 3.5 uses digital ﬁltering plus predistortion or pre-emphasis. Sig- nal bandwidth is extended by using a pre-emphasis ﬁlter with the inverse to the closed-loop transfer function T(s) [PTS97].

The characteristic of the digital filter with pre-emphasis is defined by design while the PLL transfer function depends on technology and environmental parameters [Per97, p. 65 – 93]. In practical implementations, this requires some form of adjustment or, preferably, self-calibration to ensure sufficient matching between loop and pre-emphasis.

12 [° ] rms

10 φ f = 13 MHz ref

φ = 4.81° @f = 540.42 kHz rms −3 dB 4

φ = 0.74° @ f = 1358.7 kHz rms −3 dB 2

f [Hz] −3 dB 0 5 6 7 10 10 10

Figure 3.7.: RMS phase error as a function of the open loop bandwidth [Mär00]

Σ∆PLLs with bandwidth extension have ﬁrst been used for Frequency Shift Keying (FSK) applications where the hard switching between frequencies requires a large bandwidth [Per97] and a few years later for modulation standards with tightly controlled bandwidth like Gaussian Minimum Shift Keying (GMSK) [Bax99, Mär00].

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 82 3. Introduction to the Circuit-Under-Test

Figure 3.8.: Block diagram of quad band GSM transceiver

3.3. PLL Speciﬁcations and Test Methods

Three aspects are especially important for the performance of RF PLLs: Loop bandwidth and open loop gain are critical for performance in modulation loop architectures, especially when bandwidth extension techniques are applied. These techniques rely on the matching of analog PLL characteristic and digital pre-emphasis filter, deviations distort the modulation signal. Both parameters also directly influence the noise bandwidth and hence the Total in-band phase noise of the PLL that has to be low enough not to degrade the bit error rate in both receive and transmit mode. Spectral mask requirements need to be fulfilled in transmit mode to avoid disturbances of neighbor channels and receive band. One of the parameters that is especially difficult to achieve is the specification of -113 dBc/Hz at an offset of 400 kHz, requiring a narrow PLL noise bandwidth in the range of 80 . . . 100 kHz. Communication standards operating with constant envelope modulation (GSM, TDMA) specify peak and RMS phase error over one burst, non-constant envelope standards like EDGE or UMTS usually specify the maximum error vector

Christian Münker March 10, 2010 3.3. PLL Speciﬁcations and Test Methods 83 magnitude (EVM). Typically, half of the error budget has to be reserved for other error sources outside the PLL like frequency difference between handheld device and base station, wideband noise of the VCO buffer or imperfections of modulator / demodulator. Within the PLL, both modulation distortions and phase noise contribute to the integral error. Power Density [dBc(Hz)]

Offset Frequency [kHz]

Figure 3.9.: Power spectral density mask for GSM 900 and DCS 1800 [Mär00]

The maximum emission levels in the GSM system specification at given offset frequencies are measured with a spectrum analyzer with defined measurement filter and resolution bandwidth (RBW). In Fig. 3.9 [Mär00], the GSM spectral specifications are shown as PSDs for a bandwidth of 1 Hz for comparison with the SP-BIST spectral analyzer.

The question how much the bandwidth B of the closed loop may deviate from its nominal value depends on the transceiver architecture: For unmodulated PLLs, 1 the integrated VCO noise ( B− ) and reference noise ( B) as well as the set- 1 ∼ ∼ tling time ( B− ) determine the acceptable bandwidth range, requiring control to typically∼ 20%. ±

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 84 3. Introduction to the Circuit-Under-Test

Modulated Σ∆PLLs require a tighter control of bandwidth variations as mismatches between the modulation / pre-emphasis ﬁlter and the low-pass characteristic of the PLL create distortions of the modulated signal. When Σ∆PLLs are used to create the angle modulation part in polar modulators [MKNM05, MNM+05], the loop bandwidth has to be controlled even tighter to minimize mismatches between phase and amplitude modulation paths.

10 [° ]

7.5 rms φ

5.0

2.5

ε OLG [%] 0 −20 −15 −10 −5 0 5 10 15 20

Figure 3.10.: RMS phase error as a function of the open loop gain error [Mär00]

Time-constant variations of integrated loop ﬁlters typically are in the order of 20%, creating a bandwidth variation of the same order (3.1.8).

Open loop gain KO is another main contributor to bandwidth variations in the same order of magnitude as it includes the gain variations of VCO, PD, CP and loop ﬁlter. Consequently, several methods have been developed for loop gain calibration / testing, either operating on the open [MSMG02] or the closed loop [MS02a]. However, these methods cannot track the variations due to loop ﬁlter time constants, resulting in a larger tolerance band. Alternatively, precise external components (usually too expensive and large) or switched capacitor solutions (potential issues with switching noise) can be used. The following estimations have been made for the RMS phase error due to loop bandwidth variations in a typical GSM systems with modulation loop [Mär00]: Variations of open loop gain in the range of 10% typically result in an • ±

Christian Münker March 10, 2010 3.3. PLL Speciﬁcations and Test Methods 85

additional phase error of 3...5◦ Variations in the loop ﬁlter components of only 10% create an RMS • ± phase error of φrms 3 . ≈ ◦ Either case consumes more of the phase error budget than is typically allowed for the complete PLL, showing the need for precise monitoring and possibly calibration of the loop parameters. As a consequence, the closed loop bandwidth including the aforementioned error sources should be measured to an accuracy of 5%. Near the -3 dB point, the closed loop transfer function behaves like a ﬁrst- order± lowpass, rolling off with ca. -20 dB/dec. Hence, an amplitude measurement error Aε directly translates to a bandwidth measurement error Bε : −

Bε < 5% Aε < 5% 0.4dB | | ⇒ | | ≡ As loop bandwidth and in-band phase noise influence all critical PLL performance aspects, precise on-chip measurement of both parameters is of paramount importance. Additionally, the RF signal has to measured at a few critical offset frequencies to verify conformance to spectral mask for modulated and unmodulated signal. These frequencies are usually known from lab evaluation. Finally, the out-of-band noise, dominated by VCO and VCO buffer has to be determined. For the GSM case, the following requirements result: Amplitude Accuracy: Frequency response has to be measured with an amplitude accuracy of 0.4dB. ± Noise Floor: Phase noise floor has to be below -90 dBc/Hz for in-band noise measurements, preferably even lower. Spectral Mask: Spurious tones and modulation have to be measured, the most difficult being the 400 kHz corner where the maximum emission level is -113 dBc/Hz. Out-of-Band Noise : Maximum emission level in TX mode is -129 dBc/Hz at 6 MHz offset Similar requirements can be collected for other wireless standards.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 86 3. Introduction to the Circuit-Under-Test

Christian Münker March 10, 2010 If at ﬁrst the idea is not absurd, then there is no hope for it. Albert Einstein 4

Concept and Simulation Methodology for Spectral BIST

A self-test concept for integrated PLLs is introduced that allows the direct measurement of spectral parameters in RF PLLs. The measurement principle and the partitioning of signal processing between chip and production tester are explained. Furthermore, a new simulation methodology is introduced for RF systems with a large digital part like PLLs, allowing efﬁcient co-simulation of analog blocks in a digital simulator by using discrete-time behavioral VHDL modeling.

4.1. RF PLL Test Concept

Wireless devices and circuits are usually specified in the frequency domain, re- flecting the specifications of transmission standards using frequency division multiplexing and duplexing. During production test, these specifications have to be verified. In highly integrated RF ICs, the test of individual building blocks proves increasingly difficult as internal signals are not routed to package pins to save area and to reduce the risk of unwanted crosstalk. Fig. 3.8 shows the block diagram of an integrated GPRS - transceiver produced by Infineon Tech- 88 4. Concept and Simulation Methodology for Spectral BIST nologies in 2003. By today’s standards, the level of integration is comparatively low, but already here the PLL is inaccessible from the outside. Multiplexing the PLL RF output to a shared test pin does not work well as parasitics and crosstalk deteriorate the signal quality, possibly also during normal operation mode.

DUT Multi−Tone Spectral Output Stimulus mod RF Response Generator Analysis CUT Σ∆ PLL f

BIST BIST Control and Data Bus BUS SP−BIST

Figure 4.1.: Spectral PLL BIST Concept

This makes on-chip spectral analysis of RF PLLs a highly attractive feature for improving the testability; it can also reduce the hardware requirements for the production tester. While spectral parameters could be derived from e.g. the step response, a direct measurement of spectral parameters (Fig. 4.1) is desirable as the translation of time domain parameters into the frequency domain requires high digital signal processing power.

4.2. Measurement Principle

4.2.1. PLL Bandwidth

As shown in Sec. 3.1, the loop bandwidth defines the maximum modulation frequency of a PLL at the low-pass modulation points (reference input, loop filter input, divider ratio). Modulation frequencies above the loop bandwidth give reduced frequency excursions, corresponding to a smaller modulation index. A PLL operates on phase excursions (as the name implies), however, it is easier to generate frequency modulation using digital techniques: Varying the division ratio changes the output frequency, applying the frequency control word as an oversampled Σ∆M bitstream achieves a fine granularity of frequency variation. This is utilized in indirect PM where the PLL is frequency modulated with the differentiated modulation signal.

Christian Münker March 10, 2010 4.2. Measurement Principle 89

The resulting modulation of the PLL signal can be determined from its frequency deviation, phase deviation or its amplitude spectrum. While the latter is the standard measure used e.g. in a spectrum analyzer, a simple relation to phase or frequency deviation only exists for small angle modulation indices (Sec. 2.2.2). However, high modulation indices are advantageous for a good SNR with simple demodulators. Phase deviation is inversely proportional to modulation frequency (-20 db/dec), attenuation due to the loop bandwidth can be only be determined as a deviation from this slope (Fig. 4.2). This makes an FM discriminator the ideal choice as its output is a direct measure for the frequency response of the PLL (Fig. 4.2).

CUT BW

sstim Frac−N f0 f sPLL FM sora f Σ∆− PLL Demod. m f ∆ f fm 0 fm φ Sstim (f) Sy,PLL (f) S ,PLL (f) Sora (f) Characteristic β Characteristic y Loop A Loop Am1,2 m1 f1 d1 y A m2 −20 dB/dec d2 β f2 f f f f

fm1 fm2 fm1 fm2 fm1f m2 fm1 fm2

Figure 4.2.: Principle of PLL bandwidth measurement

4.2.2. Spectral Analysis with FM Discriminator

In addition to PLL bandwidth measurements, the SP-BIST shall also be used to measure unwanted sidebands and in-band noise. As the SP-BIST only delivers the power spectral density (PSD) of frequency deviation, it has to be converted to phase noise to obtain results that can be compared to conventional lab equipment and ATE hardware.

As shown in Sec. 2.3, PSD of phase deviation Sφ is derived from frequency deviation Sy via (4.2.1):

∆ 2 f f0 φ L φ = and 4Su( f0 + fm) 2 ( fm) = S ( fm) = 2 Sy( fm) (4.2.1) fm ≈ fm c b

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 90 4. Concept and Simulation Methodology for Spectral BIST

(4.2.1) also shows that frequency discrimination emphasizes high-frequency phase modulation components.

4.3. From MADBIST to SP-BIST

The Mixed Analog-Digital Built-In Self-Test (MADBIST) concept [TR93b] described in Sec. 1.2.6 was introduced to ease production test of embedded ADCs and DACs in ICs. The following features make MADBIST a good starting point for the development of an RF self-test concept:

The stimulus, a multi-tone signal, is generated entirely in the digital do- • main.

The response is analyzed entirely in the digital domain, delivering spectral • information.

Analog signal paths remain (nearly) untouched. • In contrast to e.g. HBIST, parameters extracted by spectral techniques have "real- life" meanings like noise level or tone amplitude which allow easy implementation of tolerance bands for pass / fail decisions. As a consequence, complex measurement scenarios like signal-to-noise ratio or -3dB frequency can be reduced to a few measurements.

Building upon the basic MADBIST concept, a new self-test solution for RF PLLs has been developed under the name of Spectral PLL BIST (SP-BIST). Fig. 4.3 shows both concepts side by side. The main difference between the two concepts is the embedding of the DUT:

The PLL RF output has to be demodulated and digitized to obtain a base- • band signal containing frequency and phase deviation. The ADC output is digital and can be processed right away.

The PLL can be modulated directly with a digital bit stream. In contrast, • the analog ADC input requires an analog multiplexer, an auxiliary DAC and an analog reconstruction ﬁlter.

SP-BIST has been optimized for low chip area and low ATE requirements. This has been achieved mainly by an optimized test partitioning between BIST and ATE and by reducing accuracy without sacriﬁcing precision (Sec. 4.4); the measurement bias is removed on the ATE:

Christian Münker March 10, 2010 4.3. From MADBIST to SP-BIST 91

DUT Optional Loop−Back Test ANA f OUT DAC SW Rec−Filter DSP

ANA f IN ADC AA−Filter MUX CUT

BIST CTRL

f Multi−Tone Generator DAC

Bandpass 1b Aux− Ana. Control Bus BIST SDM DATA Dig. MADBIST Data Bus

(a) DUT RF Transmit TX DSP Path OUT Polar−Modulator Frequency + Modulation Word TX Σ∆ OUTB Σ∆ −PLL −FM− Demod Multi−Tone Generator CUT BIST Control and Data Bus BUS

t RF SDM f SP−BIST Envelope Dig. Bandpass

(b)

Figure 4.3.: Mixed Analog-Digital BIST (MADBIST) (a) vs. Spectral PLL BIST (SP-BIST) (b)

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 92 4. Concept and Simulation Methodology for Spectral BIST

Reduction of tester bandwidth: Only high-speed operations are performed on- chip; the result is generated as a static word that is read-out via the control and data bus of the DUT. The staggered forth order tunable band-pass filter has a low scalloping loss that tolerates slight deviations between stimulus and band-pass filter frequency. This allows coarse coefficient quantization reduced coefficient accuracy improves selectivity in comparison to the second order filter of the original design. The coarse coefficient quantization results in a slight deviation between tone frequency and the center frequency of the filter which could be tolerated due to the low scalloping loss of the new staggered filter. The remaining systematic errors and bias were removed in software on the ATE. It should be noted that MADBIST can be implemented with nearly no cost together with the SP-BIST: The multi-tone generator has a parallel output that can be used to stimulate e.g. DACs and an Σ∆M output for ADC - testing, requiring only an additional one-bit DAC and a simple RC low-pass filter.

4.4. Partitioning of Test Hardware

Minimum hardware complexity of the additional BIST blocks is obtained by performing as much signal processing as possible on the automated test equipment: high-speed data acquisition and compaction is performed on-chip, linearization and other slow but complex algorithms can be performed by the automated test equipment (ATE). Measurements need to be precise (highly repeatable) but not necessarily accurate (close to the true value) as long as the bias can be corrected later on (Sec. 2.1.2). Fig. 4.4 visualizes the difference between accuracy and precision using the well-known target analogy.

(a) (b) (c)

Figure 4.4.: Measurements with low accuracy and high precision (a), high accuracy and low precision (b) and high accuracy and high precision (c)

Christian Münker March 10, 2010 4.5. Simulation Methodology 93

In this work, the following operations are performed on the ATE to minimize hardware: Gain correction (neither stimulus nor band-pass gain is normalized) • Frequency dependent band-pass gain (Sec. 6.3.4) • Correction of non-linear dependency between programming parameter and • stimulus resp. band-pass center frequency (Sec. 7.1.1) Frequency dependent stimulus amplitude (Sec. 7.1.2) •

4.5. Simulation Methodology

The paradigm shift from pure analog RF ICs to highly integrated System-On- Chip (SOC) solutions described in the introduction also has a major impact on verification methodology. A few years ago the borderline between analog and digital circuitry was well defined: RF ICs had a relatively low complexity and were implemented on technologies optimized for analog performance. RF blocks were simulated using special RF simulators like SpectreRF or ADS which offer simulation modes optimized for RF problems like harmonic balance or periodic steady state analysis. These simulation modes are extensions of SPICE-like (Sim- ulation Program with Integrated Circuit Emphasis) analog simulators which are essentially non-linear differential equation solvers. Detailed device and parasitics models and the complex simulation algorithms limit the number of devices that can be simulated at the same time. Therefore, verification on chip level usually is performed by running an analog simulation of the whole chip with simplified analog behavioral models for the RF blocks. DSP functionality was implemented on a separate chip in a standard CMOS technology and verified using digital hardware description languages (HDL’s) like Verilog, VHDL etc. with event-driven simulators optimized for large digital designs. Simulation of analog designs with small digital parts (big A, small d) like an ADC with self-calibration can be sped up using mixed-mode simulators which couple an event-driven simulator core with a non-linear differential equation solver. However, this approach is still too slow for complex chips, long time frames or when there is a close interaction between analog and digital parts. Analytical approaches using Matlab, Excel etc. can verify chip performance on an abstract level (level plans etc.) but integration of digital circuit blocks to verify

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 94 4. Concept and Simulation Methodology for Spectral BIST e.g. a calibration algorithm is difficult and slow. Current RF SOCs integrate RF building blocks together with digital logic exceeding a million gates in some cases [SML+04]. Calibration algorithms involve complex interactions between RF and digital parts, noise performance is determined by analog and digital parameters alike. These systems cannot be simulated with a mixed-mode simulator, much less with SPICE type tools. The target is an "unified functional verification approach" i.e. using behavioral models for the RF blocks that can be simulated using an event-driven, discrete time simulator. Fortunately, modern HDL’s like VHDL have powerful signal algorithmic capabilities allowing an efficient modeling of analog blocks in the digital domain: s-domain transfer functions can be translated into the discrete-time z-domain [Mün04]; oscillators generate events timed with their oscillation frequency and phase noise is described by jitter processes [SFB05]. This approach allows to freely mix abstract behavioral models with gate level digital blocks. In this work, VHDL was chosen as the modeling language because its behavioral possibili- ties are far superior to Verilog. The suitability of SystemC was also tested in a Master thesis [Lay05] but at that time, stability and tool chain support were not convincing. Matlab provides the missing capabilities of digital simulation environments for post-processing and plotting data in the frequency domain (Sec. 4.5.5).

4.5.1. Special Requirements for PLLs

The simulation of PLLs is a challenging task due to the large range of time constants: The Σ∆PLL of the CUT has an output frequency around 4 GHz (Tvco = 250 ps), a reference frequency of 26 MHz (Tre f = 38.5 ns) and a loop ﬁlter corner frequency of 100 kHz (τ = 15.9 µs). In order to verify spectral purity, the loop ﬁlter voltage has to be calculated with a precision of a few µV. Classical mixed- signal simulation has proved to be far too time consuming, a faster method is to apply the event-driven approach known from digital simulation. A block diagram of the CUT is shown in Fig. 4.5. The simulation methodology has originally been developed by the author to verify the correct lock-in behavior of the PLL and to simulate the total phase noise performance at the VCO output stemming from digital Σ∆-quantization noise and jitter in the VCO. Σ∆- quantization noise is produced by the SD-modulator and the multi-modulus divider. Accumulative (FM) and non-accumulative (PM) jitters are included in the VCO model as described in [GKM+03, SFB05]. The required noise parameters are extracted from analog simulations.

Christian Münker March 10, 2010 4.5. Simulation Methodology 95

In this work, correct interaction between Σ∆PLL and SP-BIST in the time and frequency domain is veriﬁed using this method.

reference frequency output frequency ∆Φ

Phase Frequency Loop Filter VCO Detector 1/N

Divider integer Σ part

fractional part

Σ∆ Modulator

Figure 4.5.: Block diagram of Fractional-N PLL

Fig. 4.6 shows the partitioning of the system for simulation purposes: Most parts of the PLL and the BIST circuit like the Σ∆ modulator and multi-tone generator have been designed in VHDL anyway, others like the multi-modulus divider or the phase detector are high-speed logic blocks that are described in behavioral VHDL easily. The modeling of two analog blocks - the VCO and the loop ﬁlter - in a discrete-time environment is described in the next section.

4.5.2. Discrete Time Modeling of Analog Blocks

Loop Filter

The loop filter of the CUT is a non-integrating (type I PLL), third order analog low-pass (Fig. A.1). For DT simulations, it is modeled as a DT direct-form filter (A.1.2), obtained by bilinear transform of the CT transfer function (A.1). The filter calculation is performed twice per filter clock period which has an arbitrary frequency that should be 10x ... 20x higher than the maximum input frequency to achieve a reasonable accuracy of the DT filter characteristic. Higher clock frequencies slow down the simulation unnecessarily. However, the sampled filter model creates major problems for PLL simulations: The filter runs with a fixed sampling period TS, filt while the charge pump can

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 96 4. Concept and Simulation Methodology for Spectral BIST

Control Unit and Registers VHDL Plot Stimuli mod FIFO Gauss− and MASH Predist.−Filt. VHDL VHDL VHDL

f ref

VHDL MMD VHDL VHDL (Beh)

PD/CP Loop Filter VCO VHDL (Beh) VHDL (real) VHDL (real) f ref Multi−Tone

BISC Spectral Output Response Analyzer Stimulus Generator CUT VHDL SP−BIST DUT RF

Figure 4.6.: Simulation setup for CUT and SP-BIST basically switch at any time1. This means, the filter model will react to a change of the charge pump output with an average latency of TS, filt /2, creating the beat frequency effect between fS, filt and fre f shown in Fig. 4.7 for fS, filt = 2 GHz and fre f = 26 MHz. In the frequency domain, the strong ripple of the loop filter voltage in Fig. 4.7 created spurious sidebands with a level of -81 dBc. The filter sampling frequency has to be increased to thousands of GHz before the simulation artifacts become reasonably small, slowing down simulation tremendously.

Figure 4.7.: PLL simulation error due to sampled ﬁlter model

1Limited only by the minimum VHDL simulator resolution of 1 fs.

Christian Münker March 10, 2010 4.5. Simulation Methodology 97

Instead, a much more efficient solution has been developed where the timing error of the sampled filter is translated into a scaled amplitude of the next input value for the filter (App. A.1): The timing error is corrected in the filter model by translating it into an “analog” amplitude value which can be handled by the filter without error. The model tracks the time between the last switching of the phase detector / charge pump and the next sampling clock event and scales the filter input with the ratio of this time and the full sampling period (“fractional” compensation) (Fig. 4.8).

FiltClk T Thigh S,Filt

Filt in

V tune t

Figure 4.8.: Principle of fractional compensation

This linear compensation produces small "kinks" in the loop ﬁlter voltage every time the charge pump CP switches that are visible in Fig. 4.9. However, the spurious sidebands due to the sampling error are reduced by approx. 40 dB, requiring no further reﬁnement of the model.

VCO Modeling

The efficiency of VCO simulation is increased tremendously by ignoring the amplitude information and regarding only the zero crossings. This simplification is justifiable for the case of PLL simulation as the output is amplitude limited anyway. In the analog world, VCO amplitude noise is converted to phase noise in the limiting stages that can be included in the VHDL phase noise model. The VHDL model in App. A.2 calculates the ideal VCO period in fs. Last cycle’s truncation error, i.e. the remainder is added to the current period to avoid accumulation of the truncation error as this would give a period error of ca. 0.5 fs (Sec. 4.5.3).

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 98 4. Concept and Simulation Methodology for Spectral BIST

4.5.3. Limitations of Event-Driven Analog Simulation

Analog simulators use elaborate algorithms to solve non-linear differential equations and adjust the simulation time-step according to signal transients and accuracy requirements. An event-driven simulator is only capable of calculating explicit equations like x(n) = Asinω0tn at pre-calculated times stored in an event queue. Simulating the amplitude and frequency of an LC-oscillator with a SPICE simulator requires only the model parameters and netlist elements without user interaction. For an event-driven simulation, the oscillator needs to be modeled e.g. using the well-known LC-tank formula. The amplitude resolution of ﬂoating point real numbers in event driven simulators is the same as in analog simulators (data type double with 52 bits for the mantissa):

52 16 ε = 2− 2.2 10− ≈ · This corresponds to approximately 16 decimal digits of accuracy and is more than sufﬁcient for most applications. Timestep resolution is a different matter: In VHDL and SystemC, events are timed using a 64 bit integer variable and a minimum timestep of Tq = 1 fs. The resulting maximum simulation time is 263 fs 2 1/2 hrs which is plenty for the ≈ purposes of this work. However, this quantization leads to a timing error ∆T < Tq when timing events are derived from calculations in real format (see VCO model). The truncation will create the event a fraction of a fs earlier than calculated. For an oscillator, the calculated period T0 is shortened by ∆T resulting in a small frequency error ∆ f .

∆ ∆ ∆ 1 1 1 + T/T0 1 T TQ f = f0,Q f0 = = 2 2 (4.5.1) − T0 ∆T − T0 ≈ T0 − T0 T ≤ T − 0 0

For a target oscillator frequency around f0 = 4 GHz, a worst case estimation ∆T = TQ = 1fs yields ∆ f = 16.8 kHz (4.5.1). This frequency error is too large for a precise simulation of most communication standards. Tracking the difference between calculated and quantized period and correcting it in the next period brings the average frequency error to zero at the price of introducing a period jitter. The jitter has a uniform distribution in the range

Christian Münker March 10, 2010 4.5. Simulation Methodology 99

2 2 TQ/2... + TQ/2 with zero mean, variance σ = T /12 and an RMS value σ = − Q TQ/(2√3) = 0.29fs. In driven blocks like ﬂip-ﬂops or buffers, this jitter modulates the phase with a constant power spectral density (PSD) in the range 0... f0/2 (cyclostationary noise). Converting the jitter to phase error by multiplying it with ω = 2π f0 yields the quantization noise power, constant phase PSD and the phase noise over the bandwidth of B = f0/2 (4.5.2) - (4.5.4):

2 2 2 (π f0TQ) 12 PQ N = σ ω = = 52.6 10− W 102.8dBW (4.5.2) , 3 · ≡ − 2PQ,N 20 W Sφ ( f ) = = 2.63 10− 196dBc/Hz (4.5.3) f0 · Hz ≡ − Sφ ( f ) L ( f ) = 199dBc/Hz (4.5.4) 2 ≡ −

This "simulation quantization noise floor" is low enough for PLL / VCO applications with a minimum noise floor of -160 . . . -170 dBc/Hz. In autonomous blocks like oscillators, the jitter modulates the period: Referred to T0 = 250 ps, the unit 6 interval jitter is JUI,rms 1.2 10− . This jitter is white FM phase noise with a PSD of ca. -134 dBc/Hz≈ at 1 MHz· offset. The period quantization error bears a strong correlation to the carrier period which may produce spurious lines. To decorrelate the quantization error, some jitter with defined amplitude and spectral characteristic is added (Sec. 4.5.4) which is also used to model FM and PM noise in the time domain.

4.5.4. Noise / Jitter Modeling

In an event-driven language like VHDL, phase noise can only be represented in the time domain i.e. as jitter. Therefore, the first step has to be to transfer phase noise specifications from the frequency into the time domain. Here, only the special case of white noise is described, although methods for discrete-time modeling of colored noise and power-law random processes like 1/ f noise have been developed [DDHSW01]. In the simplest case, phase noise has a white spectrum and a Gaussian amplitude distribution. It is specified by a single figure in the frequency domain because the PSD is constant over frequency. Correspondingly, in the time domain the jitter

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 100 4. Concept and Simulation Methodology for Spectral BIST is completely described by its standard deviation σ. In spite of its simplicity, this noise / jitter model describes Added White Gaussian Noise (AWGN) that is present in many real-world systems with sufﬁcient accuracy. It is converted to timing jitter by non-linear signal processing stages like limiters or logic gates. How can white noise be modeled in VHDL? Non-autonomous blocks like a logic gate or a buffer process events at their inputs and pass the result on to the output with a certain latency. This latency depends on the slew rate at the input, the speed of the actual circuit etc. and varies in a random fashion due to thermal noise in the circuit. Modulating the latency of the digital model with a random process with Gaussian distribution gives white phase (PM) noise spectrum, achieving the wanted effect. The VHDL model for such a random process is described in App. A.3. Oscillators are autonomous blocks where thermal noise creates to random ﬂuc- tuations of the oscillation period. Hence, modulating the period of an oscillator model with a suitable random process creates white frequency (FM) noise. A VCO model containing both FM and PM noise is described in App. A.2.

4.5.5. Spectral Estimation of Simulation Results

In contrast to analog or mixed-signal simulators, digital simulators offer no post- processing options to regard simulation results in the frequency domain. The workaround to this drawback is based on the solution described in [Kun05], where the period data of the VCO is written to a text ﬁle. Spectral analysis of the period data, contained in the deviations of the zero crossings from ideal times, is performed with MATLAB (Sec. 2.4).

4.5.6. PLL Simulation Results

Some simulation results are presented to demonstrate the power of the developed simulation and modeling method. All the examples in this section have been simulated with an unmodulated PLL at a fractional frequency. The left abscissa displays the level of spectral (spurious) lines, the right one has been corrected with the resolution bandwidth for noise levels. Fig. 4.9 shows a simulation of the loop filter output voltage ripple, created by the filter’s finite suppression of the PLL reference frequency. The pk-pk amplitude is approx. 10µV, as predicted by circuit simulations, resulting in a VCO peak frequency deviation of ∆ f = 265Hz. The VCO gain is 53 MHz/V.

Christian Münker March 10, 2010 4.5. Simulation Methodology 101

Fig. 4.10(a) shows the corresponding PLL phase noise spectrum with the spurious line at 26 MHz and a level of -106 dBc, the same result is obtained by calculation (2.3.16), proving the validity of the simulation setup. Phase noise in the simulation is due to the Σ∆-modulation of the MASH modulator.

µ 10 Vpp VTune

530 Hzpp ∆f

1 /fref

Figure 4.9.: Simulation of Σ∆PLL tuning voltage with fre f = 26 MHz and fS, filt = 1 GHz

In a practical PLL, thermal noise sources lead to a much higher noise level. In- stead of adding individual noise source, their integral effects are modeled in Fig. 4.10(b): At high frequencies, noise typically is dominated by the VCO buffer (PM jitter, noise floor), at lower frequencies by the VCO itself (FM jitter, -20 dB/dec). For frequencies below the loop bandwidth (in-band noise), the noise level should be constant (disregarding flicker noise). However, this can only be guessed from looking at the simulation results as long simulation times and very large result files are needed to improve the frequency resolution.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 102 4. Concept and Simulation Methodology for Spectral BIST

Figure 4.10.: Simulation of Σ∆PLL spectrum without modulation (a) and with FM and PM jitter modeling (b)

Christian Münker March 10, 2010 There is no carrier, there is only concentrated noise. B.-G. Goldberg 5

Test Tone Generation

Test signal generation as the ﬁrst part of SP-BIST is developed in this chapter. The most suitable method for this work, a digital oscillator based upon a tunable, undamped resonator with a low-pass Σ∆-attenuator, is described in detail. Up- conversion by the Σ∆PLL as the circuit-under-test (CUT) into the RF domain is analyzed as well.

As shown in Sec. 3.2, most analog parameters (e.g. VCO and phase detector gain, loop filter time constants) of the PLL directly influence the loop bandwidth, making measurement of this parameter especially powerful for detecting catastrophic and parametric faults. For this purpose, a base-band test-tone generator is needed with the following requirements: Little area overhead • Reusability for new products and technologies • Robustness against parameter variations • Autonomous operation, i.e. without interaction with other blocks • Multi-tone generation for efficient tests in the frequency domain • These demands can only be fulfilled with a mainly digital concept. As men- tioned before, quantitative frequency domain characterization is performed more 104 5. Test Tone Generation efficiently using multi-tone signals. Several methods for the digital generation of such signals are compared next.

5.1. Principle of Digital Sine Generator

5.1.1. Direct Digital Synthesis

Direct digital synthesis (DDS) is a table look-up scheme where a digitized sine function is suitably compressed and stored in a read-only memory (ROM). Differ- ent signal frequencies are generated by using a phase accumulator with different increments to address the ROM, the content is converted into an analog signal with a DAC. For the purpose of BIST tone generation, this approach is too complex and leads to a large area overhead.

5.1.2. Arbitrary Waveform Generation

Arbitrary waveforms can be efficiently encoded into aperiodic pulse-density modulated (PDM) or Σ∆M serial bit streams. This principle is also based on a look- up table, although the "table" contains only single-bit data that are read out with a high oversampling rate. Compact implementations mandate the use of ring buffers and hence approximating the signal by periodic bit streams, still requiring a large number of registers (a few hundred to a few thousand) for high-quality signals. Generation of multi-tone signals has been demonstrated in [HR98, DR99]. How- ever, the proposal of re-using on-chip RAM or scan chain flip-flops for pattern storage is in contrast to the requirement of an autonomous test block and is difficult to implement in a standard digital design flow. Another disadvantage is that a new pattern needs to be loaded into the chip for each different test case (e.g. amplitude, frequency), increasing test time and volume of test patterns.

5.1.3. Lossless Digital Resonator

In principle, a lossless resonator is the most simple implementation for a sine oscillator with tunable frequency and amplitude. While analog oscillators require some form of gain control to stabilize the amplitude in presence of gain and other

Christian Münker March 10, 2010 5.1. Principle of Digital Sine Generator 105 parameter variations, this should not be necessary for digital implementations due to their deterministic nature. Here, direct-form (Fig. 5.1(a)) resonators and resonators based on lossless digital integrators (LDI) are regarded (Fig. 5.1(b)) as both allow placing the pole on the unit circle and tuning the resonance frequency with a single parameter:

LDI (BE) x[n] z −1

y[n] −g −1 −a2 = −1 z −a −1 1 −1 z z LDI (FE)

(a) (b)

Figure 5.1.: Implementations for undamped digital resonators: direct form (a) and LDI-based (b)

The characteristic equation for an undamped resonator (poles on the unit circle) has been derived in (2.7.13): 1 2 ∆ = 1 2cosΩrz− + z− = 0 − The coefﬁcients of the two resonator types above for undamped resonance are determined by comparing the coefﬁcients of their characteristic equation to the general resonator equation (2.7.13). The following condition for undamped resonance has been derived in Sec. 2.7.1 for the direct form resonator in Fig. 5.1(a):

1 2 ∆ = 1 + a1z− + a2z− a1 = 2cosΩr and a2 = 1 (5.1.1) ⇒ − The LDI-based resonator in Fig. 5.1(b) is a loop of two lossless digital integrators, one of them in a forward Euler (FE), the other one in a backward Euler (BE) integrator conﬁguration. Its characteristic equation is derived using Mason’s rule [Dor92], yielding the condition for undamped resonance as

1 2 ∆ = 1 (2 g)z− + z− 2 g = 2cosΩr . (5.1.2) − − ⇒ − It can be shown that the LDI-based resonator has a higher pole density and hence better SNR for low frequencies (near z = 1), making it more suitable for this work.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 106 5. Test Tone Generation

In both implementations, the coefﬁcient a2,Q is exactly 1, ensuring place- ment of the pole on the unity circle. The quantization of coefﬁcient a1,Q = Q 2cosΩr Q = 2cosΩr Q generally results in a slight shift of the resonance {− , } − , frequency Ωr,Q but does not move the pole from the unit circle.

Ω Ω Ω2 For small resonance frequencies r 1, the approximation cos r 1 r /2 yields the result ≪ ≈ −

g Ωr = arccos 1 √g for Ωr 1 (5.1.3) − 2 ≈ ≪ which is the same result as for an analog or SC oscillator consisting of a two- integrators loop (Fig. 5.2), e.g. [HBKZ84]. Its oscillation frequency is determined by the characteristic equation

g ∆ = 1 = 0 ω = √g. (5.1.4) − s2 ⇒

x(t) −g x(t)

−g 1 1 s s

(a) (b)

Figure 5.2.: Oscillator based on analog integrators (gain control not shown): (a) principle and (b) signal-ﬂow graph

In general, implementations of digital oscillators made from these resonators (or any other) will fail. This can be traced back to the inevitable signal quantization after multiplication, creating pseudo-random errors that can create distortions, amplitude ﬂuctuations or even quench the oscillation. A solution to get around this problem is shown in Sec. 5.2.

Christian Münker March 10, 2010 5.2. Digital Resonator with Low-Pass Σ∆-Modulation 107

5.2. Digital Resonator with Low-Pass Σ∆-Modulation

5.2.1. Principle

In principle, a compact test-tone generator with programmable resonance frequency can be constructed from the ideal digital undamped resonator (Fig. 5.3) described in Sec. 2.7.2.

LDI a x a [n] z−1

z−1 a b z−1

x b [n] LDI b

Figure 5.3.: Principle of LDI based oscillator

Analytical expressions for output signal frequency ωsig, amplitude xa,xb and initial phase φa,φb depending on sampling frequency fs, coefﬁcients a, b and the initial conditions xa(0),xb(0) have been derived in [LRJ94]:

ab ωsig = fs arccos 1 for 0 < ab 2 (5.2.1) − 2 ≤ sin(ωsigTs)xa(0) φa = arctan (1 ab cos(ωsigTs))xa(0) + axb(0) − − sin(ωsigTs)xa(0) = arctan (5.2.2) abxa(0)/2 + axb(0) − (1 ab)xa(0) + axb(0) xˆa = − (5.2.3) sin(ωsigTs + φa)

Results for φb andx ˆb are attained by exchanging xa with xb and a with b. For small coefﬁcients ab 1, the following approximations hold true − | | ≪ ab ab 1 cos√ab and arccos 1 ab , − ≈ 2 − 2 ≈ | | p

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 108 5. Test Tone Generation

yielding the following simpliﬁed relations by setting xb(0) = 0 [Mün05]:

ωsig √ab fs (5.2.4) ≈ 2sin(ωsigTs) φa = arctan π/2, φb = 0 (5.2.5) − ab ≈ − xa(0) b xˆa φ xa(0), xˆb xa(0) (5.2.6) ≈ sin a ≈ ≈ ra

(5.2.4) - (5.2.6) show that frequency and amplitude of the test tones can be set independently. The amplitude is controlled via the initial conditions of the state variables. Practical implementations battle with with finite accuracy, making it difficult to maintain a stable oscillation. This is true even for a resonator topology like the LDI based resonator where the poles remain on the unit circle when the ideal coefficient values are quantized. A solution is shown in the next section.

5.2.2. Σ∆-Attenuator

As multiplication increases the word length, the product has to undergo signal re- quantization before it can be fed back into the loop again. This process creates or destroys energy, depending on the kind of quantization applied (truncation, rounding etc.) and the sign of the signal, preventing stable oscillation for all resonators. [LRJ94] describes a stable digital oscillator based on Fig. 5.3 where one multi- α plier is replaced by a fixed bit shifter, providing multiplication by 2− without hardware. The second multiplier is substituted by a Σ∆-attenuator that first converts the parallel data x[n] into an equivalent oversampled single-bit stream xd[n] (Fig. 5.4(a)). Multiplication of xd[n] with the coefficient b now only requires selection of +b or b in a multiplexer, depending on the sign of xd[n] (Fig. 5.4(b)). − [LRJ94] and subsequent publications focus on the facts that this Σ∆-attenuator saves chip area and delivers an oversampled Σ∆M-bitstream from which various analog and digital output signals can be derived. While this is certainly true, the main benefit of the Σ∆-attenuator is that it avoids truncation or rounding, enabling stable oscillation in the first place: It processes the result of the multiplication by a (= bit shifter) with full word length, its output has the word length of coefficient b. The sampling rates at both input and output of the Σ∆M are the

Christian Münker March 10, 2010 5.2. Digital Resonator with Low-Pass Σ∆-Modulation 109

b N M M+N x[n] b x[n] M x N Bit Multiplier

M x 1 Bit Multiplier x[n] M xd[n] b x[n] SDM LPF

N fs/2 b fs/2 (a) N x 1 Bit Multiplier x[n] xd[n] b x[n] SDM LPF N b xd[n]

x[n] −b 0 b x[n] SDM LPF +b 1 N N Bit 2:1 Multiplexor (b)

Figure 5.4.: Σ∆M attenuator, principle (a) and MUX implementation (b) same, there is no decimation involved. The two integrators in the loop limit the signal bandwidth and attenuate the quantization noise.

Proving the stability of the oscillator described above is not trivial: The signal transfer function of the Σ∆M has to have exactly unity gain and a latency of one clock sample, otherwise the oscillation condition is violated, leading to saturation or quenching of the oscillation. Many publications describing this kind of oscillator only rely on empirical observations; [Zie96] proves rigorously that a stable oscillation can be achieved with an oscillator building upon a 2nd order Σ∆M.

For this work, additional VHDL simulations have been performed to verify the

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 110 5. Test Tone Generation

xa [n] digital xda [n] SDM −α LDI a a = 2 z−1 z−1 MUX LDI b 0 +b xb [n] 1 −b

x[n] +1 xd[n] z−1 − − −1 Quantizer z−1

Figure 5.5.: LDI oscillator using Σ∆M attenuator amplitude stability over a period of several 100 ms.

5.2.3. Multi-Tone Signal Generation

Multi-tone signals can be generated by adding the signals of several sine generators, increasing the hardware complexity in a linear way with the number of tones. A more economic approach is using time division multiplexing for sharing the oscillator hardware. The price for generating L tones is a reduction of the effective sampling rate to fS,eff = fS/L; each register has to be replaced by a chain of L registers to store the independent state variables for each time slot (= phase). During the L different phases, the multiplexer selects the corresponding pair of coefficients bi, bi to implement the L different multiplication factors. At − the outputs xb[n] and xda[n], the L different tones are contained in the L phases of the signal. Subsequent low-pass filtering removes the frequency component around fS/L and leaves the sum of the baseband component of all tones. This modification requires only four additional registers per tone (Fig. 5.6) [LRJ94] in the Σ∆M and the oscillator itself. The adders and the bit shifter are shared among the signals saving approx. 50% chip area compared to individual tone generation.

The comparison of Fig. 5.7 and Fig. 5.8 conﬁrms that the inband spectra ( f < 100 kHz) of parallel output and SDM bit stream are essentially the same. Erro- neously, both spectra have been normalized with the FSR of the parallel output,

Christian Münker March 10, 2010 5.2. Digital Resonator with Low-Pass Σ∆-Modulation 111

xa [n] digital xda [n] SDM z−1 z−1 −α f /2 a = 2 s

z−1 z−1 +b MUX 00 1 01 −b1 10 +b 2 11 −b2

x[n] +1 xd[n] z−1 z−1 − − −1 Quantizer z−1 z−1 2 k

Figure 5.6.: Two-tone LDI oscillator using Σ∆M attenuator

a = 2−4 −10 1

b = 0.012634 => f = 55.9 kHz 1 1 −20

b = 0.12201 => f = 173.7 kHz 2 2 −30

−40

−50 > 60 dB SFDR (Inband) stim S (dB / Hz, Spurs) −60

−70

−80

−90

−100 4 5 6 10 10 10 Frequency (Hz)

Figure 5.7.: Spectrum of two-tone signal (parallel output) ( fS = 26 MHz)

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 112 5. Test Tone Generation

−50

a = 2−4 −60 1

b = 0.012634 => f = 55.9 kHz 1 1 −70

b = 0.12201 => f = 173.7 kHz 2 2 −80

−90

−100 40dB/dec → stim

S (dB / Hz, Spurs) −110 > 60 dB SFDR (Inband)

−120

−130

−140

−150 4 5 6 7 10 10 10 10 Frequency (Hz)

Figure 5.8.: Spectrum of two-tone signal (SDM bit stream) ( fS = 26 MHz) which explains the difference in displayed output levels. The spurious lines are harmonic and intermodulation distortions created by quantization.

5.2.4. Quantization Noise

The quantization noise of the Σ∆M limits the useful signal bandwidth B of the oversampled oscillator. The achievable signal-to-noise ratio SNR depending on the effective oversampling ratio OSReff = fS,eff /2B is [LRJ94]

π2 SNR = OSR5/2 . (5.2.7) √60 eff

The effective sampling rate of a two-tone generator (L = 2) running with a sampling frequency of fS = 26 MHz is fS,eff = 13 MHz. The PLL under test has a nominal loop bandwidth of 100 kHz, resulting SNR for different bandwidth values is given in Tab. 5.1.

Christian Münker March 10, 2010 5.3. Upconversion in Σ∆PLL 113

BW [kHz] 50 100 150 200 300 400

OSReff 130 65 43.3 32.5 21.7 16.3

SNR [dB] 108 93 84 78 69 63

Table 5.1.: SNR of two-tone generator depending on bandwidth BW

5.3. Upconversion in Σ∆PLL

In the MADBIST concept, the digital multi-tone signal had to be converted and low-pass filtered to obtain an analog test signal for the ADC. This auxiliary test DAC1 needs to have a performance that is superior to the ADC under test, requiring precision analog techniques. This is true even for oversampled single-bit Σ∆-DACs, where finite slew-rate, mismatch of rising and falling edge or ringing deteriorate the analog signal [TR96]. In contrast, the digital modulation input of the Σ∆PLL offers a very efficient way to apply a digital phase / frequency correction [MMNV04] or test tones to the PLL (Fig. 5.9): No additional filter is needed to reconstruct the sine tones from the oversampled data stream of the sine generator due to the low-pass characteristic of the PLL.

The output frequency fout of a fractional-N PLL with a reference frequency fre f and a division ratio N = NI +NF , consisting of integer part NI and fractional part wf NF = FRAC/2 , is given by

FRAC f = f N + = Nf (5.3.1) out re f I 2wf re f where wf is the word length of the fractional accumulator and FRAC is the fractional word. The PLL is frequency-modulated in the digital domain by adding modulation data D[n] to the fractional word. The modulation data is low-pass ﬁl- tered by the closed loop transfer function T(ω) of the PLL [GKM+03]. Within the loop bandwidth, G(s) 1 and the digital data directly affects the PLL frequency: | | ≈

FRAC + D[n] D[n] fout (n) fre f NI + = fre f N + (5.3.2) ≈ 2wf 2wf 1Not to be confused with functional DACs on-chip which can be tested against the veriﬁed ADC.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 114 5. Test Tone Generation

RF out PFD f Reference Frequency Loop Filter VCO

÷N / N+1

1 0 dig Data [SDM]

f 0 digital TX Filter 1 SDM

TE Carrier Freq. [SDM] Word

Dig. Multitone Additional Generator BIST Block

Figure 5.9.: Fractional-N modulator with test tone generation

When D[n] is a digital sine wave with frequency fm and amplitudem ˆ , a (normalized) peak PLL frequency deviation ∆ f resp. y is created of

c b ∆ ∆ mˆ fre f mˆ f f = wf 1 = wf fre f and y = (5.3.3) 2 − 2 2 f0 c wf 1 c form ˆ < 2 − . This corresponds to a frequency modulationb index β f of

∆ β f f0 mˆ fre f f = = y = wf . (5.3.4) fm fm 2 fm c Fig. 5.10 shows the simulated phaseb spectrum of a PLL, modulated by a two- tone signal ( fm1 = 51 kHz and fm2 = 130 kHz). The phase deviation due to a constant frequency drops with 20 dB/dec. Tones outside the loop bandwidth of 100 kHz are attenuated additionally by the loop bandwidth. The tone outside the loop bandwidth appears attenuated by ∆Sφ 12 dB. The conversion Sy Sφ accounts for 8 dB, the other 4 dB are due to≈ the loop attenuation which→ is the parameter of interest. Obviously, an FM discriminator that delivers Sy directly would be a better choice for measuring the loop bandwidth.

A single-tone modulation of the RF carrier at f0 = 3.812 GHz with fm = 67.7 kHz, wf = 23,m ˆ = 45800 and fre f = 26 MHz produces a peak (normalized) frequency deviation of ∆ f = 142 kHz resp. y = 3.72 10 5 85.6 dB. This · − ≡ − c b Christian Münker March 10, 2010 5.3. Upconversion in Σ∆PLL 115

20 ∆ S φ 10

−10

−20 φ −30

20 log |S | −40

−50

−60 Samples: 20000499 Avg. Freq. = 4.0001e+09Hz −70 Max: 23.7 dB at 50799.9 Hz RBW = 600.0 Hz (27.8 dB Hz) −80 4 5 6 10 10 10 Offset Frequency from Carrier (Hz)

Figure 5.10.: Simulated phase spectrum of two-tone modulated PLL

corresponds to an FM index β f = 2.1 = φ that is identical to the peak phase 2 deviation, giving Sφ ( fm) = φ /2 = 2.2 +3.4 dB. ≡ b The small angle approximation is no longer valid for such a large phase deviation; relative carrier and sidebandb amplitudes in the amplitude spectrum have to be calculated via (2.2.13):

a0 = J0(2.1) = 0.1666 15.6dB ≡ − a1 = J1(2.1) = 0.5683 4.9dB ≡ − a2 = J2(2.1) = 0.3746 8.5dB ≡ − Most conventional spectrum analyzers cannot demodulate FM signals, display- ing the amplitude spectrum S( f ) as in Fig. 5.11 from which information about the modulation signal can only be extracted with difﬁculty. As the PLL output is not routed to a pin, the RF signal had to be tapped off by inductive coupling with a "sniffer" coil to the VCO coil inside the chip which accounts for the attenuation of 30 dB. ≈ In contrast, the built-in FM discriminator gives the frequency deviation spectrum in Fig. 7.13 resp. Fig. 7.14 for a two-tone spectrum.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 116 5. Test Tone Generation

* RBW 5 kHz Marker 1 [T1 ] VBW 20 kHz −76.26 dBm Ref −20 dBm * Att 10 dB SWT 40 ms 3.812195513 GHz

−20

A −30

1 AP CLRWR −40

−50

−60

−70 1

−80

−90

−100

−110

−120 Center 3.8122787 GHz 100 kHz/ Span 1 MHz

Dat e: 16.MAR.2007 13:59:55

Figure 5.11.: Single-tone modulation (measured with spectrum analyzer)

All simulations in this chapter were performed with a standard VHDL simulator, using the methodology described in Sec. 4.5.

Christian Münker March 10, 2010 Wichtig ist, was hinten raus kommt. H. Kohl 6

On-Chip PLL Response Analysis

On-chip response analysis in the frequency domain is developed as the second part of a SP-BIST. After an overview of conventional, swept-tuned spectrum analysis techniques, a robust sigma-delta frequency discriminator (Σ∆FD) is presented as an alternative technique for demodulation and digitization. The Σ∆-modulated bit stream of the Σ∆FD is decimated and filtered with a digital narrowband filter, based on digital resonators. It is very robust against quantization and coefficient truncation errors and requires only one parameter to tune the center frequency. The amplitude of the filtered frequency band is estimated with a digital envelope detector.

6.1. Spectrum Analysis Overview

6.1.1. Direct Spectrum Analysis

As shown in Sec. 2.3.2, phase noise can be measured by selecting a single sideband, converting phase to voltage that is measured in the amplitude domain. In practical implementations, the filtering is performed at an intermediate frequency to relax the filter requirements. In the lab, this direct spectrum analysis is often 118 6. On-Chip PLL Response Analysis performed with a spectrum analyzer. Fig. 6.1 shows a typical analog implementation of a swept-tuned, superheterodyne spectrum analyzer [Agi06] (simplified representation). The RF input frequency range of interest is mixed down to a fixed intermediate frequency (IF) in several stages by sweeping the first local oscillator frequency.

3 GHz IF = 3.6214 GHz IF = 321.4 MHz IF = 21.4 MHz Log. Amp.

RF in

Swept LO IF = 3 MHz 3.62 GHz BW = RBW Detector

... Envelope 6.52 GHz LO2 LO3 LO4 3.3 GHz 300 MHz 18.4 MHz Video Filter

Display Sweep Generator

Figure 6.1.: Principle of analog swept spectrum analyzer [Lil05]

A band-pass filter with fixed center frequency and selectable bandwidth filters out the frequency of interest, the frequency axis of the display is swept synchronously with the first LO to plot amplitude values at the corresponding frequency points (Fig. 6.2). The narrowband output signal of the band-pass is then demodulated by an envelope detector.

With the advent of fast, high resolution ADCs in the 1970s, digital signal processing (DSP) started to replace more and more analog signal conditioning in spectrum analyzers, enabling faster sweep times and higher dynamics.

Envelope and Signal Detection

Analog swept-spectrum analyzers demodulate the intermediate frequency signal for the video display by envelope detection. In its simplest analog form, this is achieved with a resistively loaded diode and a low-pass ﬁlter (Fig. 6.3) whose output only follows the average of the signal envelope but not its instantaneous value.

Christian Münker March 10, 2010 6.1. Spectrum Analysis Overview 119 | (dB / Hz) φ |S

f Frequency (Hz) IF

Figure 6.2.: Swept-tuned spectrum analysis: The input signal is converted with a variable LO frequency and analyzed with a ﬁxed band-pass

IF Signal Demodulated Signal

Figure 6.3.: Envelope detector

Video Filtering

The video ﬁlter in Fig. 6.1 smooths the (logarithmic) PSD data for the display when the video bandwidth is smaller than the resolution bandwidth. A very similar effect can be achieved by averaging several measurements (trace averaging) which is preferable for a BIST application as it can be performed off-chip in software.

The advantages and disadvantages of a conventional spectrum analyzer for phase noise measurements are:

+ Available in most labs

- AM and PM cannot be distinguished

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 120 6. On-Chip PLL Response Analysis

- Resolution limited close to the carrier due to drift between device and spectrum analyzer frequency - LO phase noise limits sensitivity

6.1.2. Indirect Measurement of Angle Modulation

High resolution phase noise measurements are often performed indirectly by demodulating the signal. This can be performed by a phase detector that converts phase ﬂuctuations to amplitude ﬂuctuations. Hence, the PSD of the phase detector output voltage is proportional to the phase instability. The most common implementation is a mixer operating in quadrature (both inputs at same frequency but phase shifted by ∆φ = π/2) (Fig. 6.4). The second input can be a copy of the signal to be measured (self-referenced measurement) or be provided by a PLL to maintain quadrature.

v(t) ∝ sin(∆φ(t)) ∆φ(t) for ∆φ(t) < 0.1 rad (6.1.1) ≈ + Highest dynamic range - Tunable resolution ﬁlter required - Delay difference between both paths limits the - Sensitive against frequency difference between both paths (drift)

π/4

s(t) Kφ ∆φ(t) LPF

Figure 6.4.: Phase detector phase noise measurement

Introducing a delay ∆T in one path of Fig. 6.5 creates a linear phase shift with offset frequency fm of δφ ∝ 2π fm∆T. Hence, frequency ﬂuctuations are converted to phase ﬂuctuations that can be measured with a phase detector as before. + More robust against frequency difference between both path

- Low sensitivity at low offset frequencies fm

Christian Münker March 10, 2010 6.2. FM Demodulation Using Σ∆ Frequency Discriminator 121

∆T PSfrag s(t) Kf ∆ f (t) LPF

Figure 6.5.: Frequency discriminator based phase noise measurement

- Resolution ﬁlter needs to be tunable The latter architecture has been used for on-chip phase noise measurement [VGKB+07, KBK07] with excellent results, however, for this work the chip area for the analog components is far too large. An architecture that avoids the tunable delay line and the high-performance analog mixer is described in Sec. 6.2.

6.2. FM Demodulation Using Σ∆ Frequency Discriminator

6.2.1. Overview of FM Demodulation

Demodulating and digitizing of the frequency information has to be performed under the same restrictions as outlined in the motivation: Little area overhead • Reusability for new products and technologies • Robustness, i.e. mainly digital implementation • Autonomous operation, i.e. requiring no functions from other blocks • The spectrum analyzer architectures described in Sec. 6.1 are "very analog" and complex, requiring large area implementations [VGKB+07, KBK07]. Therefore, a different approach is needed for extracting and digitizing the phase / frequency modulation information from the PLL signal without analog downconversion. On the other hand, the output of a PLL used for frequency multiplication is a narrowband RF signal with a constant, nearly rail-to-rail amplitude. Such a signal can be processed with digital circuits, requiring no precision analog components.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 122 6. On-Chip PLL Response Analysis

Subsampling

Subsampling or downsampling (Sec. 2.5.4) is a well known technique in digital multirate systems or high-speed ADCs for processing a high-frequency, narrow- bandwidth signal in a lower Nyquist zone (Sec. 2.5.4). As RF signals in most transmission standards are narrowband signals, subsampling recently has received a lot of attention for RF downconversion. No analog mixer is required and the concept is seemingly digital, however, practical implementations of "digital" subsampling receivers battle with mainly analog problems:

Aliasing: The frequency bands of all Nyquist zones are mapped onto the baseband which can create huge aliasing problems and SNR reduction when operating in a high order Nyquist zone i.e. with a large ratio between bandwidth and sampling frequency.

Bandwidth: The bandwidth of the sampler needs to exceed the highest signal frequency independently of the sampling frequency.

Jitter: The sampling clock needs to be exceedingly stable as jitter introduced at that point of the signal chain is referred to the RF period, not the sampling period. Consequently, the subsampling receiver presented in [MLS+04] operating directly in the RF domain is a complex analog circuit, consisting of a cascade of ﬁlters, subsamplers and a precision ADC which is unsuitable for a BIST implementation.

PLL FM Discriminator

PLLs are frequently used for FM demodulation by tapping off the control voltage of the VCO but obviously it makes no sense to implement a second PLL on-chip for testing purposes with a performance superior to the circuit-under-test.

Digital FM Discriminator

Digital FM demodulation of high-level signals is possible by only evaluating the position of the zero crossings. This can be performed by some sort of early- late detection against a reference signal. In this work, a sigma-delta frequency discriminator (Σ∆FD), a fully digital circuit, is used for FM demodulation.

Christian Münker March 10, 2010 6.2. FM Demodulation Using Σ∆ Frequency Discriminator 123

The period deviations could also be measured directly with a time-to-digital converter (TDC) (Sec. 1.2.7). However, TDCs are large precision analog blocks that are ill suited for BIST purposes. In a digital PLL where a TDC is used for phase detection, the availability of a digital measure for the phase error offers new self-test options with very little overhead [EBSB07, SP09].

Σ∆ Q Accumulator s[n] +1 sd[n] z−1 − −1 Integration ∆ Q Subtraction Quantization

(a) First order sigma-delta modulator (Σ∆M) Σ∆ Q Dual D−FF y[n] Modulus Divider φ D ref f i(t) ÷N / N+1 φ N mod div Channel Word (Integer Part) Integration and Phase Subtraction Quantization

(b) First order sigma-delta frequency discriminator (Σ∆FD)

Figure 6.6.: Comparison of Σ∆M and Σ∆FD

6.2.2. Principle of First Order Σ∆FD

In analogy to the conventional Σ∆M in Fig. 6.6(a) (Sec. 2.6), a sigma-delta frequency discriminator (Σ∆FD, Fig. 6.6(b)) generates a coarsely quantized, noise shaped, oversampled approximation to the instantaneous input frequency fi(t). It is capable of replacing both the demodulator and the ADC, making it an ideal candidate for robust BIST applications. The principle of Σ∆FD is closely related to a fractional-N synthesizer [BC94] where a fine granularity of output frequencies is achieved by alternating the division ratio between two or more values. When the divider values are switched sufficiently fast, most of the switching activity is suppressed by the loop filter and the output frequency is proportional to the average division ratio N. This works

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 124 6. On-Chip PLL Response Analysis particularly well when the divider sequence is coded as a Σ∆M data stream where the switching activity is concentrated at high frequencies (Sec. 2.6).

D−FF ÷N / N+1 fdiv D N mod f RF out N.F fref PFD Filter VCO Frequency Word SDM Mod in (a)

RF in ÷N / N+1 fdiv D−FF Dem. N mod D f Out fref N N.F Filter Frequency Word (b)

Figure 6.7.: Principle of Σ∆FD (b), derived from Σ∆-Frac-N-PLL (a)

If the VCO is replaced by an input signal with a frequency fi,0(t) in the range

Nfre f < fi,0(t) < (N + 1) fre f , (6.2.1) a divider sequence can be constructed that minimizes the phase deviation between reference signal and divided input signal and thus produces an average divided frequency that is equal to the reference frequency,

fi,0(t)/N = fdiv[i] = fre f and φi,div(t) = φdiv(t) + 2π fre f (6.2.2)

When the divided input frequency is higher than the reference frequency, the division ratio has to be set to (N + 1) until the reference phase overtakes the divided RF phase. At that point,÷ the division ratio is set back to N until the divided RF phase leads again (Fig. 6.8). In other words: the phase of÷ the divider output brackets the reference phase (Fig. 6.9) rather than locking to it. A suitable divider sequence is provided by a D-Flip-Flop (D-FF) which samples the divided RF phase at each rising edge of the reference clock (Fig. 6.6(b)), providing a binary quantization y[i] of the divider phase deviation φdiv = φi div , − φi,re f (bang-bang or early-late phase detector). Starting with perfectly aligned phases at t = 0 and a division ratio of N, the

Christian Münker March 10, 2010 6.2. FM Demodulation Using Σ∆ Frequency Discriminator 125 divider phase deviation after one reference period is

φi,0(Tre f ) φdiv(Tre f ) = φi div(Tre f ) φi re f (Tre f ) = 2π , − , N − Nφi,re f (Tre f ) N N 2π = 2π = 2π − < . (6.2.3) N − N N A similar result is obtained easily for a division ratio of N +1, deﬁning the range of the phase deviation at the divider output: 2π 2π < φdiv(t) < (6.2.4) − N + 1 N For input frequencies outside the range given above, the phase deviation becomes larger than 2π/N and cycles are lost, overloading the Σ∆FD. A PLL signal generated from the same reference frequency fre f has a bandwidth B fre f for stability reasons, fulﬁlling (6.2.1) in most cases. The notable exception≪ is when the average input frequency f0 is near one of the integer frequencies and additional frequency modulation pushes the instantaneous frequencies outside the range.

N = 4.25

N = 4 N + 1 = 5 N = 4 N = 4 N = 4 N + 1 = 5

t div,1 tdiv,k DIV Tdiv,1 Tdiv,2 ∆ ∆ tk−1 tk REF φ [i] div

y[i] t/Tref 01 2 k

Figure 6.8.: Signals in ﬁrst order Σ∆FD: Transient view

Modulation frequency has to be less than fre f /2 to avoid aliasing. As the multi- modulus divider averages over N resp. N + 1 input cycles, it acts as an anti- aliasing ﬁlter on the frequency deviation. The equivalence to conventional Σ∆M is seen clearly by regarding For each reference cycle where the division ratio is set to (N +1) instead • of N, one RF cycle is swallowed from the output of the÷ divider, subtracting÷ a phase of 2π/N.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 126 6. On-Chip PLL Response Analysis

φ / 2π i φ φ i,div [i] = i,0 / N[i]

4 φ i,ref φ i,0 / N 3 φ i,0 / (N+1)

2 φ div [i] = φ − φ 1 i,ref i,div [i]

1 2 3 4 t / Tref

N+1 N N+1 N N+1 1 01 0 1 Binary phase error approximation y[i]

Figure 6.9.: Signals in ﬁrst order Σ∆FD: Phase view

As phase is the integral of frequency, this corresponds to a perfect integra- • tion of the frequency error.

6.2.3. Signal-to-Noise Ratio of Σ∆FD

In this section, a linearized model for the Σ∆FD is developed to calculate the signal-to-quantization noise ratio (SQNR) [Bax99, p. 39 ff.,p. 107 ff., 146 ff.], [BC94]. It will also be shown that the output signal of the Σ∆FD is a coarsely quantized approximation to the relative frequency deviation y(t) which has been deﬁned in (2.2.4) as

fi(t) f0 fi(t) ∆ f (t) 1 dφ(t) y(t) := − = 1 = = . f0 f0 − f0 2π f0 dt

The average deviation ∆t0[i] from the ideal period T0 is a good approximation to the frequency deviation y[i] y(t) during that cycle: ≈ f (t) f [i] T T y(t) = i 1 y[i] = 0 1 = 0 1 = 0 1 f0 − ≈ f0 − T0[i] − T0 + ∆t0[i] − 1 ∆t [i] = 1 0 (6.2.5) 1 + ∆t0[i]/T0 − ≈ − T0

Christian Münker March 10, 2010 6.2. FM Demodulation Using Σ∆ Frequency Discriminator 127

In the derivation of (6.2.5), two approximations have been made:

The duration of the i-th divider cycle Tdiv[i] at the output of the MMD • is equal to the accumulated RF signal periods T0, j of the previous N[i] RF cycles (approx. Tre f ). Consequently, only the average period T0[i] of these accumulated cycles can be measured instead of fi,0(t) or T0, j. This is equivalent to a low-pass ﬁltering of the period / frequency deviation with sincπ f Tre f .

∑N[i] Tdiv[i] j=1 T0, j Tre f T0[i] = = = T0 + ∆t0[i] with T0 = (6.2.6) N[i] N[i] N

Truncating the series expansion 1/(1 + x) = 1 x + x2 ... after the ﬁrst • 2 − −2 term introduces a nonlinearity ε x = ∆t0[i]/T0 . For narrowband modulation, x 1, and the nonlinearity≈ − can− be neglected. ≪ First, a linearized model is developed for the multi-modulus divider as the central component: The m-th rising edge of the divider output is triggered by the k-th rising edge of the RF signal at the time tdiv[m]. The modulus input b[i] 0;1 and the integer division ratio N set the division ratio N[i] = N + b[i] of the∈ {i-th divider} cycle:

m k m N[i] m tdiv[m] = ∑ Tdiv[i] = ∑ T0, j = ∑ ∑ T0, j = ∑ N[i]T0[i] i=1 j=1 i=1 j=1 i=1

N(z)T0(z) N(z) tdiv(z) = = T0 + ∆t0(z) (6.2.7) ◦−• 1 z 1 1 z 1 − − − − (6.2.7) is the base for the MMD model in (6.10(b)).

T (z) = T + ∆t (z) T 0 0 0 0,j ÷N / N+1 t div [m] N mod 1 N tdiv (z) N(z) 1−z −1 N + b[i] b(z) (a) (b)

Figure 6.10.: Multi-modulus divider (a) and DT model (b)

As it has been assumed that the average period of the divided signal Tdiv[i] is made equal to the reference period Tre f in a feedback loop and as N N[i] < 1, the −

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 128 6. On-Chip PLL Response Analysis difference between the average division ratio N (m ∞) and its approximation over m divider cycles is bounded by ε˜[m] < 1/m: → | |

1 m 1 m NT0 = Tdiv[i] = Tre f with N = lim ∑ N[i] = ∑ N[i] + ε˜[m] (6.2.8) m ∞ m m → i=1 i=1

The instantaneous output phase of the divider φi,div[m], referred to the reference period, is calculated from (6.2.7) and (6.2.8):

m m 2πtdiv[m] 2π 2π ∆t0[i] φi div[m] = = ∑ N[i] T0 + ∆t0[i] = ∑ N[i] 1 + , T NT N T re f 0 i=1 i=1 0 m 2π ∆t0[i] 2πm ε˜[m] 2π = 2πm + ε[m] + ∑ N[i] with ε[m] = | | < N i=1 T0 | | N N ∆ φ 2π N(z) t0(z) i,div(z) = 1 1 + (6.2.9) ◦−• N 1 z T0 − − 2π ∆t (z) N N z 0 (6.2.10) 1 + ( ) ≈ N(1 z ) T0 − −

(6.2.10) is the base for the multi-modulus divider (MMD) model in Fig. 6.11.

T + ∆t (z) 0 0 1 / T0

1 2 π N φ (z) N(z) 1−z −1 N i,div b(z)

Figure 6.11.: Linearized model for multi-modulus divider phase

Next, the D-FF with the reference frequency input is added to the model to complete the Σ∆FD. The instantaneous phase of the reference frequency after m reference cycles is φi,re f [m] = 2πm. The output of the D-FF is a coarse quantization of the difference between instantaneous reference and divider phase with ∆Q = 2π/N: When the divided phase is early, the output goes high, otherwise it is low. Using (6.2.2), the difference of both instantaneous phases is the divider

Christian Münker March 10, 2010 6.2. FM Demodulation Using Σ∆ Frequency Discriminator 129

phase deviation φdiv[m]:

m 2π ∆t0[m] φdiv[m] = φi,div[m] φi,re f [m] = ∑ N[i] (6.2.11) − N i=1 T0 ◦−• ∆ φ φ φ 2π N(z) t0(z) 2π div(z) = i,div(z) i,re f (z) = 1 1 + 1 − N 1 z T0 − 1 z − − − − 2π 1 ∆t0(z) = 1 N(z) 1 + N N 1 z T0 − − − N(z) 2π ∆t0(z) 2π = 1 1 + 1 (6.2.12) N 1 z T0 − 1 z − − − −

The effect of the quantizer is modeled by adding the quantization noise en = ∆Q/√12 = π/N√3 and one delay, yielding b(z). The loop is closed by setting N(z) = N + b(z):

1 ∆ 1 φ 1 N + b(z) 2πz− t0(z) 2πz− 1 b(z) = ( div(z) + en)z− = 1 1 + 1 + enz− N 1 z T0 − 1 z − − − − 1 1 1 1 ( ) 2πz− − N 2πz− ( ) 2πz− 1 = 1 • • + enz− − N 1 z 1 N 1 z 1 − 1 z 1 − − − − − − 1 1 1 N 1 z− 2πz− N 1 z− = − ( ) 1 + en − N (1 z 1) 2π( )z 1 1 z 1 N • − 2π − − − − − − • 1 1 N 1 z− = ( ) 1 + en − 1 z 1 ( ) N • − 2π − − 1 • 2πz− − N 1 1 1 1 z− 1 N + N ( )− N ( )− en − for z− 1 ≈ − • − • 2π ≈ 1 ∆t0(z) 1 z− ∆t0(z) N N/N + 1 en − for 1 ≈ − − T − 2π T ≪ 0 0 1 N N 1 z− N y(z) + − en − (6.2.13) ≈ N − 2π (6.2.13) shows that the output b[n] of the Σ∆FD is an approximation to the frequency deviation y(t), scaled with N. The DC-component of y(t) is the fractional word, i.e. the relative deviation from the integer channel. Quantization noise is 1 high-pass shaped with 1 z− . (6.2.12) and (6.2.13) are the base for Fig. 6.12. The high-pass characteristic− of 20 dB/dec can be seen in Fig. 6.13.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 130 6. On-Chip PLL Response Analysis

T + ∆t (z) 0 0 1 / T0 T 1 / Tref e ref 1 n

1 2π z−1 b(z) N N 1−z −1

Figure 6.12.: 1st order Σ∆FD model

The PSD SY of a signal with sinusoidal frequency modulation and peak frequency deviation y is 2 y2 ∆ f b Sy( fm) = = . 2 √2 f0 ! b c At the output of the first order Σ∆FD, frequency deviation is scaled with N, resulting in a signal power of 2 2 ∆ f Sy,Σ∆FD( fm) = N . (6.2.14) √2 f0 ! c The noise power of a general first order Σ∆-modulator is given by (2.6.6): 2 2 2 3 ∆ 3/2 π en 2Bm π Q 2Bm Nq(Bm fS/2) = ≪ ≈ 3 f 6 f S S ! Σ∆ 2 σ 2 ∆2 2 2 For the case of the first order FD, en = e = Q/12 = π /3N , noise is scaled with (N/2π)2, resulting in 2 2 3 2 2 3/2 π 2Bm π N π 2Bm Nq Σ∆FD(Bm fS/2) = . , ≪ ≈ 3 f · 2 · 4π2 6 f S 3N S ! (6.2.15) The ratio between modulation bandwidth Bm and sampling frequency fS, the oversampling ratio OSR, determines the SQNR of the Σ∆FD. In analogy to a conventional Σ∆M (2.6.6), the SQNR of a first order Σ∆FD can be calculated from (6.2.14) and (6.2.15):

N∆ f π 2B 3/2 SQNR = 20log 20log m (6.2.16) √2 f0 !− 6 fS ! c S NQ = | 48.3dB{z ( 69} .1dB| ) = 20{z.8dB} (6.2.17) − − −

Christian Münker March 10, 2010 6.2. FM Demodulation Using Σ∆ Frequency Discriminator 131

using the numbers from the example in Sec. 5.3: f0 = 3.812 GHz and fS = fre f = 26 MHz result in N = 146.62. The peak (normalized) frequency deviation is 5 ∆ f = 142 kHz resp. y = 3.72 10− 85.6 dB. A bandwidth of Bm = 100 kHz has been assumed. This low· SQNR≡ −is partially due to the relatively low fre- ∆ quencyc deviation fbin comparison to the DC offset (N N/N). Hence, a precise measurement of the frequency deviation of single tones− necessitates a narrow bandwidth.

−40

Samples: 145600 RBW = 1071.4 Hz (30.3 dB) −60 y

−80 20 log |S |

−100

−120 3 4 5 6 7 10 10 10 10 10 Frequency (Hz)

Figure 6.13.: Simulated two-tone spectrum at Σ∆FD output

−40

−60 Samples: 145600 y Freq. Points: 18201 RBW = 1071.4 Hz (30.3 dB) −80 20 log |S |

−100

−120 4 5 10 Frequency (Hz) 10

Figure 6.14.: Simulated two-tone spectrum at Σ∆FD output (zoomed in)

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 132 6. On-Chip PLL Response Analysis

The zoomed-in spectrum in Fig. 6.14 reveals some spurious lines between the two modulated tones, generated by the ﬁrst order Σ∆FD.

Spurious Tones of First Order Σ∆FD

As there is only one integrator in the loop (Fig. 6.12), the first order Σ∆FD shows the same spurious tones as a first order Σ∆M (Sec. 2.6.3). These tones are due to insufficient decorrelation of signal and quantization noise. In Σ∆FDs, especially unmodulated signals (constant input frequency) can produce strong spurious lines. Modulation with e.g. a two-tone signal improves the decorrelation and hence the spurious performance.

6.2.4. Second Order Σ∆FD

Increasing the order of noise shaping reduces the spurious tones and improves the signal-to-noise ratio by shifting more quantization noise to higher frequencies. Unfortunately, the order of a Σ∆FD cannot be increased as simply as with a Σ∆PLLas the quantization error of the ﬁrst stage is given by the phase difference between reference and divided RF signal that is smaller than an average RF cycle. It can either be integrated in an analog fashion with e.g. a charge pump or digitally by oversampling the ﬁrst.

Figure 6.15.: 2nd order Σ∆FD (simpliﬁed) [BCR96]

[BC94] presents a second order multi-loop Σ∆FD architecture similar to Fig. 2.20 using two charge pumps and an analog comparator. Mismatch between charge pumps in the multi-loop architecture can be avoided by an equivalent second order single-loop Σ∆FD (Fig. 6.15) similar to Fig. 2.22 [Bax99]. However, both approaches are not attractive for BIST implementations as they require large area analog blocks.

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 133

The use of a multibit quantizer would also improve the SQNR. For this approach, the simple D-FF has to be replaced by multi-phase phase detector [RS01]. This requires multiple phases of the reference clock which is the main drawback of this approach. The multibit "DAC" could be implemented with a multi-modulus divider.

6.3. Spectral Analysis of Baseband Signal

6.3.1. Overview

In the last section, it has been shown that the output of the Σ∆FD is an oversampled, Σ∆-modulated approximation to the frequency deviation of the RF carrier. In contrast to a swept spectrum analyzer (Fig. 6.1 and Fig. 6.2), the demodulated spectrum is fixed, starting at DC. As a consequence, the resolution filter now has to be swept across the baseband (swept-filter spectrum analyzer, Fig. 6.16). One practical difficulty that has to be solved is that the bandwidth of the filter has to remain constant over the tuning range. [TR95a] discusses the quality of three different methods for achieving this target: | (dB / Hz) φ |S

Frequency (Hz)

Figure 6.16.: Swept ﬁlter spectrum analysis: A tunable ﬁlter is swept across the baseband spectrum

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 134 6. On-Chip PLL Response Analysis

Fast Fourier Transform (FFT)

While FFT has become the most common method for on-chip spectral analysis, it also requires the most hardware resources by far. More hardware efficient for the calculation of individual spectral components of a discrete-Fourier transform (DFT) is the recursive Goertzel algorithm. It can be implemented and analyzed as a direct-form IIR filter [TGS+09]. The high sensitivity of this filter type to quantization effects requires multipliers with a large word length.

Correlation

The spectral component at a certain frequency in a measured set of data can be found by correlation with a sine wave of the target frequency. This procedure can also be related to the discrete Fourier transform and has been standardized as IEEE Std 1057. The quality of the spectral estimate is identical to a DFT. Unfortunately, the computational effort is also very high.

Narrowband Filtering

Using narrowband ﬁltering, a similar quality of the spectral estimate can be achieved with low hardware complexity. As this is one of the main restrictions in this work, the spectrum will be estimated with the narrowband ﬁltering approach. This approach is especially well suited when only the analysis of a few frequency points is required as in the SP-BIST application.

6.3.2. Filter Topology

The output of the Σ∆FD is fed into the tunable narrowband filter, its center frequency is selected by the ATE or an external PC (Fig. 6.17). A digital envelope detector (Sec. 6.3.5) tracks the amplitude of the frequency band. Slow but computation intensive tasks like linearization, smoothing and logarithmic scaling are performed off-chip. Component variations and area limitations mandate the use of digital filters. Many different architectures for DT filters have been developed in the last decades, first for switched-capacitor (SC) implementations (continuous-valued), later for fully digital implementations (discrete-valued) to implement a desired transfer function H(z). Under the assumption of infinite precision (or at least

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 135

Σ∆FM Discriminator Multirate Envelope PC or ATE BP Filter Detector fRF D ÷N / N+1 |Sy ( f c )| N mod

N fref fc Sweep SP−BIST

t Oversampled BP−filtered Envelope demod. signal demod. signal of BP signal

Figure 6.17.: Principle of on-chip spectral PLL analysis with floating-point arithmetics), these architectures produce identical input- output behavior. However, in most hardware implementations, silicon area and computing power are limited, permitting only fixed-point arithmetics. This is especially true for BIST applications where minimum area overhead is of paramount importance. With fixed-point arithmetics, filter architecture, internal word length and scaling strongly influence the performance: overflow, excessive quantization noise, deviations from the target transfer function or even instability may occur for non- optimum choices [CT06]. While non-recursive filters are inherently stable and relatively insensitive against word length effects, low hardware complexity can only be achieved with recursive filters: The poles in the transfer function enable sharp transitions between pass and stop bands with a much lower filter order than with non-recursive filters which are restricted to all-zero transfer functions. The non-linear phase transfer function of recursive filters can be ignored for applications where only the magnitude transfer function is specified (as in this work). Still, recursive filters have lost a great deal of their popularity which may be due to the available high integration densities, requiring no longer minimum area solutions and to a lack of IIR design skills as the focus in most courses is on non- recursive filters [Lyo06]. This is especially true for more exotic topologies like the resonators-in-a-loop described below which have sunk into near-oblivion. The higher sensitivity of recursive filters to word length effects requires robust filter topologies to achieve good performance even with short word-length of

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 136 6. On-Chip PLL Response Analysis registers (quantization) and coefficients (truncation). This allows reducing the size of the coefficient multipliers which are the largest blocks in a digital filter. Dynamic range is limited by quantization noise on one side and saturation / overflow on the other side. It can be shown that a robust filter design automatically gives a good dynamic range [Fet97]. Tunable filters in BIST / BISC applications mandate a minimum number of tunable coefficients as each coefficient has to be programmed during test and stored on chip. Especially for BISC applications, the computational complexity for calculating the coefficients e.g. from the center frequency of a filter has to be low as well. Most tunable filters use non-recursive structures to guarantee stability while tuning the coefficients. These approaches also require high computational effort for coefficient calculation [SK97, ZB95].

DownsamplingBP Filter Envelope Detector x [n] |A(f ) | i 2 BP CIC 32 CIC 256

fS = 26 MHz fS,R1 = 812.5 kHz fS,R2 = 3.2 kHz

Figure 6.18.: Block diagram of spectral estimation

Signals with a high oversampling rate (ratio of sampling rate to signal bandwidth) like the sigma-delta modulated bitstream of the Σ∆FD in this work can be processed efﬁciently with multirate systems. Fig. 6.18 shows the principle of the multirate spectral estimation developed in this work [MW06]. The band of interest is selected with a narrow, programmable resonator based band-pass ﬁlter running at a reduced sampling rate. The moving average in the envelope detector is calculated at an even further reduced sampling rate.

6.3.3. Downsampling Cascaded-Integrator-Comb Filters

The Σ∆FD bit stream has a high oversampling ratio that would require a high order bandpass filter with precise coefficients when operating at the full sampling rate. Filter specifications can be relaxed by downsampling (Sec. 2.5.4) before doing actual signal processing. The Σ∆M coding of the bit stream concentrates the quantization noise around fS/2, hence, proper low-pass filtering is required before decimation to avoid excessive aliasing. Downsampling Cascaded Integrator-Comb (CIC) filters, are frequently used for anti-alias filtering of oversampled Σ∆M bitstreams before decimation because

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 137

f s f s /R

x[n] y[n] y[n/R]

− − R z−1 z−R z−1 z−R CIC 1 CIC 2 Decimator

Figure 6.19.: 2nd order CIC as anti-aliasing filter of their hardware efficient, multiplier-less architecture (Fig. 6.19). The coarsely quantized Σ∆M bitstream is converted to a wider word length at a lower sampling rate. The actual (single rate) CIC filter consists of N sections of a digital integrator and a comb filter with R unit delays and behaves as a moving average filter, implemented in recursive form. The integrator section generates a pole of order N on the unit circle at z = 1 ( f = 0), the comb filter R zeros of order N, distributed along the unit circle at e j2kπ/R, k = 0...R 1. The filter is only stable because the integrator pole is canceled exactly (requiring− fixed-point arithmetics) by a zero in the comb filter section. Y(z) 1 1 Integrator: HI(z) = = 1 HI( f ) = (6.3.1) X(z) 1 z | | 2sinπ f TS − − R Comb Filter: HC(z) = 1 z− HC( f ) = 2sinπR f TS (6.3.2) − | | | | Combining the transfer functions of integrator (6.3.1) and comb filter (6.3.2) yields the CIC transfer functions HCIC(z) and HCIC( f ) (6.3.3):

R N N 1 z− sinRπ f TS HCIC(z) = − and HCIC( f ) = (6.3.3) 1 z 1 | | sinπ f T − S −

Order N and number of delays R are the only two parameters for controlling the frequency characteristic of a CIC filter. When the number of delays in the comb filter is the same as the decimation ratio (Fig. 6.19), an especially efficient implementation is achieved by swapping decimator and comb filter stages and applying the Noble identity: The resulting structure Fig. 6.20 (also called Hogenauer filter [Hog81]) has the same transfer function as Fig. 6.19 and requires only one delay per comb filter section ([Mey07]). Further reduction of hardware complexity is achieved by replacing one integrator and comb filter by an accumulate-and-dump block (Fig. 6.21). The frequency re-

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 138 6. On-Chip PLL Response Analysis

f f /R x[n] s s y[n/R] − − z−1 z−1 R z−1 z−1 Integrators Decimator Comb Filters

Figure 6.20.: Efficient implementation for second order downsampling CIC filter (Hogenauer filter)

f f /R x[n] s s y[n/R] − −1 R −1 z −1 z RES z Integrator Accumulate & Dump Comb Filter

Figure 6.21.: Second order downsampling CIC ﬁlter with dump and reset sponse of the downsampling CIC ﬁlters in Fig. 6.19 - 6.21 is identical to (6.3.3), but it is usually expressed as a function of the frequency F, normalized w.r.t. the reduced sampling rate at the output (6.3.4):

N sinπF N f R HCIC(F) = πF RsincπF for F = 1 (6.3.4) | | sin ≈ | | fS ≪ R

Some effects of multirate CIC ﬁlters can be seen from (6.3.4): The ﬁlter has a N DC gain of G = R , requiring an output word length WLout :

WLout = N log R +WLin (6.3.5) ⌈ 2 ⌉ The sincN low-pass characteristic introduces a droop at the edge of the passband FC (6.3.6). N HCIC(Fc) sinπFc N | | = πF sincπFc (6.3.6) HCIC(0) Rsin c ≈ | | | | R

This droop is normally compensated in the subsequent ﬁltering stage(s). In this work, compensation is performed off-chip to avoid additional hardware. A more severe restriction is aliasing of signal components around multiples of the reduced sampling frequency, especially for Σ∆M bitstreams as in this application where the quantization noise is concentrated at high frequencies. The nulls

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 139 of the comb ﬁlter at F = k suppress multiples of the reduced sampling frequency, 1 avoiding aliasing back to DC. The comb ﬁlter maxima are at F = k+ 2 , therefore the worst case alias suppression occurs at the passband edges fc k = kfS/R fc , ± resp. Fc,k = k FC with k = 1,2,... (6.3.7) which are all mapped back to Fc by decimation (Fig.± 6.22). ±

−10

−20 −30 (F) | [dB] −40 CIC −50

20 log | H −60 −70 −80 −90 −100 0 0.5 1 1.5 2 2.5 3 3.5 4 F c Normalized Frequency F

Figure 6.22.: Transfer function of downsampling CIC ﬁlter with N = 2 and R = 4. Hatched regions are folded back to F = 0...0.25

N N N πFc πFc HCIC(Fc,k) sin R sinπ(k Fc) sin R = π ± = π (6.3.7) π (k Fc) (k Fc) HCIC(Fc) sin Fc sin ± sin ± | | R R N Fc (6.3.8) ≈ k F c ±

A higher decimation factor increases droop in the passband and aliasing for a constant corner frequency fc but reduces the requirements for subsequent ﬁlter- ing. Tab. 6.1 shows some typical cases. The conﬁguration selected for this work, R = 32, N = 2 has been highlighted, the simulated output spectrum of the Σ∆FD with the overlaid CIC frequency response is shown in Fig. 6.23.

As Σ∆M quantization increases towards fS as well as the alias rejection of a CIC ﬁlter, the order of the CIC ﬁlter should be larger than the order of the Σ∆- modulator. Fig. 6.24 gives a graphical representation of the quantization noise at

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 140 6. On-Chip PLL Response Analysis

Order Rate Gain Passb. Droop (dB) Alias Rejection (dB) 1 1 3 7 R 1 R 1 N R (dB) Fc = 4 8 4 8 2 − 4 2 − 8 1 256 48.2 -0.9 -0.22 9.5 16.9 50.3 56.3

2 16 48.2 -1.8 -0.45 19.0 33.7 52.3 64.4 2 32 60.2 -1.8 -0.45 19.1 33.8 64.4 76.4

3 16 72.2 -2.7 -0.67 28.5 50.6 78.5 96.6 3 32 90.3 -2.7 -0.67 28.6 50.7 96.6 114.7

Table 6.1.: Passband droop and alias rejection of CIC ﬁlters

−40

Samples: 145600 RBW = 1071.4 Hz (30.3 dB) −60 y

−80 20 log |S |

−100

−120 3 4 5 6 7 10 10 10 10 10 Frequency (Hz)

Figure 6.23.: Two-tone spectrum at Σ∆FD output with overlaid CIC frequency response (simulation)

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 141

the output of a CIC - filter versus the oversampling ratio OSR = fS/2 fc = R/2Fc [Can86]. Quantization noise is shown for oversampled PCM (l = 0) and Σ∆M of order l = 1 and l = 2, it is plotted relative to the level of Nyquist PCM with the same quantization step size ∆Q. When the order k of the CIC filter is larger by one than the Σ∆M(k = l +1), total output noise is independent of decimation R for a given OSR (horizontal lines). Lower decimation ratios R decrease the amount of aliasing, but the CIC filter also has a weaker low-pass characteristic. Starting from the intersection of the l-line and the OSR, the output noise is found by following the k = l or k = l + 1 line to the value of the decimation ratio. RMS Noise [dB]

Oversampling Ratio

Figure 6.24.: Σ∆M quantization noise after CIC ﬁltering plotted against the oversampling ratio [Can86]

In this work, the ﬁrst order Σ∆FD (l = 1) delivers a bit stream with a sampling rate of 26 MHz. Only an order of k = 2 was possible for the CIC ﬁlter due to severe area restrictions.

As the signal bandwidth is fc = 200 kHz with special focus on the loop bandwidth of 0...100 kHz for measuring, a decimation factor of R = 32 was chosen, giving an output sampling rate of fS,R = 812.5 kHz. This low ratio between signal bandwidth and sampling rate allowed an especially efﬁcient implementation of the band-pass ﬁlters.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 142 6. On-Chip PLL Response Analysis

−40

−60 Samples: 145600 y Freq. Points: 18201 RBW = 1071.4 Hz (30.3 dB) −80 20 log |S |

−100

(a) −120 4 5 10 10 60

30 Samples: 4476 f Freq. Points: 560 20 Peak Value = 89.64 dB at 0 Hz RBW = 1089.1 Hz (30.4 dB) 10 20 log |S | 0

−10

−20 (b) −30 4 5 10 Frequency (Hz) 10

Figure 6.25.: Simulated two-tone spectrum at Σ∆FD output (a, zoomed in) and at the output of the downsampling CIC ﬁlter (b)

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 143

The spectrum at the output of the downsampling CIC ﬁlter (sampled at fS,R = 812.5kHz) is shown in Fig. 6.25 together with the input spectrum, sampled at fS = 26MHz. As expected, the increasing droop of the CIC ﬁlter can be seen above 200 kHz and some folded back spurious lines. The frequency range of interest up to 200 kHz remains undisturbed.

6.3.4. Narrowband Filtering

As discussed in Sec. 6.3.2, spectral estimation of the decimated bitstream is performed with a tunable narrow band-pass filter where the center frequency is set with few or even a single parameter to facilitate programming. The absolute bandwidth has to stay constant across the frequency range, requiring a special filter topology as most tunable filters have a constant relative bandwidth referred to the center frequency. A similar concept has first been presented in [TR95a] for the BIST of ADCs.

Undamped Resonator

y [n] x [n] 1 z−1 −

k w[n] k f f z−1 y [n] 2

Figure 6.26.: LDI based resonator

The tunable band-pass is implemented with the undamped LDI-based resonator in Fig. 6.26 that has also been used in the multi-tone generator (Sec. 5.1.3). It is placed in the resonator-in-a-loop structure in Fig. 6.27 (Sec. 2.9.3) to obtain a deﬁned ﬁlter characteristic. Its transfer function can be derived using Mason’s rule: 1 1 z− 1 z− H1(z) = − Output y1 (6.3.9) 1 2 k2 z 1 + z 2 − − f − − 1 1 k f z− 1 z− H2(z) = − Output y2 (6.3.10) 1 2 k2 z 1 +z 2 − − f − −

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 144 6. On-Chip PLL Response Analysis

9 2 k f 1 40 200 512 715 1024 · fr [kHz] 0.253 10.1 50.8 135.4 199.9 394.8

Table 6.2.: Resonance frequency for fS,R = 812.5 kHz

The poles of (6.3.9) and (6.3.10) are given by:

2 2 k2 2 k f 4 k2 f − − f 2 4 zp1 2 = 1 r = 1 j k k /4 (6.3.11) , − 2 ± 2 − 2 ± f − f q The resonator poles have a radius of r = 1 (undamped oscillation), as a consequence the resonance frequency Ωr is the same as the pole angle θp:

2 4 2 4 k f k f /4 k f k f /4 Ω = θ = arctan − = arctan − r p q 2 q 1 k f /2 1 k2 + k4/4 − − f f 2 4 q = arcsin k k /4 = 2arcsink f /2 k f for k f < 0.1 (6.3.12) f − f ≈ q using arcsinx = arctan x = 2arctan x and arctanx = 2arctan x . √1 x2 1+√1 x2 1+√1 x2 − − − The absolute resonance frequency fr is calculated with the reduced sampling frequency fS,R = 812.5 kHz. Tab. 6.2 gives some example values.

Ωr fS,R k f k f fS,R fr = fS R = arcsin (6.3.13) 2π , π 2 ≈ 2π π fr 2π fr k f = 2sin (6.3.14) ⇔ fS,R ≈ fS,R

Resonator-in-the-Loop

An additional feedback path stabilizes the undamped resonator in Fig. 6.26 by providing a deﬁned amount of damping kBW . The resulting structure has an approximately constant bandwidth B or quality factor Q depending on the position of the feedback (Fig. 6.27). Its transfer function is derived from (6.3.9) resp. (6.3.10) [PM93]: YBP(z) kBW Hi(z) HBP,i(z) = = (6.3.15) X(z) 1 + kBW Hi(z)

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 145

Constant BW k bw − x[n] ybp1 [n] z−1 − −

k k f f z−1 y bp2 [n]

Constant Q

Figure 6.27.: Resonator based ﬁlter with constant B or constant Q

At the resonance frequency, Hi(z) becomes inﬁnity, the corresponding resonant gain of the band-pass HBP,i(z) is unity for both resonator types. For rp 1, this also corresponds to a constant peak gain of 1. ≈ ≈

For resonator 1, the band-pass transfer function HBP,1(z) is given by (6.3.16).

1 1 kBW z− (1 z− ) − 1 2 k2 z 1+z 2 YBP1(z) kBW H1(z) − − f − − HBP,1(z) = = = 1 1 X(z) 1 + k H (z) kBW z (1 z ) BW 1 1 + − − − 1 2 k2 z 1+z 2 − − f − − 1 1 kBW z− 1 z− = − (6.3.16) 2 1 2 1 2 kBW k z + (1 kBW )z − − − f − − −

The center frequency of the band-pass is Ωc Ωr = θp k f (6.3.12); comparison of (6.3.16) with (2.7.3) shows that the pole≈ radius is≈ independent of the pole angle:

kBW 2 rp = √a2 = 1 kBW 1 kBW = 1 r (6.3.17) − ≈ − 2 ⇔ − p p Approximations for bandwidth, quality factor and settling time of a high-Q second order resonator have been derived in (2.7.22) - (2.7.24), showing that BP1 has a constant absolute bandwidth over the tuning range. The relative band-

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 146 6. On-Chip PLL Response Analysis

−10

−20

|H(f)| (dB) −30

−40

−50 0 1 2 3 4 Frequency [Hz] 5 x 10

Figure 6.28.: Transfer functions of resonator based ﬁlter with constant BW for 8 9 kBW = 2 and k f = 2 100...1000 − − · width decreases and the Q-factor increases for higher center frequencies (6.3.18):

1 rp kBW BBP,1 − ≈ πTs ≈ 2πTs θp k f 1 QBP,1 (6.3.18) ≈ 2(1 rp) ≈ kBW ≈ Brel − 1 TS τBP,1 = ≈ 2πBBP,1 kBW The peak gain of Fig. 6.27 increases slightly over the frequency band of interest due to the inﬂuence of the conjugate pole at θp. It is eliminated by the modiﬁed structure Fig. 6.29 [TR93a] with an additional− zero at z = 1 (6.3.19) as described in Sec. 2.7.4. Fig. 6.28 shows the resulting transfer functions− for different center frequency settings.

1 + z+1 H (z) = H (z) BP,1b BP,1 2 1 1 k 1 z− 1 + z− = BW − (6.3.19) 2 2 1 2 1 2 kBW k z + (1 kBW )z − − − f − − − The resulting peak gain frequencies are fc,1(k f = 1) = 135.560 kHz and fc,2(k f = 9 1 + 2− ) = 135.850 kHz, the frequency step is 290 Hz. The -3 dB bandwidth is B 3 = 505 Hz and the -60 dB bandwidth is B 60 = 284 kHz, giving a large shape − − factor (= weak selectivity) of SF = B 60/B 3 = 562 . − −

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 147

k bw x[n] − z−1 − 1/2

ybp1,b [n] k k f f z−1

Figure 6.29.: Resonator based bandpass with constant peak gain

At the same time, the -3 dB bandwidth is so narrow that a tone in the middle between the maxima of two ﬁlter settings appears to have an amplitude that is lower by ∆Hsc = 1.2 dB compared to a tone exactly at the center frequency (Fig. 6.31(a)). This effect is known as (peak) scalloping loss [Har78] from DFT analysis, creatingd errors for the measurement of narrowband signals.

1 0 Time: 199448.4375 Amplitude: −0.0016361 −0.2 0.5 −0.4 0 −0.6

−0.5 −0.8

|H(f)| (dB) |H(f)| (dB) −1 −1 −1.2

−1.5 −1.4 −1.6 −2 0.5 1 1.5 2 1.98 1.985 1.99 1.995 2 5 5 Frequency f [Hz] x 10 Frequency f [Hz] x 10

nd Figure 6.30.: Bandpass gain HBP( f ) (a) and worst case scalloping loss ∆Hsc (b) of 2 | | 8 order resonator (kBW = 2− , k f = 1)

Forth Order Band-Pass

The design tradeoffs between selectivity, i.e suppression of out-of-band tones, and constant transmission in the passband are rather limited for a second order resonator. A high Q-factor enhances the selectivity at small frequency offsets, but at larger offsets only the weak ﬁrst order roll-off is effective. Cascading two identical second order resonators gives a forth order resonator with improved roll- off that also has constant bandwidth and a peak gain of 1. However, Fig. 6.31(c)

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 148 6. On-Chip PLL Response Analysis

Filter H (Ωc) Hrp BN B 3 B 60 SF | | | | − − 9 N ∆k f 2 (dB) (dB) (kHz) (kHz) (kHz) · 2 0 0 — 0.794 0.505 135.9 269.1

4 0 0 — 0.398 0.325 16.1 49.5 4 1 2.5 — 0.530 0.458 18.4 40.3 − 4 2 7.3 0.08 0.908 0.822 24.3 29.6 − 4 3 10.8 1.3 1.189 1.18 29.7 25.2 −

Table 6.3.: Bandpass properties at k f = 1( fc = 135.4 kHz) shows that the peak scalloping loss is even worse in comparison to the second order resonator (∆Hsc = 2.5 dB).

One solution for reducing the variation ∆Hsc of the measured peak amplitude is to increase the bandwidth by using a staggered filter: Two second-order band-pass sections are cascaded with slightly different center frequencies, giving a wider passband and forth order transition regions. Fig. 6.31(e) and 6.31(f) show a forth order band-pass where the coefficients de- 9 terming the center frequency of the two section differ by ∆k f = 2 2 or 584 Hz. · − This gives a reduced peak scalloping gain of ∆Hsc = 0.5 dB and a selectivity SF = 29.6 that is improved by nearly an order of magnitude compared to the second order resonator. However, this approach also has some drawbacks: The staggering reduces the peak gain and hence the SNR of the filter. The relationship (6.3.13) between the parameter k f and the center frequency Ωc is only approximately linear, the 9 difference in center frequencies that corresponds to ∆k f = 2 2 increases with · − larger values of k f . As a consequence, the bandwidth and also the peak gain H(Ωc) of the staggered band-pass now depend on the center frequency Ωc. | | 9 When ∆k f 2 2 , the resonator response has two distinct peaks and a mini- ≥ · − mum, giving a passband ripple Hrp that also depends on Ωc. | | 9 Here, a staggered tuning of ∆k f = 2 2− has been selected as a compromise between low scalloping loss and tolerable· parameter variations over the frequency range which is limited to approx. 200 kHz for the target application. Tab. 6.3 and 6.4 compare the properties of different bandpass implementations and their variation over the frequency range.

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 149

0 0

−0.5 −10

−1 −20

−1.5 −30

|H(f)| (dB) −2 |H(f)| (dB) −40

−2.5 −50

−60 −3 1.354 1.355 1.356 1.357 1.358 1.359 1.36 1.361 0.5 1 1.5 2 2.5 3 5 5 Frequency [Hz] x 10 Frequency [Hz] x 10 (a) (b)

0 0

−0.5 −10

−1 −20

−1.5 −30

|H(f)| (dB) −2 |H(f)| (dB) −40

−2.5 −50

−3 −60 1.354 1.355 1.356 1.357 1.358 1.359 1.36 1.3 1.35 1.4 5 5 Frequency [Hz] x 10 Frequency [Hz] x 10 (c) (d)

−10 −7.5 −20 −8

−8.5 −30

−40 |H(f)| (dB) −9 |H(f)| (dB)

−9.5 −50

−10 −60

1.354 1.356 1.358 1.36 1.362 1.364 1.25 1.3 1.35 1.4 1.45 5 5 Frequency [Hz] x 10 Frequency [Hz] x 10 (e) (f)

8 Figure 6.31.: -3 dB and -60 dB bandwidth of different band-pass ﬁlters with kBW = 2− at k f = 1: (a) and (b) second order, (c) and (d) forth order and (e) and (f) 9 forth order with staggered tuning ∆k f = 2 2 · −

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 150 6. On-Chip PLL Response Analysis

−5

−8.9 −6 −9 −7 −9.1

|H(f)| (dB) −8 |H(f)| (dB) −9.2

−9 −9.3

−9.4 −10 0.5 1 1.5 2 1.985 1.99 1.995 2 5 5 Frequency f [Hz] x 10 Frequency f [Hz] x 10

th Figure 6.32.: Bandpass gain HBP( f ) (a) and worst case scalloping loss ∆Hsc (b) of 4 | | 8 9 order resonator (kBW = 2 , k f = 1, ∆k f = 2 2 ) − · −

Filter HBP ( fc) (dB) Hrp,max ∆Hsc B 3 (kHz) | | | | − 9 N ∆k f 2 fc min fc max (dB) (dB) fc min fc max · , , , , 2 0 0 0 — 1.7 0.505 0.505

4 0 0 0 — 3.3 0.325 0.325 4 1 3.4 1.9 — 1.2 0.426 0.521 − − 4 2 9.0 6.0 0.47 0.5 0.710 0.981 − − 4 3 12.4 9.3 2.2 0.5 1.021 1.394 − −

Table 6.4.: Variation of bandpass properties over fc,min = 10 kHz... fc,max = 200 kHz

The equivalent noise bandwidth Bn was calculated numerically using (6.3.20). Noise bandwidth variation over the frequency range was comparable to B 3, i.e. 8 − 16 % or 1.3 dB for ∆k f = 2 . ± ± − 1 ∞ B = H2( f )d f (6.3.20) n H2( f ) c Z0

Another option for reducing the variation of the measured peak amplitude would be to apply "video ﬁltering", i.e. calculating the average of several frequency bins which is best performed off-chip. When the scaling factors are made dependent on the frequency bin, the inﬂuence of the non-equidistant frequency bins can also be compensated.

Christian Münker March 10, 2010 6.3. Spectral Analysis of Baseband Signal 151

Settling Time

The response time of a ﬁlter is inversely proportional to its bandwidth, which puts a lower bound on its time resolution. As shown, in Sec. 2.7.5, the settling time-constant τ can be estimated from the pole radius (2.7.24): 1 T τ = S ≈ 2πB 1 rp −

6.3.5. Envelope and Display Detection

Ideally, the estimation of the power spectral density requires averaging of the squared band-pass output signal (6.3.21). When only low-bandwidth signals shall be transferred to the ATE, these calculation have to be performed on-chip.

T 1 2 2 Ps = lim s (t) dt = s (t) (6.3.21) T ∞ 2T T → Z− However, the output of a narrow band-pass is nearly sinusoidal and the signal power can be approximated by (6.3.22), calculating only the average of the absolute signal value on chip and performing squaring and scaling off-chip. In contrast to analog circuits, perfect calculation of the absolute value requires very little hardware in digital signal processing.

2 2 2 2ˆs 2 sˆ π sˆsin(t) = Ps sin = s (t) = = s(t) for sinusoids (6.3.22) | | π ⇒ , 2 8 | | For slowly varying signals, ideal averaging can be approximated by a moving average over a ﬁnite time T:

T 1 2 Ps Ps(T) = s (t) dt (6.3.23) ≈ 2T T Z− This is analogous to simple analog envelope detection performed with a diode and an RC low-pass ﬁlter. The choice of the cut-off frequency is determined by two contradicting requirements, the settling time and the ripple attenuation. Both effects should generate a total error of less than 0.5 dB or 6%:

The settling time Tsettle of the ﬁlter to an accuracy of 0.25 dB (3%) should • not exceed 5 ms for an acceptable measurement time. The ripple of the demodulated, rectiﬁed, squared signal due to the second • harmonic of the test tone should be less than 0.25 dB (3%).

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 152 6. On-Chip PLL Response Analysis

Assuming a ﬁrst order system with a time constant of τ = 1/2π fc, settling within 2% is achieved after TSettle 4τ, limiting the cutoff frequency to fc > ≈ 2/πTSettle = 0.64/TSettle = 0.13 kHz. The amplitude of the harmonics of a full-wave rectiﬁed sinusoid (only even harmonics), relative to the DC component are given by [BS81, p. 617]: a 2 4 2k = = for k = 1 (6.3.24) a0 (2k + 1)(2k 1) 15 − The (relative) ripple of the squared sum of a DC signal with level A and a sinusoid with amplitude c is approximated by

ε 2 ω 2 c c = 0.03 > a0 min (a0 + csin t) 2 < 0.015 . (6.3.25) − {{ } ≈ a0 ⇒ a0 This means, the attenuation of the moving average ﬁlter for the second harmonic needs to be at least

c a0 HMA < = 0.056 25 dB. (6.3.26) a0 a2k ≡ − Averaging is performed by another downsampling CIC filter for minimum chip area. Choosing R = 256 and N = 1 yields a sampling frequency of 3.17 kHz at the output. The -3 dB frequency of a first order CIC filter is at F 0.44, i.e. at f = 1.39 kHz. ≈ The lowest frequency component that has to be regarded for aliasing is the second harmonic of the lower edge of the frequency range (10 kHz). Alias suppression at F = 6.5 ( f = 20.6 kHz) is 0.077 or 22.3 dB (6.3.7). This creates a worst case error of 0.35 dB, falling a bit short of the target of 0.25 dB. However, this error quickly decreases for higher test-tone frequencies. The averaged demodulated output value can be read via a three wire bus, video detection and filtering etc. can be performed by software when needed.

Christian Münker March 10, 2010 In theory, there is no difference between theory and practice. In practice, there is. Yogi Berra 7

Implementation and Measurement Results

The implementation of the SP-BIST concept on test chips in 130 nm CMOS technology is described. Measurement results for unmodulated and modulated PLL signals are given and a method is described to reduce the spurious lines created by the ﬁrst order Σ∆FD.

7.1. Baseband Test-Tone Generation

The test-tone generator has been synthesized from VHDL, occupying an area of ca. 0.02 mm2.

7.1.1. Oscillation Frequency

The signal frequency is monotonous but slightly nonlinear with respect to the coefficients a,bi. Fig. 7.1 shows the oscillation frequency depending on coefficient b and the error caused by the approximate frequency formula (5.2.4). The exact oscillation frequency can easily be calculated on the ATE resp. controlling PC using (5.2.1). The binary encoding of the coefficients is QU1.14 (Sec. 2.8). The 4 value a = 2− is fixed, possible values for b1 and b2 with the resulting frequencies 154 7. Implementation and Measurement Results

BinWord BinWord RWV Frequency (dec.) (kHz) Parameter a 4 010000000000 1024 2− n.a.

Parameter b1 (Tone 1) 6 000100000000 256 2− 65 5 001000000000 512 2− 91 4 010000000000 1024 2− 129.3 3 100000000000 2048 2− 183

Parameter b2 (Tone 2) 000000001111 15 9.16 10 4 15 · − 000010011111 159 9.70 10 3 51 · − 001001011111 607 3.74 10 2 100 · − 010000001111 1039 6.34 10 2 130 · − 011111111111 2047 1.25 10 1 183 · − Table 7.1.: Frequencies of programmable tones

are shown in Tab. 7.1, spanning a frequency range of 15kHz < fsig < 183 kHz for a sampling frequency of fS = 26 MHz. b1 is the reference tone which can only be set in four coarse steps, b2 can be varied in 127 steps between 15 and 2047 (the 4 LSBs are ﬁxed to 1111). Tab. 7.6 in the appendix shows the programming register for the multi-tone generator.

7.1.2. Amplitude and Amplitude Variation over Frequency

The multi-tone digital oscillator described in [LR98] has been implemented on a DSP with 24 bit arithmetics and achieves a constant amplitude for all tones by pre-calculating and storing initial conditions for each tone. The minimum area constraint in this work mandates a simpliﬁed approach: The initial conditions for all tones are set to xa(0) = x0 and xb,1(0) = xb,2(0) = 0, allowing the simpliﬁca- tion of (5.2.1) - (5.2.3):

Christian Münker March 10, 2010 7.1. Baseband Test-Tone Generation 155

200 0.04

150 0.03 (kHz) sig

100 0.02 Signal frequency f 50 0.01 Relative approximation error (%)

0 0 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 Resonator coefficient b

Figure 7.1.: Frequency of LDI oscillator

ab ωsig = fS arccos 1 for 0 < ab 2 − 2 ≤ 2sin(ωsigTs) φa = arctan − ab

(1 ab)xa(0) xˆa = − sin(ωsigTS + φa)

This simpliﬁcation results in a amplitude variationx ˆa( f ) of less than 0.1% over signal frequency, shown in Fig. 7.2. The error due to this amplitude variation is much less than other error sources and is removed by the calibration procedure described in Sec. 7.5.6. The amplitude of both tones can be set in steps of 6 dB (Tab. 7.2).

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 156 7. Implementation and Measurement Results

−0.01

−0.02

−0.03 (%) err −0.04

−0.05

−0.06

−0.07 Rel. Amplitude Error a

−0.08

−0.09

−0.1 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 Resonator coefficient b

Figure 7.2.: Amplitude error of LDI based oscillator

BinWord Amplitude Amplitude (dB) 6 000000100000000 2− -24 dB 5 000001000000000 2− -18 dB 4 000010000000000 2− -12 dB 3 000100000000000 2− -6 dB

Table 7.2.: (Ideal) amplitudes of programmable tones vs. initial condition x(0)

7.2. Output Response Analysis

7.2.1. Sigma-Delta Frequency Discriminator

The sigma-delta frequency discriminator (Σ∆FD) in this work takes advantage of the high transit frequency of the 130 nm CMOS technology: It is directly clocked with the 4 GHz signal of the VCO for maximum simplicity. The schematic is shown in Fig. 7.3.

Christian Münker March 10, 2010 7.2. Output Response Analysis 157

Figure 7.3.: Schematic of Σ∆FD

Multi-Modulus Divider

The multi-modulus divider is a critical part for the performance of the Σ∆FD as divides the RF PLL signal by a ratio that changes every reference cycle without producing glitches or random delays, ruling out asynchronous counters or dividers. In synchronous counters, all ﬂip-ﬂops are clocked with the input frequency, which is hard to design for radio frequencies and consumes a lot of power.

RF 2 / 3 2 / 3 2 / 3 2 / 3 in DIVout Fin Fout Fin Fout Fin Fout Fin Fout

M in M out M in M out M in M out M in P P P P

P P P P 0 1 n−2 n−1

Figure 7.4.: Multi-modulus divider made from a chain of 2/3 divider cells

Due to the high reference frequency of 26 MHz, the required division ratio only has to span the range of 115...154 for a PLL frequency of 3...4 GHz. This is accomplished by the architecture in Fig. 7.4 [VFL+00], consisting of a chain of 2/3 cells (Fig. 7.5). This topology has the advantage that only the ﬁrst divider÷ has to be designed for the full frequency and that the switching of division ratios is self-synchronized with the divided output signal. A simple cascade of

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 158 7. Implementation and Measurement Results dual-modulus divider cells would not work because a division ratio like N = 129 cannot be constructed from a product of 2’s and 3’s. The solution is adding one extra cycle per output period if the modulus control Pi = 1. This is achieved with the control input and output pins Min and Mout (Fig. 7.5). The modulus enable input Min enables the P input pin, the modulus enable output Mout synchronizes the Min input and passes it on to Min of the previous divider stage. This “daisy chain connection” ensures that each divider stage swallows a maximum of one pulse per divide cycle (depending on Pi), giving the targeted division ratio (7.2.1):

n n 1 NMMD = 2 + Pn 1 2 − + ... + P1 2 + P0 (7.2.1) − · ·

Divider /2 with enable F out D1 1 DQ D−FF EN 1 Q F in 2 / 3 critical path Fin Fout M => in M M Q D out in & P D−FF 2 Q D2

& M Phase Shift out M_in = 0 => /2 P = 0 => /2 P M_in = 1 => P enabled P = 1 => /3

Figure 7.5.: High-speed 2/3 divider cell with modulus enable

Fig. 7.5 shows an 2/3 divider cell with modulus enable input. High speed is achieved by shifting the P - NAND into D-FF2 (between the master and the slave stage) to shorten the critical path. Synchronizing the programming word guarantees a ﬁxed timing relationship between programming word and divided clock which allows switching the division ratio without glitches.

RF frequencies in the range of 4 GHz require special flip-flops, here, a dynamic flip-flop is used (Fig. 7.6), similar to the design presented in [YS89].

Christian Münker March 10, 2010 7.2. Output Response Analysis 159

2M 2M 2M 3M 2.4M

1.6M 2M 1.2M

2.2M

2.2M M M 2M

Figure 7.6.: Dynamic high-speed ﬂip-ﬂop

7.2.2. Spectral Analysis of Demodulated Bitstream

Downsampling

As described in Sec. 6.3.3, the ﬁrst downsampling stage is a second order (N = 2) downsampling CIC ﬁlter with a decimation ratio of R = 32 (Fig. 6.21). 2 The DC-gain is HCIC1(0) = 32 = 1024 30 dB, the word length at the in- ≡ put is WLCIC1,in = 1 (single-bit Σ∆M stream) and at the output WLCIC1,out = N log (R) +WLCIC1 in = 11. ∗ 2 ,

Band-Pass Filter

The tunable forth-order bandpass ﬁlter is based upon a resonator-in-the-loop topology, its center frequency can be tuned in the range of 0.3 . . . 400 kHz, the usable and important range for this application is limited to 200 kHz. At higher frequencies, the scalloping loss and the bandwidth variation becomes too large (Sec. 6.3.4).

The reduced sampling rate of fS,R = 812.5 kHz allows sharing of the area- intensive multiplier between blocks in the band-pass: The signal is passed through the resonator twice, the center frequency is slightly detuned for the second pass (staggered tuning). Both multipliers in the resonator have the same co- efﬁcient k f (Fig. 6.29), easing multiplier sharing. The bandpass is implemented

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 160 7. Implementation and Measurement Results with only one multiplier in an area of less than 0.03 mm2. An accumulator length of 21 bits and a tunable coefficient length of only 9 bits were sufficient to achieve a SQNR of 90 dB. This and the fact that the resonance frequency fr is set with a single parameter k f are the main advantages of this filter. An implementation error in the filter that was not detected during final simulations creates an overall transfer function (CIC-filter and bandpass) with a variation of 5 dB over the frequency range. However, the option for measuring the baseband response that has been implemented for compensating the scalloping loss can also be used to eliminate the faulty frequency response (Sec. 7.5.6).

Envelope Detection

The envelope detector has been implemented as described in 6.3.5, averaging of the rectified signal is performed with a first order downsampling CIC filter with a decimation ratio R = 256. The output word is truncated to fit the result register length WL = 16.

7.3. Area Estimation and Layout

Except for the multi-modulus divider (MMD), the whole SP-BIST was synthesized from VHDL code. The cells were placed and routed together with the other logic building blocks of the DUT. For this reason, only the layout of MMD can be shown, the other cells are absorbed into the synthesized logic of the DUT. Figures for the area consumption (including routing) were taken from the report ﬁles of the P & R software (Tab. 7.3). The layout of the MMD is shown in Fig. 7.7, occupying an area of only 75 µm x 75 µm = 0.0055mm2, half of which is consumed by decoupling capacitors and could possibly be reduced.

Block Sine Gen Σ∆FD Filter Total Area (mm2) 0.02 0.005 0.035 0.06

Table 7.3.: Silicon area of SP-BIST blocks

In comparison, the MADBIST in [TR95a, TR95b] uses an area of 3.9 mm2 in a 0.8 µm technology for a two-tone generator and a tunable band-pass alone (no

Christian Münker March 10, 2010 7.3. Area Estimation and Layout 161 downsampling, no envelope detector). This is equivalent to an area of approx. 0.1 mm2 in the 130 nm technology of this work. Although MADBIST and SP- BIST cannot be compared directly (Sec. 4.3), it can be estimated that the area reduction was achieved by reduced coefﬁcient and multiplier precision (24 bit in [TR95b]), enabled by a reduced sampling rate (multirate signal processing) and the resulting relaxed ﬁlter requirements.

Latches & Logic

50 um High−Speed Divider Cells 75 um

50 um

Decoupling C’s

75 um

Figure 7.7.: Layout of MMD

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 162 7. Implementation and Measurement Results

7.4. Test Chips

Fig. 7.8 shows the circuit-under-test (CUT) together with the SP-BIST. The multi- tone sine generator digitally modulates the PLL, the RF output of the Σ∆PLL is demodulated with the Σ∆FD.

RF out PFD f Reference Frequency Loop Filter VCO

÷N ± m

φ f mod d mod SDM dt f TX Filter Channel Word N.F SP−BIST

y Stimulus STIM +−1 Generator

Spectrum Analyzer Spectrum N t +−1 SDFD f y Pass / Fail ORA

Figure 7.8.: RF PLL under test with SP-BIST

The test-tone generator and the output response analyzer were integrated on two different highly integrated RF transceiver ICs for GSM, EDGE and UMTS cellular standards manufactured by Inﬁneon Technologies. As no interaction with RF paths was required, the circuits-under-test (receive and transmit PLLs) could remain untouched. The most challenging part of the integration was merging the synthesizable code into the complex digital state machine under the tight restrictions of a worldwide distributed project with more than 100 members. Control and read-out of the BIST blocks are performed via the common digital interface. As details of the DUT may not be disclosed here, Fig. 7.9 only shows a block diagram of one of the transceiver ICs; the two Σ∆PLLs with added SP-BIST functionality have been highlighted.

The ﬁrst test-chip was a quad band GSM transceiver chip similar to Fig. 3.8 with an additional single-tone test-tone generator. Unfortunately, the test-tone generator could not be properly tested as no spectrum analyzer with FM discriminator capabilities was available.

Christian Münker March 10, 2010 7.4. Test Chips 163

SP−BIST (RX) SP−BIST (TX)

Figure 7.9.: Block diagram of multimode RF transceiver

The second and third SP-BIST implementations were realized on the multimode RF transceiver shown in Fig. 7.9, containing two-tone stimulus generator and the full spectral RF analysis block.

On the third test chip, the SNR of the ﬁlter was improved by increasing accumulator word length from 15 to 21 bits. A higher selectivity was achieved by a higher 5 8 resonator Q (kBW = 2− 2− ) and by introducing the concept of staggered tuning. →

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 164 7. Implementation and Measurement Results

7.5. Measurement Results

Unless noted otherwise, all measurement plots in this section have been taken with the on-chip spectrum analyzer, showing the PSD Sy( f ) of the frequency deviation. Center and tone frequencies were set with a PC via the serial bus of the DUT, measurement data was read back from the chip via the same bus. All signal processing was performed on chip except optional averaging and calibration (see below), data was plotted with Matlab. For performance evaluation of the SP- BIST, the whole frequency range was swept through. Under real production test conditions, only some critical frequency points would be measured (3 ms per point) to reduce the test time.

7.5.1. Disturbances Caused by SP-BIST

(a) (b)

Figure 7.10.: Unmodulated PLL spectrum without (a) and with (b) active Σ∆FD, measured with spectrum analyzer at TX output

The multi-tone generator is connected to the digital Σ∆PLL modulation input and is completely invisible when deactivated. The additional capacitive load that also the inactive Σ∆FD presents to the VCO buffer could degrade the PLL performance, however, no degradation was measured in comparison to chip variants without SP-BIST (Fig. 7.10(a)). In active mode, spurs at multiples of the reference frequency (26 MHz) appear in the output spectrum (Fig. 7.10(b)) which do not disturb the in-band measurements. If it is intended to run the SP-BIST blocks during normal Σ∆PLL operation (e.g. for monitoring the PLL spectrum), a few

Christian Münker March 10, 2010 7.5. Measurement Results 165 more buffers have to be inserted between VCO buffer and Σ∆FD for additional isolation.

7.5.2. Spectrum of Test-Tone Generator

The output of the stimulus generator can be fed directly into the narrowband filter (see Fig. 7.8) for baseband performance verification of the tone generator and the narrowband filter with envelope detector. Fig. 7.11 show the overlaid results of measurements with different tone frequencies, using different filter staggerings. Fig. 7.11 has been constructed from the maxima of individual measurements, although this gives a pessimistic view of the noise performance. Instead of the expected droop in the frequency response due to the CIC filter, there is an unexpected increase over frequency. This effect could be traced back to a faulty implementation of the tunable bandpass filter. As the Σ∆FD has a constant frequency response over the range of interest, this error can be compensated by a reference measurement or simulation that only has to be performed once. The signal-to-noise ratio degrades at higher frequencies due the sigma-delta quantization noise of the multi-tone generator. The tunable filter has a dynamic range of approx. 90 dB as can be seen for frequencies below 50 kHz. This is consistent with simulation results.

7.5.3. Measurement Accuracy

The reproducibility of SP-BIST measurements has been analyzed by repeating a measurement 200 times and calculating the average m and the standard deviation σ at the output of the envelope detector. The tone frequency was fixed at fm = 65 kHz for all measurements. The filter center frequency fc was first set to the tone frequency ( fc = fm = 65 kHz) to assess the reproducibility of tone measurements and then at an unrelated frequency fc = 104 kHz to assess the noise level (Tab. 7.4). The noise bandwidth is Bn 900Hz 29.5 dB. ≈ ≡ First, the reproducibility of baseband measurements (i.e. without Σ∆PLL and Σ∆FD) was assessed. For this mode, noise can be attributed to the Σ∆M of the tone generator and to re-quantization in the filter. The quantity mS/mN is an indication for the SNR, although it should be noted that signal and noise have been measured at different frequencies. Unfortunately, there was not enough time for more in-depth measurements due to a job change.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 166 7. Implementation and Measurement Results

40 Amplitude (dB) 30

0 0 0.5 1 1.5 2 2.5 3 5 Offset Frequency from Carrier (Hz) x 10

(a) ∆k f = 0 90

40 Amplitude (dB) 30

0 0 0.5 1 1.5 2 2.5 3 5 Offset Frequency from Carrier (Hz) x 10 9 (b) ∆k f = 2 2 · −

Figure 7.11.: Spectrum of two-tone generator measured with different ﬁlter staggering

Christian Münker March 10, 2010 7.5. Measurement Results 167

∆k ff fc = fm fc = 104 kHz mS/mN 9 2− mS σS σS/mS mN σN σN/mN [dB] · − Baseband 0 13250 42 0.3% 20 7 35% 56.4 1 9408 50 0.5% 10 6 60% 59.4 2 6428 19 0.3% 8 5 60% 58.1 3 4057 25 0.6% 5 4 80% 58.1 Full 0 27911 102 0.4% 95 49 52% 49 SP-BIST 1 19880 120 0.6% 82 45 55% 48 2 13548 54 0.4% 63 35 56% 47 3 8538 62 0.7% 46 26 56% 45

Table 7.4.: Reproducibility of SP-BIST tone ( fc = 65 kHz) and noise ( fc = 104 kHz) measurements for a tone frequency fm = 65 kHz

In the second step, the full loop including upconversion in the Σ∆PLL and frequency discrimination in the Σ∆FD was measured. The SNR degradation of 11 dB compared to baseband measurements is mainly caused by the Σ∆FD quantization≈ noise and spurs. The RF response has been optimized to make full use of the dynamic range of the SP-BIST. The baseband response is lower by 6.5 dB which can be compensated easily on the ATE or a lab PC. Hence, no on- chip gain equalization between the Σ∆M bitstreams of test-tone generator and Σ∆FD has been implemented. The results show excellent reproducibility of the tone measurements (0.5% 0.04 dB). ≡

7.5.4. Measurement of Unmodulated Spectrum

Next, an unmodulated PLL signal was fed into the Σ∆FD. Strong spurious tones, produced by the ﬁrst order Σ∆FD can be seen in the demodulated spectrum (Fig. 7.12(a) and 7.12(b)). The position of these idle tones is determined by the fractional part of the PLL frequency as explained in Sec. 6.2.2. The nearest integer frequency is fI = 146 26 MHz = 3822 MHz, the fractional part f frac = · 3812.348 MHz fI = 9.652 MHz 0.371 26 MHz. − − ≈ · Averaging improves the SNR but Σ∆FD tones are not attenuated. Averaging the

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 168 7. Implementation and Measurement Results

50 y 40

20 log |S | 30

10 f VCO = 3812.3487 MHz

0 0 0.5 1 1.5 2 2.5 3 3.5 4 5 Offset Frequency from Carrier (Hz) x 10 (a)

50 y 40 20 log |S | 30

10 f VCO = 3812.3387 MHz

0 0 0.5 1 1.5 2 2.5 3 3.5 4 5 Offset Frequency from Carrier (Hz) x 10 (b)

Figure 7.12.: Unmodulated PLL spectrum with Σ∆FD spurious tones at different carrier frequencies (∆ f0 = 10 kHz)

Christian Münker March 10, 2010 7.5. Measurement Results 169 spectrum at K several slightly different carrier frequencies reduces the magnitude of the Σ∆FD spurs by 20logK dB as the Σ∆FD spurs now appear at different offsets. This frequency sweep averaging is feasible as the fractional-N PLL takes only a few µs to lock to the new frequency.

As the spurious tones are deterministic, these frequencies can be "blanked" out. By selecting only data points that differ less than e.g. 8 dB between measurements, different scale of y-axis), the SFDR can be improved by approximately 30 dB [MW07]. However, this selective frequency averaging has to be applied with care as some kinds of unwanted PLL sidebands also depend on the carrier frequency and may be suppressed as well. The effect of both methods can be seen in Fig. 7.13 for the case of a single-tone modulation.

7.5.5. Measurement of Modulated Spectrum

Fig. 5.11 shows the PLL phase spectrum resulting from single-tone modulation with fre f = 26 MHz, fm = 67 kHz at a carrier frequency f0 = 3.812 GHz. The frequency modulation index is β f = 2.1 and the peak frequency deviation is ∆ f = 142 kHz. c This single-tone modulation is used to calibrate the gain of the spectral analyzer: 5 An RF PSD of Sy = 3.72 10− 85.6 dB is calculated, the displayed value is 83 dB, indicating a gain of· 168 dB.≡ − The displayed noise level is around +32 dB with a noise bandwidth BN = 27 dB, yielding a noise PSD of Sy( fm = 67kHz) = 32 27 168 dB = -163 dB. This corresponds to Sφ = Sy + 20log fm = 163 + 97 −= 66− dB. At around 200 kHz, the noise has a constant value of 40 dB−. − The quantization error of a single tone modulation is still strongly correlated with the signal, leading to strong spurious tones as well (Fig. 7.13(a)). Applying selective frequency averaging improves the result (Fig. 7.13(b)) with the same drawbacks as described above.

Two-tone FM produces sufﬁcient randomization to eliminate most idle tones as shown in Fig. 7.14. Again, frequency selective averaging improves the display of measurement results (Fig. 7.14). This ﬁgure shows a two-tone spectrum measured on-chip with too weak attenuation of the out-of-band tone, indicating a faulty loop transfer characteristic. With two-tone modulation, the spurious free dynamic range (SFDR) is approx. 45 dB.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 170 7. Implementation and Measurement Results

60 y 50

20 log |S | 40

20 f VCO = 3812.3387 MHz

0 0 0.5 1 1.5 2 2.5 3 3.5 4 5 Offset Frequency from Carrier (Hz) x 10 (a) 90

y 50

40 20 log |S |

20 f VCO = 3812.3387 MHz

0 0 0.5 1 1.5 2 2.5 3 3.5 4 5 Offset Frequency from Carrier (Hz) x 10 (b)

Figure 7.13.: Single-tone (67 kHz) modulated PLL spectrum with averaging (a) and selective frequency averaging (b) (K = 4, ∆ f = 10 kHz)

Christian Münker March 10, 2010 7.5. Measurement Results 171

Error 80

70 Target Loop Characteristic

60 f 50

40 20 log |S |

f VCO = 3812.338 MHz 10

0 0 0.5 1 1.5 2 2.5 3 3.5 4 5 Offset Frequency from Carrier (Hz) x 10

Figure 7.14.: Two-tone modulated PLL spectrum with frequency sweep averaging, showing error in loop characteristic

∆HORA( fm) = Sy ORA RF ( fm) Sy ORA RF (64kHz) , , − , , ∆HPLL( fm) = Sy ORA RF ( fm) Sy BB RF ( fm) 6.5dB , , − , , − Sy( fm) = Sy ORA RF ( fm) A0 ∆HORA( fm) , , − − Sφ ( fm) = Sy( fm) + 20log f0/ fm

Sy N( fm) = Sy ORA RF ( fm) A0 ∆HORA( fm) BN( fm) , , , − − − Sφ,N( fm) = Sy,N( fm) + 20log f0/ fm

L ( fm) = Sφ N( fm) 3dB , −

Box 7.1: Formulas for calculation of frequency response and phase noise

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 172 7. Implementation and Measurement Results

40 Amplitude (dB) 30

0 0 0.5 1 1.5 2 2.5 3 5 Offset Frequency from Carrier (Hz) x 10 (a) BB-ORA 90

40 Amplitude (dB) 30

0 0 0.5 1 1.5 2 2.5 3 5 Offset Frequency from Carrier (Hz) x 10 (b) RF-ORA

Figure 7.15.: Comparison of baseband and RF output response analysis

Christian Münker March 10, 2010 7.5. Measurement Results 173

9 k ff 2 251 285 397 476 545 600 647 ·

fm (kHz) 64 73 103 125 145 162 177

f0/ fm (dB) 95.5 94.4 91.4 89.7 88.4 87.4 86.7

A0 (dB) 161.5 (BB) resp. 168 (RF)

∆HCIC( fm) (dB) 0 0.2 1.2 2.1 3.1 4.1 5.1 − − − − − −

∆HBP( fm) (dB) 0 +1.2 +4.3 +5.8 +7.8 +8.6 +10.4

∆HORA( fm) (dB) 0 +1.0 +3.1 +3.7 +4.7 +4.5 +5.3

Hy,,ORA,,BB (dB) 76.2 77.2 79.3 79.9 80.9 80.7 81.5 Tones

Hy,,ORA,,RF (dB) 82.6 83.3 83.0 81.6 79.8 77.4 75.4

∆HPLL( fm) (dB) 0.1 0.4 2.8 4.8 7.6 9.8 12.6 − − − − − − −

Sy( fm) (dB) 85.4 85.7 88.1 90.1 92.9 95.1 99.2 − − − − − − −

Sφ ( fm) (dB) +10.1 +8.7 +3.3 0.4 4.5 7.7 12.5 − − − − Noise

Sy,,ORA,,RF (dB) 25 28 32 35 36 37 38

BN (dB) 29 29 29 29 30 30 30

Sy,N ( fm) (dB) 172 170 168 166 167 166 165 ,, − − − − − − −

Sφ ,N ( fm) (dB) 77 76 77 76 78 78 79 ,, − − − − − − −

L ( fm) (dB) 80 79 80 79 81 81 82 − − − − − − −

8 Table 7.5.: Output frequency response measurements (∆k f = 2− ) at f0 = 3.812 GHz

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 174 7. Implementation and Measurement Results

7.5.6. Measurement of Frequency Response with Calibration

Due to the implementation fault of the bandpass ﬁlter and its scalloping loss that creates a ripple of 0.5 dB, a calibration run is required to obtain precise RF measurements. Other systematic error sources like the droop of the test-tone amplitude (< 0.2% 0.02 dB) are eliminated by this procedure as well. For this calibration, a test mode≡ is selected where the output of the test-tone generator is connected directly to the output response analyzer (Fig. 7.8). The measured base band test tone amplitudes Hy,ORA,BB are stored and subtracted from the measured RF amplitudes Hy,ORA,RF at the same frequencies later on. Fig. 7.15 shows the spectra of baseband and RF measurements, Tab. 7.5 the measurement results before and after calibration and Box 7.1 the equations that have been used to calculate the numbers.

Measurements at fm = 64 kHz have been taken as the reference values in Tab. 7.5, A0 = A( fm = 64kHz). For PLL frequency response measurements, the nominal value Hy,ORA,RF Hy,ORA,BB = 6.5 dB has been used as the reference value where the 6.5 dB are the− gain difference between baseband and RF response analysis (Sec. 7.5.3).

7.6. Programming Examples

A few practical production measurement scenarios are presented in the following:

Frequency response measurement

The general procedure for a frequency response measurement is: (1) Turn on PLL-under-test and enable test-tone modulation. Turn on reference clock for SP-BIST and the VCO buffer providing the Σ∆FD with the RF input signal. These registers are outside the SP-BIST and not described here. (2) Turn on Σ∆FD and select RF (Σ∆PLL) or baseband (test-tone generator) input with Frequency Discriminator Register. (3) Select carrier frequency of Σ∆PLL. This register is also outside the SP- BIST.

Christian Münker March 10, 2010 7.6. Programming Examples 175

(4) Select frequencies and amplitudes for the two test-tones and enable test- tone generation with Multi-Tone Stimulus Register. (5) Select center frequency and staggering of bandpass ﬁlter with Band-Pass Filter Register. (6) Wait for 3 ms. (7) Read out Result Register. (8) Repeat steps 4 - 7 for every frequency point. On the ATE, the coefﬁcients for the test-tones and the center frequencies have to be calculated (or read from a look-up table). The result word can be averaged to improve the SNR, if desired also at different carrier frequencies of the Σ∆PLL (selective frequency averaging) (step 3). Finally, the error introduced by the frequency response of the SP-BIST has to be compensated by subtracting the baseband response (Sec. 7.5.6). The baseband response is fully deterministic and can be either pre-computed or measured once and then be stored in a table.

Measurement of phase noise, spurious sidebands or modulation mask

(1) Turn on PLL-under-test and disable all modulation sources or select modulation with Gaussian ﬁltered PRBS source to measure modulation mask. Turn on reference clock for SP-BIST and the VCO buffer providing the Σ∆FD with the RF input signal. These registers are outside the SP-BIST and not described here. (2) Turn on Σ∆FD and select RF (Σ∆PLL) input with Frequency Discrimina- tor Register. (3) Select carrier frequency of Σ∆PLL. This register is also outside the SP- BIST. (4) Disable test-tone generation with Multi-Tone Stimulus Register. (5) Select center frequency and staggering of bandpass ﬁlter with Band-Pass Filter Register. (6) Wait for 3 ms. (7) Read out Result Register. (8) Repeat steps 4 - 7 for every frequency point.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 176 7. Implementation and Measurement Results

In addition to the ATE procedures described in the last section, the compensated output value also has to be translated from frequency deviation to phase noise using the resolution frequency and the ratio of modulation frequency and carrier frequency.

7.6.1. Programming Registers

Tab. 7.6 shows the SP-BIST parameters that can be controlled via the common serial control and data bus of the DUT: The Multi-Tone Stimulus Register enables the test tones and controls their amplitudes and frequencies. Alternatively, the stimulus generator can deliver a pseudo-random binary sequence (PRBS). The settings of the band-pass are controlled by the Band-Pass Filter Register: f c0 ... f c9 set the center frequency of 9 the band-pass with k f = fc/2 and df0 and df1 set the bandwidth via the amount of staggering between the two band-pass sections. Most bits of the Frequency Discriminator Register have been implemented for debugging and performance optimization purposes. However, no signiﬁcant performance improvements of the Σ∆FD could be measured, as the drawbacks of the ﬁrst order Σ∆M structure creates the main disturbances. The averaged magnitude of the band-pass output is read back from the Result Register via the same bus.

Christian Münker March 10, 2010 7.6. Programming Examples 177 0 0 0 r en 00 f c EN en 1 1 0 Enable 1 r 01 f c di en 2 1 2 10 r 02 f c di b Dither 3 2 3 11 r F. Tone 1 03 f c di b 4 4 20 r 04 f c b dsgn 5 5 21 r 05 f c b dinv Center Frequency 6 6 22 r 06 f c b ddis 0 7 7 23 r 07 f c Demodulator Mode b sel 1 8 8 Frequency Tone 2 24 r 08 f c b sel 9 0 9 25 r 09 f c b ch Result Register (READ) 1 26 Table 7.6.: Programming registers 10 10 r b ch n.c. Band-Pass Filter Register (WRITE) Multi-Tone Stimulus Register (WRITE) 0 2 Frequency Discriminator Register (WRITE) 20 11 11 r ch d f m 1 3 21 12 12 r ch d f Channel m Bandwidth 4 20 13 13 r ch n.c. m Amplitudes 5 21 14 14 r ch m ntch Notch 15 15 r ord man prbs Man Order PRBS

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 178 7. Implementation and Measurement Results

Christian Münker March 10, 2010 The best way to predict the future is to invent it. Alan Kay 8

Conclusion and Future Work

8.1. Comparison to Goals

A Spectral BIST concept capable of extracting spectral parameters of RF PLLs has been developed that allows a autonomous block level test. The SP-BIST is started and controlled via three 16 bit write-registers (Tab. 7.6 in Sec. 7.6.1), the result, i.e. the amplitude of the selected frequency band, is read back from the forth 16 bit register. This procedure requires no external measurement equipment and no high-speed ATE support; it can be run in parallel to other tests as long as the normal functionality of the Σ∆PLLs is not needed. The test results in the frequency domain can be directly compared to the PLL specifications. The SP-BIST consists of two distinct digital blocks, a stimulus generator and an output response analyzer and compactor. Multi-tone stimuli for efficient analysis of the PLL frequency response and loop bandwidth are generated with a low-pass Σ∆-modulated oscillator. This aspect was adopted from the MADBIST mixed-signal test concept for ADCs and DACs (Sec. 4.3). In contrast to the latter, test tones are applied directly to the digital frequency modulation input of the Σ∆PLL, avoiding intermediate D-to-A conversion. RF demodulation and digitization is performed with a fully digital Sigma- Delta frequency discriminator (Σ∆FD) and decimated in a multi-rate filter. The 180 8. Conclusion and Future Work

actual filtering is again similar to the MADBIST concept, however, in this work, the simple second order resonator has been replaced by a forth order band-pass with staggered tuning that combines a high selectivity with a small scalloping loss. The latter translates to reduced sensitivity against detuning of tone and center frequency, allowing a relatively coarse tuning of stimulus generator and band- pass filter with reduced coefficient word length. An additional envelope detector allows the static readout of the filter output via a minimal test interface. This enables simple testing of RF PLLs also on wafer level, increasing fault coverage for known-good-dies. PLL bandwidth is directly influenced by loop filter components and indirectly by the open loop gain, which in turn is influenced by many analog parameters. It is an essential PLL parameter, influencing spurs, phase noise and modulation performance. Testing bandwidth, in-band phase noise and spurious level at selected frequencies can eliminate most ATE tests. The reduction in coefficient length can be exploited for an overall size reduction as both stimulus generator and band-pass filter are based upon digital lossless resonators, a topology that has nearly fallen into oblivion but is optimally suited for this application: It is robust against coefficient truncation and quantization effects, giving very compact implementations, and the center resp. oscillation frequency is tuned with a single coefficient. Minimum area was also achieved by multi-rate signal processing and optimized test partitioning: Peak filter gain depends somewhat on the frequency and there is a slight non-linearity in the frequency vs. the control word. Correction involves some trigonometric functions and / or calibration which are easily calculated on a PC or ATE but not in hardware. A very efficient simulation and modeling strategy for RF circuits with large digital content had to be developed to simulate the interaction of the complete Σ∆PLL and SP-BIST including settling and phase noise performance with a standard VHDL simulator. One key point missing in prior works was the precise modeling of the combination of phase detector / charge pump and sampled loop filter model without beat frequency effects: Compensating the timing error due to the sampled filter model by scaling the amplitude of the filter input allowed correct simulation of e.g. the Σ∆FD performance and loop filter reference feedthrough at -106 dBc without slowing down the simulator. Synthesizable Design: All blocks of the SP-BIST except for the Σ∆FD have been described in VHDL, synthesized from library cells and placed and routed using the standard design flow. As a consequence, the BIST blocks merge seam- lessly with the other logic cells of the SOC, minimizing the design effort and maximizing the portability to different processes. The Σ∆FD is a fully digital

Christian Münker March 10, 2010 8.1. Comparison to Goals 181 block as well, but it has to be designed and laid out carefully by hand as it operates at the full RF speed of 4 GHz. This is especially true for the multi-modulus divider (MMD) as the core component of the Σ∆FD however, the additional design effort is minimal, as the MMD can be copied from the Σ∆PLL without changes.

Performance: A phase noise floor of the SP-BIST of -80 dBc/Hz and a SFDR of approximately 45 dB have been achieved, mainly limited by the spurious tones of the first order Σ∆FD which have been underestimated in the beginning. Fre- quency response measurements can be performed with an accuracy of 0.05 dB. This is achieved by calibrating the measurements against the baseband± response (Sec. 7.5.6), eliminating the ripple of the band-pass filter of 0.5 dB and other systematic error sources. ±

Area and Test Time Reduction: The additional silicon area for the SP-BIST is less than 0.06 mm2, requiring a test time reduction of 100 . . . 250 ms for break- even. Although current test strategies for embedded PLLs only allow indirect measurement of PLL bandwidth and cannot be compared directly to the SP-BIST, a test-time reduction in the range of 100 . . . 150 ms can be estimated, compensating the additional area. The improved test coverage for RF tests performed directly on the wafer also adds to the return-on-invest.

Summary

The goal of implementing an autonomous robust Spectral PLL BIST with minimum area has been achieved for performing frequency response measurements in the RF domain with high precision. This test covers many parametric faults that inﬂuence the bandwidth like loop ﬁlter time constants, gain of VCO, phase detector and charge pump.

However, it was seen that spurious sidebands of the first order Σ∆FD degrade measurements too much for a full verification of PLL sidebands, in-band noise and modulation mask against cellular standards specifications. This limits the practical use of the current implementation to PLL bandwidth measurements and some functional tests. Still, the presented concept is another step towards RF SOCs that are fully testable on digital testers. Its practical usability could be improved tremendously by a few minor changes described in the next section.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 182 8. Conclusion and Future Work

8.2. Future Work

Replacing the Σ∆FD with a second order Σ∆FD should give enough performance boost for full autonomous verification of in-band PLL phase noise and modulation mask, saving several 100 ms test time per PLL. This requires the design of an analog charge pump and comparator which have to be optimized carefully to achieve a robust yet compact design. While the performance of the other blocks is sufficient for the first order Σ∆FD the band-pass filter should be designed with somewhat longer coefficients to allow more precise tuning of the center frequency. The order of the first downsampling CIC filter should be increased, its decimation ratio decreased for a wider operating frequency range and less aliasing. These improvements can be implemented at the cost of a very moderate area increase. Speed-up of the test itself could be achieved by simultaneous multi-tone analysis using several resonators in parallel at the cost of additional chip area [PM91]. The BIST approach could be easily extended to a Spectral Built-In Self-Calibration (SP-BISC) by e.g. tuning the loop filter or the VCO bias point for optimum power consumption and phase noise performance. If necessary, silicon area of the SP-BIST could be further reduced by performing stimulus generation and / or spectral analysis off-chip e.g. in an FPGA in a combined BIST/BOST approach. However, this would mean sacrificing the concept of a fully autonomous BIST which means a higher development for test program and DUT test board; self-test and self-calibration of the finished application would no longer be possible. Test support for the measurement of out-of-band PLL noise would be a major step towards fully digital test of RF SOCs: For GSM applications, spurious emissions at offsets above 20 MHz have to be below -129 dBc/Hz for the TX band and even below -165 dBc(Hz) for the RX band (Fig. 3.9). Guaranteeing these numbers in production test currently requires expensive RF ATE and long measurement times, achieving this performance with DfT / BIST circuitry will be a another challenging research task. For technology nodes below 130 nm, the majority of PLLs will be all-digital, i.e. the VCO is replaced by a digitally controlled oscillator and the phase detector by a time-to-digital converter (TDC). These architectures offer new fully digital self-test opportunities by processing the digital output of the TDC, enabling bandwidth and in-band noise measurements in conjunction with the digital test-tone generator and the multi-rate tunable narrowband filter described in this work.

Christian Münker March 10, 2010 For every complex problem, there is a solution that is simple, neat, and wrong. H. L. Mencken A

VHDL Behavioral Models

A.1. Loop Filter

R2 R3 to VCO

R1 C1 C2 C3 I CP

CP Loop Filter

Figure A.1.: Non-Integrating loop ﬁlter with charge pump

The CT s-domain transfer function of the third order non-integrating loop ﬁlter in Fig. A.1) is given by (A.1.1): 184 A. VHDL Behavioral Models

1 H(s) = 3 2 with k33′ = R1R2R3C1C2C3, (A.1.1) k33′ s + k32′ s + k31′ s + 1

k32′ = C1C2R1R2 +C1C3R1R2 +C1C3R1R3 +C2C3R1R3 +C2C3R2R3

and k31′ = R1C2 + R2C2 + R1C3 + R2C3 + R3C3 + R1C1

It is translated to the z-domain using bilinear transform (A.1.2):

2 2 1 b33z− + b32z− + b31z− + 1 H(z) = K3 3 2 1 (A.1.2) a33z− + a32z− + a31z− + 1

1 with K3 = , k33 + k32 + k31 + 1 2 3 2 2 2 k = k , k = k , k = k 33 33′ T 32 32′ T 31 31′ T S S S a33 = K3 ( k33 + k32 k31 + 1), a32 = 3K3 (k33 k32 k31 + 3), − − − − a31 = K3 ( 3k33 k32 + k31 + 3) and b33 = 1, b32 = b31 = 3 − −

The sensitivity of the resulting direct form filter to coefficient truncation and quantization errors is not a problem as the VHDL model utilizes floating point arithmetics. The following listing shows the basic implementation of the DT loop filter model (A.1.2) in VHDL: constant TS : real := real(TS_2/fs) ∗ 5.0e 16; 1/2 sampling− interval −− constant TSS : real := TS ∗ TS ; TS ∗∗ 2 constant TSSS : real := TS ∗ TS ∗ TS ; −− TS ∗∗ 3 −− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−third order filter constants −−−−−−−−− −− −− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−constant k33 : real := C1 ∗ C2 ∗ C3 ∗ R1 ∗ R2 ∗ R3−−−−−−−−− / TSSS; constant k32 : real := (C1∗C2∗R1∗R2+C1∗C3∗R1∗R2+C1∗C3∗R1∗R3 + C2∗C3∗R1∗R3 + C2∗C3∗R2∗R3) / TSS; constant k31 : real := (R1∗C2+R2∗C2+R1∗C3+R2∗C3+R3∗C3+R1∗C1) / TS; constant K3 : real := 1.0 / (k33 + k32 + k31 + 1.0);

constant a33 : real := ( k33 + k32 k31 + 1.0) ∗ K3 ; constant a32 : real := ( 3.0 ∗−k33 k32 − k31 + 3.0) ∗ K3 ; constant a31 : real := ( 3.0 ∗ k33 − k32− + k31 + 3.0) ∗ K3 ; − − constant b33 : real := 1.0;

Christian Münker March 10, 2010 A.1. Loop Filter 185 constant b32 : real := 3.0; constant b31 : real := 3.0; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− LF : process (s_clk) begin if s_clk ’event then

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−Third Order Filter −−−−−−− −− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− mem3 <= mem2 ; mem2 <= mem1 ; mem1 <= CPval ∗ K3 a31 ∗ mem1 a32 ∗ mem2 a33 ∗ mem3 ; vtune <= CPval ∗ K3 − a31 ∗ mem1 − a32 ∗ mem2 − a33 ∗ mem3 −+ b31 ∗ mem1− + b32 ∗ mem2− + b33 ∗ mem3 ; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− end if ; event end process−−LF ;

The filter calculation is performed in the process LF each time the filter clock signal s_clk changes (s_clk’event), i.e. twice per clock period. This clock is defined in another autonomous process (not shown here) with an arbitrary frequency that should be 10x ... 20x higher than the maximum input frequency to achieve a reasonable accuracy of the filter characteristic without slowing down simulation too much. CPval is the state of the filter input, delivered by the charge-pump (current multiplied with the input resistor of the filter), it is calculated in yet another 1 process (also not shown). mem1 etc. correspond to the registers (z− in the block diagrams). The beat frequency effect between the phase detector switching and the filter clock is eliminated by the method described in section 4.5.2 in process LF_fr where the timing error between the last switching event of the phase detector / charge pump and the next sampling clock event is translated into a fractional filter input, i.e. the limited timing resolution of the sampled filter is exchanged for its nearly analog amplitude resolution. In process LF_fr, the time between the last switching of the phase detector / charge pump and the next sampling clock event is tracked and related to the sampling period (“fractional” period). The input value for the current filter cycle is then scaled with this value.

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−Loop filter model with correction of sampling error−−− −− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−LF_fr : process (s_clk , CP_i) −−−

variable TS_frac_v : real; fractional time step: −−

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 186 A. VHDL Behavioral Models

event delta time −− rel. to sampling period −− variable T_last_v : time; time of last calculation variable fracflag : boolean; −− fractional cycle? variable fracflag_d : boolean; −− prev. fractional cycle? −− begin if s_clk ’event or CP_i’event then

if (now T_last_v < TS_2t) then "fractional"− cycle: time since last event −− is less than TS: −−Ts_frac_v := real((now T_last_v)/fs)/ real((TS_2t)/fs); fracflag := true; − if CP_i = ’0’ then CP just switched off CPval <= Ts_frac_v ∗ CP_DC_c−− ; else CP just switched on CPval <= (1.0 Ts_frac_v) ∗−−CP_DC_c ; end if ; CP_i − else −− normal cycle −−if CP_i = ’1’ then CPval <= CP_DC_c; else CPval <= 0.0; end if ; CP_i fracflag_d−− := fracflag; store last fracflag fracflag := false; −− reset fracflag end if ; timestep −− −− if not fracflag_d then

T_last_v := NOW; don’t store timestep if the last one was a fractional −− one otherwise this cycle would be calculated twice .−− . . −

end if ; if not fracflag end if ; −−event end process−−LF_fr ;

A.2. Voltage Controlled Oscillator

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−Behavioral VCO model (excerpt) −− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−. . . begin p r o c e s s FREQ_GEN −− vco_out <= ’0’; period_t <= 300 ps; period_err_v := 0.0;

Christian Münker March 10, 2010 A.3. Random Number Generator 187

VCOLoop : loop

vco_out <= transport ’1’ after VCODelay , ’0’ after period_t/2 + VCODelay; wait for period_t ;

period_v := 1.0 / ((f_0 + kvco ∗ vtune_i) ∗ 1.0e 15) + period_err_v; −

period_t <= (period_v) ∗ f s ; period in fs −− calculate truncation error: period_err_v−− := period_v real ((period_v ∗ fs) / fs); calculate deviation− from target frequency: delta_f−− <= 1.0e15/period_id_v f_targ ; − end loop VCOLoop ; end process FREQ_GEN ;

vco_o <= vco_out;

A.3. Random Number Generator

A random number source with Gaussian distribution is needed to model random processes in VHDL. A simple modulus arithmetic algorithm [Jai91, p. 443], suitable for 32 bit integer arithmetic, produces a uniformly distributed pseudo- random sequence with a length of 231 2: −

x[n] = 75 x[n 1] mod (231 1) (A.3.1) · − −

Two uncorrelated uniform processes x1(n),x2(n) are transformed into two uncorrelated Gaussian processes xn,1[n],xn,2[n] using the approach described in [PM92, p. 944]. First, one of the processes is transformed into a random process xR,1(n) with Rayleigh distribution:

1 xR,1[n] = 2log (A.3.2) 1 x1[n] s −

From xR,1[n] and x2[n], two processes with Gaussian (normal) distribution (m = 0, σ = 1) can be derived:

xn,1[n] = xR,1[n]cos(2πx2[n]) (A.3.3)

xn,2[n] = xR,1[n]sin(2πx2[n]) (A.3.4)

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 188 A. VHDL Behavioral Models

The average value and standard deviation of xn,1[n],xn,2[n] are easily adapted by adding an offset m resp. scaling with a factor σ.

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Christian Münker March 10, 2010 List of Figures

1.1. Overview over DfT techniques ...... 5 1.2. Scanstructure...... 8 1.3. Scan ﬂip-ﬂop with test-logic overhead ...... 9 1.4. PrincipleofdigitalBIST ...... 14 1.5. PLL BIST for measuring cycle-to-cycle jitter ...... 17 1.6. On-chip phase noise measurement circuit ...... 18

2.1. Spectra of narrowband and wideband sinusoidal FM ...... 28 2.2. One-sided and two-sided spectra ...... 29 2.3. Phasors for small-angle PM/FM ...... 30 2.4. PSD of phase deviation and frequency deviation ...... 33 2.5. Basic slices of the signal xN ...... 36 2.6. Overlapping windowed slices of the signal xN ...... 37 2.7. Displayed PSD of noise signal ...... 38 2.8. Derivation of phase fluctuations from the VCO periods . . . . . 38 2.9. Spectral density of quantization noise ...... 41 2.10. Subsampling and frequency translation ...... 43 2.11. Delta modulation and demodulation ...... 44 2.12. (Sigma)-Delta modulation signal forms ...... 44 2.13. Sigma-Delta modulation and demodulation ...... 44 2.14. Sigma-Delta modulation (efficient implementation) ...... 45 2.15. Digital sigma-delta modulator ...... 45 2.16. Model for quantization noise in Σ∆Mbitstream ...... 46 2.17. Signal and noise transfer functions in first order Σ∆M...... 47 2.18. Nyquist rate, oversampling and Σ∆M converters ...... 48 2.19.SDMnoiseforDCinputs...... 49 2.20. Second order multi-loop SDM ...... 50 2.21. Second order multi-loop Σ∆M with a1 = a2 = 1...... 50 2.22. Equivalent second order single-loop SDM ...... 50 2.23. Quantization noise model for second order multi-loop SDM . . 51 2.24. Second order digital Σ∆M with multistage noise shaping . . . . 51 2.25. Stability region of a second order system ...... 53 2.26. Poles’ and zeros’ contribution ...... 54

203 204 List of Figures

2.27. Calculation of distance from pole ...... 55 2.28. Frequency response of the two-pole resonator ...... 56 2.29. Frequency response of the two-pole resonator ...... 57 2.30. Constant peak gain resonator ...... 58 2.31. Frequency response of the constant peak-gain biquad ...... 59 2.32. Band-pass filter specifications ...... 59 2.33. Estimation of resonator bandwidth ...... 60 2.34.Directformresonator ...... 61 2.35.LDIbasedresonator...... 62 2.36. Coupled-form resonator ...... 62 2.37. Fixed-point number representation ...... 63 2.38.Typesofdigitalfilters...... 65 2.39.TypeIIdirectformfilter ...... 66 2.40. Doubly terminated fourth order ladder LC band-pass filter . . . 67 2.41. Second order LC band-pass with SFG and DT simulation . . . . 68 2.42. Resonator based filter bank ...... 70 2.43. Singly terminated LC ladder filter bank ...... 71

3.1. Phase noise and spurious sidebands on the VCO output . . . . . 74 3.2. PLLblockdiagram ...... 75 3.3. PLL block diagram - control theory point of view ...... 75 3.4. Closed loop gain T( jω) and noise bandwidth Bn ...... 78 3.5. Principle of Σ∆-modulated| | PLL with predistortion ...... 79 3.6. Simulation of PLL lock-in with built-in self-calibration ..... 80 3.7. RMS phase error as a function of the open loop bandwidth . . . 81 3.8. Block diagram of quad band GSM transceiver ...... 82 3.9. Power spectral density mask for GSM 900 and DCS 1800 . . . . 83 3.10. RMS phase error as a function of the open loop gain error . . . . 84

4.1. Spectral PLL BIST Concept ...... 88 4.2. Principle of PLL bandwidth measurement ...... 89 4.3. MADBISTvs.SP-BIST ...... 91 4.4. Accuracy and Precision ...... 92 4.5. Block diagram of Fractional-N PLL ...... 95 4.6. Simulation setup for CUT and SP-BIST ...... 96 4.7. PLL simulation error due to sampled ﬁlter model ...... 96 4.8. Principle of fractional compensation ...... 97 4.9. Simulation of unmodulated Σ∆PLL tuning voltage ...... 101 4.10. Simulation of Σ∆PLLspectrum...... 102

5.1. Implementations for undamped digital resonators ...... 105

Christian Münker March 10, 2010 List of Figures 205

5.2. Oscillator based on analog integrators ...... 106 5.3. PrincipleofLDIbasedoscillator ...... 107 5.4. SDMattenuator ...... 109 5.5. LDI oscillator using Σ∆Mattenuator ...... 110 5.6. Two-tone LDI oscillator using Σ∆M attenuator ...... 111 5.7. Spectrum of two-tone signal (parallel output) ...... 111 5.8. Spectrum of two-tone signal (SDM bit stream) ...... 112 5.9. Fractional-N modulator with test tone generation ...... 114 5.10. Simulated phase spectrum of two-tone modulated PLL . . . . . 115 5.11. Single-tone modulation (measured with spectrum analyzer) . . . 116

6.1. Principle of analog swept spectrum analyzer ...... 118 6.2. Swept-tuned spectrum analysis ...... 119 6.3. Envelope detector ...... 119 6.4. Phase detector based phase noise measurement ...... 120 6.5. Frequency discriminator based phase noise measurement . . . . 121 6.6. Comparison of Σ∆M and Σ∆FD ...... 123 6.7. Principle of Σ∆FD (b), derived from Σ∆-Frac-N-PLL (a) . . . . 124 6.8. Signals in first order Σ∆FD: Transient view ...... 125 6.9. Signals in first order Σ∆FD: Phase view ...... 126 6.10. Multi-modulus divider ...... 127 6.11. Linearized model for multi-modulus divider phase ...... 128 6.12. 1st order Σ∆FDmodel ...... 130 6.13. Two-tone spectrum at Σ∆FDoutput ...... 131 6.14. Two-tone spectrum at Σ∆FD output (zoomed in) ...... 131 6.15. 2nd order Σ∆FD(simplified) ...... 132 6.16. Swept filter spectrum analyzer ...... 133 6.17. Principle of on-chip spectral PLL analysis ...... 135 6.18. Block diagram of spectral estimation ...... 136 6.19. 2nd orderCICasanti-aliasingfilter ...... 137 6.20. Hogenauer filter ...... 138 6.21. Second order downsampling CIC filter with dump and reset . . . 138 6.22. Transfer function and aliasing of downsampling CIC filter . . . 139 6.23. Two-tone spectrum at Σ∆FDoutput ...... 140 6.24. Σ∆Mquantization noise after CIC filtering ...... 141 6.25. Simulated Σ∆FD output spectrum with CIC filtering ...... 142 6.26.LDIbasedresonator...... 143 6.27. Resonator based filter with constant B or constant Q ...... 145 6.28. Transfer functions of resonator based filter with constant BW . . 146 6.29. Resonator based bandpass with constant peak gain ...... 147 6.30. Bandpass gain and scalloping loss of 2nd order resonator . . . . 147

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters 206 List of Figures

6.31. -3 dB and -60 dB bandwidth of different band-pass ﬁlters . . . . 149 6.32. Bandpass gain and scalloping loss of 4th order resonator . . . . 150

7.1. Frequency of LDI oscillator ...... 155 7.2. Amplitude error of LDI based oscillator ...... 156 7.3. Schematic of Σ∆FD...... 157 7.4. Multi-modulus divider made from a chain of 2/3 divider cells . . 157 7.5. High-speed 2/3 divider cell with modulus enable ...... 158 7.6. Dynamic high-speed flip-flop ...... 159 7.7. LayoutofMMD...... 161 7.8. RF PLL under test with SP-BIST ...... 162 7.9. Block diagram of multimode RF transceiver ...... 163 7.10. Unmodulated PLL spectrum with and without active Σ∆FD . . . 164 7.11. Spectrum of two-tone generator (different filter staggering) . . . 166 7.12. Unmodulated PLL spectrum with Σ∆FD spurious tones . . . . . 168 7.13. Single-tone modulated PLL spectrum ...... 170 7.14. Two-tone modulated PLL spectrum (frequency sweep avg.) . . . 171 7.15. Comparison of baseband and RF output response analysis . . . . 172

A.1. Non-Integrating loop ﬁlter with charge pump ...... 183

Christian Münker March 10, 2010 List of Tables

2.1. Examples for binary encoding ...... 64 2.2. Qualitative comparison of digital ﬁlter families ...... 72

5.1. SNR of two-tone generator depending on bandwidth BW . . . . 113

6.1. Passband droop and alias rejection of CIC ﬁlters ...... 140 6.2. Resonance frequency for fS,R = 812.5kHz...... 144 6.3. Bandpass properties at k f = 1( fc = 135.4 kHz) ...... 148 6.4. Variation of bandpass properties over 10 . . . 200 kHz ...... 150

7.1. Frequencies of programmable tones ...... 154 7.2. Amplitudes of programmable tones ...... 156 7.3. Silicon area of SP-BIST blocks ...... 160 7.4. Reproducibility of SP-BIST measurements ...... 167 7.5. Output frequency response measurements ...... 173 7.6. Programmingregisters ...... 177

207 208 List of Tables

Christian Münker March 10, 2010 Index

Symbols analog...... 14 hybrid...... 15 Σ∆PLL..... see PLL, Sigma-Delta logic...... 13 modulated memory...... 14 mixed analog-digital ...... 15 A oscillation...... 14 spectralPLL ...... 90 accuracy...... 22 built-off self-test...... 13, 20 ACF. .see auto-correlation function analog scan chain...... 10 C ATE...... 3 auto-correlation function. . . .17, 36 cascaded integrator-comb filter 136 automated test equipmemt see ATE center frequency...... 55 CICfilter...... see cascaded B integrator-comb filter circuit under test...... 11 backward Euler integrator . . . . . 105 clock-and-data recovery ...... 17 bandwidth cumulative distribution function . 17 half-power...... 60 CUT...... see circuit under test modulation...... 25 normalized...... 60 D relative ...... 60 bias...... 22 damping...... 77 BILBO . . . . see built-in logic block DDS....see direct digital synthesis observer decimation...... 42 biquad...... 57 defect...... 7 biquadratic transfer function . . . . 57 bridging...... 8 BISC . . see built-in self-calibration Design-for-Test ...... 2, 6 BIST...... see built-in self-test device under test...... 11 bit-errorrate...... 18 DfT...... see Design-for-Test BOST ...... see built-off self-test direct digital synthesis ...... 104 built-in logic block observer . . . . 14 DOT...... see test, defect-oriented built-in self-calibration ...... 3, 79 downsampling ...... 42, 122, 136 built-in self-test ...... 2, 13, 20, 79 DUT...... see device under test

209 210 Index

F I failure...... 7 idletones...... 49,167 fault...... 7 L catastrophic ...... 9 hard...... 9 LFSR...... see linear-feedback parametric ...... 10 shift-register soft...... 10 linear-feedback shift-register . . . 13 stuck-at...... 8 loopbacktest...... 11 stuck-open ...... 8 loop gain transit frequency . . . . . 77 faultmodel...... 7 lossless digital resonator ...... 62 feature extraction...... 11 ﬁlter M cascaded...... 66 non-recursive...... 135 MADBIST. . . .see built-in self-test, parallel ...... 67 mixed analog-digital, 90 recursive...... 135 messagesignal...... 24 SOS)...... 66 modulation index wavedigital...... 69 frequency...... 25 ﬁlterbank ...... 70 modulation signal ...... 24 forward Euler integrator...... 105 Moore’slaw ...... 2 Fourier transform...... 36 multiple-input signature register 14 frequency N carrier...... 23 instantaneous ...... 24 narrowband approximation . . . . . 27 modulation...... 28 natural frequency ...... 77 nominal...... 23 network offset...... 28 prototype ...... 68 resonance ...... 144 reference...... 68 frequency deviation ...... 24 noise bandwidth ...... 78, 150 peak...... 25 relative ...... 24 O frequency discriminator sigma-delta ...... 156 ORA. .see output response analysis frequency instability ...... 32 output response analysis...... 13 frequency modulation gain . . . . . 24 P

G periodogram...... 36 averaged...... 36 Goertzel algorithm ...... 134 phase

Christian Münker March 10, 2010 Index 211

instantaneous ...... 24 sigma delta modulation ...... 123 nominal...... 23 signal-flow graph...... 69 phasedeviation ...... 23f. signature...... 13f. phase instability...... 32 small angle approximation...... 27 phase modulation gain ...... 24 SPOT...... see test, specification phasenoise...... 32 oriented phase-locked loop ...... see PLL subsampling...... 42, 122 PLL...... 3 system Sigma-Delta modulated. . . . . 3 LTI...... 22 poleangle...... 53 shift-invariant ...... 22 poleradius...... 53 power spectral density ...... 36 T PRBS. . .see pseudo-random binary sequence test precision ...... 22 alternate...... 11 probability density function. . . . .17 defect-oriented...... 4 pseudo-random binary sequence 14 functional...... 4 RFstructural...... 10 Q specification oriented ...... 4 structural...... 4 qualityfactor...... 60 translation...... 11 testinsertion...... 19 R testvector...... 7 test-pattern generation ...... 13 resolution...... 22 time-to-digital converter ...... 123 resolution bandwidth ...... 83 TPG.... see test-pattern generation resonance frequency ...... 55 tranfer function noise ...... 47 S signal...... 47 sampling rate U effective...... 110 scallopingloss ...... 147 uncertainty ...... 22 scan chain undersampling...... 42 analog...... 10 SDFD . see frequency discriminator, W sigma-delta SDM . see Sigma Delta Modulation wavevariable...... 69 selectivity ...... 58 shapefactor...... 58 sigma delta frequency discrimination...... 122

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters