Logic Design 10CS33

Question Bank

Unit 1

Digital Principles, Digital Logic

1. Define: i) Rise time ii) Fall time iii) Period and iv) Frequency. (July 15) (8 Marks) 2. What is an universal gate? List the Universal gates and prove their universalities. (July 15) (6 Marks) 3. Write the verilog code for given expression. Y=AB+CD (July 15) (6Marks) 4. Using Karnaugh Map,simplify the following boolean expression and give the implementation of the same using

i)NAND gates only(SOP) ii) NOR gates only (POS )

F(w,x,y,z)=¦m(0,1,2,4,5,12,14)+dc(8,10) (Dec 14 / Jan 15) 10 Marks

5. Mention the Universal gates? Implement with respect to the basic gates. (Dec 14 / Jan 15) 10 Marks 6. Define Logic. Explain different types of logic. ( July 14) 10 Marks

7. Differentiate between Analog and Digital Signals. ( July 14) 10 Marks

8. Using Karnaugh Map,simplify the following boolean expression and give the implementation of the same using i)NAND gates only(SOP)

ii) NOR gates only (POS )

a. F(w,x,y,z)=¦m(0,1,2,4,5,12,14)+dc(8,10)

F(w,x,y,z)=¦m(0,1,2,4,5,12,14)+dc(8,10) (Dec 13/ Jan14) 8 Marks

9. Explain Duality Theorem? (Dec 13/ Jan14) 4 Marks

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Logic Design 10CS33

10. What are Universal gates? Implement the basic gates using Universal gates only. (Dec 13/ Jan14) 8 Marks 11. Name universal gates. Realize basic gates using NAND Gates. (July 13) 10 Marks 12. Explain positive and negative logic. (July 13) 10 Marks

Unit-2 Combinational Logic Circuits

1. Using K-map find the reduced SOP form of f(A,B,C,D)=∑M(5,6,7,12,13)+∑d(4,9,14,15).

(July 15) (5 marks) 2. What is hazard? List the types of hazards and explain static_0 and static-1 hazards. (July 15) (5 Marks) 3. Simplify the following using Mc-Cluskey method f=∑M(0,1,2,8,10,11,14,15). (July 15) (10 Marks) 4. Find the prime implicant with the help of Qunie-Mc Clusky Method. F(W,X,Y,Z) = ∑m(1,3,6,7,8,9,10,12,13,14) (Dec 14/Jan 15) ) (10 Marks)

5. Does circuit in below figure experience hazard? If so, verify the same with timing diagram Explain the significance of Demorgan’s theorem (Dec 14 / Jan 15) 10 Marks

6. What is a karnaugh map? State the limitations of karnaugh map. (July 14) 10 Marks 7. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC. (July 14) 10 Marks 8. Implement the following SOP function F = XZ + Y’Z + X’YZ Compare TTL and CMOS families and the integration level of ICs (Dec 13/ Jan14) 10 Marks

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Logic Design 10CS33

9. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC. (Dec 13/ Jan14) 10 Marks 10. Find the prime implicant with the help of Qunie-Mc Clusky Method. F(W,X,Y,Z) = ∑m(1,3,6,7,8,9,10,12,13,14) (July 13) 10 Marks

11. Define impliant. Explain prime and essential prime implicants with example. (July 13)10 Marks

Unit 3

Data-Processing Circuits

1. Implement the following function using a 8:1 multiplexer: f(a,b,c,)= ∑M(0,1,3,4). (July 15) (10 Marks)

2. Realize the following function using the 3:8 decoder F1(A,B,C)= ∑M(1,2,3,4) , F2(A,B,C)= ∑M(3,5,7). (July 15) (6 Marks) 3. What is a magnitude comparator? Explain with a neat block diagram an n-bit magnitude comparator (July 15) 4marks.

4. Implement 4:1 mux using 2:1 mux (Dec 14 /Jan 15) 10 Marks 5. What is a Multiplexer. Design a 4:1 multiplexer using gate. (Dec 14 /Jan 15) 10 Marks 6. Explain the 8 word X 4 bit ROM with the help of block diagram. (July 14) 8 Marks 7. Explain the Implementation of Full adder using PLA (July 14) 6 Marks 8. Differentiate between PROM, PAL, PLA (July 14) 8 Marks 9. Show that using a 3-to-8 decoder and multi input OR gate. The following Boolean expression can be realized.F1(A,B,C) = Σm(1,2,4,5), F2(A,B,C) = Σm(1,5,7)

(Dec13 / Jan 14) 10 Marks

10. Implementation of F(A,B,C,D)=∑ (m(1,3,5,7,8,10,12,13,14), d(4,6,15)) By using a 16- to-1 multiplexer. (Dec13 / Jan 14) 10 Marks

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Logic Design 10CS33

11. Design 16 to 1 multiplexer using two 8 to 1 multiplexer and one 2 to 1 multiplexer. (July 13) 6 Marks. 12. Explain n bit magnitude comparator (July 13) 8 Marks. 13. Design 7 segment decoder using PLA (July 13) 6 Marks

Unit 4

Clocks, Flip-Flops

1. With a neat block diagram, explain the working of a Master-Slave Jk flip flop. Also write its truth table. (July 15) (10 Marks) 2. Define: i)Flip flop ii) Hold time iii) Set up time iv)Characteristic equation. (July 15) (10 Marks)

3. Show how SR flip flop can be converted to a JK flip flop. (Dec 14 /Jan 15) 10 Marks 4. Write HDL design of D-Flip flop (Dec 14 /Jan 15) 10 Marks 5. With the help of a neat diagram explain the working of a Master Slave JK flip flop (July 14) 10 Marks 6. What do you mean by characteristic equation of a flip-flop? Derive characteristic equation for SR flip flop (July 14) 10 Marks

7. With the help of block diagram, explain the working of a JK Master-Slave flip flop. (Dec13 / Jan 14) 10 Marks 8. Differentiate between combinational circuit and sequential circuit. (Dec13 / Jan 14) 10 Marks 9. Explain Schmitt trigger (July 13) 6 Marks 10. Give transition diagram of JK and T Flip flops. (July 13) 8 Marks 11. Show how a D flip flop converted into JK flipflop (July 13) 6 Marks

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Logic Design 10CS33

Unit-5

Registers

1. Draw the logic diagram of a 4-bit serial in serial out shift register using J-K flip flop and explain. (July 15) (8 Marks)

2. Explain briefly serial adder with a neat sketch. (July 15) (8 Marks) 3. Write a verilog code for switched tail counter. (July 15) (4 Marks) 4. Explain Johnson Counter with neat diagram and timing diagram (Dec14 / Jan 15) 10 Marks 5. Write verilog code for Shift Register. (Dec14 / Jan 15) 10 Marks 6. Give applications of J-K flip-flops. (July 14) 10 Marks 7. Draw the general block diagram of multivibrator. (July 14 ) 10 Marks 8. Explain a 4 bit universal shift register in detail and give its timing diagram.

(Dec13 / Jan 14) 10 Marks

9. With neat timing diagram, explain the working of a 4-bit SISO register. (Dec13 / Jan 14) 10 Marks 10. Design a 3 bit PISO(DFlip flop) (July 13)6 marks 11. Design two 4 bit serial adder. (July 13) 6marks 12. Design a 4 bit Johnson counter with sate table. (July 13)8 marks

Unit-6 Counters

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Logic Design 10CS33

1. Briefly explain 3-bit binary ripple up-counter. Also write the truth table and waveform. (July 15) (10 Marks) 2. Design a modulo-5 up counter (synchronous) using J-K flip flop. (July 15) (10 Marks) 3. Design Mod 8 Johnson Counter. (Dec14 / Jan 15) 10 Marks 4. Difference between Asynchronous and Synchronous Counter. (Dec14 / Jan 15) 10 Marks 5. Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input, start input and ‘done’ output. The counter should produce ‘done’ output after completion of

counter in either direction. (July 14.) 10 Marks 6. Draw the logic circuits and the excitation tables for the T, JK flip-flops.

( July 14) 10 Marks

7. Design a 3 bit synchronous counter with the help of D flip flop. (Dec13 / Jan 14) 10 Marks 8. Design Mod 4 ring counter. (Dec13 / Jan 14) 10 Marks 9. Design a synchronous mod 6 up counter using JKflip flop. (July 13 ) 10 Marks. 10. Explain Digital clock with block Diagram. (July 13) 10 Marks

Unit-7

Design of Synchronous and Asynchronous Sequential Circuits

1. With neat block diagram compare mealy model of sequential logic system. (July 15) (8 Marks) 2. Draw the ASM chart for vending machine problem using Mealy mlodel. (July 15) (12 Marks) 3. For the given state diagram, draw the state reduction diagram. (Dec14 / Jan 15) 10 Marks

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Logic Design 10CS33

4. Difference between Mealy Model and Moore Model of Synchronous Sequential Circuit. (Dec14 / Jan 15) 10 Marks

6. Difference between Mealy Model and Moore Model of Synchronous Sequential Circuit. (Dec13 / Jan 14) 10 Marks 7. For the given state diagram, draw the state reduction diagram. (Dec13 / Jan 14) 10 Marks

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Logic Design 10CS33

8. Explain about all the notation of state machine. (July 13 ) 10 Marks.

Unit -8

D/A Conversion and A/D Conversion

1. Explain the concept of “Successive approximation’” of a A/D converter. (July 15) (10 Marks) 2. Draw a binary ladder network for a digital input 1000 and obtain its equivalent circuit. (July 15) (10 Marks) 3. Comment on the parameters which serve to describe the quality of performance of a D/A converter. (Dec14 / Jan 15) 10 Marks

4. With the help of a neat diagram explain parallel A/D converter. (Dec14 / Jan 15) 10 Marks 5. Explain the operation of successive approximation type of ADC (July 14) 10 Marks 6. An 8-bit successive approximation converter (SAC) has a resolution of 15 mV What will its, digital output be for an analog input of 2.65 V? (July 14 ) 10 Marks

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Logic Design 10CS33

7. Give performance parameters of DAC or D/A converters. (Dec13 / Jan 14) 10 Marks

8. An 4 bit DIA converter has an output range of 0 to 1.5 V. Define its resolution. (Dec13 / Jan 14) 10 Marks 9. Explain with logic diagram 3 bit simultaneous A/D converters. (July 13) 10 Marks 10. Explain with logic diagram Single-slope A/D converters ( July 13) 10 Marks

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