Title: Extended Abstract Formatting Instructions for the Technical Digest of the International

RF-WLR Investigations on 0.5 µm AlGaN/GaN HEMTs 1. 2. Bernd Schauwecker*, Simon Stolz, and Hervé Blanck

United Monolithic Semiconductors, Wilhelm-Runge-Straße 11, 89081 Ulm, Germany *e-mail: bernd.schauwecker(at)ums-ulm.de, Phone: +49-731-505-3083

Keywords: AlGaN/GaN HEMTs, RF-WLR, RF Stress Test, On Wafer Reliability

Abstract the RF WLR investigations a two finger device with a gate This paper presents the results of RF wafer level width of 1mm was used. reliability (WLR) investigations on 0.5 µm AlGaN/GaN HEMT devices at different measurement conditions. RF-WLR TEST BENCH Temperature, voltage and compression level were varied. The test bench consists of a thermo chuck to perform the INTRODUCTION tests under high temperature conditions, RF probes to contact the transistors on wafer, bias tees and DC power GaN wide-bandgap semiconductors are an attractive supplies. A generator in combination with an amplifier material for high power and high efficiency microwave delivers a continuous wave RF signal to the input of the applications due to high breakdown voltages, high sheet DUT. The impedance on the load side can be varied by a carrier density and good thermal conductivity. UMS has mechanical tuner. Output power is measured by means of a developed and qualified an industrial AlGaN/GaN 0.5 µm 20 dB attenuator and a power meter. A personal computer gate length HEMT process for power applications up to controls the components and logs the data. Figure 1 shows a 7 GHz. RF stress tests are more and more important for schematic of the test bench. power amplifier applications. Knowledge of parameter behavior at different operation conditions, such as temperature, compression levels and also the behavior by using different quiescent points is important. The long term stability and the knowledge of the variations of the main RF parameters (e.g., power and gain) and the shift of DC parameters (e.g., leakage, threshold voltage, and Schottky diode stability) are important for the development of new technologies and the modification of existing technologies in production lines. UMS has developed a WLR test bench using a RF signal, variable load impedance at the output of Figure 1: Schematic of the test bench (from [1]) the device under test (DUT) and a high temperature chuck (thermo chuck) [1]. Calibration: In order to setup the required load impedance at the TECHNOLOGY AND FABRICATION output of the DUT, a 1 port OSL calibration to the measuring plane was done. After that probes I and II are The utilized epitaxial structures consist of a GaN cap connected via a through so that the load impedance can be layer and an undoped AlGaN barrier layer grown on an configured with the mechanical tuner. To correct the insulating GaN buffer. The layers were grown on a 4” semi- measured power by the loss between probe II and the power insulating 4H SiC substrate by MOVPE. For the fabrication meter the 2-port S-parameters of the load side path have to of ohmic contacts a Ti/Al based metallization was utilized. be determined. Therefore two sets of 2-port S-parameters are Device isolation was achieved by ion implantation. A measured. The first set consists of the path from probe II to dielectric-assisted gate module was used to achieve high the mechanical tuner. yield on large periphery devices for power applications. A calibration method of such a path is explained in [2]. According to this processing scheme, 0.5 µm gate foot This method sums up all unknowns such as mismatching and openings are defined in the dielectric by optical lithography cable loss into a black box representation which includes all and subsequent dry-etching. In a second step the gate head is error terms. This leads to a signal flow chart which is shown realized. A source terminated field plate after the dielectric in Figure 2. gate module protection concludes the device fabrication. For The used test device is a 2-finger device with 2x500 µm gate width. Diode GD 1.E+00 1.E-01 Diode GD before 1.E-02 Diode GD after 1.E-03 ]

A 1.E-04 [

I 1.E-05 1.E-06 1.E-07 1.E-08 Figure 2: Simplified signal flow chart [2] 1.E-09 1.E-10 The solution for the mathematical relation between the 1.E-11 1.E-12 reflection factor at the measurement plane M and the -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 reflection factor at the output of the DUT  is: Vgs [V] (1) Figure 4: Drain Schottky Diode behaviour before/after RF stress test at 30C (2) with (3) Test results at different temperature: The equation can be solved by measuring three known Table 1 shows the used stress temperatures. The standards. This is done by measuring the three known maximum chuck temperature is 175 °C. The utilized voltage calibration standards (OSL).The second set consists of the and current levels do not have a major impact on the device attenuator and the cable that connects the power meter. This temperature due to self-heating. Our Raman measurements can be easily done with a NWA [need to define NWA]. The have shown a temperature increasing up to 5 – 10 °C. The next step is to determine the power at the input of the DUT. used load resistance (RLoad) configuration was not changed To do this, probe I is again connected to probe II via a by using different stress conditions. through and a power sweep at the signal generator is performed. By measuring the output power with the power Temperature Ids (DC) Compression Vds [V] Rload [Ω] meter and the known loss of the load side path, the power at [°C] [mA] [dB] the input of the DUT can be calculated. 30 7 50 140+j80 6.0 50 7 50 140+j80 6.1 RF WLR MEASUREMENTS AND RESULTS 100 7 50 140+j80 5.8 150 7 50 140+j80 6.0 This test has been implemented as a standard test to 175 7 50 140+j80 6.0 control the RF behavior of our GaN HEMTs in UMS 150 7 75 140+j80 5.5 production line and also for development engineering. Table 1: used stress conditions with different temperatures Standard stress conditions are: Tchuck = 150 °C, stress voltage VD = 50 V and compression level 6 dBm. Stress times up to A linear behavior in output power could be observed at

500 hr (see Figure 3) were used. We could observe a nearly different temperatures (Figure 5) with Vds = 50 V. After 50 logarithmic behavior versus stress time of more than 1 hr to hr stress time a higher power reduction for temperatures the maximum stress time. above 150 °C is visible (Figure 6). At lower stress temperatures, the reduction of the measured output power (Pout) is around 0.2 W/mm, this being the same as the measurement accuracy of the test setup. 6.8 6.6 6.4 ] 6.2 W [

1 5.8 _ t

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P 5.4 5.2 Figure 3: Power degradation of GaN HEMTs at Tcase = 150 °C for VD = 50 V 5 and 6 dB compression (> 450 hr) 4.8 30 50 100 150 175 During the test the RF output power, the DC current and Tem perature [°C] Figure 5: Output power after50 1 min stress at different temperatures voltage at the input and output are monitored. Additionally after stress time [h] (VDS = 50 V) the DUT is characterized before and after the RF stress test 1R002 Wafer GH50 2x500um _V1 at Tchuck = 30 °C. This enables us to investigate the impact of basic electrical parameters such as leakage current, threshold E222214 Lotcode voltage, Schottky diode behavior (Figure 4), amongst others. higher than 50 °C. than 50°C. higher saturation 14%. the to up of voltage drain decrease maximum the a and transconductance observed current, We 8. Figure in given is parameter (Idss) current saturation drain the of time stress the stress hr 50 after on variation the example, dependency an As temperature. clear a shown also have °C 30 at tests stress the after and before measured parameters DC (V 7: Figure after drop higher a shown have Figure 7. see °C), 100 (> temperatures higher using dBm by time stress hr 50 25 at Measurements gain. the is parameter RF important Another 6: Figure diinl ivsiain ee udrae t different overview about the variations.2 gives an at undertaken Table temperatures. different two at and levels compression were investigations Additional Compression level 8: Figure IDSS_Delta[%] [mA/mm] ΔGain_25dBm [dB] ΔPout [W] DS DS -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.45 -0.35 -0.25 -0.15 -14 -12 -10 = 50V) -0.5 -0.4 -0.3 -0.2 -0.1 -8 -6 -4 -2 0    Pout after 50 hr stress at different temperatures (V 50hr different after at temperatures Pout stress Idss (%) after 50 hr stress at different temperatures stress(V 50hr different Idss (%)after at 30 30 an2dm atr 5 r srs t dfeet tmeaue temperatures different at stress hr 50 after Gain_25dBm 30 The degradation starts at stress temperatures stress at starts degradation The 50 50 50 : : H0250m_V1 2x500um GH50 H0250m_V1 2x500um GH50 H0250m_V1 2x500um GH50 E222214 E222214 E222214 1R002 1R002 1R002 100 100 100 50 50 50 150 150 150 175 175 175 Lotcode Wafer [h] e tim stress after [°C] perature Tem Lotcode Wafer [h] e tim stress after [°C] perature Tem Lotcode Wafer [h] e tim stress after [°C] perature Tem DS DS = 50V) DS DS = 50V) Table 2: used stress conditions with different used compressions conditions stress Table 2: compression level and showsbehavior. a levellinear and compression and temperature the stress with increases higher Pout in The difference The power. given. output the is on influence stronger time a has stress temperature hr 50 after and power output the of difference the 9 Figure In in IDSS parameter for 6 dB compression and 175 °C T for 175 °C compression parameter IDSS 6dB in and 8% to up degradation calculate could We 11). (Figure levels compression higher at more degrades the IDSS) for define conditions – (IDSS interesting current an saturation drain shows The parameters behavior. DC the of analysis The 10: Figure dB). (0.6 gain in loss of amount same the to leads power output the a of degradation The dBm. 0.6 is temperatures only chuck two used shows the between @25dBm) difference The 10 dependence. temperature (Figure power output The 9: Figure ΔPout_25dBm [dB] ΔPout [dB] -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.35 -0.25 -0.15 -0.3 -0.2 -0.1 0   1.9 Pout_0dBm after 50 hr stress at differentlevels afterat compression stress 50hr Pout_0dBm 1.9 Pout_25dBm after 50 hr stress at differentlevels afterat compression stress 50hr Pout_25dBm Temperature Temperature [°C] 175 175 175 50 50 50 3.9 50 3.9 50 Ids (DC)Ids 6.1 [mA] 6.1 Sibylle_04 Sibylle_04 7 7 7 7 7 7 1R002 1R002 Vds [V] Vds 2.1 2.1 50 50 50 50 50 50 Rload [Ω] Rload 140+j80 140+j80 140+j80 140+j80 140+j80 140+j80 175 3.8 175 3.8 Compression Compression 6 6 [dB] 2.1 3.8 6.0 1.9 3.9 6.1 Lotname Wafer [°C] perature Tem [dBc] pression Com Compression [dBc] Compression Lotname Wafer [°C] Temperature  Pout before Pout chuck . Table 3: used stress conditions with different drain voltages with different used drain conditions stress Table 3: W/mm and drops down after 50 hr stress time about 1.6 about time stress hr 50 after down drops and 11.6 of W/mm power the output °C high very 50 the and at V starts 100 measurement At example. for power, output the increases voltage drain the Increasing 3). (Table undertaken were voltages drain different with investigations Additional voltagesDifferent drain 12: Figure 30-fold µA/mm70µA/mm,increase.few upto a a from degrades T leakage gate higher the levels at compression lower but 12), (Figure behavior this see we dB 6 of level compression standard the With observed. be should degradation slight a only case best the In parameter. DC important very a is behavior leakage Schottky-gate The 11: Figure h an a 5 d erds aon . B u with (Figure 14). at 25dBm dB But 1.25 dB. around degrades and more much 0.7 drops gain the drain, around the degrades at V 75 using and °C dB 150 to temperature the increasing 25 at gain also the drop power the to comparison In 13). (Figure W/mm Temperature Temperature IgLeak_Delta[abs] [μA/mm] IDSS_Delta[abs] -70 -60 -50 -40 -30 -20 -10 10

20 [mA/mm] 0 10 15 20 25 30 35 [°C] 150 0 5 50 50   1.9 1.9 Gate leakage after atcompression stress 50hr Gatelevels leakage different levels different afterat compression stress IDSS 50hr Ids(DC) [mA] 3.9 50 3.9 50 7 7 7 Vds [V] Vds 6.1 Sibylle_04 6.1 100 Sibylle_04 75 50 1R002 : : 1R002 2.1 Rload [Ω] Rload 2.1 140+j80 140+j80 140+j80 175 3.8 175 3.8 Compression Compression 6 [dB] 6 5.5 6.0 6.0 Lotname Wafer [°C] perature Tem [dBc] pression Com Lotname Wafer [°C] perature Tem [dBc] pression Com chuck and SUMMARY Figure 13: Figure field accelerated / temperature accelerated) can result. can accelerated) acceleratedtemperature / field the during (electric mechanism degradation increase the of mixture a and stress will higher temperature the device to the due voltage, Additionally, itself. mechanism stress to change the could conditionstress thisthat noted beshould It up case our V. 100 to V 50 from in voltage drain the changing by increases, 2 factor device the of the power voltages, output stress the increasing by drain important However, higher voltages. at of pronounced degradation more the is parameters that transistor see we conclude, To was °C 150 at V 75 measured. = Vd at 16% to compare V 50 = Vd at 9% of drop power output An stress. the during voltages drain higher using by power output more and gain in seen degradation have we investigation through our In relaxation formation. strain defect to leading value may critical strain total exceed and fields higher at expands effect. AlGaN piezoelectric The inverse through AlGaN defect induced in field formation electric the that proposed was [4] In the and °C 175 175°C. 3.6%to at at °C power 8% 50 at 0.2% to The from increases °C transconductance data. maximum 50 our at 2% analyzing from by increases observed we effect same be The °C. 150 could at eV 0.39 to °C 50 at using eV 1 by from higher decreases energy magnitude activation The temperatures. of higher orders two trap the is condition stress generation RF under that shown was [3] In temperatures 14: Figure ΔGain_25dBm [dB] ΔPout [W] -1.4 -1.2 -0.8 -0.6 -0.4 -0.2 -1.8 -1.6 -1.4 -1.2 -0.8 -0.6 -0.4 -0.2 -1 -1 0 0 

 OF Pout after 50hr temperatures different after at Vdsand Pout stress an @ 2 B atr 5 r srs t dfeet Vs and Vds different at stress hr 50 after dB 25 @ Gain

THE 50 50 50 50

RESULTS Sibylle_04 Sibylle_04 1R002 1R002 150 150 75 75 100 100 50 50 Vds [V] Vds [°C] perature Tem Lotname Wafer Lotname Wafer [V] Vds [°C] perature Tem Please list all the other acronyms used in your text CONCLUSIONS

In this work we have demonstrated the device behavior of 0.5 µm AlGaN/GaN HEMT´s at different RF-WLR stress test conditions.

REFERENCES [1] P. Abele, et.al, High Frequency Wafer Level Reliability Test Bench with Variable Load Impedance”, CS MANTECH Conference, May 18th-21st, 2009, Tampa, Florida, USA [2] Rytting, Doug: Network Analyzer Error Models and Calibration Methods, pp. 11-13 [3] Koudymov et al.,Phys.Stat.Solidi 1,116(2007) [4] del Alamo, IEEE IEDM, IEEE EDL 29,287(2008)

ACRONYMS HEMT: High electron mobility transistor DUT: device under test