University of California s16

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

Dejan Markovic EECS 141 Fall 2005 Project 2 Speed/Area Optimized 8-bit Adder Design

Due Monday, December 5, 11pm

Project Description The goal of this project is to design an 8-bit adder with minimum delay-layout area product. No registers (i.e. pipelining) are allowed in the design of this adder. As in the first project, work in a group of 2 students. If you have specific problems finding a partner, please let Instructor or the TAs know. No need to sign up. For systematic approach, you can organize your work in three phases. In phase-1, use the design expertise you acquired in class to find the optimum adder architecture that best optimizes the speed-area goal. Do a quick sketch of several feasible options and figure out the best architecture and circuit style. You may mix circuit styles if that helps. In phase-2, first implement the block-level schematic of the adder and verify the functionality in HSPICE. Then, identify critical path and optimize sizing for minimum delay. In the critical path evaluation, you need to determine not only the gates along the path, but also the input operands that cause worst- case delay between input and output bits. Think of the area as a way of choosing optimal circuit topology. Once you do so, you don’t need to back-off in timing to save area (maybe a chance for some extra credit). In phase-3, refine your rough layout sketch from phase-1 and layout the adder starting with basic building blocks. Area is defined as the smallest bounding box a design can fit in. Layout aspect ratio (long / short side) should be less than 1.5. Below is more detailed explanation of the steps you need to take to ensure the success of your project.

Phase 1: Choosing Adder Topology / Circuit Style (1 week) a) Determine adder topology that optimizes delay-area metric. b) Choose logic style for the implementation. You may mix several logic families. c) Implement the block-level adder in Cadence and move on to phase-2.

Phase 2: Critical Path Delay Optimization (1/2 week) a) Check functionality of the adder in HSPICE. b) Identify input vectors that will exercise critical path. Size the gates for minimum delay. c) Verify the critical path delay in HSPICE under worst-case input operands.

EECS141: FALL 05—PROJECT 2 1 Phase 3: Layout and Verification in HSPICE (1 week) a) Create layout of the adder and make sure it passes DRC and LVS. b) Extract post-layout netlist and verify critical path in HSPICE. c) Submit pre-layout and post-layout netlists. We will run LVS on your design.

Phase 4: Sleep (Dec 5, 8 hours) The purpose of this task is to ensure that you will be able to clearly present your work! The goal is to get through few REM cycles and come to your presentation relaxed. You do not have to minimize the number of REM cycles multiplied by the time you spend in each.

Final Presentation (1/2 week) Prepare a 6-slide presentation (template to be provided soon) representing your effort. Sign up for a 7’ slot. Present your results to Instructor and the TAs. Be crisp: show what your main decisions have been, explain why they are the best thing in the world, and prove that they really worked out (or did not).

Constraints (READ CAREFULLY!) a) Supply voltage: 2.5V b) Implementation choices: i. Use only static logic (e.g. CMOS, pass-transistor logic, …). You can use dynamic logic for 10% extra credit (provided that your overall optimization goal is met). c) Input operands: i. Both operands are 8-bit numbers. There is an incoming carry at bit position zero. d) Loading conditions: i. The input capacitance of all inputs is less than equal to 2 unit sized inverters (per bit). For simulation purposes, the inputs to your adder are driven by a unit sized buffer (chain of two unit sized inverters). The delay is measured as the delay after the input driver (2 inverters) to before the load (16 inverters).

ii. Each sum bit and final carry out at MSB is loaded with CL = 16 unit sized inverters. Similar to project 1, implement this load with inverters. Also add another load of 64 at the output of load gates to suppress Miller kick-back. iii. Unit sized inverter is Wp = 0.96m, Wn = 0.48m, Lp = Ln = 0.24m. e) Layout constraints: i. Minimum width of Vdd/Gnd rails is 0.96m. ii. You can use all metal layers.

HAVE FUN!

EECS141: FALL 05—PROJECT 2 2