High Speed, Video Difference Amplifier AD830

FEATURES CONNECTION DIAGRAM Differential Amplification 8-Lead Plastic PDIP (N), Wide Common-Mode Voltage Range: +12.8 V, –12 V CERDIP (Q) and SOIC (RN) Packages Differential Voltage Range: 2 V High CMRR: 60 dB @ 4 MHz Built-In Differential Clipping Level: 2.3 V X1 1 AD830 8 V Fast Dynamic Performance P G 85 MHz Unity Gain Bandwidth M X2 2 7 OUT 35 ns Settling Time to 0.1% A = 1 360 V/ s Slew Rate Y1 3 6 NC Symmetrical Dynamic Response GM C Excellent Video Specifications Y2 4 5 VN Differential Gain Error: 0.06% Differential Phase Error: 0.08 NC = NO CONNECT 15 MHz (0.1 dB) Bandwidth Flexible Operation High Output Drive of 50 mA Min input and produces an output voltage referred to a user-chosen Specified with Both 5 V and 15 V Supplies level. The undesired common-mode signal is rejected, even at Low Distortion: THD = –72 dB @ 4 MHz high frequencies. High impedance inputs ease interfacing to Excellent DC Performance: 3 mV Max Input finite source impedances and thus preserve the excellent com- Offset Voltage mon-mode rejection. In many respects, it offers significant APPLICATIONS improvements over discrete difference amplifier approaches, in Differential Line Receiver particular in high frequency common-mode rejection. High Speed Level Shifter The wide common-mode and differential voltage range of the High Speed In-Amp AD830 make it particularly useful and flexible in level shifting Differential to Single-Ended Conversion applications, but at lower power dissipation than discrete solu- Resistorless Summation and Subtraction tions. Low distortion is preserved over the many possible High Speed A/D Driver differential and common-mode voltages at the input and output. GENERAL DESCRIPTION Good gain flatness and excellent differential gain of 0.06% and The AD830 is a wideband, differencing amplifier designed for phase of 0.08° make the AD830 suitable for many video system use at video frequencies but also useful in many other applica- applications. Furthermore, the AD830 is suited for general- tions. It accurately amplifies a fully differential signal at the purpose signal processing from dc to 10 MHz.

110 9 V = 5V 6 S 100 RL = 150 3 90 CL = 33pF 0 80 VS = 15V –3 CL = 4.7pF 70 –6 GAIN – dB CMRR – dB 60 –9 VS = 5V –12 50 CL = 15pF –15 40 –18

30 –21 1k 10k 100k 1M 10M 10k 100k1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz Figure 1. Common-Mode Rejection Ratio vs. Frequency Figure 2. Closed-Loop Gain vs. Frequency, Gain = +1 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD830–SPECIFICATIONS (VS = 15 V, RLOAD = 150 , CLOAD = 5 pF, TA = 25 C, unless otherwise noted.)

AD830J/AD830A AD830S1 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC CHARACTERISTICS

3 dB Small Signal Bandwidth Gain = +1, VOUT = 100 mV rms 75 85 75 85 MHz 0.1 dB Gain Flatness Frequency Gain = +1, VOUT = 100 mV rms 11 15 11 15 MHz Differential Gain Error 0 V to 0.7 V, Frequency = 4.5 MHz 0.06 0.09 0.06 0.09 % Differential Phase Error 0 V to 0.7 V, Frequency = 4.5 MHz 0.08 0.12 0.08 0.12 Degrees

Slew Rate 2 V Step, RL = 500 Ω 360 360 V/µs 4 V Step, RL = 500 Ω 350 350 V/µs 3 dB Large Signal Bandwidth Gain = +1, VOUT = 1 V rms 38 45 38 45 MHz Settling Time, Gain = +1 VOUT = 2 V Step, to 0.1% 25 25 ns VOUT = 4 V Step, to 0.1% 35 35 ns Harmonic Distortion 2 V p-p, Frequency = 1 MHz –82 –82 dBc 2 V p-p, Frequency = 4 MHz –72 –72 dBc Input Voltage Noise Frequency = 10 kHz 27 27 nV/√Hz Input Current Noise 1.4 1.4 pA/√Hz DC PERFORMANCE Offset Voltage Gain = +1 ±1.5 ±3 ±1.5 ±3mV

Gain = +1, TMIN – TMAX ±5 ±7mV Open-Loop Gain DC 64 69 64 69 dB

Gain Error RL = 1 kΩ, G = ± 1 ±0.1 ±0.6 ±0.1 ±0.6 % Peak Nonlinearity, RL= 1 kΩ, –1 V ≤ X ≤ +1 V 0.01 0.03 0.01 0.03 % FS Gain = +1 –1.5 V ≤ X ≤ +1.5 V 0.035 0.07 0.035 0.07 % FS –2 V ≤ X ≤ +2 V 0.15 0.4 0.15 0.4 % FS

Input Bias Current VIN = 0 V, 25°C to TMAX 510510µA VIN = 0 V, TMIN 713817µA Input Offset Current VIN = 0 V, TMIN – TMAX 0.1 1 0.1 1 µA INPUT CHARACTERISTICS

Differential Voltage Range VCM = 0 ±2.0 ±2.0 V Differential Clipping Level2 Pins 1 and 2 Inputs Only ±2.1 ±2.3 ±2.1 ±2.3 V

Common-Mode Voltage Range VDM = ±1 V –12.0 +12.8 –12.0 +12.8 V CMRR DC, Pins 1, 2, ± 10 V 90 100 90 100 dB DC, Pins 1, 2, ±10 V,

TMIN – TMAX 88 86 dB Frequency = 4 MHz 55 60 55 60 dB Input Resistance 370 370 kΩ Input Capacitance 2 2 pF OUTPUT CHARACTERISTICS

Output Voltage Swing RL ≥ 1 kΩ±12 +13.8, –13.8 ±12 +13.8, –13.8 V RL ≥ 1 kΩ, ±16.5 VS ±13 +15.3, –14.7 ±13 +15.3, –14.7 V Short-Circuit Current Short to Ground ±80 ±80 mA

Output Current RL = 150 Ω±50 ±50 mA POWER SUPPLIES Operating Range ±4 ±16.5 ±4 ±16.5 V

Quiescent Current TMIN – TMAX 14.5 17 14.5 17 mA + PSRR (to VP) DC, G = +1 86 86 dB – PSRR (to VN) DC, G = +1 68 68 dB PSRR DC, G = +1, ±5 to ±15 VS 66 71 66 71 dB PSRR DC, G = +1, ±5 to ± 15 VS, TMIN – TMAX 62 68 60 68 dB NOTES 1See Standard Military Drawing 5962-9313001MPA for specifications. 2Clipping level function on X channel only. Specifications subject to change without notice.

–2– REV. B AD830

SPECIFICATIONS (VS = 5 V, RLOAD = 150 , CLOAD = 5 pF, TA = +25 C, unless otherwise noted.) AD830J/AD830A AD830S1 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC CHARACTERISTICS

3 dB Small Signal Bandwidth Gain = +1, VOUT = 100 mV rms 35 40 35 40 MHz 0.1 dB Gain Flatness Frequency Gain = +1, VOUT = 100 mV rms 5 6.5 5 6.5 MHz Differential Gain Error 0 V to 0.7 V, Frequency = 4.5 MHz, Gain = +2 0.14 0.18 0.14 0.18 % Differential Phase Error 0 V to 0.7 V, Frequency = 4.5 MHz, Gain = +2 0.32 0.4 0.32 0.4 Degrees

Slew Rate, Gain = +1 2 V Step, RL = 500 Ω 210 210 V/µs 4 V Step, RL = 500 Ω 240 240 V/µs 3 dB Large Signal Bandwidth Gain = +1, VOUT = 1 V rms 30 36 30 36 MHz Settling Time VOUT = 2 V Step, to 0.1% 35 35 ns VOUT = 4 V Step, to 0.1% 48 48 ns Harmonic Distortion 2 V p-p, Frequency = 1 MHz –69 –69 dBc 2 V p-p, Frequency = 4 MHz –56 –56 dBc Input Voltage Noise Frequency = 10 kHz 27 27 nV/√Hz Input Current Noise 1.4 1.4 pA/√Hz DC PERFORMANCE Offset Voltage Gain = +1 ±1.5 ±3 ±1.5 ±3mV

Gain = +1, TMIN – TMAX ±4 ±5mV Open-Loop Gain DC 60 65 60 65 dB

Unity Gain Accuracy RL = 1 kΩ±0.1 ±0.6 ±0.1 ±0.6 % Peak Nonlinearity, RL= 1 kΩ –1 V ≤ X ≤ +1 V 0.01 0.03 0.01 0.03 % FS –1.5 V ≤ X ≤ +1.5 V 0.045 0.07 0.045 0.07 % FS –2 V ≤ X ≤ +2 V 0.23 0.4 0.23 0.4 % FS

Input Bias Current VIN = 0 V, 25°C to TMAX 510510µA VIN = 0 V, TMIN 713817µA Input Offset Current VIN = 0 V, TMIN – TMAX 0.1 1 0.1 1 µA INPUT CHARACTERISTICS

Differential Voltage Range VCM = 0 ±2.0 ±2.0 V Differential Clipping Level2 Pins 1 and 2 Inputs Only ±2.0 ±2.2 ±2.0 ±2.2 V

Common-Mode Voltage Range VDM = ±1 V –2.0 +2.9 –2.0 +2.9 V CMRR DC, Pins 1, 2, +4 V to –2 V 90 100 90 100 dB DC, Pins 1, 2, +4 V to –2 V,

TMIN – TMAX 88 86 dB Frequency = 4 MHz 55 60 55 60 dB Input Resistance 370 370 kΩ Input Capacitance 2 2 pF OUTPUT CHARACTERISTICS

Output Voltage Swing RL ≥ 150 Ω±3.2 ±3.5 ±3.2 ±3.5 V RL ≥ 150 Ω, ±4 VS ±2.2 –2.4, +2.7 ±2.2 –2.4, +2.7 V Short-Circuit Current Short to Ground –55, +70 –55, +70 mA Output Current ±40 ±40 mA POWER SUPPLIES Operating Range ±4 ±16.5 ±4 ±16.5 V

Quiescent Current TMIN – TMAX 13.5 16 13.5 16 mA + PSRR (to VP) DC, G = +1, Offset 86 86 dB – PSRR (to VN) DC, G = +1, Offset 68 68 dB PSRR (Dual-Supply) DC, G = +1, ±5 to ±15 VS 66 71 66 71 dB PSRR (Dual-Supply) DC, G = +1, ±5 to ± 15 VS, TMIN – TMAX 62 68 60 68 dB NOTES 1See Standard Military Drawing 5962-9313001MPA for specifications. 2Clipping level function on X channel only. Specifications subject to change without notice.

REV. B –3– AD830

ABSOLUTE MAXIMUM RATINGS1 MAXIMUM POWER DISSIPATION Supply Voltage ...... ±18 V The maximum power that can be safely dissipated by the AD830 Internal Power Dissipation2 ...... Observe Derating Curves is limited by the associated rise in junction temperature. For the Output Short-Circuit Duration . . . . . Observe Derating Curves plastic packages, the maximum safe junction temperature is Common-Mode Input Voltage ...... ±VS 145°C. For the CERDIP, the maximum junction temperature is Differential Input Voltage ...... ±VS 175°C. If these maximums are exceeded momentarily, proper Storage Temperature Range (Q) ...... –65°C to +150°C circuit operation will be restored as soon as the die temperature Storage Temperature Range (N) ...... –65°C to +125°C is reduced. Leaving the AD830 in the overheated condition for Storage Temperature Range (RN) ...... –65°C to +125°C an extended period can result in permanent damage to the Operating Temperature Range device. To ensure proper operation, it is important to observe AD830J ...... 0°C to +70°C the recommended derating curves. ° ° AD830A ...... –40 C to +85 C While the AD830 output is internally short-circuit protected, ° ° AD830S ...... –55 C to +125 C this may not be sufficient to guarantee that the maximum junc- ° Lead Temperature Range (Soldering 60 sec) ...... 300 C tion temperature is not exceeded under all conditions. If the NOTES output is shorted to a supply rail for an extended period, then 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- the amplifier may be permanently destroyed. nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-Lead PDIP Package: ␪JA = 90°C/W. 8-Lead SOIC Package: ␪JA = 155°C/W. 8-Lead CERDIP Package: ␪JA = 110°C/W.

ORDERING GUIDE Model Temperature Range Package Description Package Option AD830AN –40°C to +85°C 8-Lead PDIP N-8 AD830JR 0°C to +70°C 8-Lead SOIC RN-8 5962-9313001MPA* –55°C to +125°C 8-Lead CERDIP Q-8 AD830AR –40°C to +85°C 8-Lead SOIC RN-8 AD830AR-REEL –40°C to +85°C 8-Lead SOIC RN-8 AD830AR-REEL7 –40°C to +85°C 8-Lead SOIC RN-8 AD830JR-REEL 0°C to 70°C 8-Lead SOIC RN-8 AD830JR-REEL7 0°C to 70°C 8-Lead SOIC RN-8 *See Standard Military Drawing 5962-9313001 MPA for specifications.

2.5 3.0 2.8 TJ MAX = 175 C T MAX = 145C J 2.4 2.0 2.2 2.0

1.5 1.8 8-LEAD PDIP 1.6 1.4

1.0 1.2 8-LEAD CERDIP 1.0 0.8 0.5 TOTAL POWER DISSIPATION – W TOTAL POWER DISSIPATION – W 8-LEAD SOIC 0.6 0.4 0 0.2 –50 –30 –10 10 30 50 70 90 –60 –40 –20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE – C AMBIENT TEMPERATURE – C Figure 3. Maximum Power Dissipation vs. Figure 4. Maximum Power Dissipation vs. Temperature, PDIP and SOIC Packages Temperature, CERDIP Package

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD830 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B Typical Performance Characteristics–AD830

110 100

100 90 TO VP @ 15V TO VP @ 5V 90 80 TO VN @ 15V 70 80 VS = 15V 60 TO V @ 5V 70 N 50 CMRR – dB 60 PSRR – dB VS = 5V 40 50 30 40 20

30 10 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz TPC 1. Common-Mode Rejection Ratio vs. Frequency TPC 4. Power Supply Rejection Ratio vs. Frequency

–50 3

VOUT = 2V p-p R = 150 0 L GAIN = +1 15V –3 –60 5V SUPPLIES R = 150 10V SECOND HARMONIC –6 L THIRD HARMONIC CL = 4.7pF –9

–70 –12

GAIN – dB –15 15V SUPPLIES SECOND HARMONIC –18 5V –80 THIRD HARMONIC HARMONIC DISTORTION – dBc –21

–24

–90 –27 1k 10k100k 1M 10M 10k 100k1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 2. Harmonic Distortion vs. Frequency TPC 5. Closed-Loop Gain vs. Frequency G = +1

9 3

5VS 8 2

A 1 7 10VS 0 6 –1 15VS 5 INPUT CURRENT – –2

4 INPUT OFFSET VOLTAGE – mV –3

3 –4 –60 –40 –20 0 20 4060 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE – C JUNCTION TEMPERATURE – C TPC 3. Input Bias Current vs. Temperature TPC 6. Input Offset Voltage vs. Temperature

REV. B –5– AD830

0.10 0.10 0.20 0.40 GAIN = +2 GAIN = +2 R = 500 0.09 L 0.09 0.18 RL= 150 0.36 FREQ = 4.5MHz FREG = 4.5MHz 0.08 0.08 0.16 0.32

0.07 0.07 0.14 0.28

0.06 0.06 0.12 0.24

0.05 0.05 0.10 0.20 PHASE 0.04 0.04 0.08 GAIN 0.16

DIFFERENTIAL GAIN – % 0.03 0.03 0.06 0.12 DIFFERENTIAL GAIN – % 0.02 GAIN 0.02 0.04 PHASE 0.08 DIFFERENTIAL PHASE – Degrees DIFFERENTIAL PHASE – Degrees 0.01 0.01 0.02 0.04

5 6 7 8 9 10 11 12 13 14 15 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE – V SUPPLY VOLTAGE – V TPC 7. Differential Gain and Phase vs. Supply TPC 10. Differential Gain and Phase vs. Supply Voltage, RL = 500 ⍀ Voltage, RL = 150 ⍀

–40 –40

–50 –50 HD2 5V 4MHz –60 –60

HD3 5V –70 –70 4MHz HD3 5V 100kHz HD3 15V –80 100kHz –80 HD2 15V 4MHz HARMONIC DISTORTION – dB HARMONIC DISTORTION – dB –90 –90 HD3 15V HD2 5V HD2 15V 4MHz 100kHz 100kHz –100 –100 0.25 0.50 0.751.00 1.25 1.50 1.75 2.00 0.25 0.50 0.751.00 1.25 1.50 1.75 2.00 PEAK AMPLITUDE – V PEAK AMPLITUDE – V TPC 8. Harmonic Distortion vs. Peak Amplitude, TPC 11. Harmonic Distortion vs. Peak Amplitude, Frequency = 100 kHz Frequency = 4 MHz

50 15.00

14.75

14.50 Hz 40 14.25 14.00 16.5VS

13.75 30 13.50

13.25

20 13.00 5VS INPUT VOLTAGE NOISE – nV/ 12.75

QUIESCENT SUPPLY CURRENT– mA 12.50 10 12.25 1001k 10k 100k 1M 10M –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz JUNCTION TEMPERATURE – C TPC 9. Noise Spectral Density TPC 12. Supply Current vs. Junction Temperature

–6– REV. B AD830

3 9 V1 1 AD830 8 VP 0 6 GM 15V 2 A=1 7 OUT –3 3 RL = 150 3 C = 0pF 6 –6 L 0 GM C 4 5 VN –9 –3 5V –12 –6 VOUT = 2V1 (a) –15 –9 RESISTORLESS GAIN OF 2

–18 –12 1 AD830 8 VP GAIN OF 2 CONNECTION UNITY GAIN CONNECTION GM –21 –15 2 A=1 7 OUT –24 –18 V1 3 6 G C –27 –21 M 100k 1M10M 100M 1G 4 5 VN FREQUENCY – Hz

TPC 13. Closed-Loop Gain vs. Frequency for the VOUT = V1 Three Common Connections of Figure 16 OP AMP CONNECTION (b)

8 V V1 1 AD830 P GM 2 A=1 7 OUT 100mV 3 6 VS = 5V GM C 100 4 5 VN 90

VOUT = V1 GAIN OF 1 (c) TPC 16. Connection Diagrams VS = 15V

10 1V 0% VS = 5V 20ns 100 90

TPC 14. Small Signal Pulse Response, RL = 150 ⍀, CL = 4.7 pF, G = +1

VS = 15V

9 10 VS = 5V 0% 6 RL = 150 20ns 3 CL = 33pF 0 TPC 17. Large Signal Pulse Response, R = 150 ⍀, CL = 15pF L –3 CL = 4.7 pF, G = +1 CL = 4.7pF –6 9 GAIN – dB –9 VS = 15V 6 RL = 150 –12 CL = 33pF 3 C = 15pF –15 L 0 –18 –3 CL = 4.7pF –21 10k 100k1M 10M 100M 1G –6 FREQUENCY – Hz

GAIN – dB –9 TPC 15. Closed-Loop Gain vs. Frequency vs. CL, G = +1, –12 VS = ±5 V –15

–18

–21 10k 100k1M 10M 100M 1G FREQUENCY – Hz

TPC 18. Closed-Loop Gain vs. Frequency vs. CL, G = +1, VS = ±15 V REV. B –7– AD830

TRADITIONAL DIFFERENTIAL AMPLIFICATION ADVANTAGEOUS PROPERTIES OF THE AD830 In the past, when differential amplification was needed to reject • High common-mode rejection ratio (CMRR) common-mode signals superimposed with a desired signal, most • High impedance inputs often the solution used was the classic op amp based difference • Symmetrical dynamic response for +1 and –1 Gain amplifier shown in Figure 5. The basic function VO = V1 – V2 is • Low sensitivity to the value of source R simply achieved, but the overall performance is poor and the • Equal input impedance for the + and – input circuit possesses many serious problems that make it difficult • Excellent high frequency CMRR to realize a robust design with moderate to high levels • No halving of the bandwidth of performance. • Constant power distortion versus common-mode voltage • Highly matched resistors not needed R1 R2 V 2 UNDERSTANDING THE AD830 TOPOLOGY The AD830 represents Analog Devices’ first amplifier product to embody a powerful alternative amplifier topology. Referred to R3 VOUT V1 as active feedback, the topology used in the AD830 provides inherent advantages in the handling of differential signals, dif- R 4 ONLY IF R1 = R2 = R3 = R4 fering system commons, level shifting, and low distortion, high DOES V OUT = V1 – V2 frequency amplification. In addition, it makes possible the implementation of many functions not realizable with single op Figure 5. Op Amp Based Difference Amplifier amp circuits or superior to op amp based equivalent circuits. With this in mind, it is important to understand the internal PROBLEMS WITH THE OP AMP BASED APPROACH structure of the AD830. • Low common-mode rejection ratio (CMRR) The topology, reduced to its elemental form, is shown in Figure 7. • Low impedance inputs Nonideal effects, such as nonlinearity, bias currents, and limited • CMRR highly sensitive to the value of source R full scale, are omitted from this model for simplicity, but are dis- • Different input impedance for the + and – input cussed later. The key feature of this topology is the use of two, • Poor high frequency CMRR identical voltage-to-current converters, G , that make up input • Requires very highly matched resistors R – R to achieve M 1 4 and feedback signal interfaces. They are labeled with inputs V and high CMRR X V , respectively. These voltage-to-current converters possess fully • Halves the bandwidth of the op amp Y differential inputs, high linearity, high input impedance, and wide • High power dissipation in the resistors for large common- voltage range operation. This enables the part to handle large mode voltage amplitude differential signals; it also provides high common-mode rejection, low distortion, and negligible loading on the source. The AD830 FOR DIFFERENTIAL AMPLIFICATION label G is meant to convey that the transconductance is a large The AD830 amplifier was specifically developed to solve the M signal quantity, unlike in the front end of most op amps. The two listed problems with the discrete difference amplifier approach. G stage current outputs, I and I , sum together at a high imped- Its topology, discussed in detail in the Understanding the AD830 M X Y ance node—which is characterized by an equivalent resistance and Topology section, by design acts as a difference amplifier. The capacitance connected to an “ac common.” A unity voltage gain circuit of Figure 6 shows how simply the AD830 is configured stage follows the high impedance node to provide buffering to produce the difference of the two signals, V and V , in 1 2 from loads. Relative to either input, the open-loop gain, A , is which the applied differential signal is exactly reproduced at the OL set by the transconductance, G , working into the resistance, output relative to a separate output common. Any common- M R ; A = G × R . The unity gain frequency ␻ for the open- mode voltage present at the input is removed by the AD830. P OL M P 0 dB loop gain is established by the transconductance, GM, working into the capacitance, CC; ␻0 dB = GM/CC. The open-loop descrip- V 1 → tion of the AD830 is shown below for completeness. V I V2 I X Vx1 GM Vx2 IX A = 1 VOUT IZ A = 1 VOUT IY

I Y IX = (Vx1 – V x2)GM → VY1 V I VOUT = V1 – V2 IY = (VY1 – V Y2)GM GM C R IZ = IX + IY VY2 C P

GM RP Figure 6. AD830 as a Difference Amplifier AOLS = 1 + S(CCRP) Figure 7. Topology Diagram

–8– REV. B AD830

VMAX Vx1 GM Vx2 IX VCM VPEAK A = 1 VOUT I Y CC VY1 Figure 9. Common-Mode Definition GM VY2 15 +VCM Vx1 – V x2 = V Y2 – V Y1 FOR V Y2 = V OUT 1 15V = V

V S VOUT = (Vx1 – V x2 + V Y1) 12 1 + S(CC/GM) –VCM

Figure 8. Closed-Loop Connection +VCM 9 Precise amplification is accomplished through closed-loop operation of this topology. Voltage feedback is implemented 10V = VS 6 –VCM via the Y GM stage where the output is connected to the –Y input for negative feedback, as shown in Figure 8. An input +VCM signal is applied across the X GM stage, either fully differentially

COMMON-MODE VOLTAGE – COMMON-MODE VOLTAGE 3 or single-ended referred to common. It produces a current 5V = VS signal that is summed at the high impedance node with the –VCM output current from the Y GM stage. Negative feedback nulls 0 this sum to a small error current necessary to develop the output 0 0.4 0.8 1.2 1.6 2.0 DIFFERENTIAL INPUT VOLTAGE – V PEAK voltage at the high impedance node. The error current is usually negligible, so the null condition essentially forces the Y GM Figure 10. Input Common-Mode Voltage Range output stage current to exactly equal the X GM output current. vs. Differential Input Voltage Since the two transconductances are identical, the differential Differential Voltage Range voltage across the Y inputs equals the negative of the differential The maximum applied differential voltage is limited by the voltage across the X input; VY = –VX or more precisely VY2 – VY1 = clipping range of the input stages. This is nominally set at 2.4 V VX1 – VX2. This simple relation provides the basis to easily ana- magnitude and depicted in the cross plot (X-Y) in Figure 11. lyze any function possible to synthesize with the AD830, including The useful linear range of the input stages is set at 2 V but is any feedback situation. actually a function of the distortion required for a particular

The bandwidth of the circuit is defined by the GM and the application. The distortion increases for larger differential input capacitor CC. The highly linear GM stages give the amplifier a voltages. A plot of relative distortion versus the input differential single-pole response, excluding the output amplifier and loading voltage is shown in TPCs 8 and 11. The distortion characteris- effects. It is important to note that the bandwidth and general tics could impose a secondary limit to the differential input dynamic behavior is symmetrical (identical) for the noninverting voltage for high accuracy applications. and the inverting connections of the AD830. In addition, the input impedance and CMRR are the same for either connection. This is very advantageous and unlike in a voltage or current 1V 1V feedback amplifier where there is a distinct difference in 100 performance between the inverting and noninverting gain. The 90 practical importance of this cannot be overemphasized and is a key feature offered by the AD830 amplifier topology.

INTERFACING THE INPUT

Common-Mode Voltage Range 10 The common-mode range of the AD830 is defined by the 0% amplitude of the differential input signal and the supply voltage. The general definition of common-mode voltage, VCM, is usually applied to a symmetrical differential signal centered around a Figure 11. Clipping Behavior particular voltage, as illustrated in Figure 9. This is the mean- ing implied here for common-mode voltage. The internal Choice of Polarity circuitry establishes the maximum allowable voltage on the input The sign of the gain is easily selected by choosing the polarity of or feedback pins for a given supply voltage. This constraint the connections to the + and – inputs of the X GM stage. Swap- and the differential input voltage sets the common-mode volt- ping between inverting and noninverting gain is possible simply age limit. Figure 10 shows a curve of the common-mode by reversing the input connections. The response of the ampli- voltage range versus the differential voltage for three supply fier is identical in either connection, except for the sign change. voltage settings.

REV. B –9– AD830

The bandwidth, high impedance, and transient behavior of the versus the peak output differential voltage can be easily derived AD830 is symmetrical for both polarities of gain. This is very from the maximum output swing as VOCM = VMAX – VPEAK. advantageous and unlike an op amp. 15 Input Impedance The relatively high input impedance of the AD830, for a differ- ential receiver amplifier, permits connections to modest impedance V 12 sources without much loading or loss of common-mode rejection. VP The nominal input resistance is 300 kΩ. The real limit to the VN upper value of the source resistance is in its effect on common- 9 mode rejection and bandwidth. If the source resistance is in only one input, then the low frequency common-mode rejection 6 will be lowered to ≈ RIN/RS. The source resistance/input capaci- tance pole

MAXIMUM OUTPUT SWING – 3  1  fRC=××  2π SIN 0 limits the bandwidth. 020481216 SUPPLY VOLTAGE – V Furthermore, the high frequency common-mode rejection will be additionally lowered by the difference in the frequency Figure 12. Maximum Output Swing vs. Supply × response caused by the RS CIN pole. Therefore, to maintain Output Current good low and high frequency common-mode rejection, it is The absolute peak output current is set by the short-circuit recommended that the source resistances of the + and – inputs current limiting, typically greater than 60 mA. The maximum be matched and of modest value (≤10 kΩ). drive capability is rated at 50 mA, but without a guarantee of Handling Bias Currents distortion performance. Best distortion performance is obtained The bias currents are typically 4 µA flowing into each pin of the by keeping the output current ≤20 mA. Attempting to drive Ω GM stages of the AD830. Since all applications possess some large voltages into low valued resistances (e.g., 10 V into 150 ) finite source resistance, the bias current through this resistor will cause an apparent lowering of the limit for output signal will create a voltage drop (IBIAS × RS). The relatively high input swing but is just the current limiting behavior. impedance of the AD830 permits modest values of RS, typically Driving Cap Loads ≤10 kΩ. If the source resistance is in only one terminal, then an The AD830 is capable of driving modest sized capacitive loads objectional offset voltage may result (e.g., 4 µA × 5 kΩ = 20 mV). while maintaining its rated performance. Several curves of Placement of an equal value resistor in series with the other input bandwidth versus capacitive load are given in TPCs 15 and 18. will cancel the offset to first order. However, due to mismatches The AD830 was designed primarily as a low distortion video in the resistances, a residual offset will remain and likely be speed amplifier, but with a trade-off, i.e., giving up very large greater than the bias current (offset current) mismatches. capacitive load driving capability. If very large capacitive loads Applying Feedback must be driven, the network shown in Figure 13 should be used The AD830 is intended for use with gains from 1 to 100. Gains to ensure stable operation. If the loss of gain caused by the greater than one are simply set by a pair of resistors connected resistor RS in series with the load is objectionable, the as shown in the difference amplifier (Figure 21) with gain >1. optional feedback network shown may be added to restore the The value of the bottom resistor R2 should be kept less than 1 kΩ lost gain. to ensure that the pole formed by CIN and the parallel connec- +VS tion of R1 and R2 is sufficiently high in frequency so that it does not introduce excessive phase shift around the loop and destabi- 0.1F AD830 lize the amplifier. A compensating resistor, equal to the parallel 1 8 VCM INPUT R G S combination of R1 and R2, should be placed in series with the SIGNAL M 36.5 VOUT 2 7 other Y GM stage input to preserve the high frequency common- R ZCM A = 1 C1 1 mode rejection and to lower the offset voltage induced by the 100pF 1k input bias current. 3 6 GM C Output Common Mode 4 5 *OPTIONAL FEEDBACK 0.1F The output swing of the AD830 is defined by the differential NETWORK R input voltage, the gain, and the output common. Depending on –VS S the anticipated signal span, the output common (or ground) may be set anywhere between the allowable peak output voltage R2 in a manner similar to that described for input voltage common mode. A plot of the peak output voltage versus the supply is Figure 13. Circuit for Driving Large Capacitive Loads shown in Figure 12. A prediction of the common-mode range

–10– REV. B AD830

3 However, it is also necessary as in any electronic system to 0 15V provide a return path for bias currents back to their original power supply. This is accomplished by providing a connection –3 5V between the differing grounds through a modest impedance –6 labeled ZCM (e.g., 100 Ω). –9 Single-Supply Operation –12 The AD830 is capable of operating in single power supply

–15 applications down to a voltage of 8 V, with the generalized connection shown in Figure 16. There is a constraint on the –18 common-mode voltage at the input and output that estab- –21 lishes the range for these voltages. Direct coupling may be used

–24 for input and output voltages that lie in these ranges. Any gain

CLOSED-LOOP AMPLITUDE RESPONSE – dB network applied needs to be referred to the output common –27 10k 100k 1M 10M 100M connection or have an appropriate offset voltage. In situations FREQUENCY – Hz where the signal lies at a common voltage outside the common- Figure 14. Closed-Loop Response vs. Frequency mode range of the AD830, direct coupling will not work, so ac with 100 pF Load and Series Resistor Compensation coupling should be used. Figure 28 shows how to easily accom- plish coupling to the AD830. For single-supply operation where SUPPLIES, BYPASSING, AND GROUNDING (FIGURE 15) direct coupling is desired, the input and output common-mode The AD830 is capable of operating over a wide range of supply curves (Figures 17 and 18) should be used. voltages, both single and dual supplies. The coupling may be dc V or ac provided the input and output voltages stay within the P specified common-mode voltage limits. For dual supplies, the AD830 device works from ±4 V to ±16.5 V. Single-supply operation is 1 8 V GM possible over 8 V to 33 V. It is also possible to operate the part IN VOUT with split-supply voltages (e.g., +24 V, –5 V) for special applica- 2 7 A = 1 tions such as level shifting. The primary constraint is that the VICM 3 6 total potential between the two supplies does not exceed 33 V. GM C Inclusion of power supply bypassing capacitors is necessary to 4 5 achieve stable behavior and the specified performance. It is especially important when driving low resistance loads. At minimum, connect a 0.1 µF ceramic capacitor at the supply lead V = (V – V ) + V V of the AD830 package. In addition, for the best bypassing, it is OUT IN ICM OCM OCM best to connect a 0.01 µF ceramic capacitor and 4.7 µF tanta- lum capacitor to the supply lead going to the AD830. Figure 16. General Single-Supply Connection

V V P P 30 AND AND 28 VN VN 0.1F 0.01F 4.7F V V = +30V P LOAD 24 GND LEAD LOAD GND 20 LEAD 16 VP = +15V Figure 15. Supply Decoupling Options 12 The AD830 is designed to be capable of rejecting noise and VP = +10V dissimilar potentials in the ground lines. Therefore, proper 8 care is necessary to realize the benefits of the differential ampli- 4 TO GND fication of the part. Separation of the input and output grounds LIMITS – VOLTAGE COMMON-MODE is crucial in rejection of the common-mode noise at the inputs 0 and eliminating any ground drops on the input signal line. 0 0.4 0.8 1.2 1.6 2.0 For example, connecting the ground of a coaxial cable to the DIFFERENTIAL INPUT VOLTAGE – VPEAK AD830 output common (board ground) could degrade the Figure 17. Input Common-Mode Range for Single Supply CMR and also introduce power-down loading on cable grounds.

REV. B –11– AD830

range. The voltage sources need not be of low impedance, since 28 the high input resistance and modest input bias current of the

V 24 AD830 V-to-I converters permit the use of resistive voltage dividers as reference voltages.

20 TO VP

VP 16 0.1F AD830 V1 1 8 12 INPUT GM SIGNAL VOUT V2 2 7 8 INPUT A = 1 COMMON MAXIMUM OUTPUT SWING – 3 6 4 TO GND GM C 0.1F 0 4 5 1014 18 22 26 30 SUPPLY VOLTAGE – V VN

Figure 18. Output Swing Limit for Single Supply V = V – V + V V3 OUT 1 2 3 OUTPUT Differential Line Receiver COMMON The AD830 was specifically designed to perform as a differential line receiver. The circuit in Figure 19 shows how simple it is to Figure 20. Differential Amplification with Level Shifting configure the AD830 for this function. The signal from System A is received differentially relative to A’s common and that voltage Difference Amplifier with Gain > 1 is exactly reproduced relative to the common in System B. The The AD830 can provide instrumentation amplifier style differential common-mode rejection versus frequency, shown in TPC 1, is amplification at gains greater than 1. The input signal is connected excellent, typically 100 dB at low frequencies. The high input differentially and the gain is set via feedback resistors, as shown in impedance permits the AD830 to operate as a bridging amplifier Figure 21. The gain, G = (R2 + R1)/R2. The AD830 can provide across low impedance terminations with negligible loading. The either inverting or noninverting differential amplification. The differential gain and phase specifications are very good, as polarity of the gain is established by the polarity of the connection ≤ Ω shown in TPC 7 for 500 Ω and TPC 10 for 150 Ω. The input at the input. Feedback resistor R2 should generally be R2 1 k to and output common should be separated to achieve the full maintain closed-loop stability and also keep bias current induced CMR performance of the AD830 as a differential amplifier. offsets low. Highest CMRR and lowest dc offsets are preserved by However, a common return path is necessary between Sys- including a compensating resistor in series with Pin 3. The gain tems A and B. may be as high as 100.

V VP P 0.1F 0.1 F AD830 V AD830 V1 1 8 1 1 8 V VCM CM INPUT INPUT G GM SIGNAL M V SIGNAL VOUT OUT V 2 7 V2 2 7 2 COMMON IN A = 1 R ʈR A = 1 SYSTEM A 1 2 3 6 3 6 Z ZCM CM G GM C 0.1F M C 0.1 F 4 5 4 5 R V 1 VN N

R2 VOUT = V1 – V2 COMMON IN SYSTEM B VOUT = (V1 – V2 )(1 + R1/R2) Figure 19. Differential Line Receiver Figure 21. Gain of G Differential Amplifier, G > 1 Wide Range Level Shifter The wide common-mode range and accuracy of the AD830 Offsetting the Output with Gain allows easy level shifting of differential signals referred to an Some applications, such as A/D drivers, require that the signal input common-mode voltage to any new voltage defined at the be amplified and also offset, typically to accommodate the input output. The inputs may be referenced to levels as high as 10 V range of the device. The AD830 can offset the output signal at the inputs with a ±2 V swing around 10 V. In the circuit in very simply through Pin 3 even with gain > 1. The voltage Figure 20, the output voltage, VOUT, is defined by the simple applied to Pin 3 must be attenuated by an appropriate factor equation shown below. The excellent linearity and low distortion so that V3 × G = desired offset. In Figure 22, a resistive divider are preserved over the full input and output common-mode from a voltage reference is used to produce the attenuated offset voltage.

–12– REV. B AD830

VP A diagram of this simple but potent application is shown below 0.1F in Figure 24. The AD830 summing circuit possesses several AD830 V1 1 8 V virtues not present in the classic op amp based summing cir- CM INPUT GM SIGNAL VOUT cuits. It has high impedance inputs, no resistors, very precise V2 2 7 summing, high reverse isolation, and noninverting gain. Achiev- ʈ A = 1 R1 R2 ing this function and performance with op amps requires 3 6 ZCM significantly more components. GM C 0.1F 4 5 VP

R1 VREF VN 1 AD830 8 R G 2 V M R 1 OUT 3 2 7 V 3 A = 1 VOUT = (V1 – V2 )(1 + R1/R2) R 4 3 6 G V3 M C Figure 22. Offsetting the Output with Differential Gain > 1 4 5

Loop Through or Line Bridging Amplifier (Figure 23) VN The AD830 is ideally suited for use as a video line bridging VOUT = V1 +V3 amplifier. The video signal is tapped from the conductor of the Figure 24. Resistorless Summing Amplifier cable relative to its shield. The high input impedance of the AD830 provides negligible loading on the cable. More signifi- 2× Gain Bandwidth Line Driver cantly, the benign loading is maintained while the AD830 is A gain of two, without the use of resistors, is possible with the powered down. Coupled with its good video load driving AD830. This is accomplished by grounding VX2, tying the VX1 and performance, the AD830 is well suited for video cable monitor- VY1 inputs together, and applying the input, VIN, to this wired ing applications. connection. The output is exactly twice the applied voltage, VIN; VOUT = 2 × VIN. Figure 25 shows the connections for this highly

V useful application. The most notable characteristic of this alterna- P tive gain of +2 is that there is no loss of bandwidth as in a voltage 0.1F 1 AD830 8 feedback op amp based gain of +2 where the bandwidth is halved, G therefore, the gain bandwidth is doubled. Also, this circuit is accu- M V R OUT 75 G 2 7 rate without the need for any precise valued resistors, as in the op A = 1 amp equivalents, and it possesses excellent differential gain and 249 75 3 6 phase performance, as shown in Figures 26 and 27. GM C 0.1F 4 5 VP 0.1F 499 AD830 VN 1 8 VIN GM V 75 OPTIONAL CC 499 OUT 2 7 A = 1 75 3 6

GM Figure 23. Cable Tap Amplifier C 0.1 F 4 5 Resistorless Summing Direct, two input, resistorless summing is easily realized from VN the general unity gain mode. By grounding V and applying the X2 Figure 25. Full Bandwidth Line Driver (G = +2) two inputs to VX1 and VY1, the output is the exact sum of the applied voltages V1 and V3, relative to common; VOUT = V1 + V3.

REV. B –13– AD830

0.10 0.20 0.2 GAIN = +2 0.09 RL = 150 0.18 0.1 FREQ = 3.58MHz VS = 15V 0.08 0 TO 0.7V 0.16 0

0.07 0.14 –0.1 RL = 150 0.06 –0.2 VS = 10V 0.12 GAIN = +2 0.05 0.10 –0.3 PHASE 0.04 0.08 –0.4 V = 5V 0.03 0.06 –0.5 S DIFFERENTIAL GAIN – %

0.02 GAIN 0.04 AMPLITUDE RESPONSE – dB –0.6 DIFFERENTIAL PHASE – Degrees

0.01 0.02 –0.7

–0.8 5156 71218 9 10 11 314 10k 100k 1M 10M 100M SUPPLY VOLTAGE – V FREQUENCY – Hz Figure 26. Differential Gain and Phase for the Figure 27. 0.1 dB Gain Flatness for the Circuit of Circuit of Figure 25 Figure 25 AC-COUPLED LINE RECEIVER becomes troublesome. For dual-supply operation, the 10 kΩ The AD830 is configurable as an ac-coupled differential ampli- resistors may go directly to ground. The output common is fier on a single- or bipolar-supply voltage. All that is needed is conveniently set by a Zener diode for a low impedance reference inclusion of a few noncritical passive components, as illustrated to preserve the high frequency CMR. However, a simple resis- in Figure 28. A simple resistive network at the X GM input tive divider will work fine and good high frequency CMR can be establishes a common-mode bias. Here, the common mode is maintained by placing a compensating resistor in series with the centered at 6 V, but in principle can be any voltage within +Y input. The excellent CMRR response of the circuit is shown the common-mode limits of the AD830. The 10 kΩ resistors in Figure 29. A plot of the 0.1 dB flatness from 10 Hz is also µ to each input bias the X GM stage with sufficiently high imped- shown. With the use of 10 F capacitors, the CMR is >90 dB ance to keep the input coupling corner frequency low, but not down to a few tens of hertz. This level of performance is almost too large so that residual bias current induced offset voltage impossible to achieve with discrete solutions.

+12V INPUT 10F 0.1F SIGNAL AD830 1 8 75 COAX R GM T VOUT 75 CABLE ZCM 2 7 10F 1000F A = 1 75 10k 10k 3 6 +VS 2k* GM C +12V 10k 4 5 4.7k 10k * 1N4736 OPTIONAL TUNING FOR IMPROVING 6.8V VERY LOW FREQUENCY CMR.

Figure 28. AC-Coupled Line Receiver

120 0.1

WITH CIRCUIT TRIMMED USING 0 EXTERNAL 2k POTENTIOMETER 100 –0.1

–0.2

80 WITHOUT EXTERNAL –0.3 2k POTENTIOMETER –0.4

60 –0.5

–0.6

40 AMPLITUDE RESPONSE – dB –0.7 COMMON-MODE REJECTION – dB –0.8

20 –0.9 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz Figure 29. Common-Mode Rejection vs. Frequency for Figure 30. Amplitude Response vs. Frequency for Line Receiver Line Receiver –14– REV. B AD830

OUTLINE DIMENSIONS

8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters)

0.375 (9.53) 0.365 (9.27) 0.355 (9.02)

8 5 0.295 (7.49) 0.285 (7.24) 1 4 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) 0.150 (3.81) BSC 0.135 (3.43) 0.015 0.120 (3.05) 0.180 (4.57) (0.38) MAX MIN 0.015 (0.38) 0.150 (3.81) SEATING 0.010 (0.25) 0.130 (3.30) PLANE 0.008 (0.20) 0.110 (2.79) 0.060 (1.52) 0.022 (0.56) 0.050 (1.27) 0.018 (0.46) 0.045 (1.14) 0.014 (0.36)

COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

8-Lead Standard Small Outline Package [SOIC] 8-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP] (R-8) (Q-8) Dimensions shown in millimeters and (inches) Dimensions shown in inches and (millimeters)

5.00 (0.1968) 0.005 (0.13) 0.055 (1.40) 4.80 (0.1890) MIN MAX

85 85 4.00 (0.1574) 6.20 (0.2440) 0.310 (7.87) 3.80 (0.1497) 1 4 5.80 (0.2284) PIN 1 0.220 (5.59) 1 4

0.100 (2.54) BSC 1.27 (0.0500) 0.50 (0.0196) 45 0.320 (8.13) BSC 1.75 (0.0688) 0.25 (0.0099) 0.405 (10.29) MAX 0.290 (7.37) 0.25 (0.0098) 1.35 (0.0532) 0.060 (1.52) 0.10 (0.0040) 0.200 (5.08) 0.015 (0.38) MAX 0.51 (0.0201) 8 0 1.27 (0.0500) COPLANARITY 0.33 (0.0130) 0.25 (0.0098) 0.150 (3.81) SEATING 0.200 (5.08) 0.10 0.41 (0.0160) MIN PLANE 0.19 (0.0075) 0.125 (3.18) 0.023 (0.58) SEATING 0.015 (0.38) COMPLIANT TO JEDEC STANDARDS MS-012AA 0.070 (1.78) 15 0.014 (0.36) PLANE 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.030 (0.76) 0 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. B –15– AD830 Revision History Location Page 1/03—Data Sheet changed from REV. A to REV. B. Updated ORDERING GUIDE ...... 4 Change to Figure 30 ...... 14 Updated OUTLINE DIMENSIONS ...... 15

C00881–0–1/03(B)

PRINTED IN U.S.A.

–16– REV. B