A Low-Distortion Class-Ab Audio Amplifier with High Power Efficiency

A LOW-DISTORTION CLASS-AB AUDIO AMPLIFIER WITH HIGH

POWER EFFICIENCY

CHAITANYA MOHAN, B.Tech

A thesis submitted to the Graduate School

in partial fulﬁllment of the requirements

for the degree

Master of Sciences, Engineering

Specialization in: Electrical Engineering

New Mexico State University

Las Cruces, New Mexico

March 2011 “A Low-Distortion Class-AB Audio Amplifier with High Power Efficiency,” a thesis prepared by Chaitanya Mohan in partial fulfillment of the requirements for the degree, Master of Sciences has been approved and accepted by the following:

Linda Lacey Dean of the Graduate School

Dr. Paul M. Furth Chair of the Examining Committee

Date

Committee in charge:

Dr. Paul M. Furth

Dr. Jaime Ramirez-Angulo

Dr. Jeﬀrey Beasley

ii DEDICATION

Dedicated to my father Chandolu Rama Mohan Rao, mother Chandolu

Hemalatha, sister Srujana Mohan Rao.

iii ACKNOWLEDGMENTS

First I would like to thank my parents Chandolu Rama Mohan Rao and

Chandolu Hemalatha, sister Srujana Mohan Rao and brother-in-law DeepakNadh

Tammana for supporting me at every level of my life. They are the reason behind my success at every corner in the journey of life. Srujana has been more of a friend, guide and advisor than a sister.

Dr. Paul M. Furth, the coach of VLSI V6 team is man behind the success of this thesis. I can proudly say, the knowledge I acquired from him in Electronics is more than what I have earned in my entire bachelors. The approach towards every problem and level of analyzing things before hand is what I would like to get from him.

I would also like to thank Dr. Jaime Ramirez-Angulo for imparting knowledge on analog concepts.

A special note of thanks to my childhood friend Hareesh Gottipati (Nani),

Vidhul Dev and Arka who are more than just friends. I still remember the ﬁghts we had on every other day on almost every topic. The topics included more of politics, movies, places and almost every current situation, but the discussion never involved studies.

Swetha Peri is one other person in my life who is more than a friend. She had the patience to hear everything and take any situation casually with a calm

iv mind. I would like to thank Swetha for being such a great friend and who always supported my every decision.

A thanks is just not enough for Harish Valapala. I cannot forget the help that I got from him, every time when I was supposed to meet the deadline.

I would also like to thank Alex from math department for giving an op- portunity to work as a math tutor in the ﬁnal semester. He has been very humble during my defense and allowed me to work based on my availability, which was very helpful

Finally I would like to thank all my friends and roommates: Sravan (Buggi),

Varun (Jaﬀa), Lalith (Makku bro), Venu, Madhusudhan Nagireddy (Madhu),

Suresh (Debri), Nikhilesh (Hadavidi) and especially the V6 group Punith (the buss), Rajesh, Ramesh, Venkat and Harish.

v VITA

December 17, 1986 Born in Hyderabad, India.

Education

2004 - 2008 B.Tech. Electronics and Communication Engineering, Jawaharlal Nehru Technological University, India

2009 - 2010 Teaching Assistant, New Mexico State University,USA

Since 2008 M.S in Electrical Engineering, New Mexico State University, USA

Awards and Achievments

2008 - 2011 In-State Tuition, NMSU,USA.

March - 2011 Third place in Graduate Research and Arts Symposium, NMSU, USA.

Field of Study

Major Field: Electrical Engineering (Analog Microelectronics/VLSI Design)

vi ABSTRACT

A LOW-DISTORTION CLASS-AB AUDIO AMPLIFIER WITH HIGH POWER EFFICIENCY

CHAITANYA MOHAN, B.Tech

Master of Sciences, Engineering

Specialization in Electrical Engineering

New Mexico State University

Las Cruces, New Mexico, 2011

Dr. Paul M. Furth, Chair

Place: Thomas & Brown Room-207

Date: 03/17/2011 Time: 2:00 PM

A low-distortion three-stage Class-AB audio amplifier is designed to drive a 16-Ω headphone speaker. High power efficiency in the design was achieved by using fully-differential internal stages with local common-mode feedback networks and replica biasing of the output stage. The threshold voltage of NMOS transistors were made comparable to PMOS transistors by biasing the p-substrate in order to achieve high linearity. The stability of the amplifier is achieved using multiple compensation techniques. The audio amplifier is designed to drive widely varying capacitive loads from 10 pF to 5 nF. The peak power delivered to the load is vii 93.8mW. The quiescent power of the amplifier is 1.43mW. The output signal

swing is 2.45Vpp for ±1.5V supply. The THD of the ampliﬁer is measured as - 79dB. The design has been implemented in a 0.5µm CMOS process and occupies 0.35 mm2 of area.

viii TABLE OF CONTENTS

LIST OF TABLES xii

LIST OF FIGURES xiii

1 INTRODUCTION 1

2 BASE FOR AUDIO AMPLIFIERS 4

2.1 Audio Ampliﬁer Speciﬁcations ...... 4

2.1.1 Headphone Speaker Load ...... 5

2.1.2 Total Harmonic Distortion in an Ampliﬁer ...... 5

2.1.3 Power Eﬃciency of an Ampliﬁer ...... 6

2.2 Output Stage Classiﬁcation ...... 7

2.2.1 Class-A Ampliﬁers ...... 7

2.2.2 Class-D Ampliﬁer ...... 9

2.2.3 Class-AB Ampliﬁer ...... 9

2.3 Multi-Stage Ampliﬁers ...... 11

2.3.1 Pseudo Class-AB Ampliﬁer ...... 11

2.3.2 True Class-AB Ampliﬁer ...... 13

2.4 Common-Mode Feedback Network ...... 14

2.5 Compensation ...... 15

2.5.1 Miller Compensation ...... 16

ix 2.5.2 Reverse-Nested Miller Compensation ...... 17

2.6 Three-Stage Class-AB Ampliﬁer from [1] ...... 18

2.6.1 Design from [1] ...... 18

2.6.2 Experimental Results from [1] ...... 19

2.7 Replica Biasing ...... 20

3 DESIGN OF THE THREE-STAGE CLASS-AB AUDIO AMPLI- FIER 23

3.1 Architecture and Key Aspects of the Audio Ampliﬁer ...... 23

3.2 Transistor Level Three-Stage Design ...... 25

3.3 Bias circuit ...... 25

3.4 Input-Stage ...... 29

3.5 Second-Stage ...... 30

3.5.1 PMOS diﬀerential ampliﬁer ...... 31

3.5.2 NMOS diﬀerential ampliﬁer ...... 32

3.6 Output-Stage ...... 33

3.7 Compensation used in the Design ...... 35

3.8 Small-Signal Models ...... 36

3.9 Pole-Zero Analysis ...... 40

4 SIMULATION RESULTS 43

4.1 DC analysis ...... 44

4.2 AC analysis ...... 44

4.3 Transient analysis ...... 48

4.4 THD analysis ...... 51

5 HARDWARE TESTING 54

x 5.1 Layout ...... 54

5.2 Experimental Setup ...... 54

5.3 DC Measurements ...... 56

5.4 Transient Measurements ...... 57

5.5 THD Measurements ...... 58

6 DISCUSSION AND CONCLUSION 69

APPENDICES 74

A. HARDWARE TEST PROCEDURE 75

B. POLE/ZERO ANALYSIS USING MAPLE 85

C. MATLAB CODE TO PLOT WAVEFORMS 88

REFERENCES 95

xi LIST OF TABLES

2.1 Comparison of measured results ...... 20

3.1 Transistor Dimensions ...... 26

3.2 Poles and Zeros ...... 42

4.1 Design Parameters ...... 43

4.2 AC Simulation Results ...... 46

4.3 Transient Simulation Results ...... 52

5.1 Hardware Measurements ...... 68

6.1 Summary of Hardware Test Results ...... 69

6.2 Comparison of results with state-of-the-art ([1]) ...... 70

6.3 Simulation vs Hardware (LIQ) ...... 71

6.4 Simulation vs Hardware (LTHD) ...... 72

6.5 Simulation vs Hardware (MIQ) ...... 72

6.6 Simulation vs Hardware (HCL) ...... 73

xii LIST OF FIGURES

2.1 Schematic of a Class-A ampliﬁer ...... 7

2.2 Basic design of a Class-D ampliﬁer ...... 9

2.3 Schematic of a Class-AB ampliﬁer ...... 10

2.4 Schematic of a three-stage pseudo class-AB ampliﬁer ...... 12

2.5 Schematic of a three-stage true class-AB ampliﬁer ...... 13

2.6 Schematic of a fully-diﬀerential ampliﬁer with common-mode feedback network ...... 15

2.7 Architecture of Miller compensation for two-stage ampliﬁer . . . . 16

2.8 Architecture of Reverse-Nested Miller compensation for three-stage ampliﬁer ...... 17

2.9 Architecture of the three-stage class-AB ampliﬁer of [1] ...... 19

2.10 (a) Schematic of two-stage pseudo class-AB ampliﬁer (b) Replica bias circuit to control quiescent at the output stage ...... 21

3.1 Architecture of the proposed three-stage class-AB ampliﬁer . . . . 24

3.2 Schematic of the three-stage class-AB audio ampliﬁer ...... 27

3.3 Schematic of the bias circuit ...... 28

3.4 Schematic of the ﬁrst-stage ...... 30

3.5 Schematic of the second-stage PMOS diﬀerential ampliﬁer . . . . 31

3.6 Schematic of the second-stage NMOS diﬀerential ampliﬁer . . . . 32

3.7 Schematic of the output-stage ...... 34

xiii 3.8 (a) Left-half of the input-stage (b) small-signal model for left half. 36

3.9 (a) Right-half of the input-stage (b) small-signal model for right-half. 37

3.10 (a) PMOS differential amplifier (b) small-signal model PMOS differential amplifier...... 38

3.11 (a) NMOS differential amplifier (b) small-signal model NMOS differential amplifier...... 39

3.12 (a) Schematic of output-stage (b) small-signal model for output-stage 40

3.13 Small-signal model of the designed three-stage class-AB audio am- pliﬁer ...... 41

4.1 Schematic of the DC test-bench ...... 44

4.2 DC-analysis output ...... 45

4.3 Schematic of the AC test-bench ...... 46

4.4 AC output of LIQ circuit ...... 47

4.5 AC output of LTHD circuit ...... 47

4.6 AC output of MIQ design ...... 48

4.7 AC output of HCL circuit ...... 49

4.8 Schematic of the Transient test-bench ...... 49

4.9 Transient output of LIQ circuit ...... 50

4.10 Transient output of LTHD circuit ...... 50

4.11 Transient output of MIQ circuit ...... 51

4.12 Transient output of HCL circuit ...... 52

4.13 Schematic for THD measurement ...... 53

4.14 Transient output for measuring THD ...... 53

5.1 Layout of LIQ ampliﬁer ...... 55

5.2 Layout of LTHD ampliﬁer ...... 56

5.3 Layout of MIQ ampliﬁer ...... 57 xiv 5.4 Layout of HCL ampliﬁer ...... 58

5.5 Layout of the frame with two LIQ and MIQ...... 59

5.6 Layout of the frame with two LTHD and HCL...... 60

5.7 Micrograph of the chip...... 61

5.8 Transient response of LIQ design (an oﬀset of 900mV is added intentionally for visibility) ...... 62

5.9 Transient response of LTHD design (an oﬀset of 900mV is added intentionally for visibility) ...... 62

5.10 Transient response of MIQ design (an oﬀset of 900mV is added intentionally for visibility) ...... 63

5.11 Transient response of HCL design (an oﬀset of 900mV is added intentionally for visibility) ...... 63

5.12 THD measurement for LIQ design ...... 64

5.13 THD measurement for LTHD design ...... 65

5.14 THD measurement for MIQ design ...... 66

5.15 THD measurement for HCL design ...... 67

xv Chapter 1

INTRODUCTION

The size of portable devices are decreasing with advances in technology; similarly battery size is also decreasing [2],[3],[4]. The portable devices available in the present day market such as laptops, cellphone, iPods and other music players require audio amplifiers that are capable of driving small resistive loads and wide range of capacitive loads (headphone speakers). Audio amplifiers require high current at the output stage to drive low resistive loads [5]. The main features of audio amplifiers are low power dissipation, high output power and low distortion[1],[2],[5],[6],[7]. The ideal choice for audio amplifiers are class-AB and class-D amplifiers [6]. Though class-D amplifiers have high efficiency, low power dissipation and low distortion [5], class-AB amplifiers are preferred for designing audio amplifiers because they have better power supply rejection ratio (PSRR) than class-D amplifiers [2],[6]. Moreover, class-D amplifiers are subject to electro- magnetic interference [1],[5],[7]. A three-stage pseudo class-AB amplifier from [3] experiences a large quiescent current when the output stage current increases. An adaptive biasing technique is used to transform the pseudo class-AB amplifier to a true class-AB amplifier [3],[4]. However, the gain experienced by the load through PMOS output transistor is different from the gain experienced by the NMOS output transistor. This results in asymmetry at the output, which in turn causes severe distortion. Although, the bias current of the amplifier is low, the distortion is large.

1 In order to obtain symmetry at the output, the load must experience the same gain through both the NMOS and PMOS output transistors. Biasing the output transistors at a low quiescent current is achieved using replica bias. The replica biasing circuit is used to generate the required bias voltages at the gates of the output transistor [8]. A local common-mode feedback network is used for symmetrical gain and to generate a desired common-mode output voltage. Thus it simultaneously improves the power efficiency and reduces distortion. As the number of stages in an amplifier increases, the stability starts to degrade [3],[4],[9],[10],[11]. Thus compensation networks are used to improve the stability of a multi-stage amplifier. Some of the commonly used compensations are Miller compensation with nulling resistor, nested Miller compensation and reverse-nested Miller compensation for multi-stage amplifiers. Miller compensation with nulling resistor proposed in [10] is used to create a RHP zero to split poles. Reverse-nested Miller compensation is more desirable for multi-stage amplifiers than nested Miller compensation as it improves the bandwidth [3],[9],[10]. Based on the class-AB amplifier in [3],[4], this thesis reports on the design of a new three-stage class-AB amplifier. The class-AB amplifier has fully-differential internal stages. A common-mode feedback network is used to provide the symmetrical gain and to generate a common-mode voltage at the output. Low quiescent current at the output-stage is obtained using the replica bias circuit. Substrate biasing technique is used to attain linearity at the output. Chapter 2 describes specifications for designing an audio amplifier, the types of output stages that can be used in the design of an audio amplifier, the purpose of using using multi-stage amplifiers, the stability issues of multi-stage amplifiers, and the compensation networks that are used to improve the stability, bandwidth and transient response of the multi-stage amplifiers. A summary of

2 architecture and experimental results of three-stage class-AB amplifier from [1] is described. The results of [1] are used as basis for designing a new three-stage class-AB amplifier with improved figure of merit (FOM). Chapter 3 explains the architecture of each stage of a three-stage class-AB amplifier designed in this thesis. The working of replica bias circuit to generate low quiescent currents at the output stage is discussed. The compensation networks used for stabilizing the amplifier and the small signal models that explain how the variation in compensation capacitor values improve the stability is also explained. Chapter 4 discusses the results that determine the functionality of the amplifier. The test-benches for DC, AC and transient analysis are explained. A comparison of results for four designs with variation in compensation capacitor values is summarized. A test-bench for measuring the total harmonic distortion (THD) is explained. Chapter 5 explains the hardware implementation of the three-stage class- AB audio amplifier. The layout of the design is discussed and the test-setup of the design for determining the quiescent current is explained in the DC testing. The hardware testing results obtained are compared with simulation results. Chapter 6 discusses about the figure of merit (FOM) of the designed amplifier. A summary of results obtained in [1] are compared with the hardware testing results obtained in chapter 5. APPENDICES contains the test procedure for testing the circuit in real- time, the Maple work that determines the poles and zeros in an amplifier based on the small-signal model and the code used for plotting the waveforms.

3 Chapter 2

BASE FOR AUDIO AMPLIFIERS

This chapter give an introduction to specifications of audio amplifiers, types of amplifier output-stage, multi-stage amplifiers and compensation networks. 2.1 Audio Amplifier Specifications

Ampliﬁers are used in every electronic device. Though general purpose op-amps can be used to drive a variety of loads but driving small resistive loads is a tough task. The modern portable devices such as laptops, cellphones, Ipods and other music players require audio ampliﬁers for driving headphone speakers. The resistance of headphones is small. It can vary from 32-Ω to a much smaller value depending on the supply voltage. The device dimensions and supply voltages are decreasing with advances in technology. In order to provide nearly constant output power, corresponding to the human perception of loudness, reduced voltages necessitate reduced headphone speakers. The output power POUT is given as

2 VRMS POUT = (2.1) RL

Thus for small device dimensions and supply voltages, the load resistance must be made small to maintain a constant output power. The important aspects in an audio ampliﬁer are load, total harmonic distortion and power eﬃciency.

4 2.1.1 Headphone Speaker Load

The output resistive load for an audio amplifier in portable devices is very small. As the supply voltage in these devices is very small, the resistance of the headphone must be made small to provide constant output power as shown in (2.1). If the resistance of the headphone speaker is made large, then for small supply voltages the output power of the amplifier decreases. Thus the loudness is reduced. Modern day headphone speakers have resistance as small as 8-Ω. The quiescent current is small for small supply voltages. The distortion in an amplifier is inversely proportional to the quiescent current. As the quiescent current decreases, the distortion in an amplifier increases. 2.1.2 Total Harmonic Distortion in an Amplifier

Total harmonic distortion is very important for ampliﬁers that drive large capacitive loads and low resistances such as audio ampliﬁers. Harmonic distortion

occurs in ampliﬁers when the AC component of the drain current id is comparable

to DC component of the drain current ID [12]. Every amplifier produces harmonics for a given fundamental frequency. The level, or amplitude, of these harmonics is smaller than the amplitude, or level, of its fundamental frequency. The total harmonic distortion is an important amplifier specification. It is given by

q V 2 + V 2 + V 2 ...... + V 2 2RMS 3RMS 4RMS nRMS THD = (2.2) V1RMS

where V1RMS is the rms voltage of the fundamental frequency and VnRMS is the rms voltage of the nth harmonic. The total harmonic distortion is measured in percentage (%). The lower the value better the sound quality. Audio ampliﬁers with a THD of less than 0.5% produce an audio signal with noise which is hardly perceived by the human

5 ear. Thus audio amplifiers must be designed with a THD less than 0.5% for high sound quality. In order to reduce distortion, feedback networks are used. Apart from distortion, another important feature of an audio amplifier is power efficiency. The power efficiency of an audio amplifier is made high by lowering the quiescent current in the amplifier. This is discussed in the next section. 2.1.3 Power Efficiency of an Amplifier

The battery life of a portable system is very important [1]. There will always be demand in the market for systems that run for longer time. Thus in order to have an efficient battery life, the quiescent power of the system should be minimized. The power efficiency of the amplifier is defined as the ratio of power delivered to the load to power supplied by the battery [1],[12]. The power delivered to the load is given in (2.1). The power efficiency (η) of the amplifier is given by

P η% = OUT × 100 (2.3) PS

where PS is the power supplied by the battery given by

PS = IQ(VDD − VSS) (2.4)

Thus, from (2.3) and (2.4), if PS is reduced, the efficiency of the amplifier will be improved. In order to reduce PS, the quiescent current (IQ) can be reduced. As supply voltages are smaller for new technologies, multi-stage amplifiers are used to drive the load. The quiescent current increases with increase in number of stages. The quiescent current also depends on the type of amplifier. The linearity in the operational region and low power dissipation are important aspects

6 for audio amplifiers. Thus two types of amplifiers that provide either of the two properties or both are discussed in the following sections- Class-A and Class-AB amplifiers 2.2 Output Stage Classification

The output stage of amplifiers are classified based on the circuit configuration and the type of operation [8]. Three output stage classifications of an amplifier are discussed in the following sections. 2.2.1 Class-A Amplifiers

The high linearity in the operational range of class-A amplifiers make them ideal for audio applications. Owing to their high power dissipation these amplifiers are replaced with class-AB amplifiers for audio applications. Thus class-A amplifiers are limited to applications that require only small changes in the output voltage, as the power consumption can be very low for small output signals. The schematic of the class-A amplifier is shown in Fig. 2.1.

VB IB

M2 VOUT

VIN RL M1

Figure 2.1: Schematic of a Class-A ampliﬁer

7 The gate of the transistor M2 is connected to a DC bias voltage (VB).

This turns the transistor M2 ON and a constant current (IB) is sourced from VDD

to bias transistor M1. Thus it acts as a current source. The input for a class-A

ampliﬁer is at the gate of transistor M1. The gain of the ampliﬁer is Gm1 ·Ro, where

Gm1 is the transconductance of the transistor M1 and Ro is the resistance at the

output node given by Ro = ro1 k ro2 kRL. The current from transistor M1 increases when the gate experiences a large signal at the input. The sinking current in the amplifier is not limited but the sourcing current is limited to IB as shown in Fig. 2.1. The upper-half cycle at the output observes distortion [8]. Moreover the efficiency of the class-A amplifier is low. The efficiency of an amplifier is given in (2.3). For class-A amplifiers the load power is given as

2 VOUT PL = (2.5) 2RL

and the power from battery PS is given as

PS = 2ID(VDD − VSS) (2.6)

The efficiency is maximum when VOUT = ID·RL = (VDD - VSS). The efficiency of class-A amplifier accounts to 25% [13] using equations (2.3), (2.5), (2.6). Hence makes it hard to be used in present day market of audio amplifiers. To overcome the problem of low efficiency, class-AB amplifiers are preferred over class-A amplifiers. The class-AB amplifiers have low power dissipation and low distortion. The other classification of output stage amplifier known as class-D amplifier, also provides low power dissipation and low distortion. This is explained in the following section.

8 2.2.2 Class-D Ampliﬁer

Class-D amplifiers find applications in audio amplifiers and pulse genera- tors [8]. The basic design of a class-D amplifier is shown in Fig. 2.2. The output of a Class-D amplifier is a sequence of pulses. The frequency of the output signal is higher than input signal frequency. Passive filters are used at the output-stage to eliminate undesired harmonics.

+ V A1 out – RL + Precision triangular Wave generator

Figure 2.2: Basic design of a Class-D ampliﬁer

The amplitude of the output pulses is fixed. The conduction of switching devices occurs during the transition of states. Hence, the power dissipation is reduced as the transition is only for a short duration. Though class-D amplifiers have an efficiency up to 95%, the power supply rejection ratio is higher when compared to class-AB amplifiers, as one of the supply voltage is the output voltage [8]. Hence, variations in supply voltage create variations at output. Thus class-AB amplifiers are preferred for audio applications, as they have higher power supply rejection ratio over class-D amplifiers. 2.2.3 Class-AB Amplifier

The basic schematic of the class-AB ampliﬁer is shown in Fig. 2.3. The transistor MN is ON for the negative half cycle of the output signal and the transistor MP is ON for the positive half cycle. Thus, only one transistor sources

9 current for each half cycle while other is turned OFF. This kind of operation provides a push-pull action. This minimizes the quiescent current of the ampliﬁer.

The Vbat is used to turn ON both MN and MP for the short time when the output signal is near zero. Thus it acts as a class-A ampliﬁer for very small output signals. The result is minimized crossover (crossing through zero) distortion.

MN V VIN bat VOUT

Vbat RL MP

Figure 2.3: Schematic of a Class-AB ampliﬁer

The eﬃciency of the class-AB ampliﬁer is determined using (2.3). The load power is given in (2.5). The power from the battery is the total average power drawn through the power supplies given by

2 · VOUT · (VDD − VSS) PS = + 2IQ(VDD − VSS) (2.7) (π + θ) · RL

where IQ(VDD - VSS) is the quiescent power (VOUT = 0) per transistor and (π + θ) is the conduction angle in radians, (π + θ) ≤ 2π. Thus the maximum efficiency accounts to 50% ≤ η ≤ 78.5% [13]. The push-pull action, low distortion and high power efficiency of class-AB amplifiers make them ideal choice for audio applications. 10 A single stage class-AB amplifier does not provide the enough gain to drive the load. Thus multi-stage amplifiers are used for driving small loads. As the number of stages increase, the stability starts to degrade. To stabilize these multi-stage amplifiers compensation networks are used. The following sections focus on multi-stage amplifiers and compensation networks. 2.3 Multi-Stage Amplifiers

In the past, a single-stage amplifier was sufficient for providing large gain. As the device dimensions were large, voltage levels were large to drive resistive loads. A single-stage amplifier has only one pole, thus single-stage amplifiers are highly stable. Advances in technology has made the device dimensions smaller. Low voltages are required to operate these transistors. Hence a single-stage gain is not sufficient to drive resistive loads. In order to overcome this problem, two or more stages are cascaded together to provide a gain that is the product of each gain stage [14],[15],[16].As the number of stages increase, the stability starts to degrade. A compensation network is required to provide stability. The compensation network becomes more complex when the number of stages increases beyond four. A large number of multi-stage amplifiers are proposed in the literature [9],[10],[11],[13]. A multi-stage pseudo class-AB amplifier proposed in [17] is used as the basis for audio amplifier designed in this work. 2.3.1 Pseudo Class-AB Amplifier

The schematic of a multi-stage amplifier is shown in Fig. 2.4. The first- stage is a folded cascode differential amplifier formed with transistors N1−5 and

P1−4. The gain of the ﬁrst-stage at node V1 is given by GM3 ·R1, where R1 is the output resistance at V1. The second-stage is realized using a NMOS common- source ampliﬁer N6.

11 Vb2 Vb2 P1 P2 P5

P7 P8 Vb3 P6 Vb3 P3 P4

Cm3 Cm1 Rm3 Cm2 Rm1 Vout Vin- Vin+ V3 N2 N3 Ccb RL CL

V1 V2

Vb1 N1 N4 N5 N6 N7 N8

Figure 2.4: Schematic of a three-stage pseudo class-AB ampliﬁer

The output stage for sinking the current is designed using a NMOS common-

source ampliﬁer N8. The third-stage or the output stage for sourcing the current

is realized using N7 common-source ampliﬁer and P7 and P8 current mirror. Thus

the push-pull action is provided by P8 and N8 transistors. The gain in the ﬁrst-stage is a inverting gain. The common-source ampli-

fiers N6 and N8 of second-stage have inverting gain configuration. The gain of the third stage realized with transistors N7 and P7−8 is a non-inverting gain. As the two-stages of inverting gain from P8 and N7 common-source amplifiers are cas-

caded to obtain a non-inverting gain. Thus the overall gain from Vin+ to Vout is non-inverting. This multi-stage pseudo class-AB amplifier is a low voltage design for driving small loads. Though it can drive small resistive loads, it cannot be used as audio amplifier. As stated earlier, the low power dissipation and low distortion are the main features of audio amplifiers. The quiescent current in this amplifier increases with increase in current at the output stage. Thus the power dissipation of the ampli-

12 fier is large. In order to reduce the high quiescent current in this amplifier a new technique called adaptive biasing has been proposed in [3],[4]. 2.3.2 True Class-AB Amplifier

To minimize the current through the transistor P7 in Fig. 2.4, two resistors

Rad1 and Rad2 are used, as shown in Fig. 2.5. The diode connected transistor P7 and the resistors Rad1 and Rad2 form the adaptive biasing network [3],[4]. The value of the resistors Rad1 and Rad2 are made large to minimize the current through transistor P7 .

Adaptive biasing

Vb2 Vb2 P1 P2 P5 Rad1

Vb3 P P6 7 P8

Vb3 Rad2 P3 P4

Cm3 Cm1 Rm3 Rm1 Cm2 Vout Vin- Vin+ V3 N2 N3 Ccb RL CL

V1 V2

Vb1 N1 N4 N5 N6 N7 N8

Figure 2.5: Schematic of a three-stage true class-AB ampliﬁer

The transistor P7 is in cutoﬀ region when the output current is very low.

The load at node V3 is simply Rad2. The phase margin of the ampliﬁer is improved with the presence of resistor Rad2 and it moves the non-dominant pole to high frequencies [3],[4]. When the load experiences a large sourcing current through the transistor

P8, the transistor P7 moves to the saturation region. Now, the load experienced

1 by node V3 is ( + Rad1) k Rad2. For large values of resistors, the gain at the GM7 node V3 in Fig. 2.5 is large compared to the gain at node V3 in Fig. 2.4 [3],[4]. 13 Thus the power efficiency and gain of the amplifier are improved. Though the amplifier has good power efficiency but it cannot be used for audio amplifica- tion, as the distortion in the amplifier is high. The gain experienced by the load

through P8 common-source is a three-stage gain, whereas the gain experienced by the load through N8 common-source amplifier is a two-stage gain. This creates non-linearity at the output and leads to distortion. To attain low distortion, load must experience same gain through the push-pull transistors. One way to achieve this is by using fully differential internal stages. The fully differential amplifiers require additional circuitry to attain balanced outputs. This additional circuitry is a common-mode feedback network. The working of the common-mode feedback network is explained in the following section. 2.4 Common-Mode Feedback Network

A common-mode feedback network is used for generating a known voltage at the output of a fully-differential amplifier [12] as shown in Fig. 2.6. The difference between the inverting terminal and the average of non-inverting terminals of the common-mode feedback amplifier are amplified with a gain at the output. If the difference between Vb2 and the average of Vout+ and Vout- is large, then the voltage VCMFB increases. This increases the VGS of transistors N1 and

N4 and the current through them. Thus the voltage at the output nodes reach close to Vb2. Hence a known voltage is obtained at the output. The circuit also works for diﬀerential inputs. If one of the input voltage moves above the other then one of the output goes above Vb2 by a small amount and the other output moves down the Vb2 by the same amount. There also exist some concerns while using these feedback networks. The stability of the ampliﬁer changes and it requires compensation networks to sta-

14 Vb2 P1 P2

Vout+ Vout- + - + CMFB

Vin- Vin+ N2 N3

VCMFB N1 N4

Figure 2.6: Schematic of a fully-differential amplifier with common-mode feedback network bilize the differential amplifier, as well as common-mode feedback network. The following section gives an introduction to compensation. 2.5 Compensation

Stability is an important aspect for amplifiers. The amplifiers with single stage are highly stable as they have single dominant pole. In multi-stage amplifiers the number of dominant poles are not limited to one. Thus the stability goes

15 down. Compensation networks are used, to improve the stability of multi-stage ampliﬁers. Two types of compensation networks are reported in the following sections. 2.5.1 Miller Compensation

A Miller compensation uses a resistor and a capacitor in series between the input and output of an inverting stage [9],[11]. The architecture of the Miller compensation is shown in Fig. 2.7.

CM RM

-gm1 -gm2

VIN VOUT -Av1 -Av2

RL R1 C1

Figure 2.7: Architecture of Miller compensation for two-stage ampliﬁer

If the two poles of the two-stage ampliﬁer are near each other, then a Miller compensation can be used to split the poles. The dominant pole is moved towards the low frequencies and the non-dominant pole is moved towards the high frequencies. The series resistor RM and capacitor CM create a zero. The

1 dominant pole is given by P−3dB = , the non-dominant pole is CM (RM +GM2 R1RL)

RM +GM2 R1RL 1 P2 = C (R1+R )R , and the zero is 1 . Thus the RHP zero can be L M L (RM − G )CM M2 1 eliminated by selecting RM = [9],[11], [13]. GM2

16 2.5.2 Reverse-Nested Miller Compensation

A two-stage amplifier is designed by cascading two inverting stages. Sim- ilarly, a three-stage amplifier is designed by cascading two inverting stages and a non-inverting stage. In a three-stage amplifier design the first stage is inverting stage that is implemented using a differential amplifier and the next stages are implemented with common-source amplifiers. If the second stage is made non- inverting, then nested Miller compensation is used. Likewise, if the second-stage is implemented with inverting gain configuration and third-stage with non-inverting gain configuration, then reverse-nested Miller compensation can be used to stabilize the amplifier. The architecture of the reverse-nested Miller compensation is shown in Fig. 2.8.

RM CM1

CM2

-gm1 -gm2 gm3

VIN VOUT -Av1 -Av2 Av3

R1 R2 RL C1 C2

Figure 2.8: Architecture of Reverse-Nested Miller compensation for three-stage ampliﬁer

The dominant pole for this compensation is given by

1 P−3dB = (2.8) CM1 GM2 GM3 R1R2RL

The transfer function adapted from [9] is given by

17 CM2 CM1 2 CM1 CM2 GM1 GM2 GM3 R1R2RL(1 − s( + ) − s ) GM2 GM2 GM3 R2 GM2 GM3 Arnmc = C C C C C C (1 + s 1 )[1 + s( M2 L − M2 + M2 ) + s2 M1 L ] CM1 GM2 GM3 R1R2RL GM3 CM1 GM2 GM3 GM2 GM3 (2.9) The equation 2.9 shows that the amplifier has three poles and two RHP zeros. The dominant pole is given in equation 2.8. The other two poles are high frequency poles. Thus in any amplifier after the required compensation scheme is applied, the values of compensation capacitors and resistors are determined to move the non-dominant poles and zeros to high frequencies. This stabilizes the circuit and improves the bandwidth. A large number of compensation techniques are proposed to stabilize the multi-stage amplifiers [9],[10],[11],[15],[16],[17]. These multi-stage amplifiers are used in a wide range of applications. A three-stage class-AB amplifier is proposed by [1] to drive 16-Ω headphone speakers. The design and results are summarized in the following section. This design is taken as a reference to compare the results with our work. 2.6 Three-Stage Class-AB Amplifier from [1]

The architecture of the proposed design is shown in Fig. 2.9. It is a three- stage class-AB ampliﬁer that drives 16-Ω headphone speakers and a wide range of capacitive loads. 2.6.1 Design from [1]

The first stage is implemented using a folded-cascode amplifier with an inverting gain configuration. The second-stage is implemented using common- source amplifiers with positive gain configuration. A damping factor control stage is used in the amplifiers that drive large capacitive loads [1],[11]. The damping factor control stage is used in amplifiers that have large swing to improve

18 RC

CC2

VIN VOUT -Gm1 Gm2 -Gm3

CL RL

CD CD2

V RB B GmD

Figure 2.9: Architecture of the three-stage class-AB ampliﬁer of [1]

the bandwidth and transient response [11]. The output stage is designed with common-source amplifiers to provide the required push-pull action. The output stage of the amplifier is biased at ±1V, and the rest of the amplifier is biased at ±0.6V. 2.6.2 Experimental Results from [1]

The total quiescent current of the ampliﬁer is 730 µA. The THD of the

design is -84.8dB for 1.4VPP , 1 kHz sine-wave output. A figure of merit (FOM) was defined to compare with other designs. The figure of merit defined by [1] is the ratio of peak output power to the supply power. A comparison of measured results is shown in Table 2.1. Taking the above design as a reference, a new three-stage amplifier is designed. The concept of replica biasing is used in the design to generate the bias

19 Table 2.1: Comparison of measured results

Parameter [18] [19] [20] [1]

0.35 µm 65 nm 130nm Technology - CMOS CMOS CMOS

Capacitance load 0-300 pF 0-300pF 0-12 nF 1 pF - 22 nF

Supply 3.0V 0.8V 2.5V 1.2V/2.0V THD+N @ max. -90dB -69dB -68dB -84dB output Total compensation - - 35pF 14pF capacitance

Quiescent power 12.0mW 2.5mW 12.5mW 1.2mW

FOM 8.1 1.3 4.3 33.3 voltages for the output stage. The following section gives a brief introduction to replica biasing. 2.7 Replica Biasing

A replica bias circuit is used for generating bias voltages for the output stage [21]. A replica bias circuit can be used in a class-AB amplifier to bias the common-source amplifiers of the output stage. The bias voltages generated by the replica bias circuit acts as Vbat as shown in Fig. 2.3. When no input signal is present, transistors of the output stage are in ON state but in a non-linear region. The quiescent current in the output stage is set by the current through the replica bias circuit [8]. The output stage acts as a class-A amplifier, as the output transistors are either sourcing or sinking current all the time. This eliminates the dead band region and minimizes the distortion in class-AB amplifiers.

20 The schematic of a two-stage pseudo class-AB ampliﬁer and the replica bias circuit to control quiescent current adapted from [8] are shown in Fig. 2.10.

VCTRL

M4 M5

M11 M8 x y M6

VI– VI+ RC CC M2 M3

Vout RLarge VB 2IB CC

M10 M9 M7

(a)

M5C

M6C MP VCTRL Vref RC M3C

CC VB IB IB VB M1C MN MB

(b)

Figure 2.10: (a) Schematic of two-stage pseudo class-AB ampliﬁer (b) Replica bias circuit to control quiescent at the output stage

The two-stage pseudo class-AB amplifier has a fully-differential first-stage.

The transistors M6 and M7 are common-source amplifiers that provide the push- pull action. The replica bias circuit is used for controlling the quiescent current through output-stage transistors M6 and M7. The transistors M5C , M3C , M1C and M6C are replicas of M5, M3, M1 and M6 respectively. The transistor MB 21 is biased at a voltage VB such that the current through MB is IB. The current through transistors MP , M5C and M5 are similar, as they have same VSG. Thus, the voltage at the drain of M5C is similar to the voltage at node ’y’. This causes the current through M6 to be same as the current through M6C (IB). Hence, a quiescent current of known value is obtained at the output of a two-stage pseudo class-AB amplifier. A feedback network is used along with the replica bias circuit to generate bias voltages for the output-stage. Three-stage class-AB amplifier designed in our work use the concept of replica bias to generate bias voltages and control quiescent current at the output stage. The design of the amplifier is discussed in Chapter. 3.

22 Chapter 3

DESIGN OF THE THREE-STAGE CLASS-AB AUDIO AMPLIFIER

A three-stage class-AB audio amplifier is designed to drive 16-Ω headphone speakers. The audio amplifier has high power efficiency and low distortion, and it is also capable of driving a wide range of capacitive loads. This chapter deals with the design of the three-stage class-AB amplifier. It is organized as follows: The key aspects and architecture of the audio amplifier is discussed in the first section. It is followed by the design of each stage with small signal models. The last section of the chapter deals with the stability of the amplifier that is analyzed with poles and zeros. 3.1 Architecture and Key Aspects of the Audio Amplifier

The architecture of the designed three-stage class-AB audio amplifier is shown in Fig. 3.1. The design is implemented using fully-differential internal stages. The first stage is a fully-differential folded cascode amplifier with an inverting gain configuration. The second-stage is implemented with two two differential amplifiers. A non-inverting gain configuration is used in this stage. The third stage is implemented with PMOS and NMOS common-source amplifiers for the push-pull action. The gain experienced by the load at the output through NMOS and PMOS common-source amplifiers is same. The symmetry in gain is achieved using two differential amplifiers in the second-stage. In the absence of input signal, a dead band region is created at the output, as the NMOS and PMOS common-source

23 Cc1 Rc1

2·Cc3

+ - A2 Vo2P+ - + -A3

2·Cc3 Cc2 Vin+ Vo1– Rc2 + - Vout A1 - + Vin– Vo1+ Cc2 Cc3

- + -A3 A2 Vo2N+ + -

Cc3

Figure 3.1: Architecture of the proposed three-stage class-AB ampliﬁer ampliﬁers are turned OFF. This leads to crossover distortion. To minimize the distortion, a common-mode feedback network is used in combination with replica bias in the second-stage to generate bias voltages for the third-stage . This turns ON the transistors of the third-stage and the dead band region is eliminated. The linearity in the design is achieved using a technique called substrate biasing. The threshold voltage of all NMOS transistors are made comparable to threshold voltage of the PMOS transistor. This is attained by connecting the bulk of the NMOS transistor to a voltage lower than source voltage. This is explained in detail in the following sections.

24 3.2 Transistor Level Three-Stage Design

The transistor level schematic of the three-stage class-AB audio amplifier is shown in Fig. 3.2. The first stage is a fully-differential folded cascode amplifier

realized with transistors M1-M12. The transistors M13-M20 in combination with resistors R1 and capacitors CS form the common-mode feedback network. The second-stage is realized using two differential amplifiers. A NMOS differential amplifier is formed with transistors M40-M47 and the PMOS differential amplifier is formed with transistors M21-M28. The transistors M37-M39 and M56-M58 are replica bias circuits. The output-stage is realized with transistors MP and MN . A Miller compensation is used from the output of third-stage to negative output terminal of the first-stage. A reverse-nested Miller compensation is used between input and output of the second-stage. The transistor dimensions are given in Table 3.2. In this work, four designs are implemented. The difference in each design is the dimensions of the transistors M39 and M58, the value of compensation capacitors and resistors, and the input bias current. A trade-off has been observed between the total harmonic distortion and quiescent current. This is discussed in Chapter 4. The design of each stage is explained in the following sections. 3.3 Bias circuit

The schematic of the bias circuit is shown in Fig. 3.3. The bias circuit internally generates four bias voltages Vb1, Vb2, Vb3 and Vb4. The voltage Vb2 is one VSG below VDD. This is generated by diode connecting the transistor M1A as shown in Fig. 3.3. Similarly the voltage Vb1 is generated. A long L (length) diode connected transistor is created by connecting the gates of transistors M4P 1-M4P 5 as shown in Fig. 3.3. The voltage Vb3 at the gate

of transistor M3A is 2VDSSAT + VTHP . The current through this transistor is given

25 Table 3.1: Transistor Dimensions

Device Dimensions 20µm M1A, M1B, M1C , M19, M20, M35, M36, M50, M51 1.2µm 20µm M11, M12, M27, M28, M48, M56 1.2µm, m = 2 20µm M1 1.2µm, m = 4 20µm M47 1.2µm, m = 8 20µm M2C , M17, M18, M33, M34 0.9µm 20µm M9, M10, M31, M32, M49, M57 0.9µm, m = 2 20µm M2 0.9µm, m = 4 20µm M46 0.9µm, m = 8 60µm M4A, M4B, M4C , M54, M55, M15, M16, M31, M32 1.2µm 60µm M4, M5, M13, M29, M37, 1.2µm, m = 2 60µm M5, M6, M21, M40, M41, M44, M45 1.2µm, m = 4 60µm M23, M26 1.2µm, m = 6 60µm M3A, M3B, M3C , M52, M53 0.9µm 60µm M7, M8, M14, M30, M38 0.9µm, m = 2 60µm M22, M42, M43 0.9µm, m = 4 30µm M4P 1, M4P 2, M4P 3 , M4P 4, M4P 5 1.2µm 10µm M1N1, M1N2, M1N3 , M1N4, M1N5 1.2µm 150µm M39 0.6µm , m = 4,6 150µm MN 0.6µm , m = 40 300µm M58 0.6µm , m = 4,6 300µm MP 0.6µm , m = 40

26 Bias circuit First-stage

M Vb2 M Vb2 M Vb2 Vb2 Vb2 5 6 13 M4A M4P5 M4B M4C Vb3 Vb3 Vb3 M14 M3A M4P4 M3B Vb3 M Vb3 M M M3C 7 8 4P3 Vb4 Vr M15 M16 CS CS Vc Cc2 M4P2 Vo2 M1N1 P+

Vin+ Vin- V

M4P1 o M3 M4 - Vo1+ 1 M1N2 1 R1

R1 + o

V Rc2 Vo2N+ M1N3 Vb4 M2C Vb4 Vb4 Vb4 Cc2 M2 M9 M10 M17 M18 Vbias M1N4 Vb1 M1A M1B M1N5 M1C Vb1 M1 M11 M12 M19 M20 Replica-bias

27 Vb2 Vb2 Vb2 M21 M29 M37 Vo2P+ Vrp MP M40 M41 M54 M55 M58 Vb3 Vb3 Vb3 M M30 M38 22 Vb3 M42 Vb3 M43 M52 M53 Vrs

Vo1! Vo1+ Vo1! !

M M P 23 24 M31 M32 CS CS + 2 P o Cc3 2 Cc3 o V Rc1 Cc1 V Vout 2·Cc3 R2/2 R2/2 2·Cc3

! C C S S + Vrc N N 2 2 o o M M45 M50 M51

V 44 R2 R2 V Vo1! Vo1+ Vb4 Vb4 M25 M26 M33 M34 Vb4 Vb4 Vb4 M46 M49 M57 Vrn M M M M M Vo2N+ 27 28 35 36 39 M Vb1 Vb1 Vb1 N M47 M48 M56 Replica-bias Second-stage Third-stage

Figure 3.2: Schematic of the three-stage class-AB audio ampliﬁer Vb2 Vb2 Vb2 M4A M4P5 M4B M4C Vb3 Vb3 M3A M4P4 M3B Vb3 M M4P3 Vb4 3C

M4P2 M1N1

M4P1 M1N2

Vb3 M1N3 Vb4 M2C IB1 Vbias IB2 M1N4 Vb1 M1A M1B M1N5 M1C

Figure 3.3: Schematic of the bias circuit by

µN · COX W3A 2 ID = · · (VGS − VTHP ) (3.1) 2 L3A

As the current

IB1 = IB2 (3.2)

The current through the Long ’L’ transistor formed by the transistors M4P 1-M4P 5 is given by

µN · COX W4P 2 ID = · ((2VDSSAT + VTHP ) − VTHP ) (3.3) 2 L4P

This equation can be rewritten in terms of VGS as

µN · COX W4P 2 ID = · · 4(VGS − VTHP ) (3.4) 2 L4P

28 Thus from (3.1), (3.2) and (3.4) we obtain

W 1 W 4P = 3A (3.5) L4P 4 L3A

The transistor M4A is biased at the edge of the saturation region, thus pulling more current from transistor M4A, moves it from saturation to triode region [12].

Hence, the length of the long L transistor is assumed ﬁve times the length of M3A

rather than four times. This generates a voltage Vb3 that is VSDSAT away from Vb2.

Similarly, the voltage Vb4 is generated that is VDSSAT away from Vb1. The bias voltages are replicated to others stages of the ampliﬁer through transistors

M1C -M4C . The current through the branch M1C -M4C is mirrored to the next stages based on the aspect ratio of the current mirror. 3.4 Input-Stage

The first stage of the amplifier is realized using a fully-differenatial folded cascode amplifier, as they have wide swing and high gain. The schematic of the

ﬁrst stage is shown in Fig.3.4. Transistors M1-M12 represent the folded cascode

amplifier. The transistors M13-M20 in combination with resistors R1 and capacitors CS form the common-mode feedback network. A common-mode feedback network is used for generating a known voltage Vr at the output of the folded cascode amplifier. The operation of the first-stage is as follows. The voltage Vr is set to 0V, this allows the current to pass through the transistor M16. The voltage at the node VX increases. The transistors M20, M11 and M12 form the current mirror.

The current through the transistors M11 and M12 depends on the aspect ratio

29 Vb2 Vb2 M5 M6 M13 Common-mode Feedback network Vb3 M14 Vb3 M7 M8 Vr M15 M16 CS CS Vc

Vin+ Vin- V o

M3 M4 - 1 1 R1 R1 + o VX V

Vb4 Vb4 Vb4 M2 M9 M10 M17 M18

Vb1 M1 M11 M12 M19 M20

Figure 3.4: Schematic of the ﬁrst-stage

of the mirror. Hence the voltages Vo1+ and Vo1- are pulled towards VSS. The voltage Vc acts as virtual ground, as it is the center voltage of Vo1+ and Vo1-.

The gain of the ﬁrst-stage is determined by the gm4,3 resistors R1, as R1 ro of the transistors. The tail of the folded cascode ampliﬁer and common-mode feedback network are cascoded to provide better matching between the transistors and to obtain good precision in matching the currents. Under equilibrium condition, the voltage Vo1+ and Vo1- are approximately at 0V. This voltage is used for biasing the second stage. The implementation of second-stage is explained in the following section. 3.5 Second-Stage

The second stage of the amplifier is implemented using a NMOS differential amplifier and a PMOS differential amplifier. The NMOS differential amplifier is used for biasing PMOS common-source amplifier of the third-stage and the PMOS

30 differential amplifier is used for biasing NMOS common-source amplifier of the third-stage. 3.5.1 PMOS differential amplifier

The schematic of a PMOS diﬀerential ampliﬁer is shown in Fig. 3.5

Vb2 Vb2 CMFB Vb2 M21 M29 M37

Vb3 Vb3 Vb3 M22 M30 M38

Vo1– Vo1+ M23 M24 M31 M32 Cc3 Cc3

– C C S S + Vrc N N 2 2 o o V R2 R2 V Vb4 Vb4 M25 M26 M33 M34

Vrn M27 M28 M35 M36 M39

Replica bias

Figure 3.5: Schematic of the second-stage PMOS diﬀerential ampliﬁer

Transistors M21-M28 form the PMOS diﬀerential ampliﬁer. The common- mode feedback network (CMFB) is realized with transistors M29-M36 and resistors

R2 and capacitors CS. Transistors M37-M39 form the replica bias circuit. The current through this circuit is determined by the current source formed by transistors

M37 and M38. The voltage Vrn is at VGS above VSS. The common-moded feedback network generates the known voltage Vrn at the output of the PMOS differential amplifier. The gain of the amplifier is determined by resistors R2 and the

transconductance gm23,24 . 31 Under equilibrium, the common-mode voltage Vrc is equal to V o2N+. This voltage is used as the input for the NMOS common-source amplifier of the third- stage. Since, V o2N+ is equal to Vrn, transistors M39 and MN form a virtual current mirror. Thus, the quiescent current of the output stage is determined by the current through M39. The ratio of currents depends on the ratio of multiplicity of transistor dimensions. 3.5.2 NMOS differential amplifier

The NMOS differential amplifier is similarly designed. The schematic of the NMOS differential amplifier is shown in Fig. 3.6.

Replica bias

Vrp M40 M41 M54 M55 M58

Vb3 M42 Vb3 M43 M52 M53 Vrs

– P CS CS + 2 P o 2 o V V 2·Cc3 R2/2 R2/2 2·Cc3

M44 M45 M50 M51 Vo1– Vo1+

Vb4 Vb4 Vb4 M46 M49 M57

Vb1 Vb1 Vb1 M47 M48 M56 CMFB

Figure 3.6: Schematic of the second-stage NMOS diﬀerential ampliﬁer

Transistors M40-M47 form the NMOS diﬀerential ampliﬁer. The common- mode feedback network (CMFB) is realized with transistors M48-M55 and resis-

R2 tors 2 and capacitors CS. Transistors M56-M58 form the replica bias circuit. The 32 current through this circuit is determined by the current-source formed by tran-

sistors M56 and M57. The voltage Vrn is at VSG below VDD. The common-moded feedback network generates the known voltage Vrp at the output of the NMOS

R2 differential amplifier. The gain of the amplifier is determined by resistors 2 and

the transconductance gm44,45 .

Under equilibrium, the common-mode voltage Vrs is equal to V o2P +. This voltage is used as the input for the PMOS common-source ampliﬁer of the third-

stage. Since V o2P + is equal to Vrp, transistors M58 and MP form a virtual current mirror. Thus, the quiescent current of the output stage is determined by

the current through M58. The ratio of currents depends on the ratio of multiplicity of transistor dimensions.

The dimensions of the transistors M46 and M47 are doubled to obtain twice

the bias current than the current through M21 and M22 of Fig. 3.5. Thus, the

R2 gain of the NMOS diﬀerential pair is 2·gm44,45 · 2 , which is equivalent to the PMOS

differential amplifier gain gm23,24 ·R2. The gain of the PMOS differential amplifier is made equal to the NMOS differential amplifier to attain symmetry at the output of the amplifier. Unlike the first-stage, the second-stage is a single-ended differential amplifier. The output of the NMOS and PMOS differential amplifiers are the inputs for PMOS and NMOS common-source amplifiers of the third-stage, respectively. The design of the third-stage is discussed in the next section. 3.6 Output-Stage

The output-stage of the ampliﬁer is implemented with huge PMOS and

NMOS common-source ampliﬁers. In order to have same current ID through

transistors MP and MN , the dimensions of the PMOS transistor MP is made twice

the size of NMOS transistor MN , as the mobility of the electrons is approximately

33 about 2.5 times the mobility of holes. The schematic of the output-stage is shown in Fig. 3.7

Vo2P+ MP

Vo1–

Rc1 Cc1 Vout

Vo2N+ MN

Figure 3.7: Schematic of the output-stage

The input capacitance CGS associated with transistor MP is twice the capacitance CGS of the transistor MN , as dimensions of the transistor MP is twice the size of transistor MN . The pole of the second-stage PMOS differential amplifier is approximately at 1 . In order to have the same pole at the output R2·CGSN of NMOS differential amplifier, the resistance R2 is halved and the compensation capacitance is doubled. The pole of NMOS differential amplifier is approximated

1 as R2 . 2 ·(2CGSN )

34 Output swing at the second-stage NMOS differential amplifier must be equal to the output swing of PMOS differential amplifier to attain linearity at the output. The swing at the output of second-stage is determined by voltages Vrn and Vrp shown in Fig. 3.5 and Fig. 3.6. The voltage Vrn is made equal to Vrp to obtain same swing at the input of third-stage and this is achieved by biasing

the bulks of NMOS transistors at a voltage lower than VSS. This increases the threshold voltage of NMOS transistors. Hence, more voltage is required at the

gate of transistor M39 to allow the current from transistors M37 and M38 to pass through. Thus, VGS of transistor M39 increases and this is comparable to Vrp. The designed amplifier has three stages. Hence, the stability of the amplifier cannot be achieved without a compensation network. Miller compensation and reverse-nested Miller compensation are used to stabilize the three-stage class- AB amplifier. A brief description of the compensation network used in this design is given in the following section. 3.7 Compensation used in the Design

The first-stage is an inverting gain configuration and second stage is a non- inverting gain configuration. The output-stage is implemented with an inverting gain configuration. A Miller compensation network is applied between the output of first-stage and the output of the third-stage. Reverse-nested Miller compensation is used across the second-stage for NMOS and PMOS differential amplifiers as shown in Fig. 3.1. A symmetry is maintained while using the compensation networks at the second-stage. This simplifies the small-signal model of the amplifier. The small- signal model of each stage is discussed in the next section.

35 3.8 Small-Signal Models

The small-signal model of a symmetric folded-cascode ampliﬁer is represented with a current source and a resistor parallel to it. The input-stage in this

design is not symmetric, as the compensation capacitor CC1 is connected to Vo1- and there is no compensation capacitor to Vo1+. Hence, the circuit is divided into two equivalent circuits. The left-half of the folded-cascode ampliﬁer and its corresponding small signal model is shown in Fig. 3.8, where gm1 is the transcon-

Vb2 M5 Vo1-

Vb3 M7

CS -

1 R1 Vin+ o

M3 V R1 gm1·Vin/2

Vb4 Vb4 M2 M9

Vb1 M1 M11

(a) (b)

Figure 3.8: (a) Left-half of the input-stage (b) small-signal model for left half.

V in ductance of the transistor M3. The input signal is assumed as 2 , since Vin =

(Vin+ - Vin-) and Vin+ is only half of the signal Vin. The resistor R1ro. Thus R1 is the output resistance at node Vo1-. One end of the resistor R1 is connected to node Vo1- and the other end is at virtual ground. Similarly, the small-signal model for right-half of the folded cascode am-

pliﬁer is as shown in Fig. 3.9, where gm1 is the transconductance of M4 and Rc2 is the compensation resistor. Under quiescent conditions the current through M3

36 Vb2 M6

Vb3 M8 C Rc2 S Vo1+ Vx Vin- M4 Vo1+ Vx R1 gm1·(-Vin/2) Rc2 R1

M Vb4 Vb4 2 M10

Vb1 M 1 M12

(a) (b)

Figure 3.9: (a) Right-half of the input-stage (b) small-signal model for right-half.

is equal to current through M4. Thus the gm’s are equal. The signal Vin- is

−V in represented as 2 . The resistor R1 is approximately equivalent to resistor R1 shown in Fig. 3.8(a). The second-stage is implemented with NMOS differential amplifier and PMOS differential amplifier. Thus for each amplifier, the small-signal models are drawn separately. The PMOS differential amplifier has symmetry at compensation, hence only the output side of the differential amplifier is considered for drawing the small-signal model as shown in Fig. 3.10.

The transconductance of the transistor M24 is gm2. The resistor R2 is

the output resistance at node V o2n+. Cc2 and Cc3 are compensation capacitors.

Capacitor C2 in Fig. 3.10(b) is the input capacitance CGS of the transistor MN of the output-stage. The voltage Va is (Vo1+ - Vo1-) and the voltage Vo1+ is

V a represented as 2 .

37 Vb2 M21

Vb3 M22

Vo1+ M24 Cc3 Cc2 Cc3 CS Vx Vo2n+ Vo1+

Vo2n+ Vx R2 R2 Vb4 Cc2 C2 M26 gm2·Va/2

M28

(a) (b)

Figure 3.10: (a) PMOS differential amplifier (b) small-signal model PMOS differential amplifier.

The part of NMOS differential amplifier and it corresponding small-signal model are shown in Fig. 3.11. Similar to the PMOS differential amplifier, the compensation in NMOS differential amplifier is symmetric.

The input capacitance C2 of the transistor MP of output-stage is twice

the input capacitance of NMOS transistor MN of the output-stage, as the size of

PMOS transistor MP is twice the NMOS transistor MN . Thus to provide the same pole frequency at the output of second-stage the common-mode feedback resistor

R2 is made 2 and the compensation capacitor Cc3 is doubled. The transconductance

of the transistor M45 is 2·gm2, as the current through the transistor M45 is twice

V a the current through transistor M24 in Fig. 3.10. The signal Vo1+ is 2 . The V a current through current source in Fig. 3.11(b) is given by 2·gm2 · 2

38 M41

Vb3 M43

Vo2p+ Vx

Cc2

R2/2 2Cc3 M 45 2Cc3 Cc2 Vo1+ Vo1+ Vo2p+ Vx

Vb4 M46 gm2·Va 2·C2 R2/2 Vb1 M47

(a) (b)

Figure 3.11: (a) NMOS differential amplifier (b) small-signal model NMOS differential amplifier.

The third stage is implemented with NMOS and PMOS common-source ampliﬁers. These transistors provide the required push-pull action for the class-AB output-stage. The schematic of output-stage and its corresponding small-signal model are shown in Fig. 3.12.

The transconductance of transistors MN and MP is gm3, as the quiescent

current through transistors MN and MP is same. Cc1 and Rc1 are the Miller compensation capacitor and nulling resistor across the outputs of input-stage and output-stage. Cout is the load capacitance. Rout is the output resistance of the ampliﬁer and is given by

Rout = RLkroN kroP (3.6)

39 Vo2P+ MP

Vo1–

Rc1 Cc1 Vout

Cc1 Rc1 Vout- Vout

Rout gm3·Vop+ Cout gm3·Von+ Vo2N+ MN

(a) (b)

Figure 3.12: (a) Schematic of output-stage (b) small-signal model for output-stage

Rout ≈ RL as RL roN,P The complete small-signal model of the designed three-stage class-AB audio ampliﬁer is shown in Fig. 3.13. The equations for current at each node are put in a software Maple to determine the poles and zeros in the ampliﬁer. The equation of the currents at each node and equations used to determine the pole/zero frequencies is shown in APPENDIX B. 3.9 Pole-Zero Analysis

The gain of the ampliﬁer is determined from the equations in APPENDIX B as

Gain = gm1 · R1 · gm2 · R2 · gm3 · Rout (3.7)

The designed audio ampliﬁer has six poles and ﬁve zeros. The poles and zeros obtained are shown in Table 3.2. The fourth pole is at high frequency, hence the last two high frequency poles are neglected. The third zero is a RHP zero. The

40 Rc2 Cc1 Rc1

2·Cc3 Cc3 Cc2 Cc2 Vout Vo1- Vo1+ Vo2P+ Vo2N+ Vx R1 41 gm2·Va R2 Rout 2·C2 C2 Cout R1 gm1·Vin/2 gm1·(-Vin/2) R2/2 gm2·Va/2 gm3·Vo2P+ gm3·Vo2N+

Figure 3.13: Small-signal model of the designed three-stage class-AB audio ampliﬁer other two zeros are high frequency zeros, thus neglected. The ﬁrst zero (ωZ1) is used, to cancel the second pole (ωP 2). Similarly the second zero ωZ2 cancels third pole ωP 3. Thus the system acts as a two-pole system, where the fourth-pole is considered as second-pole.

Table 3.2: Poles and Zeros

Poles / Zeros

2 ωP 1 gm2·R1·R2(2·Cc2+2·gm3·Rout·Cc1+3·Cc3)

2·Cc2+2·gm3·Rout·Cc1+3·Cc3 ωP 2 Cc1·(2·gm3·Rout·R2·C2+2·R1·Cc2+3·R1·Cc3)

2·gm3·Rout·R2·C2+2·R1·Cc2+3·R1·Cc3 ωP 3 R1·R2·C2·(6·gm3·Rout·Cc3+4·gm3·Rout·Cc2+2·Cc2+3·Cc3)

gm2·(2·gm3·Rout+1) ωP 4 Cout·Rout·gm2+2·C2

2 ωZ1 Cc1·R1+2·R2·C2

1 2 ωZ2 R2·C2 + Cc1·R1

gm2 ωZ3 - 2·Cc3

42 Chapter 4

SIMULATION RESULTS

To test the functionality of the designed three-stage class-AB audio amplifier, the amplifier is subjected to DC, AC and transient analysis tests. The following sections discuss the response of the of the amplifier. The obtained waveforms are plotted using the Matlab code given in APPENDIX C. Four designs have been implemented by varying the input bias current, dimensions of M39 and M58 shown in Fig. 3.2, compensation capacitor and resistor values and its corresponding results are plotted. The designs are named after their performance as LIQ (Low quiescent current), LTHD (Low THD), MIQ (Moderate quiescent current) and HCL (High load capacitance). The design parameters of the four designs are given in Table 4.1.

Table 4.1: Design Parameters

Design IB Rc1 Rc2 Cc2 Cc3 M39 & M58

HCL 8 µA 1 kΩ 1 kΩ 500 fF 500 fF m = ×4

LTHD 9 µA 1 kΩ 2 kΩ 200 fF 300 fF m = ×4

MIQ 9 µA 1 kΩ 2 kΩ 200 fF 300 fF m = ×6

LIQ 8 µA 1 kΩ 2 kΩ 300 fF 300 fF m = ×6

43 The bulk terminal of all the NMOS transistors are connected to -3V for all the tests performed. 4.1 DC analysis

The DC analysis determines the symmetry and linearity of the amplifier. The test-bench for DC analysis of the amplifier is shown in Fig 4.1. The input is a DC voltage varied from -2mV to 2mV. To obtain the differential input voltage, two voltage controlled voltage sources (VCVS) are used. One VCVS is with 0.5 gain and the other is with -0.5 gain. The input bias current of the amplifier is 8µA.

vdd Ibias + + Vin-vdd - egain= -0.5 Vbias Vb2 Vout Vin + Vin+

R =16 Ω CL + + + egain= 0.5 Vr vss L - b

vss_sub u s _ s s vss v

Figure 4.1: Schematic of the DC test-bench

The simulation results obtained for a resistive load of 16-Ω and capacitive load of 500 pF are shown in Fig 4.2 The maximum current through the NMOS and PMOS transistors of the output stage is 83.5mA. The maximum swing at the output is observed as ±1.25V. 4.2 AC analysis

The AC analysis determines the stability of the ampliﬁer. The test-bench for the AC analysis is shown in FIg. 4.3. Input is a 1V AC signal given at positive input terminal of the ampliﬁer. A large resistor and capacitor are used in the feedback network to provide open-loop operation. 44 1.5 M = ON N M = ON 1 P M = OFF N M = ON P 0.5

−0.5

Output Voltage (V) M = ON N M = OFF P −1

−1.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 100

80 I , M I , M D N D P 60

20 Output − Stage Current (mA) 0

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 DC Input (mV)

Figure 4.2: DC-analysis output

The simulation results of the LIQ design is given in Fig. 4.4. The circuit has input bias current of 8µA. The open loop gain of the amplifier is 48.4 dB The input bias current of the LTHD design is made 9µA. The magnitude and phase plots of the design is given in Fig. 4.5. The open-loop gain of the amplifier is 53.7 dB. The MIQ design is tested with a input bias current of 9µA. The simulation results of the design is given in Fig. 4.6 and open-loop gain of the amplifier is 50.6 dB

45 1GΩ

vdd

I + bias

Vin-vdd 1F Vbias Vb2 Vout + Vin+ 1Vac + + C vss_sub Vr vss RL=16 Ω L b u s _

vss s s v

Figure 4.3: Schematic of the AC test-bench

Table 4.2: AC Simulation Results Phase Gain Design Gain Gain Bandwidth Margin Margin

HCL 51.5 dB 72.04 ◦ 15.52 dB 1.23 MHz

LTHD 53.7 dB 70.8 ◦ 11.5 dB 2.03 MHz

MIQ 50.6 dB 70.3 ◦ 14.5 dB 1.56 MHz

LIQ 48.4 dB 70.7 ◦ 16.4 dB 1.24 MHz

The simulation results of the HCL design is given in Fig. 4.7. The circuit has input bias current of 8µA.The open loop gain of the ampliﬁer is 51.5 dB The open loop gain, gain margin, phase margin and unity gain frequency of four designs are tabulated and given in Table 4.2. The gain-bandwidth product of the LTHD design is 2.03 MHz. MIQ design has the highest phase-margin among the four designs.

46 50

Gain (dB) −50

−100 100 101 102 103 104 105 106 107 108 100

−100

−200 Phase (deg)

−300

−400 100 101 102 103 104 105 106 107 108 Frequency (Hz)

Figure 4.4: AC output of LIQ circuit

−20 Gain (dB) −40

−60

−80 100 101 102 103 104 105 106 107 108 100

−100

−200 Phase (deg) −300

−400 100 101 102 103 104 105 106 107 108 Frequency (Hz)

Figure 4.5: AC output of LTHD circuit

47 60

−20 Gain (dB) −40

−60

−80 100 101 102 103 104 105 106 107 108

100

−100

−200 Phase (deg)

−300

−400 100 101 102 103 104 105 106 107 108 Frequency (Hz)

Figure 4.6: AC output of MIQ design

4.3 Transient analysis

The transient analysis determines the time domain response of a amplifier. A square wave of ±100mV and 50kHz frequency is given at the negative input terminal. The rise time and fall time of the input is 10 nS. The amplifier has a inverting gain of ’4’. The test-bench for transient analysis is shown in Fig. 4.8. The simulation result for LIQ is shown in Fig. 4.9. The load capacitance of the amplifier is varied from 10 pF to 1.5 nF. LTHD design has no ringing at the output up-to 1 nF. The output of the amplifier for different load capacitances is shown in Fig. 4.10.

48 60

−20 Gain (dB)

−40

−60

−80 100 101 102 103 104 105 106 107 108 100

−100

−200 Phase (deg)

−300

−400 100 101 102 103 104 105 106 107 108 Frequency (Hz)

Figure 4.7: AC output of HCL circuit

40KΩ

vdd

Ibias + 10KΩ Vin-vdd + V Va=100mV bias Freq=50KHz Vout Vin+ Vb2

+ + CL vss_sub Vr vss RL=16 Ω b u s _

vss s s v

Figure 4.8: Schematic of the Transient test-bench

49 0.1

0 Input (V) −0.1

5 10 15 20 25 2.5

2 C = 1.5 nF L

1.5

1 C = 500 pF

Output (V) L

0.5

C = 10 pF L 0

5 10 15 20 25 Time (µS)

Figure 4.9: Transient output of LIQ circuit

0.1

Input (V) −0.1

5 10 15 20 25

2.5

2 C = 1 nF L

1.5

1 C = 500 pF

Output (V) L

0.5

C = 10 pF L 0

5 10 15 20 25 Time (µS)

Figure 4.10: Transient output of LTHD circuit

50 The simulation result for MIQ is shown in Fig. 4.11. The load capacitance of the ampliﬁer is varied from 10 pF to 1 nF.

0.1

Input (V) −0.1

5 10 15 20 25

2.5

2 C = 1 nF L

1.5

1 C = 500 pF L Output (V)

0.5

C = 10 pF L 0

5 10 15 20 25 Time (µS)

Figure 4.11: Transient output of MIQ circuit

The load capacitance for HCL design is varied from 10 pF to 5 nF, and there was no ringing at the output. The slew-rate of the design is 1.25 V/µS. The simulation result for HCL design is shown in Fig. 4.12. 4.4 THD analysis

A transient analysis has been performed on the amplifier to determine the total harmonic distortion. The amplifier is connected in inverting gain configuration with gain 1. The input is a sine wave of 2.45VPP and frequency of 1kHz. The test-bench for the measuring THD is shown in Fig. 4.13. The input has a dead time of 10 µS. The quiescent power of the amplifier is determined at 5 µS, when there is no input signal. The THD of designs is measured by using the THD-option of the simulator for a sample of the output signal. To 51 0.1

Input (V) −0.1

5 10 15 20 25

2.5

2 C = 5 nF L

1.5

1 C = 500 pF

Output (V) L

0.5

C = 10 pF L 0

5 10 15 20 25 Time (µS)

Figure 4.12: Transient output of HCL circuit

Table 4.3: Transient Simulation Results Quiescent Peak Design C THD FOM LOAD Power Power

HCL 10 pF - 5 nF -77 dB 1.77 mW 97.6 mW 55.23

LTHD 10 pF - 1 nF -80.89 dB 1.98 mW 97.6 mW 49.27

MIQ 10 pF - 1 nF -78.56 dB 1.66 mW 97.6 mW 59.40

LIQ 10 pF - 1.5 nF -77.29 dB 1.47 mW 97.6 mW 66.25 measure the THD precisely, the time step parameters have been modiﬁed. The step is given as 1µ and Max. step as 1µ. The output waveform for measuring the THD is shown in Fig. 4.14. The THD and quiescent power measurements for four designs are shown in Table 4.3.

52 40KΩ

vdd

Ibias + 40KΩ Vin-vdd + Va=1.25V Vbias Freq=1KHz Vout Vin+ Vb2

+ + CL vss_sub Vr vss RL=16 Ω b u s _

vss s s v

Figure 4.13: Schematic for THD measurement

1.5

0.5

0 Input (V) −0.5

−1

−1.5 0 0.5 1 1.5 2 2.5 1.5

0.5

0 Output (V) −0.5

−1

−1.5 0 0.5 1 1.5 2 2.5 Time (mS)

Figure 4.14: Transient output for measuring THD

53 Chapter 5

HARDWARE TESTING

The three-stage class-AB audio amplifier is fabricated in ON-SEMI 0.5µm process through MOSIS. The hardware test is the real-time test for determining the functionality of the amplifier. This chapter describes the layout techniques used in the design, the experimental setup used for testing and the tests performed to determine the operation of the audio amplifier. 5.1 Layout

The layout of four designs is implemented using the virtuso environment of Cadence. A common-centroid technique is used to attain matching between devices. The current at the output-stage is huge, hence strapping technique is used for the huge current to ﬂow through the transistor of the output-stage. In order to avoid noise that can be coupled with bias voltage, the bias voltage Vb1 and Vb4 are shielded with substrate biasing voltage and Vb2 and Vb3 are shielded

with VDD. The layout of the four designs are shown in Fig. 5.1, Fig. 5.2, Fig. 5.3 and Fig. 5.4. The designs are arranged in the frame of 40 pins. The layout of the frame with the designs is shown in Fig. 5.5 and Fig. 5.6. The micrograph of the chip is shown in Fig. 5.7. 5.2 Experimental Setup

The following apparatus are used for measuring the outputs:

54 Figure 5.1: Layout of LIQ ampliﬁer

1. Oscilloscope: Hewlett Packard: 54600B: 100MHz, Digital Storage Oscillo- scope.

The oscilloscope is used for plotting the input and output waveforms for a transient response.

2. Function Generator: Agilent: 33120A: 15 MHz Function/Arbitary Wave- form Generator.

The function generator is used for generating the input signals/waveforms.

1 3. Digital Multimeter: Agilent: 34401A: 6 2 Digit Multimeter.

55 Figure 5.2: Layout of LTHD ampliﬁer

The Digital multimeter is used in this work for determining the DC voltages AC voltages and DC currents.

4. Stanford Research System: SR770 FFT Network Analyzer.

The Stanford research system is used to determine the THD in the design.

The DC, Transient and THD measurements are obtained using the above apparatus. The test procedure for these measurements is given in APPENDIX A. 5.3 DC Measurements

The amplifier is connected as a voltage follower and both input terminals of the amplifier are connected to ground. The output voltage is measured using 56 Figure 5.3: Layout of MIQ amplifier the digital multimeter. Under quiescent conditions the voltage obtained at the output is offset voltage. The offset voltages of all the designs are discussed in Chapter 6. The quiescent current is measured with the digital multimeter by creating an open circuit between the VDD and the VDD pin of the chip. 5.4 Transient Measurements

The test-setup for transient measurements is similar to the test-bench used in Fig. 4.8. The results obtained for each design for diﬀerent capacitive loads are plotted using the Matlab code given in APPENDIX C.

57 Figure 5.4: Layout of HCL ampliﬁer

5.5 THD Measurements

The ampliﬁer is used in inverting gain conﬁguration with a gain of 1. A in-

put signal of 2.45VPP and 1kHz frequency is applied at the negative input terminal of the ampliﬁer. The output amplitude is measured using a digital multimeter. The output is connected to the Stanford research system (SRC) to measure the THD at the output. The SRC gives the amplitude of fundamental frequency and its harmonics. The amplitude of ﬁrst 10 harmonics for each design are shown in Fig. 5.12, Fig. 5.13, Fig. 5.14 and Fig. 5.15.

58 MIQ

LIQ

Figure 5.5: Layout of the frame with two LIQ and MIQ.

The noise ﬂoor is at -106dB. The hardware measurements for all the designs are shown in Table 5.1.

59 LTHD

HCL

Figure 5.6: Layout of the frame with two LTHD and HCL.

60 Figure 5.7: Micrograph of the chip.

61 100

0 Input (mV) −100 0 5 10 15 20 25

2000

C = 2 nF L

1500

1000 C = 500 pF L Output (mV)

500

C = 10 pF L 0

−500 0 5 10 15 20 25 Time (µS)

Figure 5.8: Transient response of LIQ design (an oﬀset of 900mV is added intentionally for visibility)

100

Input (mV) −100 0 5 10 15 20 25

2000

C = 750 pF L

1500

1000 C = 500 pF L Output (mV)

500

C = 10 pF L 0

−500 0 5 10 15 20 25 Time (µS)

Figure 5.9: Transient response of LTHD design (an oﬀset of 900mV is added intentionally for visibility)

62 100

0 Input (mV) −100 0 5 10 15 20 25

2000

C = 1 nF L

1500

1000 C = 500 pF L Output (mV)

500

C = 10 pF L 0

−500 0 5 10 15 20 25 Time (µS)

Figure 5.10: Transient response of MIQ design (an oﬀset of 900mV is added intentionally for visibility)

100

0 Input (mV) −100 0 5 10 15 20 25

2000

C = 5 nF L

1500

1000 C = 500 pF L Output (mV)

500

C = 10 pF L 0

−500 0 5 10 15 20 25 Time (µS)

Figure 5.11: Transient response of HCL design (an oﬀset of 900mV is added intentionally for visibility)

63 20

−20

−40

−60 Magnitude (dBv)

−80

−100

−120 0 2 4 6 8 10 12 Frequency (KHz)

Figure 5.12: THD measurement for LIQ design

64 20

−20

−40

−60 Magnitude (dBv)

−80

−100

−120 0 2 4 6 8 10 12 Frequency (KHz)

Figure 5.13: THD measurement for LTHD design

65 20

−20

−40

−60 Magnitude (dBv)

−80

−100

−120 0 2 4 6 8 10 12 Frequency (KHz)

Figure 5.14: THD measurement for MIQ design

66 20

−20

−40

−60 Magnitude (dBv)

−80

−100

−120 0 2 4 6 8 10 12 Frequency (KHz)

Figure 5.15: THD measurement for HCL design

67 Table 5.1: Hardware Measurements Quiescent Output Design Oﬀset SR+ SR- THD Current Voltage

HCL 1.2 mV 475 µA 1.35 V/µs 1.47 V/µs 0.885 Vrms 11.34 m%

LTHD 6.66 mV 837 µA 1.23 V/µs 1.23 V/µs 0.883 Vrms 11.74 m%

MIQ 2.51 mV 391 µA 1.28 V/µs 1.07 V/µs 0.882 Vrms 11.85 m%

LIQ 6.6 mV 520 µA 1.35 V/µs 1.80 V/µs 0.882 Vrms 11.20 m%

68 Chapter 6

DISCUSSION AND CONCLUSION

A low distortion and high power efficiency three-stage class-AB audio amplifier was designed in 0.5 µm CMOS process. The parameter dimensions in the design were varied and a trade-off between total harmonic distortion (THD) and quiescent current (IQ) was observed. As the quiescent current in the amplifier was increased, the distortion of the amplifier decreased. To determine the power efficiency of an amplifier, a figure of merit (FOM) was defined by [1] as

P eak power delivered to the load FOM = (6.1) quiescent power

The ﬁgure of merit for each design was measured and tabulated in Table 6.1.

Table 6.1: Summary of Hardware Test Results Peak Design Quiescent current FOM Capacitive Load (CL) Power

HCL 475 µA 93.78 mW 65.81 10 pF - 5 nF

LTHD 827 µA 94.54 mW 38.10 10 pF - 750 pF

MIQ 391 µA 89.88 mW 76.63 10 pF - 1 nF

LIQ 520 µA 93.79 mW 60.12 10 pF - 2nF

69 The designed three-stage class-AB audio ampliﬁer (HCL) was compared with state-of-the-art. It was observed, [1] works for wide range of capacitive loads. The FOM of this work is greater than [1] by a factor of 2. Table 6.2 shows the comparison results between state-of-the-art and this work.

Table 6.2: Comparison of results with state-of-the-art ([1])

Parameter [18] [19] [20] [1] This Work

0.35-µm 65-nm 130-nm 0.5-µm Technology - CMOS CMOS CMOS CMOS

Capacitance 0-300 pF 0-300 pF 0-12 nF 1 pF-22 nF 1 pF-5 nF Load

Resistive 16 Ω 16 Ω 16 Ω 16 Ω 16 Ω Load

Supply 3.0 V 0.8 V 2.5 V 1.2 V/2 V 3.0 V

Output 2.5 V 0.45 V 1.85 V 1.60 V 2.45 V Voltage PP PP PP PP PP

THD+N∗ -90 dB -69 dB -68 dB -84 dB -78.90 dB

Total Com- pensation - - 35 pF 14 pF 14.5 pF Capacitance

Quiescent 12.0 mW 2.5 mW 12.5 mW 1.2 mW 1.43 mW Power

FOM 8.1 1.3 4.3 33.3 65.6

∗ @ Maximum Output

70 In order to attain similar results for simulation and hardware testing, the quiescent currents for all the designs in testing were made equal to the corresponding simulation results. The THD of designs observed in hardware testing were lower than their corresponding simulation results by approximately 5%. The comparison table for all four designs are shown in Table 6.3, Table 6.4, Table 6.5 and Table 6.6.

Table 6.3: Simulation vs Hardware (LIQ)

LIQ

Parameter Simulation Result Testing result

IQ 490 µA 490 µA

PQ 1.47 mV 1.47 mV

PP eak 97.6 mW 97.6 mW

VSSSUB -3V -3V

FOM 66.25 66.25

THD -77.29 dB -72.63 dB

The design and hardware issues encountered while testing the ampliﬁer are discussed below:

1. As two designs were inscribed in one chip, the transistors of the output stage can generate current even without the input. This unwanted current could not be accounted when calculating the quiescent current. Hence, a switch was used to turn OFF one design while testing the other.

2. While measuring the quiescent current, an oﬀset was observed at the output. As the load resistance is very small at the output node, a small oﬀset 71 Table 6.4: Simulation vs Hardware (LTHD)

LTHD

Parameter Simulation Result Testing result

IQ 660 µA 660 µA

PQ 1.98 mV 1.98 mV

PP eak 97.6 mW 97.6 mW

VSSSUB -3V -3V

FOM 49.27 49.27

THD -80.89 dB -74.34 dB

Table 6.5: Simulation vs Hardware (MIQ)

MIQ

Parameter Simulation Result Testing result

IQ 553 µA 556 µA

PQ 1.66 mV 1.67 mV

PP eak 97.6 mW 96.8 mW

VSSSUB -3V -3V

FOM 58.83 57.96

THD -78.58 dB -73.76 dB generates a current through the load. This current cannot be accounted for quiescent current calculation, hence a small voltage was applied at the input to obtain an oﬀset of 0V. This turns OFF any current to the load.

72 Table 6.6: Simulation vs Hardware (HCL)

HCL

Parameter Simulation Result Testing result

IQ 590 µA 590 µA

PQ 1.77 mV 1.77 mV

PP eak 97.6 mW 97.6 mW

VSSSUB -3V -3V

FOM 55.23 55.23

THD -77 dB -77.15 dB

3. The THD of the output of an ampliﬁer depends on the THD of input. The input THD of the signal from the function generator was 13m% when the expected output was 13m%. Thus to attain a lower distortion at the input, a RC low-pass network was used.

The chips were tested successfully by countering every issue that occurred. The designed ampliﬁers have a Figure of Merit higher than state-of-the-art ([1]). Future work involves

1. Design modiﬁcations to drive smaller resistive load (8-Ω) headphone speakers available in the market.

2. Improvisation of the design is required to use this class-AB ampliﬁer for other applications.

73 APPENDICES APPENDIX A HARDWARE TEST PROCEDURE Project Name: Audio Amplifier Project Author: Chaitanya Mohan Submitted: July 26, 2010 Fabrication: 0.5!m AMI double-poly n-well with 3 metal layers Apparatus: Oscilloscope, PCB board, DMM, Function Generator, DC Voltage source Description: First stage is a fully differential folded cascode amplifier with local common mode feedback and replica biasing. A NMOS differential pair and PMOS differential pair with local common mode feedback and replica biasing forms the second stage. The third stage of the design is a common source amplifier.

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Mosis Reply Id: 00363789 -001-001

Table 1:

Pin Name Type Description No: 1 vss_B protect -1.5V to power the circuit B 2 vss_B protect -1.5V to power the circuit B 3 Vout_B protect Output connect to load 4 Vout_B protect Output connect to load 5 Vout_B protect Output connect to load 6 Vdd_B protect +1.5V to power circuit B 7 Vdd_B protect +1.5V to power circuit B 8 Vdd_B protect +1.5V to power circuit B 77 9 Vdd_B protect +1.5V to power circuit B 10 Vr_B protect 0V 11 Vb2_B protect External resistor to generate bias current 12 Vbias_B protect External resistor to generate bias current 13 Vin+ B protect Connect to Ground 14 Vin- B protect Connect to external resistors 15 NC pad_vdd 1.5V to protect IC 16 NC pad_vss -3V to protect IC (Short to pin 18) 17 Stand-by_A protect 1.5V or -1.5V to turn ON/OFF circuit A 18 Vss_sub pad_bare -3V substrate biasing (short to pin 38) 19 Vss_A protect -1.5V to power the circuit A 20 Vss_A protect -1.5V to power the circuit A 21 Vss_A protect -1.5V to power the circuit A 22 Vss_A protect -1.5V to power the circuit A 23 Vout_A protect Output of circuit A 24 Vout_A protect Output of circuit A 25 Vout_A protect Output of circuit A 26 Vdd_A protect 1.5V to power the circuit A 27 Vdd_A protect 1.5V to power the circuit A 28 Vdd_A protect 1.5V to power the circuit A 29 Vdd_A protect 1.5V to power the circuit A 30 Vr_A protect 0V 31 Vb2_A protect External Resistor to generate bias current 32 Vbias_A protect External Resistor to generate bias current 33 Vin+ A protect Connect to 0V 34 Vin- A protect Connected to external resistors 35 NC protect No Connection 36 NC protect No connection 37 Stand-by_B protect -1.5V or 1.5V to turn ON/OFF circuit B 38 Vss_sub Pad_bare -3V substrate biasing (short to pin 18) 39 Vss_B protect -1.5V to power the circuit B 40 Vss_B protect -1.5V to power the circuit B

Suggested Test Procedure: (I) Connect pad_vdd (pin 15) to 1.5V, pad_vss (pin 16) and Vss_sub (pin 18, 38) to - 3V to protect the IC. The circuit should not draw any current.

(II) Electrical Testing; Circuit A

Power Supplies: Vdd_A = +1.5 V, Vss_A = -1.5 V,

78 Vr = 0V (Reference voltage) The stand-by_A (pin 17) should be connected to -1.5V and stand-by_B (pin 37) to 1.5V, such that no digital inputs are floating. To power the circuit “A” connect VDD to pins 26,27,28,29 and VSS to pins 19,20,21 and 22. Check for excess heat dissipation and smoke. If there is smoke, then the chip is fried.

Testing the Transient response

1. Put a resistor ‘RB’ between pins 31 and 32. RB " 88k# 2. Measure the voltage between pins 31 and 32 using a DMM. From the figure below and the equations determine the value of RB

a. $V = ______($V = Vb2-Vbias : from DMM)

b. Measure the current IB through the resistor RB.

IB = $V/RB = ______

c. Adjust the value of RB to attain a current IB of 8µA.

Measure RB = ______(using DMM)

Note: Internal resistance of DMM has no effect on the current as RIN || RB and

RIN >> RB

3. Attach a bias resistor RB determined above between Vb2_A (pin 31) and Vbias_A (pin 32). 79 4. Short the audio amplifier outputs Vout_A (pin 23, 24 and 25). Attach one end of the 40k# resistor (R2) to the Vout_A and other end to Vin- A (pin 34). Add a 10k# resistor (R1) to Vin- A. The other end of the 10k# resistor is connected to the function generator.

Measure R2 = ______(using DMM ; Tolerance 1%)

R1 = ______(using DMM ; Tolerance 1%)

Ratio = R2/R1 = ______(Matching 0.2%, i.e 3.992<4<4.008) 5. Connect Vr_A (pin 30) to 0V. The positive input terminal of the amplifier Vin+ A is connected to ground.

6. Attach one end of a 16-# resistor (RL) and 500pF capacitor (CL) to the output of the amplifier Vout_A. The other end of the resistor and capacitor goes to ground.

Measure RL = ______(Tolerance 0.5%)

CL = ______(Tolerance 10%) 7. Initially ground the floating end of the 10k# resistor in step 4. Measure the current (IVDD) from the positive power supply to the circuit (pin 26, 27, 28 and 29) using DMM.

IVDD = ______The quiescent power of the audio amplifier is

PQ = IVDD * 3 = ____(Total supply voltage is vdd-vss = 1.5-(-1.5)=3V) 8. Set the function generator output to 100mV amplitude square wave signal that has a frequency of 50kHz. Remove the ground and attach this signal to the floating end of 10k# resistor in 4. 9. Use a 1x probe to connect the input to channel A of the scope. Use a 10x probe to connect the output Vout_A to channel B of the scope. The output should have a frequency equal to the input signal. The amplitude of the output signal must be 40mV because of the 10x probe. Measure the output amplitude and slew-rate. Store the input and output waveforms obtained on the scope digitally to a disk. 10. Change the load capacitance value 500pF in step 4 to 1nF and observe the output on scope. The output should be similar to that in 6. Store the obtained waveforms.

80 Output waveforms:

Test for Measuring THD of the amplifier

1. Replace the 10k# resistor (R1) attached between the function generator and Vin- A (pin 34) with 40k# resistor.

Measure R1 = ______(Using DMM; Tolerance 1%)

Ratio = R2/R1 = ______(Matching 0.1%, i.e 0.999<1<1.001)

2. Switch the load capacitance CL back to the same from step 6 (Testing Transient Response) 500pF from 1nF attached between Vout_A and ground. 3. Set the function generator output to 1.25V amplitude sine wave signal that has a frequency of 1kHz. Attach this signal to the floating end of 40k# resistor in step 1. 4. Use a 10x probe to connect the output Vout_A to scope. The output should be a sine wave that has a frequency equal to the input signal. Set the scope such that it measures the output signal amplitude in rms. Determine the amplitude of the output signal

Vrms = ______

Vout =Vrms * %2 = ______Store the input and output waveforms obtained on the scope digitally on a disk. 5. Compute the peak power to the load using the following equation and enter the value in the Table 2. 2 Ppeak = Vout /RL = ______6. Follow the procedure below to set the Stanford Research System (SRS) spectrum analyzer to measure THD a. Turn ON the SRS network analyzer while holding the backspace button till it runs all the tests.

81 b. Turn ON the function generator and set the frequency and amplitude as required. Connect the function generator to channel A of the SRC network analyzer using 1x probe. c. On top right of the SRS network analyzer screen select the soft-key and set its value (12.5KHz) d. Select option under ENTRY. e. Under the Marker select . This moves the marker to max value. f. Now set and then select . Use the soft keys on the right side of the screen to set fundamental frequency and Harmonics (10 harmonics). g. Select under MENU and set the to 100 using soft-key. h. Hit under CONTROL option to compute the average. i. The THD of the signal is displayed on the left of the screen. 7. Connect the input signal from the function generator directly to the SRS network analyzer using a 1x probe to measure the THD.

THDI_IN = ______8. Connect the input signal from the function generator to the input of the amplifier using a 1x probe and connect the same to SRS network analyzer and measure the THD

THDIN = ______9. Now connect the output of the audio amplifier to the Stanford Research System using a 1x probe. Measure the THD of the output signal. Enter this value in table 2 below to compare the result with the simulated result.

THDOUT = ______10. Change the load capacitance value 500pF in 2 to 1nF and observe the output on scope. The output should be similar to that in step 4. Store the output waveform obtained on the scope digitally on a disk. Output waveforms:

82 NOTE : Now turn OFF the circuit A by switching the stand-by_A (pin 17) from - 1.5V to 1.5V and turn ON the circuit B by connecting -1.5V to stand-by_B (pin 37). Repeat the procedure for all the four designs and measure the output power as in 5, THD in 9 and quiescent power as in 7 (Testing the Transient response). Enter these values in the table below. Store the waveforms of all the designs digitally on a disk.

Table 2 : Designs and its corresponding outputs Input Bias Quiescent Design Peak power THD Current power A B C D

83 !"#$%& '(!!)*& +$,$%-./",& /,!(.2"(.!(.& !"%.'& 01/!&

!!!!! !!!!!!!!!Figure 2: Test setup of the chip APPENDIX B POLE/ZERO ANALYSIS USING MAPLE gm1$Vin Voutn Vout K Voutn gm1$Vin Voutp collect solve C = Ic1, Ic1 = ,K C C Ic2 2 R1 1 2 R1 Rc1 C s$Cc1 2$Voutpp C Ic3 C Ic4 = 0, gm2$ Voutp K Voutn C C Voutpp$s$2$ C2 = Ic4 C Ic5, R2

gm2$ Voutp K Voutn Voutnp C C Voutnp$s$C2 = Ic3 C Ic6, Ic2 = Ic5 C Ic6, Ic2 2 R2

Voutp K Vx = , Ic5 = Vx K Voutpp $s$Cc2, Ic6 = Vx K Voutnp $s$Cc2, Ic4 = Voutp Rc2 Vout K Voutpp $s$2$Cc3, Ic3 = Voutp K Voutnp $s$Cc3, gm3$Voutpp C gm3$Voutnp C Rout C Vout$s$Cout C Ic1 = 0 , Vout, Voutp, Voutn, Voutnp, Voutpp, Vx, Ic1, Ic2, Ic3, Ic4, Ic5, Ic6 ,

s = 0, Vout = gm1 R1 Rout gm3 gm2 R2 (1)

2 wp1 = (2) gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 2 4 solve wp1 = , wp1$wp2 = , gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 Coefficient of S2 wp1, wp2

2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 wp2 = (3) Cc1 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 2 solve wp1 = , wp2 gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 4 = , wp1$wp2$wp3 = , Cc1 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 Coefficient of S3 wp1, wp2, wp3

2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 wp3 = (4) R1 R2 C2 6 gm3 Rout Cc3 C 4 gm3 Rout Cc2 C 2 Cc2 C 3 Cc3

86 2 solve wp1 = , wp2 gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 = , wp3 Cc1 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 = , wp1$wp2$wp3$wp4 R1 R2 C2 6 gm3 Rout Cc3 C 4 gm3 Rout Cc2 C 2 Cc2 C 3 Cc3 4 = , wp1, wp2, wp3, wp4 Coefficient of S4

gm2 2 gm3 Rout C 1 wp4 = (5) Cout Rout gm2 C 2 C2

8 gm3 gm2 R2 solve wz1 = K , wz1 K4 gm3 Cc1 gm2 R2 R1 K 8 gm3 gm2 R2 2 C2 2 wz1 = (6) Cc1 R1 C 2 R2 C2 2 8 gm3 gm2 R2 solve wz1 = , wz1$wz2 =K , wz1, wz2 Cc1 R1 C 2 R2 C2 Coefficient of S2

1 2 wz2 = C (7) R2 C2 Cc1 R1 2 1 2 8 gm3 gm2 R2 solve wz1 = , wz2 = C , wz1$wz2$wz3 =K , Cc1 R1 C 2 R2 C2 R2 C2 Cc1 R1 Coefficient of S3 wz1, wz2, wz3

1 gm2 wz3 = K (8) 2 Cc3

87 APPENDIX C MATLAB CODE TO PLOT WAVEFORMS To plot THD of all Circuits: LIQ

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’CKT-A’); 6 plot (a1(:,1)/1000,a1(:,2),’b’); 7 axis ([0 12.5 -120 20]) 8 xlabel(’Frequency (KHz)’); 9 ylabel(’Magnitude (dBv)’); 10 grid on;

LTHD

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’CKT-B’); 6 plot (a1(:,1)/1000,a1(:,2),’k’); 7 axis ([0 12.5 -120 20]) 8 xlabel(’Frequency (KHz)’); 9 ylabel(’Magnitude (dBv)’); 10 grid on;

MIQ

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’CKT-C’); 6 plot (a1(:,1)/1000,a1(:,2),’k’); 7 axis ([0 12.5 -120 20]) 8 xlabel(’Frequency (KHz)’); 9 ylabel(’Magnitude (dBv)’); 10 grid on;

89 HCL

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’CKT-D’); 6 plot (a1(:,1)/1000,a1(:,2)-13.974,’r’); 7 axis ([0 12.5 -120 20]) 8 xlabel(’Frequency (KHz)’); 9 ylabel(’Magnitude (dBv)’); 10 grid on;

Code to plot Transient Results

1 clc; 2 clear all; 3 close all; 4 5 6 q = 25; 7 H = 0:q/999:q; 8 H1 = transpose(H); 9 10 a1=csvread(’84046/CKT_D/input/input1.csv’); 11 a2=csvread(’84046/CKT_D/input/input2.csv’); 12 a3=csvread(’84046/CKT_D/input/input3.csv’); 13 a4=csvread(’84046/CKT_D/input/input4.csv’); 14 a5=csvread(’84046/CKT_D/input/input5.csv’); 15 a6=csvread(’84046/CKT_D/input/input6.csv’); 16 a7=csvread(’84046/CKT_D/input/input7.csv’); 17 a8=csvread(’84046/CKT_D/input/input8.csv’); 18 a9=csvread(’84046/CKT_D/input/input9.csv’); 19 a10=csvread(’84046/CKT_D/input/input10.csv’); 20 a11=csvread(’84046/CKT_D/input/input11.csv’); 21 a12=csvread(’84046/CKT_D/input/input12.csv’); 22 a13=csvread(’84046/CKT_D/input/input13.csv’); 23 a14=csvread(’84046/CKT_D/input/input14.csv’); 24 a15=csvread(’84046/CKT_D/input/input15.csv’); 25 a16=csvread(’84046/CKT_D/input/input16.csv’); 26 27 28 a(:,1)=(a1(:,1)+a2(:,1)+a3(:,1)+a4(:,1)+a5(:,1)+a6(:,1)+a7(:,1)+a8(:,1) 29 +a9(:,1)+a10(:,1)+a11(:,1)+a12(:,1)+a13(:,1)+a14(:,1)+a15(:,1) 30 +a16(:,1))/(16); 31 a(:,1)=(a(:,1)*0.8)*1000; 32 33 34 b1=csvread(’84045/CKT_A/single_pulse_10pF/output1.csv’); 90 35 b2=csvread(’84045/CKT_A/single_pulse_10pF/output2.csv’); 36 b3=csvread(’84045/CKT_A/single_pulse_10pF/output3.csv’); 37 b4=csvread(’84045/CKT_A/single_pulse_10pF/output4.csv’); 38 b5=csvread(’84045/CKT_A/single_pulse_10pF/output5.csv’); 39 b6=csvread(’84045/CKT_A/single_pulse_10pF/output6.csv’); 40 b7=csvread(’84045/CKT_A/single_pulse_10pF/output7.csv’); 41 b8=csvread(’84045/CKT_A/single_pulse_10pF/output8.csv’); 42 b9=csvread(’84045/CKT_A/single_pulse_10pF/output9.csv’); 43 b10=csvread(’84045/CKT_A/single_pulse_10pF/output10.csv’); 44 b11=csvread(’84045/CKT_A/single_pulse_10pF/output11.csv’); 45 b12=csvread(’84045/CKT_A/single_pulse_10pF/output12.csv’); 46 b13=csvread(’84045/CKT_A/single_pulse_10pF/output13.csv’); 47 b14=csvread(’84045/CKT_A/single_pulse_10pF/output14.csv’); 48 b15=csvread(’84045/CKT_A/single_pulse_10pF/output15.csv’); 49 b16=csvread(’84045/CKT_A/single_pulse_10pF/output16.csv’); 50 51 52 53 b(:,1)=(b1(:,1)+b2(:,1)+b3(:,1)+b4(:,1)+b5(:,1)+b6(:,1)+b7(:,1) 54 +b8(:,1)+b9(:,1)+b10(:,1)+b11(:,1)+b12(:,1)+b13(:,1)+b14(:,1) 55 +b15(:,1)+b16(:,1))/(16); 56 b(:,1)=(b(:,1)*0.8)*1000; 57 58 59 c1=csvread(’84045/CKT_A/single_pulse_500pF/output1.csv’); 60 c2=csvread(’84045/CKT_A/single_pulse_500pF/output2.csv’); 61 c3=csvread(’84045/CKT_A/single_pulse_500pF/output3.csv’); 62 c4=csvread(’84045/CKT_A/single_pulse_500pF/output4.csv’); 63 c5=csvread(’84045/CKT_A/single_pulse_500pF/output5.csv’); 64 c6=csvread(’84045/CKT_A/single_pulse_500pF/output6.csv’); 65 c7=csvread(’84045/CKT_A/single_pulse_500pF/output7.csv’); 66 c8=csvread(’84045/CKT_A/single_pulse_500pF/output8.csv’); 67 c9=csvread(’84045/CKT_A/single_pulse_500pF/output9.csv’); 68 c10=csvread(’84045/CKT_A/single_pulse_500pF/output10.csv’); 69 c11=csvread(’84045/CKT_A/single_pulse_500pF/output11.csv’); 70 c12=csvread(’84045/CKT_A/single_pulse_500pF/output12.csv’); 71 c13=csvread(’84045/CKT_A/single_pulse_500pF/output13.csv’); 72 c14=csvread(’84045/CKT_A/single_pulse_500pF/output14.csv’); 73 c15=csvread(’84045/CKT_A/single_pulse_500pF/output15.csv’); 74 c16=csvread(’84045/CKT_A/single_pulse_500pF/output16.csv’); 75 76 77 78 c(:,1)=(c1(:,1)+c2(:,1)+c3(:,1)+c4(:,1)+c5(:,1)+c6(:,1)+c7(:,1)+c8(:,1) 79 +c9(:,1)+c10(:,1)+c11(:,1)+c12(:,1)+c13(:,1)+c14(:,1)+c15(:,1) 80 +c16(:,1))/(16); 81 c(:,1)=(c(:,1)*0.8)*1000; 82 83 84 e1=csvread(’84045/CKT_A/single_pulse_2nF/output1.csv’); 85 e2=csvread(’84045/CKT_A/single_pulse_2nF/output2.csv’);

91 86 e3=csvread(’84045/CKT_A/single_pulse_2nF/output3.csv’); 87 e4=csvread(’84045/CKT_A/single_pulse_2nF/output4.csv’); 88 e5=csvread(’84045/CKT_A/single_pulse_2nF/output5.csv’); 89 e6=csvread(’84045/CKT_A/single_pulse_2nF/output6.csv’); 90 e7=csvread(’84045/CKT_A/single_pulse_2nF/output7.csv’); 91 e8=csvread(’84045/CKT_A/single_pulse_2nF/output8.csv’); 92 e9=csvread(’84045/CKT_A/single_pulse_2nF/output9.csv’); 93 e10=csvread(’84045/CKT_A/single_pulse_2nF/output10.csv’); 94 e11=csvread(’84045/CKT_A/single_pulse_2nF/output11.csv’); 95 e12=csvread(’84045/CKT_A/single_pulse_2nF/output12.csv’); 96 e13=csvread(’84045/CKT_A/single_pulse_2nF/output13.csv’); 97 e14=csvread(’84045/CKT_A/single_pulse_2nF/output14.csv’); 98 e15=csvread(’84045/CKT_A/single_pulse_2nF/output15.csv’); 99 e16=csvread(’84045/CKT_A/single_pulse_2nF/output16.csv’); 100 101 102 e(:,1)=(e1(:,1)+e2(:,1)+e3(:,1)+e4(:,1)+e5(:,1)+e6(:,1)+e7(:,1) 103 +e8(:,1)+e9(:,1)+e10(:,1)+e11(:,1)+e12(:,1)+e13(:,1)+e14(:,1) 104 +e15(:,1)+e16(:,1))/(16); 105 e(:,1)=(e(:,1)*0.8)*1000; 106 107 108 109 subplot(2,1,1); 110 plot(H1(:,1),a(:,1),’k’); 111 axis([0 25 -125 125]); 112 ylabel(’Input (mV)’); 113 grid on; 114 subplot(2,1,2); 115 plot(H1(:,1),b(:,1),’b’,H1(:,1),c(:,1)+900,’g’,H1(:,1),e(:,1)+1800,’r’); 116 axis([0 25 -500 2300]); 117 xlabel(’Time (\muS)’); 118 ylabel(’Output (mV)’); 119 grid on;

92 Code to Simulation Results: DC Plots

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’DC_A.csv’); 6 subplot (2,1,1); 7 hold on; 8 plot (a1(:,1)*1000,a1(:,4),’k’); 9 ylabel (’Output Voltage (V)’); 10 grid on; 11 12 subplot (2,1,2); 13 plot (a1(:,1)*1000,a1(:,2)*1000,’r’); 14 axis([-2 2 -10 100]); 15 hold on 16 plot (a1(:,1)*1000,a1(:,3)*1000,’b’); 17 18 axis([-2 2 -10 100]); 19 xlabel(’DC Input (mV)’); 20 ylabel(’Output-Stage Current (mA)’); 21 grid on;

AC Plots

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’AC_A.csv’); 6 subplot (2,1,1); 7 semilogx (a1(:,1),a1(:,2),’k’); 8 axis([1 10^8 -100 60]); 9 grid on; 10 ylabel(’Gain (dB)’); 11 subplot (2,1,2); 12 semilogx (a1(:,1),a1(:,3),’k’); 13 axis([1 10^8 -400 100]); 14 xlabel(’Frequency (Hz)’); 15 ylabel(’Phase (deg)’); 16 grid on;

93 THD Plots

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’THD.csv’); 6 subplot (2,1,1); 7 plot (a1(:,1),a1(:,2),’k’); 8 %axis([1 10^8 -100 60]); 9 grid on; 10 ylabel(’Input’); 11 subplot (2,1,2); 12 plot (a1(:,1),a1(:,3),’k’); 13 %axis([1 10^8 -400 100]); 14 xlabel(’Time’); 15 ylabel(’Output’); 16 grid on;

Transient Plots

1 clc; 2 clear all; 3 close all; 4 5 a1 = csvread(’TR_A_10pf.csv’); 6 a1(:,1)=(a1(:,1)*1000000); 7 a2 = csvread(’TR_A_500pf.csv’); 8 a2(:,1)=(a2(:,1)*1000000); 9 a3 = csvread(’TR_A_1_5nf.csv’); 10 a3(:,1)=(a3(:,1)*1000000); 11 12 subplot (2,1,1); 13 plot (a1(:,1),a1(:,3),’k’); 14 axis([5 25 -0.15 0.15]); 15 grid on; 16 ylabel(’Input (V)’); 17 subplot (2,1,2); 18 plot(a1(:,1),a1(:,2),’b’,a2(:,1),a2(:,2)+0.9,’g’,a3(:,1),a3(:,2)+1.8,’r’); 19 axis([5 25 -0.45 2.5]); 20 xlabel(’Time (\muS)’); 21 ylabel(’Output (V)’); 22 grid on;

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