DMA (Direct Memory Access) CONTROLLER Basics & Features Of DMA

>> The activity involved in transferring a byte or word over the system bus is called a bus cycle. >> During bus cycle one component must be the master – which will have complete control over the bus. Taking control of the bus for a bus cycle is called cycle stealing. >> DMA is a data transfer technique between Main Memory and External device. It can be used to memory to memory transfers also. >> There is no involvement of Microprocessor. >> DMA controller controls the Main Memory in the same way the Microprocessor do. >> Ensures very high data transfer rate. Because the data transfer is handled totally in hardware. >> Microprocessor and DMA controller gets control of data, address and control bus by time sharing. Steps to Perform DMA

1) Interface of the external Device (DMA requesting I/O device) activates the DREQ line high to send a request for DMA service to the controller. 2) If the input of the DMA controller is unmasked, the DMA controller sends a bus request to the microprocessor through its HOLD pin. 3) After the current bus cycle is complete the microprocessor will respond by putting a 1 on the HLDA pin to DMA controller. When the requesting device receives this grant signal it becomes the master. It will remain master until it drops signal to the HOLD pin, at which time 8086 will drop the grant on the HLDA pin. 4) After receiving HLDA, DMA controller sends out a signal and takes the full control of Data, Address and Control buses. 5) DMA controller puts the content of the address register on the address bus.. 6) DMA controller sends a DACK signal to the interface to tell it to put data on data bus. 7) At the same time DMA controller asserts appropriate signals to IOR/IOW and MEMW/MEMR pins. 8) Bytes of data are transferred to the memory location indicated by the address bus . 9) After completion of DMA, DMA controller releases a) its hold request HOLD to the processor. b) control of buses. 10) The address register is incremented by 1. 11) The byte count register is decremented by 1. 12) If the byte count register is non-zero, return to step 1;otherwise stop. Overview of a standard DMA controller Block Diagram of DMA controller (Ref. D.V. Hall) DMA controller • A DMA controller is capable of becoming the bus master and supervising a transfer between an I/O interface and memory. • A DMA controller is designed to service one or more I/O interfaces and each interface is connected to the controller by a set of conductors. • A portion of a DMA controller for servicing a single interface is called a channel. • It has n channels for n different I/O devices. 8237 has 4 channels. A DMA controller has control and status register.There is also a temporary register. And Each channel contains >>Address Registers (base and current) >>Byte count register(base and count) >> Mode register >>Request flag and Mask flag One Channel DMA controller 8086 System with 8237 DMA controller Description of the parts of 8237

Mode Register: >>Bit 5: indicates whether the content of address register are to be incremented (0) or decremented (1) after each transfer .Thus it determines the order in which data are stored in memory. >> Bit 4: If 1 auto-initialization is enabled. (When the controller is initialized, the address register is filled with the beginning or ending address of the memory array and Byte count register is filled with the number if bytes to be transferred. These contents of current address and current byte registers are also put in base address and base byte count registers. If Auto-initialization is enabled , then current registers are automatically reloaded from the base registers whenever the count goes to 0.) >> Bit 2 & 3: Indicates the type of transfer to be made. The three types are: verify (00),write (01) and read (10). Description of the parts of 8237

Control Register: >>Bit 0: Set to 1 to enable memory to memory transfer. In this case if Bit 1=1 , the source address is held constant. >> Bit 2: It is used for enabling (0) and disabling (1) controllers to accept DMA request. >> Bit 4: Determine whether the priority is fixed or rotating.(If Bit 4 is 1 and before transfer the priority is 2-3-0-1 ,then after transfer the priority is 3-0- 1-2). By rotating the priority the controller can prevent one channel from dominating the bus. >> Bit 6: If 1 , then indicates that DREQ is active Low. >> Bit 7: If 1 , then indicates that DACK is active High. Description of the parts of 8237

Status Register: Lower 4 bits indicates the states of the terminal count of the four channels and upper 4 bits indicates the current presence or absence of DMA request. For the lower 4 bits, a 1 in bit n indicates that channel n is active. For the upper 4 bits, a 1 in bit n+4 indicates the presence of request on channel n. Description of the parts of 8237

Request Flag & Mask Flag: Setting the Request flag for a channel has the same effect as the DREQ pin becoming active and it is cleared when EOP goes active.

If the mask flag is set, it disables the channel so that DMA requests are not recognized. If a channel is not programmed for auto-initialization, then this flag is automatically set when EOP goes active. Memory to memory transfers Temporary Register: • Channel 0 ‘s current address and count registers are used as source addressing and counting • Channel 1’s current address and count registers are used for destination address and counting • Bytes are brought in from the source memory area into the temporary register in 8237 and then outputting it to destination memory area. • If destination address is incremented or decremented as usual by setting appropriate bits of the control register and source address is kept constant, same data byte is transferred into the entire destination array. Description of the parts of 8237

The addressing of these various registers is done via CS, IOR,IOW and A3-A0 lines. ¾ CS=0 indicates that the controller is being accessed. ¾ A3=0 when address or count register is addressed. ¾ A3=1 when control or status is being accessed. ¾ when A3=0 (addressing address or count register) A2-A1 gives the channel number and A0=0 means current address register, A0=1 means current count register. ¾ For a read IOR is Low and IOW is high. ¾ For a write IOR is High and IOW is low. ¾ A write to either current address or current count register also writes to base address or base count register. 8237-What’s going on.. • When the controller is master it must supply the address. >>It puts lower order address byte on A7-A0 >> the higher address byte on DB7-DB0 >> and sets AEN to high • Shortly after AEN is 1 (when active) a pulse is sent out over ADSTB pin.This pulse is used to strobe the upper byte of the address into the 8282 address latch connected to A15-A8 lines. • It also disables the latches connected to CPU’s A19-A8 and AD7- AD0 pins. • The upper 4 bits of address A19-A16 cannot be obtained from 8237 and so they must be hardwired or connected to the output of a 4-bit I/O port (like any other I/O port to hold the high order 4 bits of the address) that is initialized before each transfer. • While it is master the controller must also output the necessary read/write commands.These commands are IOR, MEMR,IOW, MEMW.But these signals do not match the RD,WR and IO/M signals output by a 8088. During DMA transfer, the controller disables the output of the read/write encoder for the command lines by activating the AEN lines. Other features…

• EOP: is bidirectional. >>The count going zero causes a negative pulse on EOP which can be used either as an interrupt request or by the device interface. >>Again the interface can send a low on this pin to 8237 to suspend the block transfer. >> In either case, a Low on the EOP will result in the block transfer being suspended.After the suspension the block transfer may resume according to the mode of 8237. • Ready signal is used to extend the bus cycles by inserting wait states when servicing the slow devices. • Reset signal clears the control,status and temporary registers and the request flags and sets the mask flags. 8086 System with 8237 DMA controller 8086 System with 8237 DMA controller 8086 System with 8237 DMA controller Modes (determined by mode register of each channel)

• Single : After each transfer controller releases bus to CPU for at least one bus cycle. Then tests DREQ and as soon as DREQ active steals another bus cycle. • Block :The bus is released only after entire block transfer. • Demand : DREQ is checked after each transfer. If inactive waits until it becomes active and resumes the transfer.It allows interface to stop transfer in the event that its device cannot keep up. • Cascade : This is not a transfer mode – in this mode more than 4 channels can be included by having a slave controller connected to the master Flowchart of 8237 DMA controller activity by states The 8237 timing can be divided into SI,S0,S1,S2,S3,S4 and SW states. >> Between transfers the controller is in idle SI states. >> during each SI state the DREQ lines are tested to determine if a channel is requesting DMA transfer. >> If there is an active DREQ input, HRQ is activated and S0 state is entered. >> S0 states are repeated until a HLDA signal is returned and then a sequence of S1 through S4 occurs. >> S1 may be skipped if high order byte of the transfer address does not need to be changed. >> If the device is slow, wait SW states are inserted. >> If normal timing is used, S3 states are needed. But if compressed timing is used S3 state is deleted. >> during S4 the transfer mode is tested. Except for incomplete block transfers in block and demand modes, a return is made to SI. Timing Diagram for 8237 DMA controller