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A Taxonomy of Accelerator Architectures and Their
A taxonomy of accelerator C. Cas$caval S. Chatterjee architectures and their H. Franke K. J. Gildea programming models P. Pattnaik As the clock frequency of silicon chips is leveling off, the computer architecture community is looking for different solutions to continue application performance scaling. One such solution is the multicore approach, i.e., using multiple simple cores that enable higher performance than wide superscalar processors, provided that the workload can exploit the parallelism. Another emerging alternative is the use of customized designs (accelerators) at different levels within the system. These are specialized functional units integrated with the core, specialized cores, attached processors, or attached appliances. The design tradeoff is quite compelling because current processor chips have billions of transistors, but they cannot all be activated or switched at the same time at high frequencies. Specialized designs provide increased power efficiency but cannot be used as general-purpose compute engines. Therefore, architects trade area for power efficiency by placing in the design additional units that are known to be active at different times. The resulting system is a heterogeneous architecture, with the potential of specialized execution that accelerates different workloads. While designing and building such hardware systems is attractive, writing and porting software to a heterogeneous platform is even more challenging than parallelism for homogeneous multicore systems. In this paper, we propose a taxonomy that allows us to define classes of accelerators, with the goal of focusing on a small set of programming models for accelerators. We discuss several types of currently popular accelerators and identify challenges to exploiting such accelerators in current software stacks. -
SOL: Effortless Device Support for AI Frameworks Without Source Code Changes
SOL: Effortless Device Support for AI Frameworks without Source Code Changes Nicolas Weber and Felipe Huici NEC Laboratories Europe Abstract—Modern high performance computing clusters heav- State of the Art Proposed with SOL ily rely on accelerators to overcome the limited compute power API (Python, C/C++, …) API (Python, C/C++, …) of CPUs. These supercomputers run various applications from different domains such as simulations, numerical applications or Framework Core Framework Core artificial intelligence (AI). As a result, vendors need to be able to Device Backends SOL efficiently run a wide variety of workloads on their hardware. In the AI domain this is in particular exacerbated by the Fig. 1: Abstraction layers within AI frameworks. existance of a number of popular frameworks (e.g, PyTorch, TensorFlow, etc.) that have no common code base, and can vary lines of code to their scripts in order to enable SOL and its in functionality. The code of these frameworks evolves quickly, hardware support. making it expensive to keep up with all changes and potentially We explore two strategies to integrate new devices into AI forcing developers to go through constant rounds of upstreaming. frameworks using SOL as a middleware, to keep the original In this paper we explore how to provide hardware support in AI frameworks without changing the framework’s source code in AI framework unchanged and still add support to new device order to minimize maintenance overhead. We introduce SOL, an types. The first strategy hides the entire offloading procedure AI acceleration middleware that provides a hardware abstraction from the framework, and the second only injects the necessary layer that allows us to transparently support heterogenous hard- functionality into the framework to enable the execution, but ware. -
Deep Learning Frameworks | NVIDIA Developer
4/10/2017 Deep Learning Frameworks | NVIDIA Developer Deep Learning Frameworks The NVIDIA Deep Learning SDK accelerates widelyused deep learning frameworks such as Caffe, CNTK, TensorFlow, Theano and Torch as well as many other deep learning applications. Choose a deep learning framework from the list below, download the supported version of cuDNN and follow the instructions on the framework page to get started. Caffe is a deep learning framework made with expression, speed, and modularity in mind. Caffe is developed by the Berkeley Vision and Learning Center (BVLC), as well as community contributors and is popular for computer vision. Caffe supports cuDNN v5 for GPU acceleration. Supported interfaces: C, C++, Python, MATLAB, Command line interface Learning Resources Deep learning course: Getting Started with the Caffe Framework Blog: Deep Learning for Computer Vision with Caffe and cuDNN Download Caffe Download cuDNN The Microsoft Cognitive Toolkit —previously known as CNTK— is a unified deeplearning toolkit from Microsoft Research that makes it easy to train and combine popular model types across multiple GPUs and servers. Microsoft Cognitive Toolkit implements highly efficient CNN and RNN training for speech, image and text data. Microsoft Cognitive Toolkit supports cuDNN v5.1 for GPU acceleration. Supported interfaces: Python, C++, C# and Command line interface Download CNTK Download cuDNN TensorFlow is a software library for numerical computation using data flow graphs, developed by Google’s Machine Intelligence research organization. TensorFlow supports cuDNN v5.1 for GPU acceleration. Supported interfaces: C++, Python Download TensorFlow Download cuDNN https://developer.nvidia.com/deeplearningframeworks 1/3 4/10/2017 Deep Learning Frameworks | NVIDIA Developer Theano is a math expression compiler that efficiently defines, optimizes, and evaluates mathematical expressions involving multidimensional arrays. -
1 Amazon Sagemaker
1 Amazon SageMaker 13:45~14:30 Amazon SageMaker 14:30~15:15 Amazon SageMaker re:Invent 15:15~15:45 Q&A | 15:45~17:00 Amazon SageMaker 20 SmartNews Data Scientist, Meng Lee Sagemaker SageMaker - FiNC FiNC Technologies SIGNATE Amazon SageMaker SIGNATE CTO 17:00~17:15© 2018, Amazon Web Services, Inc. or itsQ&A Affiliates. All rights reserved. Amazon Confidential and Trademark Amazon SageMaker Makoto Shimura, Solutions Architect 2019/01/15 © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark • • • • ⎼ Amazon Athena ⎼ AWS Glue ⎼ Amazon SageMaker © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark • • Amazon SageMaker • Amazon SageMasker • SageMaker SDK • [ | | ] • Amazon SageMaker • © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark 開発 学習 推論推論 学習に使うコードを記述 大量の GPU 大量のCPU や GPU 小規模データで動作確認 大規模データの処理 継続的なデプロイ 試行錯誤の繰り返し 様々なデバイスで動作 © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark 開発 学習 推論推論 エンジニアがプロダク データサイエンティストが開発環境で作業 ション環境に構築 開発と学習を同じ 1 台のインスタンスで実施 API サーバにデプロイ Deep Learning であれば GPU インスタンスを使用 エッジデバイスで動作 © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark & • 開発 学習 推論推論 • エンジニアがプロダク データサイエンティストが開発環境で作業 • ション環境に構築 開発と学習を同じ 1 台のインスタンスで実施 API サーバにデプロイ • Deep Learning であれば GPU インスタンスを使用 エッジデバイスで動作 • API • • © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark © 2018, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Amazon Confidential and Trademark Amazon SageMaker © 2018, Amazon Web Services, Inc. -
Intel® Optimized AI Frameworks
Intel® optimized AI frameworks Dr. Fabio Baruffa & Shailen Sobhee Technical Consulting Engineers, Intel IAGS Visit: www.intel.ai/technology Speed up development using open AI software Machine learning Deep learning TOOLKITS App Open source platform for building E2E Analytics & Deep learning inference deployment Open source, scalable, and developers AI applications on Apache Spark* with distributed on CPU/GPU/FPGA/VPU for Caffe*, extensible distributed deep learning TensorFlow*, Keras*, BigDL TensorFlow*, MXNet*, ONNX*, Kaldi* platform built on Kubernetes (BETA) Python R Distributed Intel-optimized Frameworks libraries * • Scikit- • Cart • MlLib (on Spark) * * And more framework Data learn • Random • Mahout optimizations underway • Pandas Forest including PaddlePaddle*, scientists * * • NumPy • e1071 Chainer*, CNTK* & others Intel® Intel® Data Analytics Intel® Math Kernel Library Kernels Distribution Acceleration Library Library for Deep Neural Networks for Python* (Intel® DAAL) (Intel® MKL-DNN) developers Intel distribution High performance machine Open source compiler for deep learning optimized for learning & data analytics Open source DNN functions for model computations optimized for multiple machine learning library CPU / integrated graphics devices (CPU, GPU, NNP) from multiple frameworks (TF, MXNet, ONNX) 2 Visit: www.intel.ai/technology Speed up development using open AI software Machine learning Deep learning TOOLKITS App Open source platform for building E2E Analytics & Deep learning inference deployment Open source, scalable, -
Getting Started with Machine Learning
Getting Started with Machine Learning CSC131 The Beauty & Joy of Computing Cornell College 600 First Street SW Mount Vernon, Iowa 52314 September 2018 ii Contents 1 Applications: where machine learning is helping1 1.1 Sheldon Branch............................1 1.2 Bram Dedrick.............................4 1.3 Tony Ferenzi.............................5 1.3.1 Benefits of Machine Learning................5 1.4 William Golden............................7 1.4.1 Humans: The Teachers of Technology...........7 1.5 Yuan Hong..............................9 1.6 Easton Jensen............................. 11 1.7 Rodrigo Martinez........................... 13 1.7.1 Machine Learning in Medicine............... 13 1.8 Matt Morrical............................. 15 1.9 Ella Nelson.............................. 16 1.10 Koichi Okazaki............................ 17 1.11 Jakob Orel.............................. 19 1.12 Marcellus Parks............................ 20 1.13 Lydia Sanchez............................. 22 1.14 Tiff Serra-Pichardo.......................... 24 1.15 Austin Stala.............................. 25 1.16 Nicole Trenholm........................... 26 1.17 Maddy Weaver............................ 28 1.18 Peter Weber.............................. 29 iii iv CONTENTS 2 Recommendations: How to learn more about machine learning 31 2.1 Sheldon Branch............................ 31 2.1.1 Course 1: Machine Learning................. 31 2.1.2 Course 2: Robotics: Vision Intelligence and Machine Learn- ing............................... 33 2.1.3 Course -
Fault Tolerance and Re-Training Analysis on Neural Networks
FAULT TOLERANCE AND RE-TRAINING ANALYSIS ON NEURAL NETWORKS by ABHINAV KURIAN GEORGE B.Tech Electronics and Communication Engineering Amrita Vishwa Vidhyapeetham, Kerala, 2012 A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science, Computer Engineering, College of Engineering and Applied Science, University of Cincinnati, Ohio 2019 Thesis Committee: Chair: Wen-Ben Jone, Ph.D. Member: Carla Purdy, Ph.D. Member: Ranganadha Vemuri, Ph.D. ABSTRACT In the current age of big data, artificial intelligence and machine learning technologies have gained much popularity. Due to the increasing demand for such applications, neural networks are being targeted toward hardware solutions. Owing to the shrinking feature size, number of physical defects are on the rise. These growing number of defects are preventing designers from realizing the full potential of the on-chip design. The challenge now is not only to find solutions that balance high-performance and energy-efficiency but also, to achieve fault-tolerance of a computational model. Neural computing, due to its inherent fault tolerant capabilities, can provide promising solutions to this issue. The primary focus of this thesis is to gain deeper understanding of fault tolerance in neural network hardware. As a part of this work, we present a comprehensive analysis of fault tolerance by exploring effects of faults on popular neural models: multi-layer perceptron model and convolution neural network. We built the models based on conventional 64-bit floating point representation. In addition to this, we also explore the recent 8-bit integer quantized representation. A fault injector model is designed to inject stuck-at faults at random locations in the network. -
WWW 2013 22Nd International World Wide Web Conference
WWW 2013 22nd International World Wide Web Conference General Chairs: Daniel Schwabe (PUC-Rio – Brazil) Virgílio Almeida (UFMG – Brazil) Hartmut Glaser (CGI.br – Brazil) Research Track: Ricardo Baeza-Yates (Yahoo! Labs – Spain & Chile) Sue Moon (KAIST – South Korea) Practice and Experience Track: Alejandro Jaimes (Yahoo! Labs – Spain) Haixun Wang (MSR – China) Developers Track: Denny Vrandečić (Wikimedia – Germany) Marcus Fontoura (Google – USA) Demos Track: Bernadette F. Lóscio (UFPE – Brazil) Irwin King (CUHK – Hong Kong) W3C Track: Marie-Claire Forgue (W3C Training, USA) Workshops Track: Alberto Laender (UFMG – Brazil) Les Carr (U. of Southampton – UK) Posters Track: Erik Wilde (EMC – USA) Fernanda Lima (UNB – Brazil) Tutorials Track: Bebo White (SLAC – USA) Maria Luiza M. Campos (UFRJ – Brazil) Industry Track: Marden S. Neubert (UOL – Brazil) Proceedings and Metadata Chair: Altigran Soares da Silva (UFAM - Brazil) Local Arrangements Committee: Chair – Hartmut Glaser Executive Secretary – Vagner Diniz PCO Liaison – Adriana Góes, Caroline D’Avo, and Renato Costa Conference Organization Assistant – Selma Morais International Relations – Caroline Burle Technology Liaison – Reinaldo Ferraz UX Designer / Web Developer – Yasodara Córdova, Ariadne Mello Internet infrastructure - Marcelo Gardini, Felipe Agnelli Barbosa Administration– Ana Paula Conte, Maria de Lourdes Carvalho, Beatriz Iossi, Carla Christiny de Mello Legal Issues – Kelli Angelini Press Relations and Social Network – Everton T. Rodrigues, S2Publicom and EntreNós PCO – SKL Eventos -
EECS 498/598: Brain-Inspired Computing: Models, Architectures, and Programming
NEW COURSE ANNOUNCEMENT FOR FALL 2019 EECS 498/598: Brain-Inspired Computing: Models, Architectures, and Programming Time: Tuesday and Thursday 1:30 to 3:00 pm Instructor: Prof. Pinaki Mazumder Phone: 734-763-2107; e-mail: [email protected] Brain-inspired computing is a subset of AI-based machine learning and is generally referred to both deep and shallow artificial neural networks (ANN) and spiking neural networks (SNN). Deep convolutional neural networks (CNN) have made pervasive market inroads in numerous commercial applications and their software implementations are widely studied in computer vision, speech processing and other courses. The purpose of this course will be to study the wide gamut of shallow and deep neural network models, the methodologies for specialized hardware design of popular learning algorithms, as well as adapting hardware architectures on crossbar fabrics of emerging technologies such as memristors and spin torque nanomagnetic devices. Existing software development tools such as TensorFlow, Caffe, and PyTorch will be leveraged to teach various aspects of neuromorphic designs. Prerequisites: Senior undergrad and grad student standing in Electrical Engineering, Computer Engineering, Computer Science or Applied Physics program. Outline: i) Fundamentals of brain-inspired computing and history of neural computing, ii) Basics of linear algebra and probability theory needed for modeling of neural networks, iii) Deep learning by convolutional neural networks such as AlexNet, VGG, GoogLeNet, and ResNet, iv) Deep Neural -
In-Datacenter Performance Analysis of a Tensor Processing Unit
In-Datacenter Performance Analysis of a Tensor Processing Unit Presented by Josh Fried Background: Machine Learning Neural Networks: ● Multi Layer Perceptrons ● Recurrent Neural Networks (mostly LSTMs) ● Convolutional Neural Networks Synapse - each edge, has a weight Neuron - each node, sums weights and uses non-linear activation function over sum Propagating inputs through a layer of the NN is a matrix multiplication followed by an activation Background: Machine Learning Two phases: ● Training (offline) ○ relaxed deadlines ○ large batches to amortize costs of loading weights from DRAM ○ well suited to GPUs ○ Usually uses floating points ● Inference (online) ○ strict deadlines: 7-10ms at Google for some workloads ■ limited possibility for batching because of deadlines ○ Facebook uses CPUs for inference (last class) ○ Can use lower precision integers (faster/smaller/more efficient) ML Workloads @ Google 90% of ML workload time at Google spent on MLPs and LSTMs, despite broader focus on CNNs RankBrain (search) Inception (image classification), Google Translate AlphaGo (and others) Background: Hardware Trends End of Moore’s Law & Dennard Scaling ● Moore - transistor density is doubling every two years ● Dennard - power stays proportional to chip area as transistors shrink Machine Learning causing a huge growth in demand for compute ● 2006: Excess CPU capacity in datacenters is enough ● 2013: Projected 3 minutes per-day per-user of speech recognition ○ will require doubling datacenter compute capacity! Google’s Answer: Custom ASIC Goal: Build a chip that improves cost-performance for NN inference What are the main costs? Capital Costs Operational Costs (power bill!) TPU (V1) Design Goals Short design-deployment cycle: ~15 months! Plugs in to PCIe slot on existing servers Accelerates matrix multiplication operations Uses 8-bit integer operations instead of floating point How does the TPU work? CISC instructions, issued by host. -
Abstractions for Programming Graphics Processors in High-Level Programming Languages
Abstracties voor het programmeren van grafische processoren in hoogniveau-programmeertalen Abstractions for Programming Graphics Processors in High-Level Programming Languages Tim Besard Promotor: prof. dr. ir. B. De Sutter Proefschrift ingediend tot het behalen van de graad van Doctor in de ingenieurswetenschappen: computerwetenschappen Vakgroep Elektronica en Informatiesystemen Voorzitter: prof. dr. ir. K. De Bosschere Faculteit Ingenieurswetenschappen en Architectuur Academiejaar 2018 - 2019 ISBN 978-94-6355-244-8 NUR 980 Wettelijk depot: D/2019/10.500/52 Examination Committee Prof. Filip De Turck, chair Department of Information Technology Faculty of Engineering and Architecture Ghent University Prof. Koen De Bosschere, secretary Department of Electronics and Information Systems Faculty of Engineering and Architecture Ghent University Prof. Bjorn De Sutter, supervisor Department of Electronics and Information Systems Faculty of Engineering and Architecture Ghent University Prof. Jutho Haegeman Department of Physics and Astronomy Faculty of Sciences Ghent University Prof. Jan Lemeire Department of Electronics and Informatics Faculty of Engineering Vrije Universiteit Brussel Prof. Christophe Dubach School of Informatics College of Science & Engineering The University of Edinburgh Prof. Alan Edelman Computer Science & Artificial Intelligence Laboratory Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology ii Dankwoord Ik wist eigenlijk niet waar ik aan begon, toen ik in 2012 in de cata- comben van het Technicum op gesprek ging over een doctoraat. Of ik al eens met LLVM gewerkt had. Ondertussen zijn we vele jaren verder, werk ik op een bureau waar er wel daglicht is, en is het eindpunt van deze studie zowaar in zicht. Dat mag natuurlijk wel, zo vertelt men mij, na 7 jaar. -
CV, Dlib, Flask, Opencl, CUDA, Matlab/Octave, Assembly/Intrinsics, Cmake, Make, Git, Linux CLI
Arun Arun Ponnusamy Visakhapatnam, India. Ponnusamy Computer Vision [email protected] Research Engineer www.arunponnusamy.com github.com/arunponnusamy ㅡ Skills Passionate about Image Processing, Computer Vision and Machine Learning. Key skills - C/C++, Python, Keras,TensorFlow, PyTorch, OpenCV, dlib, Flask, OpenCL, CUDA, Matlab/Octave, Assembly/Intrinsics, CMake, Make, Git, Linux CLI. ㅡ Experience care.ai (5 years) Computer Vision Research Engineer JAN 2019 - PRESENT, VISAKHAPATNAM Key areas worked on - image classification, object detection, action recognition, face detection and face recognition for edge devices. Tools and technologies - TensorFlow/Keras, TensorFlow Lite, TensorRT, OpenCV, dlib, Python, Google Cloud. Devices - Nvidia Jetson Nano / TX2, Google Coral Edge TPU. 1000Lookz Senior Computer Vision Engineer JAN 2018 - JAN 2019, CHENNAI Key areas worked on - head pose estimation, face analysis, image classification and object detection. Tools and technologies - TensorFlow/Keras, OpenCV, dlib, Flask, Python, AWS, Google Cloud. MulticoreWare Inc. Software Engineer JULY 2014 - DEC 2017, CHENNAI Key areas worked on - image processing, computer vision, parallel processing, software optimization and porting. Tools and technologies - OpenCV, dlib, C/C++, OpenCL, CUDA. ㅡ PSG College of Technology / Bachelor of Engineering Education JULY 2010 - MAY 2014, COIMBATORE Bachelor’s degree in Electronics and Communication Engineering with CGPA of 8.42 (out of 10). Favourite subjects - Digital Electronics, Embedded Systems and C Programming. ㅡ Notable Served as one of the Joint Secretaries of Institution of Engineers(I) (students’ chapter) of PSG College of Technology. Efforts Secured first place in Line Tracer Event in Kriya ‘13, a Techno management fest conducted by Students Union of PSG College of Technology. Actively participated in FIRST Tech Challenge, a robotics competition, conducted by Caterpillar India.