UNIVERSITI TUNKU ABDUL RAHMAN
Process Integration
Dr. Lim Soo King 03/25/2013
Table of Contents Page
Chapter 1 Process Integration ...... 5 1.0 Introduction ...... 5 1.1 Bipolar Technology ...... 5 1.1.1 Conventional Bipolar Junction Transistor ...... 5 1.1.2 Figures of Merit of Bipolar Junction Transistor ...... 7 1.1.3 Performance of Bipolar Junction Transistor ...... 8 1.1.4 Device Optimization ...... 9 1.1.5 Advanced Bipolar Junction Transistor ...... 12 1.1.6 Self Aligned Double-Polysilicon Bipolar Structure ...... 14 1.1.7 Heterojunction Bipolar Junction Transistor ...... 16 1.2 CMOS Technology ...... 19 1.2.1 Gate Engineering Technology ...... 20 1.2.2 Salicidation ...... 22 1.2.3 Local Interconnect ...... 22 1.2.4 Well-Formation Technology ...... 23 1.2.5 Advanced Isolation Technology ...... 24 1.3 BiCMOS Technology ...... 25 1.3.1 BiCMOS Device Structure and Fabrication ...... 25 1.3.2 BiCMOS Digital Logic Circuits ...... 28 1.4 Gallium Arsenide Technology...... 30 1.4.1 Basic MESFET Operation ...... 31 1.4.2 Modulation Doping Field Effect Transistor ...... 33 1.4.3 Analysis of Current Equations ...... 37 1.4.4 Cut-Off Frequency ...... 41 1.5 Microelectromechanical Systems (MEMs) ...... 41 1.5.1 Applications of MEMs ...... 42 1.5.1.1 Medicine ...... 42 1.5.1.2 Communication ...... 42 1.5.1.3 Inertial Sensing ...... 43 1.5.2 Fabrication of MEMs ...... 43 1.5.2.1 Bulk Micromachining ...... 43 1.5.2.2 Surface Micromachining...... 47 1.5.3 Wafer Bonding ...... 48 Exercises ...... 49 Bibliography ...... 52
- ii - List of Figures Page
Figure 1.1: Structure of a bipolar junction transistor showing two pn junctions ...... 6 Figure 1.2: It illustrates the current components of a p+np transistor ...... 6 Figure 1.3: The high frequency small signal model of bipolar junction transistor ...... 8 Figure 1.4: Equations and typical values for the bipolar junction transistor model ...... 9 Figure 1.5: Flowchart of a generic bipolar device design optimization ...... 10 Figure 1.6: A simple traditional npn bipolar junction transistor showing the active or intrinsic region and parasitic or extrinsic region...... 12 Figure 1.7: Illustration of poly emitter technology used to diffuse emitter and intrinsic base ...... 14 Figure 1.8: Process sequence of fabrication of self align double polysilicon for the emitter of an npn bipolar transistor ...... 15 Figure 1.9: The cross sectional view of a self-aligned double polysilicon npn bipolar junction transistor...... 16 Figure 1.10: Emitter-base energy band diagram of a homojunction and heterojunction bipolar junction transistor ...... 17 Figure 1.11: An AlxGa1-xAs/ GaAs/ AlxGa1-xAs heterojunction bipolar junction transistor 18 Figure 1.12: Structure of complementary MOSFET (CMOS): (a) cross-sectional view of CMOS, (b) top plain view of CMOS ...... 19 Figure 1.13: Basic process flow of CMOS ...... 20 Figure 1.14: Conventional CMOS structure with a single polysilicon gate ...... 21 Figure 1.15: Advanced CMOS structure with dual polysilicon gates ...... 22 Figure 1.16: TiN is used to provide local short connection from diffusion region of MOSFET to a polyslicon gate...... 23 Figure 1.17: Various well formation technologies (a) single well and (b) twin well ...... 23 Figure 1.18: Process sequence for forming deep and narrow trench isolation ...... 24 Figure 1.19: A shallow trench isolation for CMOS process ...... 25 Figure 1.20: Cross-sectional view of BiCMOS structure ...... 26 Figure 1.21: Typical process flow of a BiCMOS device ...... 26 Figure 1.22: Relative gate delays for equal area CMOS and BiCMOS devices ...... 27 Figure 1.23: Digital and mixed-signal BiCMOS device structures ...... 28 Figure 1.24: A BiCMOS inverter or NOT gate ...... 29 Figure 1.25: BiCMOS 2-input NAND gate ...... 30 Figure 1.26: Cross sectional of a simple mesa-isolated MESFET ...... 32 + Figure 1.27: Energy band diagram of n -Al0.3Ga0.7As/n-GaAs heterojunction ...... 34 + Figure 1.28: A schematic of a recess-gate n -AlxGa1-xAs/GaAs MODFET ...... 35 + Figure 1.29: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET at thermal equilibrium ...... 35 + Figure 1.30: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for VG > Vt ..... 36 + Figure 1.31: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for –Vt - iii - List of Figures Page Figure 1.36: Illustration of a surface micromachining process for fabricating an anchor cantilever ...... 47 Figure 1.37: Set-up for anodic bonding ...... 48 - iv - Chapter 1 Process Integration ______ 1.0 Introduction In this chapter, we shall discuss the process integration technologies. The process integration technologies that would be covered including bipolar technology, CMOS and BiCMOS technologies, gallium arsenide technology, and MEM‟s technology. 1.1 Bipolar Technology The fabrication of a bipolar junction transistor BJT has evolved from the using conventional junction isolation process to high performance advanced sub- micron design using double poly self assigned process to ultra high performance SiGe alloy heterojunction bipolar transistor etc. The technologies involve in designing the BJT has also evolved from the conventional design using silicon semiconductor to advanced materials such as gallium arsenide compound semiconductor, and SiGe alloy semiconductor materials. In this section, one will study the physics underlying how these transistors are designed and implemented in fabrication. The learner will also how to strike a balance to decide how the design can be optimized and at the same time learn how the limitation of each design type can be overcome by implementing new design using different semiconductor material and technology. 1.1.1 Conventional Bipolar Junction Transistor There are three common designs of a conventional bipolar junction transistor using reverse-biased pn junction to provide an isolation called junction isolation JI between collectors of the device on the same silicon. The three design structures are standard buried-collector SBC, collector-diffused isolation transistor DCI, and triple-diffused transistor 3D. Bipolar junction transistor can be viewed as two pn junctions connected back to back to form np-pn or pn-np structures name as npn or pnp transistor. Figure 1.1 shows a cross sectional structure of a bipolar junction transistor showing presence of two pn junctions. 01 Process Integration Like a typical pn junction the current components of a bipolar junction transistor come from two carrier types, which are hole and electron current. This is also the reason why it is called bipolar device. Figure 1.1: Structure of a bipolar junction transistor showing two pn junctions The current components shown in Fig. 1.2 are consisted of diffusion hole, diffusion electron, drift hole, and drift electron. Note that the drift hole current consists of two components namely the injected hole from emitter and drift hole current from the base. Figure 1.2: It illustrates the current components of a p+np transistor Bipolar junction transistor has three terminals. One terminal is used to inject carrier named as emitter E, one is used to control the passage of the carrier named as base B, and one is used to collect the carrier named as collector C. - 6 - 01 Process Inegration Conventionally the bipolar junction transistor is designed in such that the doping concentration of its emitter is higher than the doping concentration of the base and collector. The order of doping concentration is the highest for emitter 1018cm-3, followed by collector 1017cm-3 and then base 1016cm-3. This is to ensure closed to 100% of the injected carrier from the emitter can pass through the without much recombination and are collected by collector. In this manner, the injected carriers from the emitter have outnumbered the recombination of carrier in the base. The low doping concentration of the collector is necessary to improve the reverse breakdown voltage BVCEO of the device. The base is also designed to be much shorter than the diffusion length L of the minority hole or electron carriers so that it reduces the chance of recombination, hence improve the current gain of the transistor, and improve the bandwidth of the device due to shorter transit time in the base. 1.1.2 Figures of Merit of Bipolar Junction Transistor There are a number of figures of merit for bipolar junction transistor. In the digital bipolar process, the cut-off frequency fT is a well-known figure of merit for speed. fT is defined by a common-emitter configuration with its output short- circuited and extrapolating the small signal current gain to unity gain or it is simply called the unity gain frequency. This unity gain frequency is called cut- off frequency. From a circuit perspective, a more adequate figure of merit is the gate delay time td measured for a ring-oscillator circuit containing an odd number of inverters. The time delay td can be expressed as a linear combination of the incoming time constants weighted by a factor determined by a circuit topology. Alternative expressions for td calculations have been proposed. Besides time delay, power dissipation can also be a critical issue in densely packed bipolar digital circuits, resulting in the power-delay product as a figure of merit. In the analog bipolar process, dc properties of the transistor are utmost important factors. This involves minimum values on common-emitter current gain β, Gummel plot linearity βmax/β, breakdown voltage BVCEO, and Early voltage VA. The product βVA is often introduced as a figure of merit for the device dc characteristics. Rather than the unity gain fT, the maximum oscillation frequency fmax = fT /(8R BCBC ) is preferred as a figure of merit in high-speed analog design, where RB and CBC denote the total base resistance and the base- collector capacitance respectively. Alternative figures of merit such as corner - 7 - 01 Process Integration frequency are the figure of merit for low-frequency application and noise figure as the figure of merit for high-frequency applications. 1.1.3 Performance of Bipolar Junction Transistor High performance shall mean the device requires high input impedance r, high Early voltage VA, which directly determines the output impedance ro, and high transconductance gm. This would mean that the device will be biased to as high as possible voltage for high collector current before Kirk effect occurred. Kirk effect occurs when the concentration of the injected majority carrier from emitter is closed to or has same the doping concentration of the collector. The high frequency small signal model of bipolar junction transistor is shown in Fig. 1.3. The unity gain frequency of the transistor is equal to g m fT = (1.1) 2(C C ) where Cµ and C are the ac impedance between collector and base and ac input impedance at base respectively and gm is the transconductance of the device. The corner frequency (fC) is defined as 1 fC = (1.2) 2r (C g m roC ) where ro is the ac output impedance between collector and emitter. Figure 1.3: The high frequency small signal model of bipolar junction transistor - 8 - 01 Process Inegration Typical values and equations used for the bipolar junction transistor model shown in Fig. 1.6 are shown in Fig. 1.4, where ICQ and VT are the quiescent collector current and thermal voltage of the transistor. Parameters Equation Typical value (IC = 1.0mA) r /gm 2.6 k r [5 to 10]x(ro) 100 M ro VA/ICQ 100 k gm ICQ/VT 40 mA/V C - 1.0 pF C - 0.3 pF CCS - 3.0 pF Figure 1.4: Equations and typical values for the bipolar junction transistor model 1.1.4 Device Optimization The flowchart of generic device optimization of the bipolar technology is shown in Fig. 1.5. It starts with defining the device/circuit requirements like the beta value β, Early voltage VA, collector current, and reverse breakdown voltage BVCEO. All of these defined requirements or specifications are to be determined by the vertical profiles of the device, which are the collector current density JC, the doping concentrations of base NB and collector NC, and the horizontal layout of the device in terms of emitter width, length, thickness etc. One will also notice that the width, length, and thickness of the emitter particularly the width will determine the collector current density of the transistor and certainly determine the cut-off frequency fT of the transistor. From the chart, one can see that thicker collector and lower doping concentration of collect NC mean higher reverse breakdown voltage BVCEO. However, higher BVCEO means lower cut-off frequency fT and high propagation delay D. Thus, it is a gain a strike a balance game between these two parameters. So far, the discussion of optimization of the bipolar design is a matter of strike a balance game, where designer has made decision on what are the requirements according to a typical modeled parameters as shown in Fig. 1.4 and of course the field of applications – digital or analogue applications. - 9 - 01 Process Integration Figure 1.5: Flowchart of a generic bipolar device design optimization The beta value β is the common-emitter current gain, which is defined as the ratio of collector current IC to base current IB i.e. IC / IB . However, in terms of device parameters and design dimensions, beta value is also equal to N D L E B E (1.3) N BDE WB where N is the doping concentration, D is the diffusivity of the minority carrier, L is the diffusion length, and WB is the width of the base. For the non-uniform doped base, the factor NBWB is replaced by Gummel number (GB), which is defined as - 10 - 01 Process Inegration G N(x)dx B (1.4) If the diffusion length LB of the minority carrier in the base is not infinite, then equation (1.5) is redefined as D L N B E E (1.5) 3 DB WBL E N E G B DE 2 2G BL B A number of deductions can be obtained from equation (1.5). For high beta device, the diffusion length of the minority carrier in the base should be infinite, which shall mean the device is required to design with short base width WB. Ideally, the base width is designed such that it is less than the minority diffusion length in the base .i.e. WB A heavily doped emitter is necessary for obtaining higher collector current IC simply more carrier from emitter will be collected at collector, in which it forms most part of the collector current. Higher Early voltage VA is necessary for analog design particular since the output conductance acts as a parasitic output load. If one recalls that the small signal gain of the common-emitter amplifier is equal to gmRC||(VA/IC). Typically the Early voltage VA is equal to 30V for analog application and 10 to 15V for digital application. Early voltage can be increased by increasing the width of the base WB. This is done to reduce the effect due to base width modulation due thickness of depletion region from reverse biasing of collector-to-base terminal of the device. There is a trade-off by doing so. The gain would be reduced. Reverse breakdown voltage BVCEO is achieved with defined epitaxial thickness with formed part of the collector. Normally, the collector is lightly doped. Thus, the reverse breakdown voltage BVCEO is usually high. However, the trade-off is the switching of the device. This is because the RC time constant is normally high for thick collector and lightly doped collector. - 11 - 01 Process Integration The cross sectional area of the emitter would determine the current density. This would decide the switching time due to large capacitance. Large cross sectional area and high current condition cause lateral voltage drop and Kirk effect. Large cross sectional area causes vary base voltage that reducing the drive capability of the device. Too high collector current would mean the concentration of minority injection from base may reach the value of doping concentration of the collector. In this condition, the electric field would be reduced to zero and the base is encroached into the metallurgical collector. This shall mean base width increase. Thus, the gain decreases. The collector current density JC shall follow equation (1.6). 2SVCB J C qVsat NC (1.6) qWC 1.1.5 Advanced Bipolar Junction Transistor A conventional sample lateral npn bipolar junction transistor is shown in Fig. 1.6. They are a number of inherent trade-offs in this design technology as already discussed in earlier section. Only modest improvement can be made to either digital or analog performance of intrinsic device i.e. in terms of doping concentration, dimension etc. Decreasing the base width reduces the base transmit time but it requires higher base doping to prevent an excessively low Early voltage. Higher base doping would also mean higher emitter-base capacitance that reduces the base mobility. Reducing the width of emitter strip helps meaning it helps to reduce the base resistance. But base resistance (RB) is not a prime factor to determine the digital circuit performance. Figure 1.6: A simple traditional npn bipolar junction transistor showing the active or intrinsic region and parasitic or extrinsic region - 12 - 01 Process Inegration A clear improvement in the intrinsic device is by introducing a poly emitter contact as shown in Fig. 1.7. When a layer of heavily doped (>1020cm-3) 0 polysilicon, at least 500 A thick, is placed between the emitter and metal contact, the gain of the device increases. Any minority carrier in emitter would immediately combine at the metal-semiconductor contact. Thus, it increases collector current. Conventionally design without the polysilicon layer, if the thickness of emitter is less than diffusion length LE, the concentration gradient of the minority carrier increases. Thus, it increases the base current. Thus, it reduces the gain (). By introducing the polysilicon layer, it moves always the minority concentration at the metal-semiconductor contact. Thus, it reduces this effect. The diffusion length of minority carrier is in the range of 0.2 to 0.4µm. Increasing the thickness of emitter beyond this value decreases the base current. However, with the polysilicon layer emitter, it increases the gain. Poly emitter also allows fabricating very shallow emitter-base junction typically is in the 0 range between 200 A and 500 . (a) (b) - 13 - 01 Process Integration (c) Figure 1.7: Illustration of poly emitter technology used to diffuse emitter and intrinsic base 1.1.6 Self Aligned Double-Polysilicon Bipolar Structure To further improve on the performance of bipolar device, the solution is to use self-alignment process as illustrated in Fig. 1.8. The base and emitter contacts would be aligned themselves automatically due to surface topology. The most successful method is using double-polysilicon method, which has been shown in Fig. 1.7 due to several advantages. The contact is done through the p+ poly over field oxide. This reduces the base-to-collector capacitance hence improving frequency bandwidth. The base-to-collector area is less than 0.5µm times the length of the transistor instead of 10 to 12µm times the length of the transistor. Typically the self aligned emitter width is about 0.3 to 0.5µm. This allows small dimension design with small base, shallow emitter, and cut-off frequency of 16.0GHz to be designed. The base material for the fabrication of self-aligned double-polysilicon bipolar device is the poly filled trench tub and oxide isolated n material with p- type as substrate. (a) (b) - 14 - 01 Process Inegration (c) (d) (e) Figure 1.8: Process sequence of fabrication of self align double polysilicon for the emitter of an npn bipolar transistor The first process step is polysilicon layer deposition and heavily doped with boron. The p+-polysilicon called poly 1 will be used as a solid-phase diffusion source to form the extrinsic base region and the base electrode. CVD oxide and silicon nitride are then deposited as shown in Fig. 1.8(a). The second process step is patterning the emitter region and a dry-etch process to produce an opening in the CVD oxide and poly layer (Fig. 1.8(b)). This is followed by thermal oxide grown over the etch area and relatively thick oxide 0.1-0.4µm is grown on the vertical sidewall of heavily doped polysilicon. The oxide thickness will determine the spacing between the edges of base and emitter contacts. The extrinsic p+ base regions are also formed during this process as the result of out-diffusion of boron from poly 1 into the substrate. It is because the boron is diffusion vertically and laterally, the extrinsic base region will be able to make contact with intrinsic base region that is formed next under the emitter contact. The intrinsic base is then formed using ion implantation of boron. This process step acts as the self-align of the intrinsic and extrinsic base region. After - 15 - 01 Process Integration this process step, poly 2 is formed by heavily doping with either arsenic or phosphorus (Fig. 1.8(d)). The n+-polysilicon, which is also called poly 2, is used as solid-phase diffusion source to form the emitter region and emitter electrode. A rapid thermal annealing (RTA) for the base and emitter out diffusion steps facilities the formation of shallow emitter-base and collector-base junctions. The last process step is depositing a Pt film and sintered to form PtSi over the n+-polysilicon emitter and the p+-polysilicon base contact. The cross sectional view of a self-aligned double polysilicon bipolar junction transistor is shown in Fig. 1.9. Figure 1.9: The cross sectional view of a self-aligned double polysilicon npn bipolar junction transistor Self-align process allows the fabrication of emitter region smaller than the minimum lithographic dimension. When the sidewall-spacer oxide is grown, it fills the contact hole to some degree because the thermal oxide occupies a larger volume than original volume polysilicon. Thus, an opening 0.8µm wide will shrink to about 0.4µm if sidewall oxide a 0.2µm thick is grown on each side. 1.1.7 Heterojunction Bipolar Junction Transistor The and of a homojunction bipolar junction transistor is equal to I B e = B B En and , where B is the base transport factor, IEn is the e 1 B IEn IEp e majority emitter current, IEp is the minority emitter current, and e is the emitter efficiency. Thus, traditional design of homojunction bipolar transistor has to reduce the concentration of base and increase the doping concentration of emitter in order to achieve high emitter efficiency. However, increase - 16 - 01 Process Inegration concentration of emitter would reduce speed due to larger capacitance and reducing doping concentration of the base would increase transit time. A transistor made with heterojunction material, its emitter efficiency can be increased without strict requirement on the doping concentration. As shown in Fig. 1.10, the built-in potentials qVbin for electron and hole qVbip are the same for homojunction bipolar junction transistor, whilst qVbin is lower than qVbip for an npn heterojunction bipolar junction transistor that uses a wide band-gap emitter such as AlxGa1-xAs and narrow energy band-gap base such GaAs. Since the carrier injection varies exponentially with built-in potential, even a small difference in these two built-in potentials can make a very large difference in the transport of electron and hole across the emitter junction. Knowing that the 2 minority carrier for homojunction n-type emitter is peo = ni /NDe. For a heterojunction n-type emitter, the minority carrier peo depending on an additional exponential term, which is 2 ni EG peo exp (1.7) N De kT where EG = EGe – EGb. Figure 1.10: Emitter-base energy band diagram of a homojunction and heterojunction bipolar junction transistor The additional term EG in equation (1.7), which is the difference between wide band-gap emitter and narrow band-gap base, allows choosing lightly doped emitter for reducing junction capacitance and heavily doped base to reduce base resistance freely without affecting the emitter efficiency. - 17 - 01 Process Integration For a small EG of 0.4eV such as the case of Al0.3Ga0.7As and GaAs 11 emitter-base junction, the value of minority hole in emitter peo is at least 1x10 time smaller than the peo of homojunction BJT. This implies that the emitter efficiency is essentially unity, so do and values would be improved. Thus, using this approach it does not scarify operation speed of the device. + A basic heterojunction bipolar junction transistor utilizing n-AlxGa1-xAs/P - + GaAs/n -AlxGa1-xAs is shown in Fig. 1.11. The minority carrier concentration in the emitter and base of an npn HBT are given by equation (1.8) and (1.9). 2 nie NCeN Ve EGe peo = exp (1.8) N De N De kT 2 nib NCbN Vb EGb nbo = exp (1.9) N Ab N Ab kT Figure 1.11: An AlxGa1-xAs/ GaAs/ AlxGa1-xAs heterojunction bipolar junction transistor n D L n The current gain is bo b e bo for the homojunction transistor. The peoDeWbn peo current gain for heterojunction transistor shall be N N N E E N E Cb Vb De exp Ge Gb De exp G (1.10) N Ab NCeN Ve kT N Ab kT where EG = EGe –EGb. - 18 - 01 Process Inegration InP/InGaAs heterostructure has very low surface recombination and higher electron mobility in InGaAs than GaAs. Thus, InP-based HBT has high cut-off frequency and as high as 254GHz has been obtained. The InP collector region has higher drift velocity than GaAs collector at high electric field and it has high breakdown voltage than gallium arsenide GaAs. 1.2 CMOS Technology Figure 1.12 shows the structure of a CMOS device. The transistors are n- channel MOSFET and p-channel MOSFET. Each MOSFET consists of a polysilicon gate electrode, source, drain, channel, and a substrate sitting in a tub. Figure 1.13 shows the basic fabrication process flow of CMOS device. The base wafer is p-lightly doped (~1015cm3) type of (100) orientation. This is chosen because the interstate trap density is smaller than those of (111) and (110) orientation silicon. Owing to the fact that the carrier of the MOSFET device flows near that semiconductor-oxide interface, lesser interstate trap density reduces the scattering of the carrier. Hence, it reduces that the transport time from source to drain of the device. The surface densities of (100), (110), and (111) orientation of silicon crystal are equal to 6.78x1014 atom cm-2, 9.59x1014 atom cm-2 and 7.83x1014 atom cm-2 respectively. (a) (b) Figure 1.12: Structure of complementary MOSFET (CMOS): (a) cross-sectional view of CMOS, (b) top plain view of CMOS - 19 - 01 Process Integration The first process step is formation of p-tub and n-tub in silicon substrate because CMOS has two types of MOS MOSFETs namely n-channel MOSFET is formed in p-tub and p-channel MOSFET in n-tub. The isolation process is used to form field oxide for separating each MOSFET active area in the same tub. Impurity is then doped into channel region to adjust the threshold voltage Vt for each type of MOSFET. The gate insulator layer, usually silicon dioxide SiO2, is grown by thermal oxidation. Polysilicon is deposited as the gate electrode material and gate electrode is patterned by reactive ion etching RIE method. Substrate p-type Tub/well formation Isolation Gate oxide Gate electrode formation Source/drain formation Metallization Figure 1.13: Basic process flow of CMOS 1.2.1 Gate Engineering Technology Figure 1.14 illustrates a conventional CMOS structure with a single polysilicon gate. The single poly gate CMOS structure has n+-polysilicon is used for p- MOS and n- MOS gates, the threshold voltage for p-MOS has to be adjusted by boron implantation. This makes the channel of the p-MOS as a buried type. The buried type p-MOS suffers serious short-channel effects as the device size shrinks below 0.25μm. The most noticeable phenomena for short-channel effects are threshold voltage lower, drain-induced barrier lowering, and the large leakage current at the switch off state. - 20 - 01 Process Inegration Figure 1.14: Conventional CMOS structure with a single polysilicon gate To alleviate these problems for sub-micron VLSI design, the n+-polysilicon can be changed to p+-polysilicon for the p-MOSFET. Owing to the work function difference between them, which is 1.0eV from n+- to p+-polysilicon, a surface p- type channel device can be achieved without the boron adjustment implantation. Thus, for channel length less than 0.25μm, dual-gate structures are fabricated, which p+-polysilicon gate for p-channel MOSFET and n+-polysilicon for n- channel MOSFET. Fig. 1.15 shows the advanced CMOS structure with dual polysilicon gates. The gate length L is the critical dimension because it determines the performance of MOS transistor and should be small for improving device performance. Impurity is doped in the source and drain regions of MOSFET by ion implantation. In this process step, the gate electrodes act as a self-aligned mask to cover channel layers. Thermal annealing is then carried out to activate the impurity of diffused layers. As the channel length is scaled down, hot ion effect is dominant. In order to prevent this effect, lightly doped drain LDD is fabricated. - 21 - 01 Process Integration Figure 1.15: Advanced CMOS structure with dual polysilicon gates 1.2.2 Salicidation Salicidation is a self align silicidation. The process covers the entire source, drain region and the top of polysilicon gate of a MOSFET. This process is necessary because in the case of high speed VLSI device, the drain and source are shallow and the gate is thin. In order to reduce parasitic resistance, self- aligned silicidation process is applied to the gate electrode, and source and drain diffused layers. In the earlier day, TiSi2 is widely used as a silicide in VLSI integrated circuit. However, in the case of ultra-small geometry MOSFET of VLSI design, using titanium silicide TiSi2 has several problems. When the titanium silicide TiSi2 is made thick, a large amount of silicon is consumed during silicidation, and this causes the problems of junction leakage at the source or drain. On the contrary, if a thin layer of titanium silicide TiSi2 is deposited, agglomeration of the film occurs at higher silicidation temperature. To resolve these problems, cobalt silicide CoSi2 is chosen, which has a large silicidation temperature window for low sheet resistance and is widely used as silicidation material for advanced VLSI integrated circuit fabrication. 1.2.3 Local Interconnect Local interconnect that derived from salicidation described in previous section can be used to replace buried contact by making direct contact from the diffusion to the polysilicon gate forming local short interconnection. During silicidation using titanium, titanium silicide is deposited on the diffusion region and at the same time titanium nitride TiN is deposited on the exposed surface of the polysilicon gate, silicon dioxide SiO2, and TiSi2. TiN is a conductor that can be used to provide short local connection between components like the structure illustrated in Fig. 1.16. - 22 - 01 Process Inegration Figure 1.16: TiN is used to provide local short connection from diffusion region of MOSFET to a polyslicon gate 1.2.4 Well-Formation Technology The well of CMOS device can be a single well, a twin well or retrograde well as shown in Fig. 1.17. The single well type can be p-well or n-well type. The twin well exhibits some disadvantage such as it needs high temperature 1,0500C processing and long diffusion time about 8.0hrs to achieve required depth of 2- 3m. (a) (b) Figure 1.17: Various well formation technologies (a) single well and (b) twin well - 23 - 01 Process Integration 1.2.5 Advanced Isolation Technology Conventional oxide such as field oxide has disadvantages that makes it unsuitable for deep-submicron (<0.25µm) fabrication. The high temperature oxidation of silicon and long oxidation time result in encroachment of channel stop (chanstop) implantation, which usually boron for n-channel MOSFET to active region and cause threshold shift. The area of active region is reduced because of the lateral oxidation. In addition, the field oxide thickness in submicron isolation spacing is significantly less than the thickness of field oxide grown in wider spacing. To resolve this problem, the trench isolation technology is used and it becomes the mainstream of the technology for isolation. Figure 1.18 shows the process sequence for forming a deep (> 3.0µm) and narrow (< 2.0µm) trench isolation structure. There are process steps which are patterning the area, trench etching and oxide growth, refilling with dielectric materials such as oxide or undoped polysilicon, and planarization. (a) (b) (c) (d) Figure 1.18: Process sequence for forming deep and narrow trench isolation - 24 - 01 Process Inegration The structure of the shallow-trench isolation of less than 1.0µm for CMOS integrated circuit is shown in Fig. 1.19. The process steps involves patterning, the trench area etch, refilled with oxide, and planarization using chemical mechanic process CMP. Before refilling, chanstop implantation can be performed. (a) (b) (c) (d) Figure 1.19: A shallow trench isolation for CMOS process 1.3 BiCMOS Technology BiCMOS is a combination of both bipolar and CMOS that allows the designer to use both devices on a single integrated circuit. The development of BiCMOS technology began in the early 1980s. In general, bipolar devices are attractive because of their high speed, better gain, better driving capability, and low wide- band noise properties that allow high-quality analog performance. CMOS is particularly attractive for digital applications because of its low power and high packing density. Thus, the combination of both device types would not only lead to the replacement and improvement of existing integrated circuit, but would also provide access to design completely new circuits. 1.3.1 BiCMOS Device Structure and Fabrication Figure 1.20 shows a typical BiCMOS structure. Generally, it has a vertical npn bipolar transistor, a lateral pnp transistor, and CMOS on the same chip. - 25 - 01 Process Integration Additional mask steps are used to integrated passive device. The main feature of the BiCMOS structure is the existence of a buried layer because bipolar processes require an epitaxial layer grown on a heavily doped n+ sub-collector to reduce collector resistance. Figure 1.20: Cross-sectional view of BiCMOS structure Figure 1.21 shows a typical process flow for BiCMOS. This is the simplest arrangement for incorporating bipolar junction transistor devices and a low-cost BiCMOS fabrication processes. Here, the BiCMOS process is completed with minimum additional process steps required to form the npn bipolar junction transistor device, transforming the CMOS baseline process into a full BiCMOS technology. For this purpose, many processes are merged. The p-tub of n- MOSFET shares an isolation of bipolar junction transistors, the n-tub of p- MOSFET is used for the collector, the n+ source and drain are used for the emitter regions and collector contacts, and also extrinsic base contacts have the p+ source and drain of p-MOSFET device for common use. Buried n+ and epitaxial layer Twin well/tub Collector n- Isolation Collector n+ implant Channel implant Gate oxidation Polysilicon gate LDD Source/drain p+ Base p+ Source/drain n+ Emitter n+ Base p Contact/Metallization Figure 1.21: Typical process flow of a BiCMOS device - 26 - 01 Process Inegration There have been two significant uses of BiCMOS technology. One of the usages is in the design of the high-performance microprocessor unit (MPU) using the high driving capability of bipolar junction transistor because bipolar junction transistor has better transconductance. Comparing the gate delay time and load capacitance capability for same area design, BiCMOS has a lower gate delay time than the CMOS at high load capacitive environment as illustrated in Fig. 1.22. Figure 1.22: Relative gate delays for equal area CMOS and BiCMOS devices In static RAM design, bipolar junction transistor is used in the sense amplifier to detect small voltage change in the bit line. In the mixed signal circuit design, BiCMOS design utilizes the excellent analog performance of the double poly self aligned bipolar junction transistor. Fig. 1.23 shows the side view structure of the digital BiCMOS and mixed signal BiCMOS device structures. For a high-performance microprocessor unit MPU, merged processes were commonly used by merging well and diffusion. As for the mature version of the MPU product, it has been replaced by CMOS VLSI design. However, this design has become less popular now a day because with reduction in the supply voltage, it is now not viable for the design. Mixed-signal BiCMOS device requires high performance, especially with respect to cut-off frequency fmax and low noise figure NF. Hence, a double polysilicon bipolar junction structure with a silicon or SiGe base with deep trench isolation together CMOS structure is fabricated in non-merged processes. - 27 - 01 Process Integration Figure 1.23: Digital and mixed-signal BiCMOS device structures 1.3.2 BiCMOS Digital Logic Circuits Figure 1.24 shows the circuit design of a BiCMOS inverter or NOT logic gate. Resistor R1 and R2 are used to provide sufficient voltage drop across base-to emitter voltage of transistor Q3 and Q4 for switching on purpose and at the same time used to discharge when the MOSFETs are switched-off. Let‟s begin with the output of the circuit at logic 0. A logic 0 at input will switch-on MOSFET Q1 and switched off MOSFET Q2. As the result, transistor Q4 is also switch-off while transistor Q3 is switched-on due to sufficient voltage developed across its base-to-emitter junction (>0.7V) and the load capacitor + begins to charge to V voltage. When the input is set to logic 1, transistor Q1 and Q3 are switched-off, while transistor Q2 is switched-on because of the logic 1 applied to its gate and Q4 are switched-on due to the charged voltage of load capacitor has created sufficient voltage across its base-to-emitter. As the result, the charge in the load capacitor begins to discharge until its voltage reaches V- voltage. - 28 - 01 Process Inegration Figure 1.24: A BiCMOS inverter or NOT gate The BiCMOS 2-input NAND gate is shown in Fig. 1.25. Either input A or B or both inputs of the NAND gate are set at logic 0, one of the transistors Q1 and Q2 or both transistors will switch- on, while the path connecting to the base of transistor Q6 is disconnected because one of the transistors Q3 and Q4 or both transistors will be switched- off. Thus, transistor Q5 switches- on and charges the load capacitor until the output voltage reaches V+. When both input A and B are set at logic 1, transistor Q3, Q4, and Q6 + switch-on (Q6 switches on if the output is at V voltage), while transistor Q1, Q2, and Q5 switch-off. As the result, output will discharge via transistor Q3, Q4, and Q6 until its voltage reaches V-. - 29 - 01 Process Integration Figure 1.25: BiCMOS 2-input NAND gate With the described examples on how to design BiCMOS digital circuit, any other BiCMOS logic circuit can be designed. 1.4 Gallium Arsenide Technology Gallium arsenide GaAs is distinct from silicon in several ways. First it is made in the form of very-high resistivity semi-insulating substrate. This provides a unique advantage for high speed analog application such as amplifiers and receivers for communication and radar. This feature is also made GaAs very useful for building digital integrated circuit that might be exposed to radiation such as that found on satellites. GaAs has high low field mobility (8,500cm2/V- s) and material is amenable to growth of heterostructures. Both favor for the fabrication of high speed, although the defect density and power dissipation limit the pack density as compared with CMOS devices. GaAs and other III-V semiconductors are direct semiconductors. This means that electron-hole - 30 - 01 Process Inegration recombination is lightly to give up a photon without involvement of momentum. Therefore, GaAs is a popular material for making various light emitting structure like infrared light-emitting diode, laser diode, and solar cell. GaAs is also used to fabricate monolithic microwave integrated circuit MMICs. Gallium arsenide can be prepared with a number industrial processes. The crystal growth can prepared using horizontal zone furnace, which is Bridgeman- Stockbarger technique, where gallium and arsenic vapor react and deposit on a seed crystal at the cooler end of the furnace. Liquid encapsulated Czochralski LEC is another method. Some techniques to produce GaAs film are vapor phase epitaxy VPE and Metal organic chemical vapor deposition MOCVD. In VPE process gaseous gallium reacts with arsenic trichloride to form GaAs thin film and chlorine. 2Ga +2AsCl3 2GaAs +3Cl2 (1.11) In MOCVD process, trimethylgallium reacts with arsine to form the GaAs thin film. Ga(CH3)3 + AsH3 GaAs +3CH4 (1.12) 1.4.1 Basic MESFET Operation The cross sectional area of a typical mesa isolated GaAs metal semiconductor field effect transistor MESFET is shown in Fig. 1.26. The internal pinch off voltage VP is equal to (Vbi - VG), which is also called intrinsic pinch off voltage. It is defined as 2 qN Dh VP (1.13) 2S where h is the thickness of the channel. The gate voltage VG required to cause pinch off is denoted by threshold voltage Voff, which is when gate voltage VG is equal to Voff. i.e. Vt = (Vbi - Vp). If Vbi > Vp, then the n-channel is already depleted. It requires a positive gate voltage to enhance the channel. If Vbi < Vp, then the n-channel requires a negative gate voltage to deplete. The gate voltage VG needed for pinch off for the n-channel MESFET device is - 31 - 01 Process Integration kT N qN h 2 C D Voff = Vbi -Vp= b ln (1.14) q ND 2S where b is Schottky barrier potential, which is defined as b m s . m and s are metal work function and electron affinity of semiconductor. NC is the effective density of state in conductor band of the semiconductor respectively. 17 -3 For GaAs semiconductor, the value of NC is 4.7x10 cm . Figure 1.26: Cross sectional of a simple mesa-isolated MESFET Like the MOSFET device, the current characteristics of the MESFET has the linear and saturation values, which are governed by the equation (1.15) and (1.16) respectively. 3/ 2 3/ 2 qn NDWh 2VDS Vbi VG Vbi VG IDS VD (1.15) L 3(qN h 2 / 2 )1/ 2 D S for 0 VDS VDSsat and VP VG 0. 3/ 2 Vp 2Vbi VG IDSsat go Vbi VG 1/ 2 (1.16) 3 3Vp for VDS VDSsat and VG VP. go is the channel conductance, which is defined q N Wh as g n D . o L - 32 - 01 Process Inegration 1.4.2 Modulation Doping Field Effect Transistor In order to maintain high transconductance for MESFET devices, the channel conductance must be as high as possible, which can be seen from equation (1.15) and (1.16) for MESFET device. The channel conductance is dependent on the mobility and doping concentration. But increasing doping concentration would lead to degradation of mobility due to scattering effect from ionized dopant. Thus, the ingredient is to keep concentration low and at the same time maintaining high conductivity. As the result of this need, heterojunction modulated doping field effect transistor MODFET is the choice. The most common heterojunctions for the MODFETs are formed from AlGaAs/GaAs, AlGaAs/InGaAs, InAlAs/InGaAs, and AlxGa1-xN/GaN heterojunctions. The better MODFET is fabricated with molecular beam epitaxy MBE or MOCVD etc and it is an epitaxial grown heterojunction structures. AlxGa1-xAs/GaAs MODFET is an unstrained type of heterojunction. This is o o because the lattice constants of GaAs (5.65 A ) and AlAs (5.66 A ) are almost the same except the energy band-gap. The energy band-gap of GaAs is 1.42eV, while the energy band-gap of AlAs is 2.16eV. The energy band-gap of the alloy can be calculated using equation Alloy 2 EG = a + bx + Cx (1.17) where a, b, and c are constant for a particular type of alloy. For AlxGa1-xAs, a is equal to 1.424, b is equal to 1.247, and c is equal to 0. For MODFET fabricated with AlxGa1-xAs/GaAs material, the approach is to create a thin undoped well such as GaAs bounded by wider band-gap modulated doped barrier AlGaAs. The purpose is to suppress impurity scattering. When electrons from doped AlGaAs barrier fall into the GaAs, they become trapped electrons. Since the donors are in AlGaAs layer not in intrinsic GaAs layer, there is no impurity scattering in the well. At low temperature the photon scattering due to lattice is much reduced, the mobility is drastically increased. The electron is well is below the donor level of the wide band-gap material. Thus, there is no freeze out problem. This approach is called modulation doping. If a MESFET is constructed with the channel along the GaAs well, the advantage would be reduced scattering, high mobility, and no free out problem. Thus, high carrier density can be maintained at low temperature and of course low noise. These features are especially good for - 33 - 01 Process Integration deep space reception. This device is called modulation doped field effect transistor MODFET and also called high electron mobility transistor HEMT or selective doped HT. Figure 1.27 illustrates the energy band diagram of n+- AlxGa1-xAs and n-GaAs heterojunction showing EC and EG. The delta energy band-gap between the wide band-gap and narrow band-gap device are determined from equation (1.18) and (1.19) respectively. EC = q(narrow - wide) (1.18) and EV = EG -EC (1.19) wide and narrow are respectively the electron affinity of wide band-gap and narrow band-gap semiconductor respectively. + Figure 1.27: Energy band diagram of n -Al0.3Ga0.7As/n-GaAs heterojunction The construction of a recess-gate AlGaAs/GaAs MODFET is shown in Fig. 1.28. The dotted line shows the quantum well where two-dimensional electron o gas 2-DEG flows. The undoped AlGaAs, which acts as buffer is 30 – 60 A thick. The n-AlGaAs is around 300 thick with concentration of approximately 2x1018cm-3. For recess-gate type, its thickness is about 500 . The source and - 34 - 01 Process Inegration drain contacts are made of alloy containing Ge such as AuGe. The gate materials can be from Ti, Mo, WSi, W and Al. + Figure 1.28: A schematic of a recess-gate n -AlxGa1-xAs/GaAs MODFET + Figure 1.29 shows the energy band diagram of the n -AlxGa1-xAs and undoped GaAs under thermal equilibrium, where b is the Schottky barrier potential. + Figure 1.29: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET at thermal equilibrium + Figure 1.30 shows the energy band diagram of the n -AlxGa1-xAs and undoped GaAs under applied gate voltage VG greater than threshold voltage Voff, which shows the 2-dimensional electron-gas 2-DEG. The threshold voltage Voff is defined as the gate voltage VG applied to the gate such that the Fermi energy level is touching the bottom of the GaAs conduction band. - 35 - 01 Process Integration + Figure 1.30: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for VG > Vt In this condition is charge density ns is at maximum value and the gate has no control on the channel. The electron is „force‟ to leave the AlGaAs either by tunneling through the spacer layer or by thermionic emission. An applied negative voltage at gate will begin to deplete the 2DEG in the + triangular quantum well. In this condition, the condition band of n -AlxGa1-xAs- AlGaAs is moving away from Fermi energy level. The triangular quantum well begins to flatten as shown in Fig. 1.31. + Figure 1.31: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for –Vt Further application of negative gate voltage will eventually completely deplete the 2DEG. This voltage is the threshold voltage Voff and in this condition, the triangular quantum well disappears and the carrier density equals to zero as shown in Fig. 1.32. + Figure 1.32: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for –Vt =VG The band bending function 2 in the barrier layer can be obtained by solving 2 qN D (z) Poisson equation 2 , where ND(z) is the doping concentration in b the barrier region. In the case that the whole barrier region ids depleted, ND(z) = ND for – d ≤ z ≤ - ds and ND(z) = 0 for – ds ≤ z ≤ 0. 1.4.3 Analysis of Current Equations In current control mechanism in MESFET is by means of controlling the thickness of channel h, while the mobile carrier density ns remained constant. For MODFET, the mobile carrier density ns in the channel is controlled, while the quantum will remain approximately constant. Using the same approach as the way how to analyze MESFET, the threshold voltage Voff of MODFET is expressed in equation (1.20). EF0 Ec Voff = V (1.20) b q p Vp is the pinch off voltage, which is potential difference between the modulated donor layer edges as shown in Fig. 1.30. Pinch off voltage follows equation - 37 - 01 Process Integration (1.21), where d is the barrier thickness and ds= dud is the spacer layer thickness and ddop is the thickness of doped layer which is equal to (d -ds). d q qN D 2 qN D 2 Vp = N (x)xdx = d d = d (1.21) D 2 s 2 dop b ds b b If we substitute equation (5.17) into equation (5.16), it yields the threshold voltage to be EF0 Ec qN D 2 Voff = b ddop (5.18) q 2b Equation tells us the thickness of the doped barrier layer ddop can be used to control threshold voltage Voff of the MODFET. From equation (5.18), if we denote the thickness of the doped barrier layer ddop to be ddop0 then ddop0 is equal to 2b EF0 EC ddop0 b (5.19) NDq q If the thickness of the doped barrier layer ddop is greater than ddop0 then the MODFET is in depletion mode and it will register current at VGS = 0 because its threshold voltage is a negative value. If the thickness of the doped barrier layer ddop is less than ddop0, it is either off or in operating enhancement mode and it will not pass current for VGS = 0 because the threshold voltage is a positive value. From equation (5.15), using linear approximation, the sheet carrier charge density ns of the 2-DEG gas at the interface is defined as b ns VG Voff (5.20) q(ddop dud d) where d is the thickness of mobile electron, which can be approximated as o equals to 80 A . The d value can also be calculated using equation (5.21). a d b (5.22) q - 38 - 01 Process Inegration With the presence of transverse electric field dV(y)/dy due to presence of drain- to-source voltage VDS and applying gradual channel approximation, the electron or sheet charge distribution ns across the channel is b ns (y) VG Voff V(y) (5.23) q(ddop dud d) where V(y) is the potential across the channel at distance y from source with drain-to-source bias voltage VDS and source to drain channel length L. The gate-channel capacitance of n-AlxGa1-xAs is equal to dn C q(WL) s b (5.24) AlxGa1xAs gate dVG ddop dud d where (WL)gate is the width and length of the gate. For gate voltage less than threshold voltage i.e. VG < Voff, the gate-channel capacitance follows equation (5.24). For the condition VG > Voff, the first order approximation of the gate- channel is equal to zero because the 2DEG is depleted. Since drift current is the major current component and diffusion current is assumed to be negligible, the current in the channel IDS shall be dV(y) IDS = Wnqns (5.25) dy Solving equation (5.25) for boundary conditions y = 0 to y = L for V(y) = 0 to V(y) = VDS, it would yield equation (5.26). Wnb VDS IDS = VG Voff VDS . (5.26) (ddop dud d)L 2 At saturation, the drain to source voltage VDS shall be VDSSAT = (VG – Voff). The saturation current IDSsat shall follow equation (5.27), which is Wnb 2 IDSsat = VG Voff (5.27) 2(ddop dud d)L Equation (5.27) is also termed as constant mobility saturation current IDSsat . - 39 - 01 Process Integration Since MODFET is a high mobility device, it needs a low critical electrical field Ecrit to attain saturation velocity vsat. Thus, the saturation drain-to-source voltage VDSSAT is VDSsat = Ecrit L. The saturation current IDSSat at velocity- saturation shall be IDSsat = qnsvsatW (5.28) This shall mean that saturation current is independent of channel length L. If we substitute equation (5.2), vsat = nECrit, and VG = VGS –VDSS into equation (5.28), it yields the constant velocity saturation current equation. Wnb IDDsat VGS Voff VDDS ECrit L (5.29) (ddop dup d)L Since equation (5.27) and (5.29) are saturation current equation transiting from constant mobility to constant velocity, equating these two equations will yield a quadratic equation for VDSS, which is 2 V V V V V E L GS off 1 GS off (5.30) DSS Crit E L E L Crit Crit Substituting equation (5.30) into equation (5.29), it yields the saturation current equation (5.31). 2 W (E L)2 V V I n b Crit 1 GS off 1 (5.31) DDsat (d d d)L E L dop up Crit The transconductance gmsat shall be equal to equation (5.29) by differentiating IDSSAT with respect to gate voltage VG. Wnb gmsat = VG Voff (5.32) (ddop dud d)L or Wnb (VGS Voff ) gmsat = (5.33) 2 V V GS off (ddop d ud d)L 1 ECrit L - 40 - 01 Process Inegration 1.4.4 Cut-Off Frequency The gate-to-source capacitance CAlGaAs is found to be following equation (5.34), which is L CAlGaAs gmsat (5.34) sat The cut-off frequency fT for MODFET follows equation (5.35). g msat fT = (5.35) 2(WLC AlGaAs Cpar ) where CAlGaAs is the gate-to-source capacitance and Cpar is parasitic capacitance. The cut-off frequency fT as high as 100GHz has been achieved for 0.25m device. It is expected to be higher than 150GHz for 0.10m device. 1.5 Microelectromechanical Systems (MEMs) In the early 1960s, researchers realized that the fabrication techniques developed for standard silicon integrated circuit processing could be extended to fabricate non-traditional silicon devices. Unlike ICs, which rely on the electrical properties of silicon, these devices utilized silicon‟s mechanical properties to form flexible membrances capable of moving in response to pressure chage. Thus, micoelectromechnical system (MEM) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through micro-fabrication technology. While the electronics are fabricated using integrated circuit (IC) fabrication techniques such as CMOS, Bipolar, or BICMOS processes, the micromechanical components are fabricated using compatible “micromachining” processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices. MEMs is revolutionized nearly every product category by bringing together silicon based microelectronics with micromachining technology making possible the realization of complete systems-on-a-chip circuit. MEMs is an enabling technology allowing the development of smart products that augmenting, enhancing the computational ability of microelectronics with the perception and control capabilities of micro-sensors and micro-actuators and expanding the space of possible designs and applications. - 41 - 01 Process Integration Microelectronics integrated circuit can be thought of as the main controller of a system and MEM augments the decision making capability which acts as peripherals to allow micro-system to sense and control the environment. The microelectronics circuit then processes the information derived from the sensors and making decision to direct the actuators to respond by moving, positioning, regulating, pumping, and filtering, thereby controlling the environment for the desired outcome. Owing to the fact MEMs device is manufactured using batch fabrication techniques similar to the mature techniques used for fabricating integrated circuit, unprecedented levels of functionality, reliability, and sophistication can be placed on a small silicon chip at a relatively low cost. MEMS technology is based on a number of tools and methodologies, which are used to form small structures with dimensions in the micron scale. The technology used to fabricate MEMs is adopted from current integrated circuit technology that has three basic process steps, which are deposition, lithography and etching. 1.5.1 Applications of MEMs There are numerous possible applications for MEMs. The breakthrough technology allows unparalleled integration between previously unrelated fields such as biology and microelectronics with it. Many new MEMs applications have been emerged and expanded beyond what is currently identified or known. We shall list a few here. 1.5.1.1 Medicine The main application of MEMs in medicine is MEMs pressure sensors, which are used to monitor the blood pressure in intravenous (IV) drip line of the patient, to measure intrauterine pressure during birth, to monitor the vital signs of the patient like respiratory rate and blood pressure in the hospital, to control the vacuum level used to remove fluid in eye surgery and etc. 1.5.1.2 Communication The performance of the electrical components such as inductors and tunable capacitors used in the radio frequency (RF) communication can be improved significantly as compared to integrated circuit components if they are made using MEMs. With the integration of MEMs components, not only the performance of communication circuit will improve, the total area of the circuit, power consumption, and cost will be reduced too. Another successful - 42 - 01 Process Inegration application of MEMs is in resonators as mechanical filters for RF communication circuits. 1.5.1.3 Inertial Sensing MEMS inertial sensors especially the accelerometer and gyroscope have replaced conventional accelerometers for crash air bag deployment systems in automobile. The previous technology, it requires several bulky accelerometers made of discrete components mounted in the front of the car with separate electronics near the air bag, which are costly and taken large space area. MEMs technology has made it possible to integrate the accelerometer and electronics onto a single silicon chip, which are less costly and occupy smaller area, more functional, lighter, and reliable. MEMS gyroscope has been developed for both automobile and consumer electronics applications like mobile phone. 1.5.2 Fabrication of MEMs Fabrication of MEMs uses many of the fabrication processes that are similarly used in fabrication of integrated circuit such as oxidation, diffusion, ion implantation, low pressure chemical vapor deposition (LPCVD), sputtering, etc. and the highly specialized micromachining processes. We shall discuss some of the most widely used micromachining processes. 1.5.2.1 Bulk Micromachining The oldest micromachining technology is bulk micromachining. This technique involves the selective removal of the substrate material in order to realize miniaturized mechanical components. Bulk micromachining can be accomplished using chemical or physical means, with chemical means being far more widely used in the MEMs industry. A widely used bulk micromachining technique is chemical wet etching, which involves the immersion of a substrate into a solution of reactive chemical that will etch the exposed regions of the substrate at determined rate. Chemical wet etching is a popular process in MEMS because it can provide a very high rate of etching and selective etching. Furthermore, the rate of etching and selectivity can be modified by altering the chemical composition of the etchant solution, adjusting the temperature of etchant solution, different doping concentration of the substrate, and selection of crystal plane of the substrate. There are two general types of chemical wet etching in bulk micromachining, which are isotropic and anisotropic wet etching. In isotropic wet etching, the rate of etching is not dependent on the crystal orientation of the - 43 - 01 Process Integration substrate and the etching proceeds in all directions at equal rates. Theoretically, lateral etching under the masking layer etches at the same rate as the rate of etching in normal direction. However, in practice lateral etching is usually slower without stirring. As the result, isotropic wet etching has to be performed with vigorous stirring of the etchant solution. Figure 1.33 illustrates the profile of the etch using an isotopic wet etchant with and without stirring of the etchant solution. (a) (b) Figure 1.33: Isotropic etch section showing undercutting (a) with agitation and (b) without agitation of etch profile Any etching process that requires a masking material like silicon dioxide and silicon nitride to be used has high selectivity relative to the substrate material. Silicon nitride has a lower rate of etching as compared to silicon dioxide and therefore is more frequently used. The rate of etching of a certain isotropic wet etchant solution is dependent on the doping concentration of the substrate material. For example, the commonly used etchant solution like HC2H3O2:HNO3:HF in the ratio of 8:3:1 will etch highly doped silicon (> 5x1018 atoms/cm3) at a rate of 50 to 200 - 44 - 01 Process Inegration microns/hour but will etch lightly doped silicon material at a rate 150 times slower. Nevertheless, the rate of etching and selectivity with respect to doping concentration are highly dependent on solution mixture. The widely used wet etching for silicon micromachining is anisotropic wet etching. Anisotropic wet etching involves the immersion of the substrate into a chemical solution wherein the etch rate is also dependent on crystallographic orientation of the substrate. The mechanism by which the etching varies according to the type of silicon crystal plane is attributed to the different bond configurations and atomic surface density that exposed to the etchant solution. Wet anisotropic chemical etching is typically described in terms of the rate of etching according to the types of crystal orientation, which usually are (100), (110), and (111). In general, silicon anisotropic etching etches slower along the (111) plane than the other planes in the crystal lattice. The difference in rate of etching between the different lattice directions can be as high as 1,000 to 1. The reason for the slower rate of etching on (111) plane is because this plane has highest surface density of exposed silicon atoms and there are three silicon covalent bonds below the plane that has provided chemical shielding effect of the surface. Figure 1.35 illustrates some of the shapes that are possible fabricated using anisotropic wet etching of (100) oriented silicon substrate. There includes an inverted pyramidal and a flat bottomed trapezoidal etch pit. One has to note that the shape of the etch pattern is primarily determined by the slower etching (111) planes. Figures 1.35(a) and 1.35(b) are SEM pictures of a silicon substrate after an anisotropic wet etching. Figure 1.34(a) shows a trapezoidal etch pit that has been subsequently diced across the etch pit and Fig. 1.35(b) shows the backside of a thin membrane that could be used to make a pressure sensor. Note that the etch profiles shown in the Fig. 1.35 are only for a (100) oriented silicon wafer. Substrates with other crystal orientations will exhibit different shapes. At time, substrate with other orientations is used in MEMs fabrication but it is in lesser extend because of the cost, lead times and availability. Thus, the vast majority of substrate used in bulk micromachining have (100) crystal orientation. - 45 - 01 Process Integration (a) (b) Figure 1.34: Illustration of shape of the etch profiles of a (100) oriented silicon substrate after immersion in an anisotropic wet etchant solution (a) (b) Figure 1.35: SEM picture of a (100) orientation silicon substrate after immersion in an anisotropic wet etchant Silicon nitride Si3N4 is a commonly used masking material for anisotropic wet etching because it has a very low rate of etching in most etchant solutions. However, the silicon nitride must not have any pinhole defect that will result the underlying silicon being etched. Low stress silicon rich nitride can be used for a - 46 - 01 Process Inegration higher rate of etching as compared to stoichiometric silicon nitride type. Thermally grown silicon dioxide SiO2 is another frequently used masking material. The thickness of the oxide must be sufficiently thick if potassium hydroxide KOH etchant is used because the rate of etching of silicon dioxide by KOH is high too. 1.5.2.2 Surface Micromachining Surface micromachining is another popular technique used for the fabrication of MEMs device. There are a large number of variations of how surface micromachining is performed, which are depending on the materials and etchant. However, the common process sequence starts with the deposition of a thin film material to act as a temporary mechanical layer or sacrificial layer onto which the actual device layer is to be built. It is followed by the deposition and patterning of the thin film material layer for device, which is the mechanical structural layer. The subsequent process is the removal of the temporary sacrificial layer to release the mechanical structural layer by etching away the temporary sacrificial layer for allowing movement of the mechanical structural layer. An illustration of a surface micromachining process for fabricating the anchor cantilever is shown in Fig. 1.36. The silicon oxide layer is a temporary sacrificial layer deposited and patterned as shown in Fig. 1.36(a). Subsequently, a thin film structural layer of polysilicon is deposited and patterned as shown in Fig. 1.36(b). Lastly, the temporary mechanical layer is removed and the polysilicon layer is now free to move as an anchor cantilever. (a) (b) (c) Figure 1.36: Illustration of a surface micromachining process for fabricating an anchor cantilever There are many other techniques for micromachining of MEMs device. The techniques include Xenon Difluoride micromachining, Electro-Discharge micromachining, Laser Micromachining, Focused Ion Beam micromachining etc. Learners are encouraged to learn these techniques with their own time. - 47 - 01 Process Integration The techniques of fabrication of MEMs device are not restrictive to the methods discussed above. There is another technique, which is termed as high- aspect ratio MEMs fabrication technology. High aspect ratio means that the etching to be performed into silicon substrate with the sidewall of the etched hole nearly vertical and the depth of the etching can be hundreds or even thousands of microns into the silicon substrate. There are many techniques to achieve it such as Deep Reactive Ion etching, LIGA, which is a German acronym for LIthographie Galvanoformung Adformung, Hoot Embossing etc. Again learners are encouraged to learn these techniques with their own time. 1.5.3 Wafer Bonding Wafer bonding is a micromachining method that is analogous to welding involving the joining of two or more wafers together to create a multi-wafer stack. There are three basic types of wafer bonding including direct or fusion bonding, field-assisted or anodic bonding, and bonding using an intermediate layer. In general, all bonding methods require substrates that are very flat, smooth, and clean so that the wafer bonding is free of void. Direct or fusion bonding is typically used to join two silicon wafers together or alternatively to join one silicon wafer to another silicon wafer that has been oxidized. Direct wafer bonding can be performed on bare silicon to a silicon wafer with a thin-film of silicon nitride on the surface. Anodic bonding is a popular wafer bonding technique. In anodic bonding a silicon wafer is bonded to a Pyrex glassed wafer using electric field at elevated temperature (2000C to 4000C). The set-up is shown in Fig. 1.37. It basically has hot chuck to place and heat the wafers and a holding tool to keep the wafers in contact so that there is continuity of electric current. Figure 1.37: Set-up for anodic bonding - 48 - 01 Process Inegration Anodic bonding works based on the fact that Pyrex glass wafer has a high concentration of sodium ion (Na+). A few hundred volts positive voltage is applied to the silicon wafer. It draws the Na+ ion in the Pyrex glass to its surface near the silicon interface of wafer 1. This leaves the negative charge at the interface with wafer 2. When the Na+ ion reaches the interface, a high field results the sodium ion forms sodium hydroxide with water in the atmosphere leaving oxygen ion moving downward to form silicon dioxide that fuses the two wafers together. An advantage of this process is that Pyrex glass has a thermal expansion coefficient nearly equal to that of silicon and therefore there is a low stress in the layers. Anodic bonding is a widely used technique for MEMs packaging. In addition to anodic bonding there are other wafer bonding techniques that are used in MEMs fabrication. One method is eutectic bonding and involves the bonding of a silicon substrate to another silicon substrate at elevated temperature using an intermediate layer of gold on the surface of one of the wafers. Eutectic bonding works because diffusion of gold into silicon is extremely rapid at elevated temperature. In fact this is a preferred method of wafer bonding at relatively low temperature. Other wafer bonding technique used in MEMs such glass frit bonding, using various intermediate layers for bonding etc, which will not discuss here. Exercises 1.1. Discuss conceptually how an npn Si bipolar junction transistor shall be designed? 1.2. What are carrier components in an npn Si bipolar junction transistor when it is biased in forward active mode? 1.3. Consider an npn Si bipolar junction transistor which is to be designed with an emitter efficiency of e = 0.995. To maintain a reasonable base 16 -3 resistance, the base is doped with boron of NA = 1.2x10 cm . Calculate the n-type doping concentration needed in the emitter. Given that Le ~ Wb 2 -1 2 -1 = 0.7m, De = 12cm s , and Db = 30cm s . 1.4. A Si pnp transistor at 300K has device area of 10-3cm2, base width of 1.0m, and minority carrier diffusion length for both electron and hole of 16 -3 17 -3 10m. The doping parameters are NC = 2x10 cm and NB = 1x10 cm - 49 - 01 Process Integration -7 and bo = 1x10 s. Calculate the collector current for the active mode case for condition i) VEB = 0.6V and ii) IB = -2.0A. 1.5. When an npn transistor is in saturation mode why the collector-base is forward biased instead of reverse biased? 1.6. Discuss how the Early voltage of a bipolar junction transistor be improved. By doing this improvement, what is the associated trade-off? 1.7. You are given processed dielectric isolation (111) orientation n-type wafer as shown in the figure. Write down the brief process steps for fabrication an npn transistor using this wafer. 1.8. State the reason that lightly doped drain LDD is essential in the CMOS fabrication. 1.9. State the reason why single poly gate CMOS structure is not commonly used to fabricate CMOS device that has channel length less than 0.25µm? 1.10. Describe how electromigration happened and how to solve the problem. 1.11. Discuss the solution to prevent the occurrence of latch-up problem. 1.12. Name two advantages of GaAs technologies over CMOS technologies. 1.13. A GaAs MESFET with gold Schottky barrier of barrier height 0.8V has n-channel doing concentration 4.0x1017cm-3 and channel thickness 0.20m. Calculate the threshold voltage for this MESFET. 1.14. Consider an n-channel GaAs MESFET that has ideal saturation current 3.80mA at VDSSAT = 3.0V, channel length 2.0m, and doping - 50 - 01 Process Inegration concentration 5.0x1017cm-3. What is the channel resistance of the device for VDS change from 3.0V to 3.2V? + 1.15. The energy band diagram of n -Al0.3Ga0.7As/n-GaAs heterojunction is shown in the figure. Calculate the delta energy band-gap and electron affinity of Al0.3Ga0.7As. 1.16. Name two commonly used masking materials for fabricating MEMs devices. 1.17. Name three factors that influencing the etching rate of an isotropic etch for MEMs. 1.18. State the reason why (100) orientation wafer is preferred for the design of MEMs device. 1.19. State the reason why anodic wafer bonding is usually done at elevated temperature. 1.20. What do you mean by high-aspect ratio MEMs fabrication? - 51 - 01 Process Integration Bibliography 1. Stephen A. Campbell, "The Science and Engineering of Microelectric Fabrication", second edition, Oxford University Press, Inc. 2001. 2. Gary S. May, Simon M. Sze, “Fundamentals of Semiconductor Fabrication”, John Wiley & Son Inc., 2004. 3. P. Rai-Choudhury, “Handbook of Microlithography, Micromachining, and Microfabrication, Vol. 1 and Vol. 2, SPIE Press and IEE Press, 1997. - 52 -