Characterization and Modeling of Polysilicon MEMS Chemical-Mechanical Polishing by Brian D
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(12) United States Patent (10) Patent No.: US 6,737,723 B2 Farrar (45) Date of Patent: *May 18, 2004
USOO6737723B2 (12) United States Patent (10) Patent No.: US 6,737,723 B2 Farrar (45) Date of Patent: *May 18, 2004 (54) LOW DIELECTRIC CONSTANT SHALLOW 4,096,227 A 6/1978 Gore ...................... 264/210 R TRENCH ISOLATION 4,368,350 A 1/1983 Perelman .................... 174/102 4,482.516. A 11/1984 Bowman et al. ............ 264/127 (75) Inventor: Paul A. Farrar, So. Burlington, VT 4,561,173 A 12/1985 Te Velde .................... 438/619 (US) 4,599,136 A 7/1986 Araps et al. ................ 156/643 (73) Assignee: Micron Technology, Inc., Boise, ID ( List continued on next page.)page. (US) FOREIGN PATENT DOCUMENTS EP 57.8856 A1 7/1992 ......... HO1 L/21/334 (*) Notice: Subject to any disclaimer, the term of this GB 2158995 A 11/1985 .......... HO1O/17/OO patent is extended or adjusted under 35 p. O1-2305.05 8/2001 ............ HO5K/1/03 U.S.C. 154(b) by 0 days. OTHER PUBLICATIONS This patent is subject to a terminal dis- Labadie et al., Nanopore Foams of High Temperature Poly claimer. mers, IEEE Trans. Components, Hybrids, Manufacturing Tech., 15 (Dec. 1992)925.* (21) Appl. No.: 10/184,321 Bhusari et al., Fabrication of Air-Channel Structures for Microfluidic, Microelectromechanical, and Microelectronic (22) Filed: Jun. 27, 2002 Applications, J. Microelectromechanical Systems, 10 (Sep. (65) Prior Publication Data 2001) 400.* US 2002/0163044 A1 Nov. 7, 2002 (List continued on next page.) Related U.S. ApplicationO O Dat Primaryy Examiner-Richard Elms eae pplication Uata ASSistant Examiner-Christian Wilson (62) Division of application No. 09/503.278, filed on Feb. -
Introduction to Microelectronic Fabrication
020144941jaegFM_v5 9/10/01 8:55 PM Page i MODULAR SERIES ON SOLID STATE DEVICES Gerold W. Neudeck and Robert F. Pierret, Editors Volume V Introduction to Microelectronic Fabrication Second Edition Richard C. Jaeger Auburn University Prentice Hall Upper Saddle River, New Jersey 07458 020144941jaegFM_v5 9/10/01 8:55 PM Page ii Library of Congress CataIoging-in-Publication Data Jaeger, Richard C. Introduction to microelectronic fabrication / Richard C. Jaeger—2nd Edition p. cm. (Modular series on solid state devices; v. 5) Includes bibliographical references and index. ISBN 0-201-44494-7 1. Integrated circuits—Very large scale integration—Design and construction—Congresses. I. Title. II. Series. CIP Data available. Vice President and Editorial Director, ECS: Marcia J. Horton Publisher: Tom Robbins Associate Editor: Alice Dworkin Editorial Assistant: Jody McDonnell Vice President and Director of Production and Manufacturing, ESM: David W. Riccardi Executive Managing Editor: Vince O’Brien Managing Editor: David A. George Production Editor: Irwin Zucker Director of Creative Services: Paul Belfanti Manager of Electronic Composition and Digital Content: Jim Sullivan Electronic Composition: William Johnson Creative Director: Carole Anson Art Director: Jayne Conte Art Editor: Gregory Dulles Manufacturing Manager: Trudy Pisciotti Manufacturing Buyer: Lisa McDowell Marketing Manager: Holly Stark Marketing Assistant: Karen Moon © 2002, 1998 by Prentice Hall Published by Prentice-Hall, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. No part of this book may he reproduced in any format or by any means, without permis- sion in writing from the publisher The author and publisher of this book have used their best efforts in preparing this book. -
2003Nnunreura.Pdf
The 2003 National Nanofabrication Users Network Research Experience for Undergraduates Program Table of Contents NNUN REU Introduction ............................. 3 NNUN REU Interns ....................................... 4 Blast From the Past ........................................ 5 2003 NNUN REU Program at Howard...... 41 The Effects of Thermal Annealing on InGaAsN and GaAsN .................................... 42 Characterization of Ion-Implanted Nanofiltration Membranes ................................. 44 2003 NNUN REU Program at CNF............ 15 GaAlAs/GaAs Heterojunction Prosthetic Retina ... 46 Laser Lysis of Liposomes in a Microfluidic Device . 16 Catalytic Growth of GaN and other Nitride Nanowires Interdigitated Microelectrode Arrays for for Electronic and Photonic Applications ............. 48 Organic Light Emitting Diodes .......................... 18 Fabrication of Silicon Carbide Optimizing Shallow Trench Isolation for Atomic Force Microscopy Probes ...................... 50 SOI CMOS Transistors....................................... 20 Developing IR (8-14 µm) Detectors Two-D Nanobumps Using Ion Sputtering ............. 22 (External Photoemission) ................................... 52 Microfluidic Device for Pharmaceutical Research ... 24 Fabrication of Biomolecular Sieves with Novel Geometry ......................................... 26 Chemistry-on-a-Chip: Multiphase Microfluidic Devices ....................... 28 Embossing Polymer Waveguides for Integrated Optical Devices ........................... 30 Novel Gate -
Chapter 1 Process Integration
UNIVERSITI TUNKU ABDUL RAHMAN Process Integration Dr. Lim Soo King 03/25/2013 Table of Contents Page Chapter 1 Process Integration ........................................................... 5 1.0 Introduction ................................................................................................ 5 1.1 Bipolar Technology .................................................................................... 5 1.1.1 Conventional Bipolar Junction Transistor ........................................................ 5 1.1.2 Figures of Merit of Bipolar Junction Transistor ............................................... 7 1.1.3 Performance of Bipolar Junction Transistor ..................................................... 8 1.1.4 Device Optimization ............................................................................................. 9 1.1.5 Advanced Bipolar Junction Transistor ............................................................ 12 1.1.6 Self Aligned Double-Polysilicon Bipolar Structure ......................................... 14 1.1.7 Heterojunction Bipolar Junction Transistor ................................................... 16 1.2 CMOS Technology ................................................................................... 19 1.2.1 Gate Engineering Technology ........................................................................... 20 1.2.2 Salicidation .......................................................................................................... 22 1.2.3 Local Interconnect .............................................................................................