UNIVERSITI TUNKU ABDUL RAHMAN Process Integration Dr. Lim Soo King 03/25/2013 Table of Contents Page Chapter 1 Process Integration ........................................................... 5 1.0 Introduction ................................................................................................ 5 1.1 Bipolar Technology .................................................................................... 5 1.1.1 Conventional Bipolar Junction Transistor ........................................................ 5 1.1.2 Figures of Merit of Bipolar Junction Transistor ............................................... 7 1.1.3 Performance of Bipolar Junction Transistor ..................................................... 8 1.1.4 Device Optimization ............................................................................................. 9 1.1.5 Advanced Bipolar Junction Transistor ............................................................ 12 1.1.6 Self Aligned Double-Polysilicon Bipolar Structure ......................................... 14 1.1.7 Heterojunction Bipolar Junction Transistor ................................................... 16 1.2 CMOS Technology ................................................................................... 19 1.2.1 Gate Engineering Technology ........................................................................... 20 1.2.2 Salicidation .......................................................................................................... 22 1.2.3 Local Interconnect .............................................................................................. 22 1.2.4 Well-Formation Technology .............................................................................. 23 1.2.5 Advanced Isolation Technology ........................................................................ 24 1.3 BiCMOS Technology ............................................................................... 25 1.3.1 BiCMOS Device Structure and Fabrication .................................................... 25 1.3.2 BiCMOS Digital Logic Circuits ........................................................................ 28 1.4 Gallium Arsenide Technology................................................................. 30 1.4.1 Basic MESFET Operation ................................................................................. 31 1.4.2 Modulation Doping Field Effect Transistor ..................................................... 33 1.4.3 Analysis of Current Equations .......................................................................... 37 1.4.4 Cut-Off Frequency ............................................................................................. 41 1.5 Microelectromechanical Systems (MEMs) ............................................ 41 1.5.1 Applications of MEMs ....................................................................................... 42 1.5.1.1 Medicine .......................................................................................................................... 42 1.5.1.2 Communication .............................................................................................................. 42 1.5.1.3 Inertial Sensing ............................................................................................................... 43 1.5.2 Fabrication of MEMs ......................................................................................... 43 1.5.2.1 Bulk Micromachining .................................................................................................... 43 1.5.2.2 Surface Micromachining................................................................................................ 47 1.5.3 Wafer Bonding .................................................................................................... 48 Exercises .......................................................................................................... 49 Bibliography ................................................................................................... 52 - ii - List of Figures Page Figure 1.1: Structure of a bipolar junction transistor showing two pn junctions ................. 6 Figure 1.2: It illustrates the current components of a p+np transistor .................................. 6 Figure 1.3: The high frequency small signal model of bipolar junction transistor .............. 8 Figure 1.4: Equations and typical values for the bipolar junction transistor model ............. 9 Figure 1.5: Flowchart of a generic bipolar device design optimization ............................. 10 Figure 1.6: A simple traditional npn bipolar junction transistor showing the active or intrinsic region and parasitic or extrinsic region.............................................. 12 Figure 1.7: Illustration of poly emitter technology used to diffuse emitter and intrinsic base .................................................................................................................. 14 Figure 1.8: Process sequence of fabrication of self align double polysilicon for the emitter of an npn bipolar transistor .............................................................................. 15 Figure 1.9: The cross sectional view of a self-aligned double polysilicon npn bipolar junction transistor............................................................................................. 16 Figure 1.10: Emitter-base energy band diagram of a homojunction and heterojunction bipolar junction transistor ................................................................................ 17 Figure 1.11: An AlxGa1-xAs/ GaAs/ AlxGa1-xAs heterojunction bipolar junction transistor 18 Figure 1.12: Structure of complementary MOSFET (CMOS): (a) cross-sectional view of CMOS, (b) top plain view of CMOS ............................................................... 19 Figure 1.13: Basic process flow of CMOS ........................................................................... 20 Figure 1.14: Conventional CMOS structure with a single polysilicon gate ......................... 21 Figure 1.15: Advanced CMOS structure with dual polysilicon gates .................................. 22 Figure 1.16: TiN is used to provide local short connection from diffusion region of MOSFET to a polyslicon gate.......................................................................... 23 Figure 1.17: Various well formation technologies (a) single well and (b) twin well ........... 23 Figure 1.18: Process sequence for forming deep and narrow trench isolation ..................... 24 Figure 1.19: A shallow trench isolation for CMOS process ................................................ 25 Figure 1.20: Cross-sectional view of BiCMOS structure ..................................................... 26 Figure 1.21: Typical process flow of a BiCMOS device ..................................................... 26 Figure 1.22: Relative gate delays for equal area CMOS and BiCMOS devices .................. 27 Figure 1.23: Digital and mixed-signal BiCMOS device structures ...................................... 28 Figure 1.24: A BiCMOS inverter or NOT gate .................................................................... 29 Figure 1.25: BiCMOS 2-input NAND gate .......................................................................... 30 Figure 1.26: Cross sectional of a simple mesa-isolated MESFET ....................................... 32 + Figure 1.27: Energy band diagram of n -Al0.3Ga0.7As/n-GaAs heterojunction ................... 34 + Figure 1.28: A schematic of a recess-gate n -AlxGa1-xAs/GaAs MODFET ........................ 35 + Figure 1.29: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET at thermal equilibrium ....................................................................................................... 35 + Figure 1.30: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for VG > Vt ..... 36 + Figure 1.31: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for –Vt <VG < 0 .......................................................................................................................... 36 + Figure 1.32: Energy band diagram of n -AlxGa1-xAs and GaAs MODFET for –Vt =VG .... 37 Figure 1.33: Isotropic etch section showing undercutting (a) with agitation and (b) without agitation of etch profile .................................................................................... 44 Figure 1.34: Illustration of shape of the etch profiles of a (100) oriented silicon substrate after immersion in an anisotropic wet etchant solution ................................... 46 Figure 1.35: SEM picture of a (100) orientation silicon substrate after immersion in an anisotropic wet etchant .................................................................................... 46 - iii - List of Figures Page Figure 1.36: Illustration of a surface micromachining process for fabricating an anchor cantilever .......................................................................................................... 47 Figure 1.37: Set-up for anodic bonding ................................................................................ 48 - iv - Chapter 1 Process Integration _____________________________________________ 1.0 Introduction In this chapter, we shall discuss the process integration technologies. The process integration technologies that would be covered including bipolar technology, CMOS and BiCMOS technologies, gallium arsenide technology, and MEM‟s technology. 1.1 Bipolar Technology The