TS9: Em35x NCP Breakout Board Technical Specification

TS9

® EMBER EM35X NCP BREAKOUT BOARD TECHNICAL SPECIFICATION

The Silicon Labs’ Ember EM35x Network Co-Processor (NCP) Breakout Board contains the hardware peripherals for the development and deployment of a low-data-rate, low-power ZigBee application on a host micro interfacing via EZSP protocol to the EM300 series NCPs. The NCP Breakout Board supports SPI and UART EZSP interfaces for development flexibility. Modules separately contain the EM35x NCP and the HOST microcontroller to allow for higher degrees of freedom during application development. The modules are connected to the NCP Breakout Board though robust connectors. The EM35x NCP Breakout Board hardware stimuli include a temperature sensor, two buttons, a piezo buzzer, two LEDs, and a 1.6" x 1.8" through-hole prototyping area. The EM35x NCP Breakout Board also contains a USB transceiver with USB connector, a RS-232 transceiver with DB-9 connector, Data Emulation Interface (DEI), Packet Trace Port programming interface, and regulated power planes. The EM35x NCP Breakout Board also includes an optional host interface to 2 Mbit external DataFlash in support of the ZigBee OTA upgrade cluster for over-the-air (OTA) application bootloader purposes. You can obtain the EM35x NCP Breakout Board voltage supply from one of four sources: Debug Adapter (ISA3) (through the Packet Trace Port), external VDC supply, USB port, or AAA battery pack. The various voltage supplies offer a degree of flexibility when testing different network topologies. This document provides the technical specification for the EM35x NCP Breakout Board. It describes the board-level interfaces as well as the key performance parameters. In addition, it provides the necessary information for developer to validate their application designs using the EM35x NCP Breakout Board. New in This Revision Document renumbering. Contents 1 EM35x NCP Breakout Board Features ...... 3 2 Components ...... 5 2.1 Power supply and distribution ...... 5 2.1.1 External DC Power Supply (J1 and J32 or J3.2 and J32) ...... 7 2.1.2 Battery Connector (J8) ...... 7 2.1.3 Packet Trace Port (J8) ...... 7 2.1.4 USB Host (J5) ...... 7 2.2 NCP Current Measurements ...... 7 2.3 Host Current Measurements...... 7 2.4 Deep Sleep Testing of the EM35x Module ...... 7 2.5 ZigBee Application Peripherals ...... 8 2.5.1 Temperature Sensor (U4) ...... 8 2.5.2 Buttons (EM1, EM2) ...... 9

2.5.3 Buzzer (SPK1) ...... 9 2.5.4 LEDs (DS6 and DS7) ...... 9 2.5.5 External DataFlash (U7) ...... 9 2.6 EZSP and Serial Mode Configuration Switch (SW1) ...... 10 2.7 Data Emulation Interface (J43) ...... 15 2.8 EM35x Module Interface Connector (J21-J24) ...... 15 2.9 Host Module interface connector (J37-J38)...... 18 2.10 Prototyping Area ...... 20 3 EM35x NCP Breakout Board Schematic ...... 21

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1 EM35x NCP Breakout Board Features The EM35x NCP Breakout Board offers: • Configurable hardware support for application development Temperature sensor (connects to host GPIO) Two buttons (connect to host GPIO) Piezo buzzer (connect to host GPIO) Two LEDs (connect to host GPIO) • RS-232 transceiver with DB-9 connector for serial communication (with hardware (HW) handshake support) • USB transceiver with USB connector (Type B) • 2 MB external DataFlash for ZigBee OTA Profile support • Control Interface for the EM35x Radio Communications Module (RCM) RCM RESET and Bootload buttons Voltage Supply connection (V_NCP_EN) • Control Interface for the Host Module RCM RESET and Bootload buttons Voltage Supply connection (V_HOST_EN) • 1.6" x 1.8", 0.1" pitch prototyping area • 26-pin, 0.1" pitch, dual-row logic-analyzer shrouded connector • 10-pin, 0.05" pitch, dual-row Packet Trace Port connector • 12-pin, 0.1” pitch, dual-row, data emulation interface (DEI) with configuration header • 14-pin, 0.05” pitch, single-row along with a 19-pin 0.05” pitch, single-row, board-to-board connector for the module • 16-pin, 0.1” pitch, single-row along with a 20-pin 0.1” pitch, single-row, board-to-board connector for the host module • Selection pins for DC power source selection (either external DC power supply, USB, Debug Adapter (ISA3), or AAA battery pack). LEDs indicate which power supply has been selected. • 2-pin module VDC pin for connection of an ammeter for EM5x module current measurements • 2-pin module VDC pin for connection of an ammeter for host module current measurements • 2-pin jumpers for each of the HW application peripherals, buzzer, buttons, piezo, temperature sensor, and LEDs • 2-pin jumpers for connection to TTL UART for either the EM35x UART (SC1) or host UART2. The selection jumpers route signals (RXD, TXD, nRTS, and nCTS) allow access to the TTL levels.

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Table 1 lists the DC electrical characteristics of the EM35x NCP Breakout Board.

Table 1. DC Electrical Characteristics Parameter Min. Typ. Max. Unit VDD supply External DC Supply (J1 / J32) 4 20 V USB Host 4.5 5 V Debug Adapter 3.1 3.3V 3.5 V Battery 2.1 3.6 External DC supply (J3.2) 3.1 3.3 3.5 V Current draw (peripherals) Piezo buzzer 10 mA Buttons (enabled) 6 mA Temperature sensor (enabled) 5 mA Current draw (miscellaneous) RS-232 transceiver 4 mA USB transceiver 15 mA LDO distribution 10 mA Operating temperature 0 + 55 C

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2 Components Figure 1 illustrates the components on layer 1 (top side).

Host Module Power NCP Module Power Isolation Jumper (J34) Isolation Jumper (J34)

Power Source ZigBee Application Selection Jumpers Peripherals EM35x Radio Module Connectors (X1: J21-J22) Power Source LEDs

DataFlash & Interface Connectors

USB Connector (J5) Packet Trace Port (J31)

Data Emulation TTL Access Jumpers Interface Selection (J25-J28) Header (J27)

Data Emulation Interface (J28)

SPI/UART Mode DB-9 Connector – Config Switch (SW1) RS-232 (J30)

Host Module Connectors (X2: J37-J38)

Prototype Area

Reset and Bootload Host Bootloader NCP Bootloader Enable Jumpers (EM6) and Reset (EM3) and Reset (J14, J16, J35, J40) (EM5) Buttons (EM4) Buttons Figure 1. Assembly Print for Layer 1

2.1 Power Supply and Distribution The EM35x NCP Breakout Board can be powered from one of five sources: • 4 V to 20 V External DC Power supply (Positive connected J1 and Ground connected to J32) • Battery pack connector (J8) • USB Host (J5, via Wall wart or PC connection) • Debug Adapter (ISA3) (through Packet Trace Port, J31) • 2.1 to 3.6 V External DC Power supply (Positive connected to J3.2 and Ground connected to J32)

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The EM35x NCP Breakout Board contains power source selection jumpers (J2 and J3) which allows only one DC source to power the board. This eliminates the possibility of overcurrent resulting from power supply contention. Table 2 illustrates the connection scheme and LED indication for each power source.

Table 2. Power Supply connections Power Source Selection Scheme (J2 and J3) LED Indicator

1 VPS High Voltage External VBATT supply (4 V to 20 V) VUSB VISA Connect VDD to J1 and GND J2 3 VISA to J32. VREG J3 VBAT

VPS 1 VBATT USB Host VUSB VISA Connect USB cable to J5. J2 3 VREG VISA J3 VBAT

VPS 1 VBATT Debug Adapterr (ISA3) VISA VUSB Connect Debug Adapter (ISA3) to J31. J2 3 VREG VISA J3 VBAT

VPS 1 Battery pack VBATT VUSB Connect AAA battery pack VISA (supplied by Silicon Labs) to J2 3 VISA J8. VREG J3 VBAT

VPS 1 Low Voltage External DC VBATT supply (3.1 to 3.5) VUSB VISA Connect directly to J3.2 with J2 3 VISA Ground connected to J32. VREG J3 VBAT

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2.1.1 External DC Power Supply (J1 and J32 or J3.2 and J32) The EM35x NCP Breakout Board allows two easy to use connections to an external power supply. • The first connection (Low Voltage) allows for a 3.1 to 3.5 V DC external supply to be connected to J3.2 (positive) and J32 (Ground). The power supply should be able to source up to 250 mA at the set voltage. When using a power supply in this mode, there should be no jumpers on J2 or J3 as shown in Table 2. • The second connection (High Voltage) allows for a 4 V to 20 V DC external supply to be connected to J1 (positive) and J32 (Ground). The power supply should be able to source up to 300 mA at the set voltage. When using a power supply in this mode, there should be a jumper connecting J3.3 and J3.2 as shown in Table 2.

2.1.2 Battery Connector (J8) The 2-pin, keyed battery connector (Hirose, P/N: DF13-2P-1.25H(50)) allows for connection to a DC power supply or battery pack. The EM35x NCP Breakout Board is shipped with a 2-AAA battery pack with appropriate mating connector for easy attachment. Batteries are sold separately. When using a battery pack, a jumper must be connected between J3.1 and J3.2 as shown in Table 2.

2.1.3 Packet Trace Port (J8) The EM35x NCP Breakout Board can also be powered from a Debug Adapter (ISA3). To enable this power supply, simply connect the Debug Adapter (ISA3) to the Packet Trace Port (J8) and connect the power selection jumper between J2 and J3.2 as shown in Table 2. In addition, the Debug Adapter (ISA3) selection toggle switch must be put in the INT. The Debug Adapter (ISA3) provides a target voltage of 3.3V and sources as much as 250 mA. See document TS7, Debug Adapter (ISA3) Technical Specification, for more details on the Debug Adapter (ISA3).

Note: If the Debug Adapter (ISA3) is connected directly to the Packet Trace Port on the Module, the jumpers at J4 and J34 must be connected as well as the jumper across J2 and J3.2.

2.1.4 USB Host (J5) The EM35x NCP Breakout Board can also be powered by a USB Host (PC or Silicon Labs-supplied USB power supply). To operate in this mode, a USB Host must be connected to J5 and the power selection jumper must be connected between J3.1 and J3.2 as shown in Table 2.

2.2 NCP Current Measurements To allow for NCP current measurements, the EM35x NCP Breakout Board isolates the NCP module VDD power supply from the regulated power domain on the Breakout Board. The only connection point between the NCP module power supply and the Breakout Board supply is through the V_NCP_EN header (J4). Remove J4 and place an ammeter across this jumper to measure the NCP current draw.

2.3 Host Current Measurements To allow for Host current measurements, the EM35x NCP Breakout Board isolates the Host module VDD power supply from the regulated power domain on the Breakout Board. The only connection point between the Host module power supply and the Breakout Board supply is through the V_HOST_EN header (J34). Remove J34 and place an ammeter across this jumper to measure the Host current draw.

2.4 Deep Sleep Testing of the EM35x Module To perform accurate deep sleep measurements of the EM35x NCP, configure the EM35x NCP Breakout Board as follows: • Remove J4 and place ammeter across this jumper.

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• Remove J6 so the V_NCP LED DS4 is not driven. If supplying voltage through J8 battery connector, also remove J7 so the V_BATT LED DS5 is not driven. • Remove J33 jumpers to isolate DataFlash IC from circuit. • Issue "shutdown" in nodetest. • Once command is issued and node is asleep, remove J25-J28 (TTL jumpers). • Make sure the Packet Trace Port cable, DEI cable, and RS-232 cable are all detached from the Breakout Board. This connection scheme offers the highest degree of power supply flexibility. Wake the EM35x NCP from deep sleep by pressing the NCP reset button.

Note: The use of virtual UART port 4900 is not recommended when interfacing to nodetest for deep sleep testing, since this does not allow for proper configuration of the EM35x for deep sleep measurements. Therefore, please use either pass-through UART port 4901, USB, or RS-232 to interface to the nodetest application.

2.5 ZigBee Application Peripherals As previously mentioned, the EM35x NCP Breakout Board offers six host peripherals to assist in ZigBee application development including: • Temperature sensor • Two (2) “normally open” buttons • 4 kHz piezo buzzer • Two (2) LEDs • External DataFlash Each peripheral connects to a host GPIO through a two-pin peripheral header. Because each peripheral header on the EM35x NCP Breakout Board ships with a jumper in place, the peripherals default to “HW Enabled.” If application development does not require the peripheral, simply remove the jumper.

Note: Each peripheral consumes power. Be sure to factor this into the current consumption equations when testing the module in deep sleep mode or if using the battery pack to power the Breakout Board.

2.5.1 Temperature Sensor (U4) The temperature sensor is an off-the-shelf component from National Semiconductor (MFG P/N: LM20BIM7). The temperature sensor requires an enable signal to be asserted (active high) prior to generating an analog voltage proportional to the ambient temperature of the EM35x NCP Breakout Board. Therefore, two host GPIO signals, HGPIO7 and HGPIO8, are routed to pin 2 of peripheral headers J13 and J15, respectively. • HGPIO7 enables the temperature sensor when asserted (active high), when a jumper is installed at J13. • HGPIO8 contains the analog temperature information from the sensor, when it is enabled and a jumper is installed at J15. The temperature sensor output is scaled to between 0 and 1.2 V through a resistive voltage divider. If you want to connect a temperature sensor from a different manufacturer, scale the output in a similar manner. The EM35x NCP Breakout Board is shipped with a jumper installed at J13 and J15. If the jumpers are removed, a different compatible device can be attached to pin 2 of both J13 and J15. For more information on the temperature sensor, refer to its data sheet (http://www.ti.com/product/LM20).

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2.5.2 Buttons (EM1, EM2) Two programmable, normally-open buttons are provided for software debugging and application development. When either button is pressed, the connected net is driven low. A single-pole RC filter minimizes the effects of switching noise. These buttons map to the backchannel button commands as follows: • EM2: controlled by the button 0 command • EM1: controlled by the button 1 command For information about the button command, see document UG110, the EM35x Development Kit User Guide. Two host GPIO signals, HGPIO3 and HGPIO2, are routed from the EM35x Module to pin 2 of peripheral headers J9 and J10, respectively. In the default configuration of the EM35x NCP Breakout Board, jumpers are positioned across J9 and J10 to enable buttons EM1 and EM2, respectively. If the jumpers are removed, different compatible devices can be attached to pin 2 of breakout headers J9 and J10 instead of the buttons.

2.5.3 Buzzer (SPK1) A programmable buzzer is provided for software debugging and application development. A host GPIO signal, HGPIO4, is routed to pin 2 of peripheral header J17. In the default configuration of the EM35x NCP Breakout Board, a jumper is positioned across J17 to enable use of the buzzer. The buzzer installed on the EM35x NCP Breakout Board is from CUI (MFG P/N: CEP-1160). For more information on the buzzer, refer to its datasheet (http://www.cui.com/Product/Resource/PDFRedirect/110/CEP-1160.pdf).

2.5.4 LEDs (DS6 and DS7) The EM35x NCP Breakout Board contains two LEDs for software debugging and application development. Each LED is buffered (non-inverting) to allow for connection to any host GPIO. Two host GPIOs, HGPIO0 and HGPIO1, are routed to pin 2 of headers J12 and J11 respectively. To turn on DS7 (RED) from the host module, install a jumper at J12, configure HGPIO0 as an output and drive it low. To turn on DS6 (GREEN), install a jumper at J11, configure HGPIO1 as an output and drive it low.

2.5.5 External DataFlash (U7) The external DataFlash is an off-the-shelf component from Atmel (MFG P/N: AT45DB021D-SSH-B). The DataFlash is used in cases where ZigBee OTA Profile application bootloader is required for the host. The DataFlash is connected to the host module through jumper block J33. The EM35x NCP Breakout Board is shipped with jumpers installed in a disconnected state at J33. If all six jumpers are installed properly at J33, the external DataFlash connects to the host for application bootloading. Figure 2 illustrates the J33 jumper configuration for the DataFlash interface.

J33 DF_nSD HGPIO11 DF_SI HGPIO14 DF_SO HGPIO15 DF_SCK HGPIO13 DF_nCS HGPIO12 DF_3V 3V 2 1

Figure 2. Jumper for DataFlash connections

For more information on the DataFlash, refer to its datasheet (http://www.atmel.com/Images/doc3638.pdf).

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2.6 EZSP and Serial Mode Configuration Switch (SW1) To enhance the software development experience, the EM35x NCP Breakout Board allows for EZSP interfaces between the EM35x NCP and a host via both SPI and UART (either to the host module or an external host). A configuration switch (SW1) is used to set up EZSP mode and serial communication paths. Access to either the EM35x SC1 UART or host UART1 is available directly from the EM35x NCP Breakout Board or by telnetting into port 4901 of a Debug Adapter (ISA3) connected to an Ethernet network. On the EM35x NCP Breakout Board, it is available as RS-232, USB and TTL-compliant signal levels. To minimize current consumption and allow for the different configuration options, the EM35x NCP Breakout Board individually routes the TTL UART signals RXD, TXD nCTS, and nRTS to pin 2 of headers J25, J26, J27, and J28 respectively. To route the UART signals to the USB transceiver, move SW1 Serial to TTL and TTL Path to USB. To route the UART signals to the RS-232 transceiver, move SW1 Serial to TTL and TTL Path to 232. To access TTL signals, move SW1 Serial to TTL, remove the jumpers on J25, J26, J27 and J28 and connect to pin 2 of these jumpers. To route the UART signals to DEI, move SW1 Serial to DEI and place jumpers on the DEI jumper connector (J42) as summarized below and shown in Figure 3. • TXD: J27.1 to J27.2 • RXD: J27.5 to J27.6 • nRTS: J27.7 to J27.8 • nCTS: J27.9 to J27.10 Each SW1 configuration is shown in Table 3. TTL Access Jumper configuration is shown in Table 4.

Table 3. EZSP and Serial Configuration Switch UART Path Selection Scheme (J22, J25, J24, and J26) 1 2

RXD J25 TXD J26 nCTS J27 EZSP SPI Mode, Host UART2 to DEI nRTS J28

Connect Debug Adapter (ISA3) DEI SW1 cable to J31. EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

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UART Path Selection Scheme (J22, J25, J24, and J26) 1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP SPI Mode, Host UART2 to RS-

232 SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP SPI Mode, Host UART2 to USB SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP SPI Mode, Host UART2 to TTL SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

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UART Path Selection Scheme (J22, J25, J24, and J26) 1 2

RXD J25 TXD J26 J27 EZSP UART Mode to nCTS Host Module, Host J28 UART2 to DEI nRTS

Connect Debug Adapter (ISA3) DEI SW1 cable to J31. EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP UART Mode to Host Module, Host UART2 to RS-232 SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP UART Mode to Host Module, Host UART2 to USB SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

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UART Path Selection Scheme (J22, J25, J24, and J26) 1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP UART Mode to Host Module, Host UART2 to TTL SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

1 2

RXD J25 TXD J26 nCTS J27 EZSP UART Mode to External Host, NCP nRTS J28 UART to DEI

Connect DEI cable to J31. SW1 EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP UART Mode to External Host, NCP UART to RS-232 SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

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UART Path Selection Scheme (J22, J25, J24, and J26) 1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP UART Mode to External Host, NCP UART to USB SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

1 2

RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP UART Mode to External Host, NCP UART to TTL SW1

EZSP MODE: SPI UART UART HOST: MOD EXT SERIAL: DEI TTL TTL PATH: USB 232

Note: To connect to the UART through a Debug Adapter (ISA3), the Debug Adapter (ISA3) must be connected to an Ethernet connection. It can be accessed by issuing “Serial 1” within the Console view of the Ember Desktop or by telnetting to Port 4901.

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J42 HOST_BTL SW_UART_MOD_EN SW_SPI_EN HOST_nRESET HGPIO2 nCTS nRTS RXD HGPIO3 TXD 2 1

Figure 3. Jumper Settings Required for EM35x SC1 UART Access by Debug Adapter (ISA3)

Table 4. TTL Access Jumpers Configuration Selection Scheme (J25, J26, J27, and J28) 1 2

RXD J25

UART via USB or TXD J26 Serial nCTS J27 nRTS J28

1 2

RXD J25

UART via TTL TXD J26 Access nCTS J27 nRTS J28

2.7 Data Emulation Interface (J43) The 12-pin, dual-row, data emulation interface contains 4 host GPIO signals, 4 host or EM35x NCP UART signals, and 2 DEI control pins, as well as voltage (VBRD) and ground (GND) connections. When connected to the Debug Adapter (ISA3), the connector provides additional debug features to software developers. One feature involves the port 4901 UART connection through Debug Adapter (ISA3). To enable the UART connection to either the host or the EM35x NCP UART signals, configure SW1 for DEI mode as shown in Table 3 and install four jumpers on J42 as shown in Figure 3 for nCTS, nRTS, RXD, and TXD. Another feature involves manipulation of BUTTON0 and BUTTON1 GPIO signals. To enable GPIO manipulation of BUTTON0 and BUTTON1, install jumpers on J42 at HGPIO2 and HGPIO3, respectively.

2.8 EM35x Module Interface Connector (J21-J24) Two single-row, 0.05” pitch, connectors make up the EM35x module interface to the EM35x NCP Breakout Board. In addition, two single-row, guide connectors assist with connecting the EM35x module to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access to all EM35x GPIO as well as nRESET and the JCLK signals. The connector is illustrated in Figure 4, while the dimensions are shown in Figure 5.

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J21

GND 1

EM35x_PC5 2

EM35x_PC6 3

EM35x_PC7 4 NC NC

EM35x_PA7 5 J23 34 35

EM35x_PB3 6 33 GND

EM35x_nRESET 7 32 VDD_3V_EM35X J22 EM35x_PB4 8 31 GND

HOST_MOSI 9 30 EM35x_PB5

HOST_MISO 10 29 nWAKE

HOST_SCK 11 28 EM35x_PB7

HOST_nSS 12 27 EM35x_PC0

GND 13 26 EM35x_PC1

EM35x_PA4 14 25 nSIMRST

EM35x_PA5 15 24 EM35x_PC4

EM35x_PA6 16 23 EM35x_PC3

EM35x_PB1 17 22 EM35x_PC2

EM35x_PB2 18 21 EM35x_JCLK

GND 19 20 GND

J24 36 37

NC NC

Figure 4. Board-to-Board Connector for the EM35x Module

Figure 5. Board-to-Board Connector Dimensions for the EM35x Module

Table 5 describes the pinout and signal names at J21-J24. The EM35x UART1 signals (PB1, PB2, PB3, PB4) are exposed on the EM35x NCP Breakout Board at the 26-pin, dual row, 0.1” pitch GPIO connector (J41) for application development.

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Note: Custom EM35x modules (not shipped with development kits) containing external DataFlash should NOT be connected to the EM35x NCP Breakout Board, as the EM35x SPI1 is used for the EZSP SPI interface.

For more information on the alternate functions of the GPIO connector, refer to document 120-035X-000, the EM351/7 Data Sheet.

Table 5. Pinout and Signal Names of the NCP Interface Connector Pin # Signal name Direction2 Connector Description 1 GND Power J21 Ground Connection 2 PC5 I/O J21 EM35x GPIO 3 PC6 I/O J21 EM35x GPIO 4 PC7 I/O J21 EM35x GPIO 5 PA7 I/O J21 EM35x GPIO 6 PB3 I/O J21 EM35x GPIO 7 nRESET I/O J21 Active low chip reset (internal pull-up on EM35x) 8 PB4 I/O J21 EM35x GPIO 9 PA0 I/O J21 EM35x GPIO 10 PA1 I/O J21 EM35x GPIO 11 PA2 I/O J21 EM35x GPIO 12 PA3 I/O J21 EM35x GPIO 13 GND Power J21 Ground connection 14 PA4 I/O J21 EM35x GPIO 15 PA5 I/O J21 EM35x GPIO 16 PA6 I/O J21 EM35x GPIO 17 PB1 I/O J21 EM35x GPIO 18 PB2 I/O J21 EM35x GPIO 19 GND Power J21 Ground connection 20 GND Power J22 Ground connection 21 JCLK Input J22 JTAG interface, serial clock 22 PC2 I/O J22 EM35x GPIO 23 PC3 I/O J22 EM35x GPIO 24 PC4 I/O J22 EM35x GPIO 25 PB0 I/O J22 EM35x GPIO 26 PC1 I/O J22 EM35x GPIO 27 PC0 I/O J22 EM35x GPIO 28 PB7 I/O J22 EM35x GPIO 29 PB6 I/O J22 EM35x GPIO 30 PB5 I/O J22 EM35x GPIO 31 GND Power J22 Ground connection 32 VDD Power J22 2.1 to 3.6V Module Power Domain 33 GND Power J22 Ground connection 34 NC N/A J23 Not connected; guide pin 35 NC N/A J23 Not connected; guide pin

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Pin # Signal name Direction2 Connector Description 36 NC N/A J24 Not connected; guide pin 37 NC N/A J24 Not connected; guide pin 2 with respect to the RCM

2.9 Host Module interface connector (J37-J38) Two single-row, 0.1” pitch, connectors make up the host module interface to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access to 16 host GPIO. The connector is illustrated in Figure 6, while the dimensions are shown in Figure 7.

J38 VDD_3V_HOST 17

J37 EZSP_UART2_nRTS 18 1 HGPIO10 EZSP_UART2_nCTS 19

2 HGPIO11 EZSP_UART2_RXD 20

3 HGPIO0 EZSP_UART2_TXD 21

4 HGPIO1 HGPIO7 22

5 HOST_nRESET HGPIO6 23

6 HGPIO8 HGPIO5 24

7 HGPIO9 HGPIO4 25

8 SER_UART1_nCTS HGPIO15 26

9 SER_UART1_nRTS HGPIO14 27

10 SER_UART1_TXD HGPIO13 28

11 SER_UART1_RXD HGPIO12 29

12 HOST_nSS HGPIO3 30

13 HOST_SCK HGPIO2 31

14 HOST_MISO HOST_BTL 32

15 HOST_MOSI NCP_nRESET 33

16 nHOST_INT nWAKE 34

N/C 35

GND 36

Figure 6. Board-to-Board Connector for the Host Module

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Figure 7. Board-to-Board Connector Dimensions for the Host Module

Table 6 describes the pinout and signal names at both J37 and J38. 16 host GPIOs are exposed on the EM35x NCP Breakout Board at the 26-pin, dual row, 0.1” pitch GPIO connector (J41) for application development. For more information on the alternate functions of the GPIO connector, refer to the data sheet for the host microprocessor included on the host module.

Table 6. Pinout and Signal Names of the Host Interface Connector Pin # Signal name Direction2 Connector Description 1 HGPIO10 I/O J37 Spare Host GPIO 2 HGPIO11 I/O J37 DataFlash Shutdown (DF_nSD) 3 HGPIO0 I/O J37 Application LED (LED0) 4 HGPIO1 I/O J37 Application LED (LED1) 5 HOST_nRESET I/O J37 Active low host reset Temperature Sensor ADC 6 HGPIO8 I/O J37 (TEMP_SENSOR) 7 HGPIO9 I/O J37 Spare Host GPIO 8 SER_UART1_nCTS I/O J37 Host UART1 Clear to Send 9 SER_UART1_nRTS I/O J37 Host UART1 Ready to Send 10 SER_UART1_TXD I/O J37 Host UART1 Transmit Data 11 SER_UART1_RXD I/O J37 Host UART1 Receive Data 12 HOST_nSS I/O J37 EZSP SPI Slave Select 13 HOST_SCK I/O J37 EZSP SPI Clock 14 HOST_MISO I/O J37 EZSP Master In-Slave Out 15 HOST_MOSI I/O J37 EZSP Master Out-Slave In 16 nHOST_INT I/O J37 EZSP Host Interrupt 17 VDD_3V_HOST Power J38 3.3V Connection 18 EZSP_UART2_nRTS I/O J38 EZSP UART Ready to Send 19 EZSP_UART2_nCTS I/O J38 EZSP UART Clear to Send

Rev. 0.6 19 TS9

Pin # Signal name Direction2 Connector Description 20 EZSP_UART2_RXD I/O J38 EZSP UART Receive Data 21 EZSP_UART2_TXD I/O J38 EZSP UART Transmit Data Temperature Sensor Enable 22 HGPIO7 I/O J38 (TEMP_ENABLE) 23 HGPIO6 I/O J38 Spare Host GPIO 24 HGPIO5 I/O J38 Spare Host GPIO 25 HGPIO4 I/O J38 Application Speaker (PIEZO) 26 HGPIO15 I/O J38 DataFlash SPI Serial Out (DF_SO) 27 HGPIO14 I/O J38 DataFlash SPI Serial In (DF_SI) 28 HGPIO13 I/O J38 DataFlash SPI Clock (DF_SCK) 29 HGPIO12 I/O J38 DataFlash SPI Chip Select (DF_nSS) 30 HGPIO3 I/O J38 Application Button (BUTTON1) 31 HGPIO2 I/O J38 Application Button (BUTTON0) 32 HOST_BTL I/O J38 Host Bootloader 33 NCP_nRESET I/O J38 Active low NCP reset 34 nWAKE I/O J38 EZSP SPI Wake 35 NC N/A J38 Not connected 36 GND Power J38 Ground connection 2 with respect to the host

2.10 Prototyping Area The 1.6" x 1.8" (0.1” pitch) prototyping area on the EM35x NCP Breakout Board offers software developers an extra degree of flexibility. As shown in Figure 4, it allows access to VBRD, GND, and 16 host GPIOs. Therefore, you can solder any sensor or input device to the prototyping area and connect it to the host GPIO for development and debugging. As shown in Figure 8, the leftmost column is connected to GND and the rightmost column to VBRD. The top row is connected to the host GPIOs. Included in the top row are additional GND and JCLK connections. The remainder of the array is available for application development.

20 Rev. 0.6 TS9 4 5 8 9 12 13 1 2 3 7 10 11 6 14 15 0 HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO HGPIO VBRD HGPIO HGPIO HGPIO GND

Figure 8. EM35x NCP Breakout Board prototyping area

3 EM35x NCP Breakout Board Schematic The EM35x NCP Breakout Board schematic is included at the end of this document.

Rev. 0.6 21 4 3 2 1

B B EM35X NCP Breakout Board

Sheet Details 1 COVER SHEET 2 POWER MANAGEMENT, MANUFACTURING 3 APPLICATIONS CIRCUITS, BREADBOARD 4 EM35X RCM CONNECTORS, USER INTERFACES 5 HOST MODULE CONNECTOR, INTERFACES 6 SPI/UART MUX/DEMUX CIRCUIT 7 SPI/UART BLOCK DIAGRAM 8 REVISION NOTES

A A

Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.silabs.com DWG SCH0681 REV A0 TITLE EM35X NCP BREAKOUT BOARD PAGE COVER SHEET

The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation

SIZE B DATE: 19-09-2010_22:13 SHEET: 1 of 8 4 3 2 1 4 3 2 1 POWER SUPPLY, DC, 4V to 20V * Place J1 close to J31 USB / VIN_PWR_JACK Down Conversion Breakout Board and Module Power Selector Headers J2 and J3 allow the user to select the power source. There are five possible power sources for the Breakout board. VIN_PWR_SUPPLY 1. External 3V Supply (Connect directly to J3.2) J1 2. External Regulated supply from 4V to 20V (Connect shorting jumper between J3 pins 2.3) TEST_POINT D1 3. Ember battery pack with 2 AAA (Connect shorting jumper between J3 pins 1.2) 1 VIN_PWR_SUPPLY BAT54C VDD_3V 2. USB Bus Powered (Connect shorting jumper between J3 pins 2.3) U1 4. Debug Adapter (Connect shorting jumper between J2 and J3.2) 1 LT1763CS8-3.3#PBF R1 J32 C1 Datasheet 0_Ohm TEST_POINT 330NF VIN_USB 3 VREGIN 8 1 VOUT_SENSE

L4P IN 7 OUT 2 VIN_BATT VDD_ISA VDD_3V VDD_3V_BB 1 GND-3 SENSE 2 C2 VDD_3V_EM35X 6 3 10NF J2 J3 5 GND-2 GND-1 4 BYPASS C3 HEADER-1 HEADER-3 J4 NSHDN BYP 10uF 1 HEADER-2 3 C30 20V MAX IN, 2 1 2 1uF 3V/500mA OUT 1

BATTERY INTERFACE The shorting jumper at J4 can be replaced with a VDD_3V_HOST current meter to measure EM35x module current draw Kit Provide Battery Pack for 2 AAAs, voltage range 1.5V to 3.1V J34 B HEADER-2 B EM35x IC will not operate properly at voltages below 1.8V 1 2 D2 J8 BAT54C VIN_BATT DF13-2P-1.25H(50) 1 BATTERY_IN 1 The shorting jumper at J34 can be replaced with a 2 current meter to measure Host module current draw C7 3 220NF L4P 2 NC Power Indicator LEDs

* Remove J67 when performing * Remove J6, J36 when performing a Deep Sleep Test a Deep Sleep Test with Battery USB CONNECTION (TYPE B) 5V VIN_BATT VIN_USB VDD_ISA VIN_PWR_SUPPLY VDD_3V_EM35X VDD_3V_HOST

VIN_USB J6 J36 J7 DS2 DS3 DS1 HEADER-2 HEADER-2 HEADER-2 RED RED RED FB1

USB_DM 1 2 1 2 BLM18PG600SN1D 1 2 U2 C4 J5 NUP2301MW6T1G 2 47PF USB-B-RA R3 R4 R2 DS4 DS8 S1 VIN_USB DS5 1.0K 510 2.2K GREEN GREEN SHIELD1 1 VBUS RED VBUS 2 D- 3 1 3 D+ 4 GND S2 C6 R5 R39 SHIELD2 R6 510 510

10NF 5 Datasheet 510 USB_DP

C5 47PF

A PCB Information Fiducials A Shorting Jumpers PCB1 ESD Suppression (Power Supply) 710-0681-000 FID1 FID2 FID3 Place shorting jumpers across the following connector pins; VIN_PWR_SUPPLY Test Equipment GND Connection VIN_USB J2 and J3.2 J33.2 SN1 D3 J4 J33.4 130-0681-000 GSOT15C-GS08 J6 J33.6 J29 is placed close to J41 Datasheet J7 J33.8 J29 1 2 J9 J33.10 HEADER-2 J10 J33.12 J11 J34 SHORTING Silicon Labs, 25 Thomson Place, Boston, MA 02210 2 1 3 J12 J35 TEL: 617-951-0200, FAX: 617-951-0999 J13 J36 JUMPER X 35 www.silabs.com J14 J39.1 DWG REV J15 J40 SCH0681 A0 VIN_BATT J16 J42.1 and J42.2 TITLE D4 J17 J42.3 and J42.4 EM35X NCP BREAKOUT BOARD GSOT12C-GS08 J25 J42.5 and J42.6 PAGE Datasheet J26 J42.7 and J42.8 POWER MANAGEMENT, MANUFACTURING 1 2 J27 J42.9 and J42.10 The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this NC J28 J42.11 and J42.12 document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is J42.13 and J42.14 the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise

3 used without the express permission of Ember Corporation

SIZE B DATE: 19-09-2010_22:20 SHEET: 2 of 8 4 3 2 1 4 3 2 1 Host Application LEDs VDD_3V_BB Host Application Buttons

Buttons

C9 C8 J9 R9 EM1 VDD_3V_BB 100nF 100nF HEADER-2 1.0K B3S-1000 HGPIO3 2 1 BUTTON1 EM1 1 3

2 4 C10 R7 R8 U3 SN74LVC2G07DBVR 100nF 100K 100K SN74LVC2G07DBVR 5 Datasheet VDD_3V_BB J10 R12 EM2 J11 R10 DS6 HEADER-2 1.0K B3S-1000 VCC HEADER-2 510 GREEN HGPIO2 2 1 BUTTON0 EM2 1 3 HGPIO1 2 1 LED1 1 6 LED_1 DS6 IN1 OUT1 2 4 C11 HGPIO0 2 1 LED0 3 4 LED_0 DS7 100nF IN2 OUT2 J12 R11 HEADER-2 510 DS7 RED GND

B 2 B

EM35x RESET Button (Active Low)

Host Temperature Sensor D5 BAT54AWT-TP EM35x Reset Selection J15 R15 HEADER-2 100K HGPIO8 2 1 TEMP_SENSOR TEMP_SENSE MUX_nRESET 1 J16 HEADER-2 R33 DNI nSIMRST EM4 R17 3 EM35X_nRESET_BUTTON 2 1 EM35X_nRESET_SRC B3S-1000 1.0K R32 0_Ohm EM35X_nRESET J13 U4 R13 1 3 EM4 2 HEADER-2 LM20BIM7/NOPB 0_Ohm HGPIO7 2 1 TEMP_ENABLE VO 2 4 4 V+ VO 3

C12 GND1 R16 100nF 2 C13 100K NC DNI 5 GND2 NC 1

Datasheet LM20BIM7/NOPB

EM35x Bootloader Button (Active Low) Host RESET Button (Active Low)

SPK1 Host Piezo Speaker CEP-1160 Datasheet EM3 R14 J14 EM5 R31 J35 J17 B3S-1000 1.0K HEADER-2 B3S-1000 1.0K HEADER-2 HEADER-2 1 3 EM3 2 1 EM35X_PA5 1 3 EM5 2 1 HOST_nRESET HGPIO4 2 1 PIEZO 1 V+ 2 2 4 2 4 V-

Host Bootloader Button (Active Low) Peripheral Scratch Pad (0.1" pitch) A A VDD_3V_BB 26-Pin, Dual Row Test Connector EM6 R34 J40 J19 J18 15x16_PIN_BREADBOARD_AREA J20 B3S-1000 1.0K HEADER-2 DNI DNI DNI 1 3 EM6 2 1 HOST_BTL 1 HGPIO0 1 1 2 HGPIO1 2 2 J41 2 4 3 HGPIO2 3 3 S-HEADER-26 4 HGPIO3 4 4 HGPIO0 1 2 HGPIO1 5 HGPIO4 5 5 HGPIO2 3 4 HGPIO3 6 HGPIO5 6 6 HGPIO4 5 6 HGPIO5 7 HGPIO6 7 7 HGPIO6 7 8 HGPIO7 8 HGPIO7 8 8 HGPIO8 9 10 HGPIO9 9 HGPIO8 9 9 HGPIO10 11 12 HGPIO11 HGPIO9 HGPIO12 13 14 HGPIO13 Silicon Labs, 25 Thomson Place, Boston, MA 02210 10 10 10 TEL: 617-951-0200, FAX: 617-951-0999 11 HGPIO10 11 11 HGPIO14 15 16 HGPIO15 www.silabs.com 12 HGPIO11 12 12 HOST_MOSI 17 18 HOST_MISO 13 HGPIO12 13 13 HOST_SCK 19 20 HOST_nSS DWG REV 14 HGPIO13 14 14 EM35X_PB1 21 22 EM35X_PB2 SCH0681 A0 15 HGPIO14 15 15 EM35X_PB3 23 24 EM35X_PB4 TITLE 16 HGPIO15 16 16 nWAKE 25 26 EM35X NCP BREAKOUT BOARD X3 PAGE APPLICATIONS CIRCUITS, BREADBOARD

SIZE B DATE: 19-09-2010_22:13 SHEET: 3 of 8 4 3 2 1 4 3 2 1

EM3XX RCM Interface Header USB / UART IC VIN_USB VCC30 U5 USB IC Decoupling FTDi GPIO Test Points FT232RQ_R X1 Datasheet VIN_USB

RCM_INTERFACE NC NC 1 VCC30 VCCIO 19 30 FTDI_TXD CBUS3 TP1 VCC TXD 34 35 J21 2 FTDI_RXD C15 C14 CBUS2 TP2 RXD HEADER-19 J23 DNI USB_DM 15 C16 4.7UF 100nF USBDM Datasheet VDD_3V_EM35X 32 FTDI_NRTS 100nF CBUS4 TP3 RTS# 1 USB_DP 14 USBDP EM35X_PC5 2 J22 8 FTDI_NCTS NDCD TP4 CTS# EM35X_PC6 3 HEADER-14 NC EM35X_PC7 4 Datasheet 5 31 NDTR NDSR TP5 NC NC-6 DTR# EM35X_PA7 5 33 12 NC NC-5 EM35X_PB3 6 32 13 6 NDSR NRI TP6 NC NC-1 DSR# EM35X_nRESET 7 31 25 NC NC-4 EM35X_PB4 8 30 EM35X_PB5 VCC30 29 7 NDCD U5 CBUS0 TP7 NC-3 DCD# HOST_MOSI 9 29 nWAKE FT232RQ_R HOST_MISO 10 28 EM35X_PB7 3 NRI 5 via grid for U5 PCB Footprint CBUS1 TP8 RI# HOST_SCK 11 27 EM35X_PC0 18 RESET# HOST_nSS 12 26 EM35X_PC1 NDTR TP9 NC 13 25 nSIMRST 23 22 CBUS0 GND-5 B NC NC-2 CBUS0 GND-6 GND-7 GND-8 GND-9 B EM35X_PA4 14 24 EM35X_PC4 27 21 CBUS1 T491A475K020AT NC OSC1 CBUS1 EM35X_PA5 15 23 EM35X_PC3 28 10 CBUS2 OSC2 CBUS2 EM35X_PA6 16 22 EM35X_PC2 11 CBUS3 CBUS3

EM35X_PB1 17 21 EM35X_JCLK 16 9 CBUS4 34 35 36 37 38 3V3OUT CBUS4 EM35X_PB2 18 20 19 C17 J24 DNI 100nF AGND GND-2 GND-1 GND-3 GND-4 TEST 37 36 4 24 33 17 20 26 NC NC VALUE

TTL to RS-232 Transceiver TTL Signal Access EM35x GPIO Header EM35x Packet Trace Port VDD_3V_BB FROM DEI/TTL MUX <------> TO USB/232 MUX Access to unused EM35x GPIO Datasheet C18 10NF J31 VDD_3V_BB VDD_3V_BB FTSH-105-01-F-DV-K U6 J25 J44 LTC1386CS#PBF HEADER-2 J30

(Target Power) 1 16 TTL_RXD 2 1 SERIAL_RXD EM35X_PA6 1 EM35X_PC2 2 1 2 C19 100nF RECEPTACLE_DB9 1 (JTDO/SWO) C1+ V+ EM35X_PA7 2 (nJRST) EM35X_PC0 3 R18 R19 C20 100nF 3 2 C1- VCC EM35X_PB5 3 EM35X_PC3 4 100K 100K NC 1 J26 3 (JTDI) 1 EM35X_PB7 4 5 C21 100nF 4 6 C22 100nF NC 6 HEADER-2 4 C2+ V- 6 EM35X_PC1 5 EM35X_JCLK 6 5 2 TTL_TXD 2 1 SERIAL_TXD 5 (JTCK/SWCLK) C2- 2 EM35X_PC5 6 EM35X_PC4 7 7 6 (JTMS/SWDIO) 7 EM35X_PC6 7 EM35X_nRESET 8 RS232_TXD 11 14 DB9_TXD 3 7 (nRESET) TR1_IN TR1_OUT 3 EM35X_PC7 8 EM35X_PA4 9 RS232_nRTS 10 7 DB9_nRTS 8 J27 8 (Packet Trace Frame) TR2_IN TR2_OUT 8 (Packet Trace Data) EM35X_PA5 10 NC 4 4 HEADER-2 RS232_RXD 12 13 DB9_RXD NC 9 TTL_nCTS 2 1 SERIAL_nCTS RX1_OUT RX1_IN 9 DNI RS232_nCTS 9 8 DB9_nCTS 5 RX2_OUT RX2_IN 5 15 GND J28 HEADER-2 Datasheet TTL_nRTS 2 1 SERIAL_nRTS

VDD_3V_BB A A Configuration Mode Enable Switches

DS10 DS11 DNI DNI

VDD_3V_BB

SPI_EN R36 R37 UART_MOD_EN DNI DNI R22 R23 R24 R25 Silicon Labs, 25 Thomson Place, Boston, MA 02210 10K 10K 10K 10K TEL: 617-951-0200, FAX: 617-951-0999 SW1 www. ADE0404 silabs.com Datasheet DWG REV SW_SPI_EN R29 DNI R26 0_Ohm HW_SPI_EN 1 8 SCH0681 A0 SW_UART_MOD_EN R30 DNI R27 0_Ohm HW_UART_MOD_EN 2 7 TITLE DEI_EN 3 6 EM35X NCP BREAKOUT BOARD USB_EN 4 5 PAGE EM35X RCM CONNECTORS, USER INTERFACES

The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is Software/Hardware Enable the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation

SIZE B DATE: 19-09-2010_22:13 SHEET: 4 of 8 4 3 2 1 4 3 2 1

Host DEI Host Module Interface Headers Host Module Application Peripheral GPIO Mapping

VDD_3V_BB J43 S-HEADER-12 1 2 DEI_TXD X2 DEI_BUTTON1 3 4 DEI_RXD HOST_INTERFACE VDD_3V_HOST DEI_nRTS 5 6 DEI_nCTS HOST NET NAME GPIO FUNCTION DEI_BUTTON0 7 8 DEI_HOST_nRESET DEI_SW_SPI_EN 9 10 DEI_SW_UART_MOD_EN J38 DEI_HOST_BTL 11 12 SOCKET-20 HGPIO0 Application LED (LED0) J37 Datasheet SOCKET-16 17 HGPIO1 Application LED (LED1) Datasheet 18 EZSP_UART2_nRTS HGPIO10 1 19 EZSP_UART2_nCTS HGPIO2 Application Button (BUTTON0) HGPIO11 2 20 EZSP_UART2_RXD HGPIO0 3 21 EZSP_UART2_TXD HGPIO3 Application Button (BUTTON1) HGPIO1 4 22 HGPIO7 HOST_nRESET 5 23 HGPIO6 HGPIO4 Application Speaker (PIEZO) HGPIO8 6 24 HGPIO5 B HGPIO9 7 25 HGPIO4 HGPIO5 Spare GPIO B SER_UART1_nCTS 8 26 HGPIO15 Host DEI Jumpers SER_UART1_nRTS 9 27 HGPIO14 HGPIO6 Spare GPIO Should be placed near J43 SER_UART1_TXD 10 28 HGPIO13 SER_UART1_RXD 11 29 HGPIO12 HGPIO7 Temperature Sensor Enable (TEMP_ENABLE) HOST_nSS 12 30 HGPIO3 J42 HOST_SCK 13 31 HGPIO2 HGPIO8 Temperature Sensor ADC (TEMP_SENSOR) Header-20 HOST_MISO 14 32 HOST_BTL DEI_TXD 1 2 DEI_TXD_JMP HOST_MOSI 15 33 NCP_nRESET HGPIO9 Spare GPIO DEI_BUTTON1 3 4 HGPIO3 nHOST_INT 16 34 nWAKE DEI_RXD 5 6 DEI_RXD_JMP 35 NC HGPIO10 Spare GPIO DEI_nRTS 7 8 DEI_nRTS_JMP 36 DEI_nCTS 9 10 DEI_nCTS_JMP HGPIO11 DataFlash Shutdown (DF_nSD) DEI_BUTTON0 11 12 HGPIO2 DEI_HOST_nRESET 13 14 HOST_nRESET HGPIO12 DataFlash SPI Chip Select (DF_nCS) DEI_SW_SPI_EN 15 16 SW_SPI_EN DEI_SW_UART_MOD_EN 17 18 SW_UART_MOD_EN J37p35 - NC, available for later use HGPIO13 DataFlash SPI Clock (DF_SCK) DEI_HOST_BTL 19 20 HOST_BTL HGPIO14 DataFlash SPI Serial In (DF_SI)

HGPIO15 DataFlash SPI Serial Out (DF_SO)

DataFlash (SPI Interface with Host)

Voltage range of the AT45DB021D is 2.7V to 3.6V Radio Modules which are expected to operate at voltages below 2.7V will require a DC to DC up-converter supply source for the AT45DB021D Input data on SI is always latched on the rising edge of SCK Output data on SO is always clocked out on the falling edge of SCK

VDD_3V_DF

C23 U7 10NF VDD_3V_HOST J33 VDD_3V_DF VDD_3V_DF AT45DB021D-SSH-B Header-12 Datasheet 1 2 DF_SI 1 8 DF_SO HGPIO12 DF_nCS SI SO 3 4 R20 DF_SCK 2 7 NDS355N HGPIO13 DF_SCK SCK GND 5 6 A DF_nRESET 3 6 HGPIO15 DF_SO A nRESET VCC 7 8 0_Ohm DF_nCS 4 5 HGPIO14 DF_SI nCS nWP 9 10 VDD_3V_DF 3 HGPIO11 11 12 DF_nSD R21 R35 DF_nWP DNI 1 0_Ohm DF_nSD 2 R28 Q1 100K NDS355N

Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.silabs.com DWG SCH0681 REV A0 TITLE EM35X NCP BREAKOUT BOARD PAGE HOST MODULE CONNECTORS, INTERFACES

SIZE B DATE: 19-09-2010_22:13 SHEET: 5 of 8 4 3 2 1 4 3 2 1 SPI/UART Multiplexer/Demultiplexer Circuit

VDD_3V_BB

C24 100nF VDD_3V_BB VDD_3V_BB

U8 CD74HC4053M

16 Datasheet 12 EM35X_PB2_UART C25 C26 EM35X_PB2 14 X0 13 nHOST_INT 100nF 100nF

X VCC X1 2 U9 U10 15 Y0 1 EZSP_UART2_TXD CD74HC4053M CD74HC4053M

Y Y1 16 Datasheet 16 Datasheet 5 12 SERIAL_RXD 12 RS232_nCTS 4 Z0 3 SER_UART1_RXD RXD 14 X0 13 DEI_RXD_JMP TTL_nCTS 14 X0 13 FTDI_nRTS

Z Z1 X VCC X1 X VCC X1 11 SPI_EN 2 RS232_RXD 2 RS232_nRTS B 7 A 10 AorB TTL_RXD 15 Y0 1 FTDI_TXD TTL_nRTS 15 Y0 1 FTDI_nCTS B 6 VEE B 9 Y Y1 Y Y1 J39 nEN C

GND 5 RS232_TXD 5 NDTR_MUX HEADER-2 NDTR TTL_TXD 4 Z0 3 FTDI_RXD MUX_nRESET 4 Z0 3 NCP_nRESET 1 2 Z Z1 Z Z1 8 11 DEI_EN 11 USB_EN 7 A 10 USB_EN 7 A 10 6 VEE B 9 6 VEE B 9 SPI_EN nEN C nEN C GND GND 8 8

VDD_3V_BB VDD_3V_BB VDD_3V_BB

C27 C28 C29 100nF 100nF 100nF

U11 U12 U13 CD74HC4053M CD74HC4053M CD74HC4053M

16 Datasheet 16 Datasheet 16 Datasheet 12 12 12 EM35X_PB1 14 X0 13 EZSP_UART2_RXD EM35X_PB3 14 X0 13 EZSP_UART2_nRTS EM35X_PB4 14 X0 13 EZSP_UART2_nCTS

X VCC X1 X VCC X1 X VCC X1 2 2 2 TXD 15 Y0 1 SER_UART1_TXD nCTS 15 Y0 1 SER_UART1_nCTS nRTS 15 Y0 1 SER_UART1_nRTS Y Y1 Y Y1 Y Y1 5 SERIAL_TXD 5 SERIAL_nCTS 5 SERIAL_nRTS 4 Z0 3 DEI_TXD_JMP 4 Z0 3 DEI_nCTS_JMP 4 Z0 3 DEI_nRTS_JMP Z Z1 Z Z1 Z Z1 11 AorB 11 AorB 11 AorB 7 A 10 7 A 10 7 A 10 6 VEE B 9 DEI_EN 6 VEE B 9 DEI_EN 6 VEE B 9 DEI_EN nEN C nEN C nEN C GND GND GND 8 8 8

A A

SPI_EN (A) or UART_MOD_EN (B)

U14 74LX1G32STR Silicon Labs, 25 Thomson Place, Boston, MA 02210 Datasheet VDD_3V_BB TEL: 617-951-0200, FAX: 617-951-0999 www.silabs.com SPI_EN 1 5 DWG REV 1A VCC SCH0681 A0 UART_MOD_EN 2 TITLE 1B EM35X NCP BREAKOUT BOARD 3 4 AorB GND 1Y PAGE SPI/UART MUX/DEMUX CIRCUIT

SIZE B DATE: 19-09-2010_22:13 SHEET: 6 of 8 4 3 2 1 4 3 2 1

SPI_EN (A) || UART_MOD_EN (B) EM35X_PB1 (TXD) 0 EM35X_PB2 (RXD)

UART EM35X_PB3 (nCTS) 1 EM35X_PB4 (nRTS)

EM35X_PA0 (MOSI) EM35X EM35X_PA1 (MISO) B EM35X_PA2 (SCLK) B EM35X_PA3 (nSSEL)

SPI EM35X_PB0 (nSIMRST) EM35X_PB2 (nHOST_INT) EM35X_PB6 (nWAKE) DEI_TXD SPI_EN (A) || DEI_EN DEI_RXD UART_MOD_EN (B) DEI_nCTS DEI_nRTS TXD 1 MOSI 0 RXD MISO nCTS SCK 1 nRTS 0 TTL_TXD nSS SPI TTL_RXD nHOST_INT TTL_nCTS nWAKE TTL_nRTS NCP_nRESET

USB_EN FTDI_RXD TTL signal access FTDI_TXD EZSP_UART2_RXD by pulling 4 jumpers FTDI_nRTS EZSP_UART2_TXD SERIAL_TXD 1 J25, J26,J27,J28 FTDI_nCTS HOST EZSP_UART2_nRTS SERIAL_RXD EZSP_UART2_nCTS SERIAL_nCTS SERIAL_nRTS 0 RS232_TXD RS232_RXD A RS232_nCTS A UART RS232_nRTS SER_UART1_TXD SER_UART1_RXD SER_UART1_nCTS SER_UART1_nRTS Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.silabs.com DWG SCH0681 REV A0 TITLE EM35X NCP BREAKOUT BOARD PAGE SPI/UART BLOCK DIAGRAM

SIZE B DATE: 19-09-2010_22:13 SHEET: 7 of 8 4 3 2 1 2 1 SCHEMATIC NOTES: PCB LAYOUT NOTES: -- Version P0 -- -- Version P0 -- *Released: 2010-06-11 *Released: 2010-06-11 *Initial version released, Version P0 (initial draft) *Initial version released, Version P0 (initial draft)

-- Version A0 -- -- Version A0 -- *Released: 2010-09-20 *Released: 2010-09-20 *Production version release *Production version release *Changes from P0 to A0: *Changes from P0 to A0: 1) Swapped UART1 nets with UART2 nets based on changes for UART1 STM32 BTL. 1) Schematic changes reflected in layout. 2) Renamed UART1 nets to SER_UART1_TXD, etc. 2) Corrected J41p15 SST error (was HGPIO1 instead of HGPIO14). 3) Renamed UART2 nets to EZSP_UART1_TXD, etc. 3) Added pin1 marking for U7 SST. 4) Updated sheet 7 chart for UART changes. 4) Corrected board outline dimensioning error. 5) Added SJ34-35 for J7 and J33.12. 5) Added bump-on outlines in SSB and ASB. 6) Removed SW_DEI_EN and DEI_SW_DEI_EN (DS9, R28, R35, R38). 6) Corrected D5 decal error (was SOT23 instead of SOT323). 7) Updated J43p11 from DEI_SW_DEI_EN to DEI_HOST_BTL. 7) Updated LED0603 decal with Cathode C marking. 8) Updated J42p19/20 from DEI_EN to HOST_BTL. 8) Test point coverage for nets without probe access. B 9) Symbol clean-up for using PART_NUMBER rather than Manufacturer P/N. B 10) Replaced 570_0603_100 with _101, and _400 with _401. 11) Added Q1 shutdown transistor circuit for DataFlash. 12) Changed title block text from EZSP to NCP to reflect product name. 13) Corrected 500_4053_001 symbol due to error with Ember P/N (-000 instead of -001). 14) Added 1uF cap to input of regulator U1. 15) Changed C3 from 554-106A-016 (ESR 7 ohm) to 554-106A-020 (ESR 1 ohm).

A A

Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.silabs.com DWG SCH0681 REV A0 TITLE EM35X NCP BREAKOUT BOARD PAGE REVISION NOTES The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation

SIZE A DATE: 19-09-2010_22:13 SHEET: 8 of 8 2 1 TS9

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Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and Ember are registered trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

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