Engineering Applications of Fpgas Esteban Tlelo-Cuautle José De Jesús Rangel-Magdaleno Luis Gerardo De La Fraga

Engineering Applications of FPGAs Esteban Tlelo-Cuautle José de Jesús Rangel-Magdaleno Luis Gerardo de la Fraga

Engineering Applications of FPGAs Chaotic Systems, Artiﬁcial Neural Networks, Random Number Generators, and Secure Communication Systems

123 Esteban Tlelo-Cuautle Luis Gerardo de la Fraga INAOE Computer Science Department Tonantzintla, Puebla CINVESTAV-IPN Mexico Mexico City Mexico José de Jesús Rangel-Magdaleno Department of Electronics INAOE Tonantzintla, Puebla Mexico

ISBN 978-3-319-34113-2 ISBN 978-3-319-34115-6 (eBook) DOI 10.1007/978-3-319-34115-6

Library of Congress Control Number: 2016939064

© Springer International Publishing Switzerland 2016 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made.

Printed on acid-free paper

This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG Switzerland The authors want to dedicate this book to their families for the support provided during the preparation of this material. Preface

Field-programmable gate arrays (FPGAs) were invented in 1984 by Ross Freeman. Basically, it is a semiconductor consisting of programmable logic blocks that can be used to reproduce simple functions up to a complex system on a chip (SoC). The main advantages of the FPGAs are: they can be reprogrammed, have low development and acquisition costs, and their application is a good option if the product is not in high numbers. That way, FPGAs are gaining the attention of researches for the development of applications in a wide variety of fields, for example, medicine, communications, signal processing, avionics, space, finance, military, electronics, and other areas that exploit their flexibility and capability of being reprogrammed/configured. Configurability for engineering applications makes FPGA very crucial in initial stages for any embedded project. Some analog circuits and any digital circuit can be implemented using FPGA, so the possibilities are endless. However, applications found on recent articles and books did not detail the realizations from the model to the physical synthesis. That way, this book details engineering applications of FPGAs from mathematical models descriptions to VHDL programming issues and hardware implementation of applications involving chaos theory. The reader can find insights on FPGA-based implementations for chaos generators, artificial neural networks (ANNs), random number generators (RNGs), and master–slave synchronization of chaotic oscillators to implement a secure communication system for image transmission. The plus of this book is focused on providing VHDL programming guidelines and issues, along with co-simulation examples with Active-HDL and Simulink. In addition, we list some challenges on applying different kinds of numerical methods, problems on optimizing chaotic systems, selection of an ANN topology, its training, improvements on designing activation functions, data supply using serial communication with a computer, generation of random number generators from chaos theory, realization of chaotic secure communication systems, and other open problems for future research.

vii viii Preface

In summary, this book details FPGA realizations for: • Chaos generators, which are described from their mathematical models, are characterized by their maximum Lyapunov exponent, and are implemented using minimal FPGA resources. • Artiﬁcial neural networks (ANNs), discussing some topologies, different learning techniques, kinds of activation functions, and issues on choosing the length of the digital words being processed. One ANN topology is applied to chaotic time series prediction. • Random number generators (RNGs), which are designed using different chaos generators, in the continuous-time and discrete-time domains. The RNGs are characterized by their maximum Lyapunov exponent and entropy, and are evaluated through NIST tests. • Optimized chaotic oscillators are synchronized in a master–slave topology that is used to implement a secure communication system to process black and white, and grayscale images. Some chapters discuss computer arithmetic issues to minimize hardware resources and to reduce errors, before synthesizing the FPGA realization. At the end, the reader can infer open lines for future research not only in areas where chaos generators, ANNs, random number generators, and secure communications are required, but also to extend the presented material to other problems in engineering. Acknowledgments

The authors acknowledge the pretty good help of the graduate students at INAOE for preparing simulations and experiments. They are: Ana Dalia Pano-Azucena and Antonio de Jesus Quintas-Valles. Special acknowledgments to CONACyT-Mexico for funding support under projects 168357 and 237991.

ix Contents

1 Introduction to Field-Programmable Gate Arrays ...... 1 1.1 FPGA Architectures...... 1 1.2 Blocks Description ...... 2 1.2.1 Logic Blocks ...... 2 1.2.2 Lookup Tables (LUTs) ...... 5 1.2.3 I/O Blocks ...... 7 1.3 Programming Environments ...... 7 1.3.1 Vivado...... 7 1.3.2 Quartus II ...... 16 1.3.3 Aldec Active-HDL ...... 21 1.4 Computer Arithmetic ...... 26 1.4.1 Fixed Point Numbers...... 29 1.4.2 Operations with 2’ Complement Numbers ...... 30 1.4.3 Floating-Point Numbers ...... 31 2 VHDL...... 33 2.1 A Brief History of VHDL ...... 33 2.2 VHDL Structure ...... 33 2.3 Levels of Abstraction...... 36 2.3.1 Behavioral Description...... 36 2.3.2 Data Flow Description ...... 39 2.3.3 Structural Description ...... 42 2.4 Modules Description Examples ...... 46 2.4.1 Combinational Circuits ...... 46 2.4.2 Sequential Circuits ...... 51 3 Matlab-Simulink Co-Simulation ...... 61 3.1 Co-Simulation Active-HDL/Matlab-Simulink ...... 61 3.2 Co-Simulation Xilinx System Generator/Matlab-Simulink ...... 67 3.3 Co-Simulation Altera DSP Builder/Matlab-Simulink ...... 72

xi xii Contents

4 Chaos Generators ...... 77 4.1 On Piecewise-Linear (PWL) Functions ...... 77 4.1.1 Saturated Function Series as PWL Function ...... 77 4.1.2 Chua’s Diode as PWL Function ...... 78 4.1.3 Sawtooth as PWL Function ...... 79 4.2 On the Simulation of Chaos Generators for FPGA Implementation ...... 80 4.2.1 One-Step Methods for Simulating the Generation of 2-Scrolls ...... 82 4.3 Symmetric and Nonsymmetric PWL Functions ...... 84 4.3.1 Symmetric PWL Function ...... 85 4.3.2 Nonsymmetric PWL Function...... 87 4.3.3 VHDL Simulation and Computer Arithmetic Issues ...... 87 4.4 VHDL Code Generation...... 92 4.5 Bifurcation Diagrams ...... 94 4.6 Multi-scroll Chaotic Attractors with High MLE and Entropy. . . . . 94 4.6.1 Lyapunov Exponents ...... 103 4.6.2 Evaluation of Entropy ...... 109 4.7 Generating a 50-Scrolls Chaotic Attractor at 66 MHz...... 111 5 Artiﬁcial Neural Networks for Time Series Prediction ...... 117 5.1 Introduction ...... 117 5.2 Generating Chaotic Time Series Using FPGAs ...... 118 5.3 ANN Design Issues ...... 121 5.3.1 ANN Topology Selection...... 124 5.3.2 ANN Training ...... 126 5.3.3 Weights Updating by Batches and Incremental Methods...... 129 5.3.4 On the Activation Function in the Last Layer oftheANN...... 131 5.3.5 Time Series Prediction of Chaotic Signals with Different MLE...... 132 5.4 FPGA-Based ANN for Time-Series Prediction of Chaotic Signals ...... 133 5.4.1 FPGA Realization of the Hyperbolic Tangent Activation Function ...... 133 5.5 Serial Communication Protocol: PC-FPGA ...... 144 6 Random Number Generators ...... 151 6.1 Generating Pseudorandom Binary Sequences ...... 151 6.2 Numerical Method for Solving a Chaotic Dynamical System . . . . 151 6.3 Double-Scroll and Multi-scroll Chaos Generators...... 152 6.3.1 Chua’s Chaotic Oscillator...... 152 6.3.2 Saturated Function Series-Based Chaotic Oscillator ...... 153 Contents xiii

6.4 Measuring the Entropy of a RNG ...... 155 6.5 NIST Measurements ...... 157 6.6 Different RNGs ...... 157 7 Secure Communication System...... 173 7.1 Chaotic Secure Communication Systems ...... 173 7.2 Hamiltonian Synchronization Approach ...... 174 7.3 Synchronization of Multi-scroll Chaotic Attractors...... 176 7.4 Synchronization of 2D-4-Scroll Chaos Generators ...... 179 7.5 Synchronization of 3D-4-Scroll Chaos Generators ...... 182 7.5.1 Numerical Simulation Results ...... 184 7.6 Image Transmission Through a Chaotic Secure Communication System...... 184 7.6.1 Multi-scroll Chaos Generators Based on PWL Functions ...... 185 7.6.2 FPGA Realization ...... 190 7.6.3 Master–Slave Synchronization ...... 191 7.6.4 FPGA Realization ...... 194 8 Challenges in Engineering Applications ...... 205 8.1 On the Length of the Digital Words...... 205 8.1.1 Example of a Design with the Lorenz System...... 205 8.1.2 Variables Range Determination ...... 206 8.1.3 Number of Bits in the Integer Part ...... 207 8.1.4 Fixed Point Implementation ...... 208 8.2 Current Challenges ...... 210

References ...... 215

Index ...... 221 Acronyms

ALM Adaptive logic module ANN Artificial neural network ASIC Application-specific integrated circuit CAD Computer-aided design CLB Configurable logic block CLK Clock CLT Central limit theorem CRAM Configuration of random access memory CTW Context-tree weighting DCM Digital clock manager DSP Digital signal processor EDA Electronic design automation FPGA Field-programmable gate array FPL Field-programmable logic FSM Finite-state machine GNG Gaussian noise generator HDL Hardware description language IP Intellectual property LC Logic cells LE Logic elements LR Learning rule LSB Least significant bit LUT Look-up table MC Moment constant MEMS Microelectromechanical system MLE Maximum Lyapunov exponent MSB Most significant bit MSE Mean square error NIST National Institute for Standards and Technology ODE Ordinary differential equation OPC Operation counter

xv xvi Acronyms

PC Personal computer PLL Phase-locked loop PWL Piecewise linear RAM Random access memory RNG Random number generator ROM Read-only memory RST Reset RTL Register transfer level SCM Single constant multiplication SFS Saturated function series SM Sign-magnitude SQNR Signal to quantization noise ratio SRAM Static random access memory TDL Tapped delay line VHDL Very-high-speed integrated circuit hardware description language