ABSTRACT TIAN, QI. Modeling and Control Of

ABSTRACT

TIAN, QI. Modeling and Control of Single-phase Single-stage Isolated AC/DC Converter. (Under the direction of Dr. Alex Q. Huang).

Most of the present grid-tied isolated AC/DC converter, e.g., Electrical-Vehicle (EV) on-board chargers utilize the conventional multi-stage design, i.e., a front-end PFC + an isolated DC/DC converter, which limits the wall-to-battery efficiency to ~94%. In addition, the bulky DC link capacitor makes the system power density relatively low. A single-stage dual-active-bridge (DAB) based AC/DC topology is a better candidate for directly converting the grid AC to a battery DC and eliminating the DC link capacitor thereby increasing the system efficiency and power density.

Such single-stage topology adopts a novel variable-switching-frequency (VSF) and single-dual-phase-shift (SDPS) control strategy, which consists of three degrees of control freedom, i.e., two phase shifts and one variable switching frequency to secure Zero-Voltage-

Switching (ZVS) turn-on for all semiconductor devices and achieve the boost-type Power-

Factor-Correction (PFC) simultaneously. Both single-phase-shift (SPS) and dual-phase-shift

(DPS) modulation and their ZVS conditions under a whole range of grid voltages are analyzed thoroughly in this paper. The proposed VSF-SDPS control algorithm will guarantee ZVS and PFC not only for heavy load but also for light load, especially reducing the grid-current distortion. Simulation results and experimental validation indicate that by using the proposed VSF-SDPS control, the grid-current THD drops significantly, especially in a light load condition.

With the VSF control method, the system operation frequency varies from 100kHz to

500kHz. In order to optimize the system efficiency, a decent design must carefully choose

the leakage inductor and the saturation frequency, and then operate the system at an optimized switching frequency range. The semiconductor loss and magnetic loss breakdown are analyzed thoroughly in this dissertation. The power losses under different leakage inductor/ saturation frequency/ power are analyzed. A practical design method is proposed to optimize the system efficiency.

A DAB DC/DC converter is a key component in electric vehicles to manage power flow. Its averaged model and the small-signal model have been studied in-depth for years.

With the conventional constant-switching-frequency(CSF) and single-phase-shift(SPS) DAB control, the input voltage and output voltage are limited into a very narrow operation range.

The conventional model can handle the CSF-SPS DAB control well, however, it is not satisfactory with VSF-SPS control because they overlook the influence of the DC blocking capacitor and assume there is no DC offset of the inductor current. Actually, with VSF-SPS control, the DC blocking capacitor has a certain influence on ZVS conditions because there always are sinusoidal excitations coming from DAB input voltage and the control variables, switching frequency and phase-shift. There will be a low frequency oscillation of inductor current because of the electric resonance. Since the inductor current is designed to only have high switching frequency current component, in one switching period, the low frequency oscillation performance is like a DC offset and may lead to losing the ZVS. Therefore, a full-order continuous time average model of DAB is proposed and verified by the simulation and experimental result. The influence of a DC blocking capacitor has been taken into consideration.

Nowadays, the fast charging station attracts lots of attention due to the capability to shorten EV battery charging time. Input series output parallel (ISOP) topology is a very

promising and practical candidate to handle high input voltage and high output current. The key control challenge is how to balance the energy delivered by each module and how to balance the input voltage. Previous researches about the ISOP system were almost focused on the DC/DC system. In our application, the ISOP topology is applied to AC/DC system.

Furthermore, each module only has one stage. VSF control is creatively applied to the DAB based single stage AC/DC system. The system control method is validated by simulation.

Modeling and Control of Single-phase Single-stage Isolated AC/DC Converter

by Qi Tian

A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy

Electrical Engineering

Raleigh, North Carolina

2017

APPROVED BY:

______Dr. Alex Q. Huang Dr. Wensong Yu Committee Chair

______Dr. Srdjan Lukic Dr. Fen Wu

DEDICATION

To My Husband, Qilong Hao.

To My Parents, Yiping Tian and Zhenhua Wang.

To My Parents-in-law: Lingjun Hao and Chunying Zhang

BIOGRAPHY

Qi Tian was born in 1988 and raised in Taiyuan, Shanxi Province, People’s Republic of China. She received her B.S. degree in Electrical Engineering at Tsinghua University,

China, in July, 2010. She received her M.S. degree in Electrical Engineering at Tsinghua

University, China, in July, 2012. She is currently working towards her Ph.D. degree in the

Department of Electrical and Computer Engineering at North Carolina State University.

She received research scholarship as a part-time Research Assistant at the Future

Renewable Electric Energy Delivery and Management Systems (FREEDM) center at North

Carolina State University in the fall of 2012 and has been working there ever since. Her research interests include solar system distributed control, advanced Dual-active-bridge based AC/DC system control, and AC/DC power conversions.

iii

ACKNOWLEDGMENTS

I would like to take advantage of this opportunity, after four-and-a-half-year sojourn, to thank all those who have helped me along the way and have contributed to my success.

First and foremost, I would like to acknowledge with deep gratitude and respect the invaluable help of my advisor Dr. Alex Q. Huang, without whose guidance and support I would not have been able to do all of my research during this time. I would like to give special recognition to his ability to see the whole picture and his vast knowledge, profound insight and warm character. In addition, my undying thanks go to Dr. Wensong Yu, Dr.

Srdjan Lukic and Dr. Fen Wu for being on my committee and for their discussion, feedback and unwavering support.

I would also like to thank all the members of the Future Renewable Electric Energy

Delivery and Management (FREEDM) Systems Center, who have made this four year sojourn a pleasant and unforgettable journey. To all those at the FREEDOM Center I would like to say that I am forever in your debt. It goes without saying that that there are many others who have helped me in my studies who I would also like to thank for all of their invaluable support not only in my research but also in my personal life such as Professor

Iqbal Husain, Professor Mo-yuen Chow, Professor David Lubkeman, Professor Burgos

Rolando, Professor Mesut Baran, Professor Subhashish Bhattacharya for all the advices I have received over the years. I would like to thank Mr. Rogelio Sullivan, Dr. Ewan Pritchard,

Mr. Hulgize Kassa, Mr. Gregory Norris, Ms. Audrey Callahan, Ms. Colleen Reid, and Ms.

Karen Autry, and many more for which there is not enough room to mention by name, but

without whom I would not have been able to accomplish all that I have done during my stay here.

I also appreciate the help from my friends in FREEDM Systems Center, for their help and support both in life and research. I'd like to thank Dr. Ruiyang Yu, Ms. Li Wang, Mr.

Qianlai Zhu, Dr. Xiaomin Li, Dr. Kuijun Lee, Dr. Xijun Ni, Dr. Mohammad Ali Rezaei, Mr.

James McLamara, Mr. Qingyun Huang, Mr. Yizhe Xu, Dr. Yenmo (Morris) Chen, Ms. Huan

Hu, Mr. Yang Lei, Dr. Sheng Zong, Dr. Mengqi Wang, Dr. Dong Chen, Dr. Fei Wang, Dr.

Gangyao Wang, Mr. Kai Tan, Mr. Zhiping Chen, Mr. Xiaoqing Song, Mr. Fei Xue, Dr.

Chang Peng, Mr. Yang Xu, Dr. Xunwei Yu, Dr. Xu She, Dr. Xing Huang, Mr. Nan Xue, Mr,

Ms. Yuling Zhao, and many other that I cannot list the name here.

With a deep sense of gratitude for his guidance and backing for the last year I would additionally like to thank Dr. Hua Bai at the Kettering University. His unparalleled knowledge and incredibly deep understanding of power electronics has been immensely helpful. It has been an enormous blessing and opportunity to have been able to work with the prestigious Kettering University on this ambitious project.

To all of my colleagues at Kettering University Hui Teng, Juncheng Lu, Bo Lei,

Chenguang Jiang and Lei Shi, I say thanks for all your support! My research project would never have been able to progress so seamlessly and rapidly without your assistance and thoughtful constructive suggestions.

In addition to all the foregoing, I would like to say a million thanks to the Hella

Corporate Center USA, Inc. Without their confidence and trust in me I would not have been able to collaborate on the 7.2kW on-board electric vehicle charger design project. It was

amazing to be given the latitude and freedom to be able to research my own interests as well.

It was without a doubt one of the most important and challenging projects I have ever had the honor to participate in. GaN Systems Inc. also deserves a big thanks for the device and technical support provided.

TABLE OF CONTENTS

LIST OF TABLES ...... xi

LIST OF FIGURES ...... xii

Chapter 1. Introduction ...... 1

1.1 Electrical Vehicle Charger Classification and Standards ...... 1

1.2 Review of AC Level 2 On-board Electrical Vehicle Charger ...... 10

1.2.1 Single–stage AC Level 2 On-board Electrical Vehicle Charger ...... 11

1.2.2 Two–stage AC Level 2 On-board Electrical Vehicle Charger ...... 13

1.2.3 Single-stage AC Level 2 On-board Electrical Vehicle Charger ...... 17

1.3 Dissertation outline ...... 19

Chapter 2. Dual-active-bridge Single-phase-shift, Dual-phase-shift Modulation and

Zero-voltage-switching Operation Conditions Analysis...... 20

2.1 Single-phase-shift Modulation of Dual-active-bridge Control ...... 21

2.1.1 Single-phase-shift Modulation Theoretical Analysis ...... 21

2.1.2 Zero Voltage Switching Analysis ...... 24

2.2 Dual-phase-shift Modulation of Dual-active-bridge Control ...... 26

2.2.1 Dual-phase-shift Modulation Theoretical Analysis ...... 26

2.2.2 Zero Voltage Switching Analysis ...... 29

2.3 Conclusion ...... 32

Chapter 3. Variable-switching-frequency and Single-phase-shift/ Dual-phase-shift

Control Algorithm of Single-phase Single-stage AC/DC Isolated Converter ...... 33

vii

3.1 Variable Frequency and Dual-phase-shift Based Control Algorithm of Single- phase Single-stage AC/DC Isolated Converter...... 33

3.1.1 Theoretical Analysis ...... 33

3.1.2 Simulation Result ...... 38

3.2 Light Load Performance Enhanced Hybrid Variable Switching Frequency and

Single-phase-shift and Dual-phase-shift Control Algorithm ...... 43

3.2.1 Theoretical Analysis ...... 43

3.2.2 Simulation Result ...... 52

3.3 DSP Implementation and Experiment Result ...... 57

3.3.1 Digital Control Implementation Using DSP TMS320F28335 ...... 57

3.3.2 VSF-SDPS Control Experiment Result ...... 69

3.4 Conclusion ...... 78

Chapter 4. Power loss breakdown and system optimization...... 79

4.1 Semiconductor loss...... 79

4.1.1 VSF-DFS control semiconductor loss ...... 79

4.1.2 VSF-SDFS control semiconductor loss ...... 81

4.2 Magnetic Loss ...... 83

4.2.1 No Load Loss ...... 84

4.2.2 Load Loss ...... 84

4.2.3 Design Example ...... 87

4.3 Full Load Loss Breakdown ...... 93

4.3.1 VSF-DFS control loss breakdown ...... 93

viii

4.3.2 VSF-SDFS control loss breakdown ...... 95

4.4 System optimization ...... 97

4.5 Conclusion ...... 106

Chapter 5. Full-order State-space Modeling of Variable-switching-frequency and

Phase-shift Dual-active-bridge Control and the System Dynamic Analysis Considering the Influence of DC Blocking Capacitance ...... 107

5.1 Full-order Continuous Time Average Modeling of Dual-active-bridge Using Time- varying-state-space Method ...... 108

5.2 Time-varying Full-order Dual-active-bridge Modeling of Variable-switching- frequency Single-phase-shift Control in Matlab/Simulink ...... 116

5.3 Simulation Result and Analysis ...... 118

5.3.1 Case 1 @Cb=1mF, Lδ=12uH, Rδ=10mohm ...... 119

5.3.2 Case 2 @Cb=0.5mF, Lδ=12uH, Rδ=10mohm ...... 125

5.3.3 Case 3 @Cb=1mF, Lδ=12uH, Rδ=1mohm ...... 131

5.4 Experiment Result ...... 137

5.5 Conclusion ...... 141

Chapter 6. Variable Switching Frequency Control for Input-Series-Output-Parallel

Modular EV Fast Charging Stations...... 142

6.1 Input-Series-Output-Parallel Modular Topology and Operation ...... 147

6.2 System Control Strategy for Input-Series–Output-Parallel Modular Designed Fast

Charging Station ...... 153

6.2.1 Single-phase DQ Transformation ...... 153

6.2.2 Voltage and Current Control Loop Design ...... 156

6.3 Simulation Result ...... 160

6.4 Conclusion ...... 167

Chapter 7. Conclusion and Future Work ...... 169

7.1 Conclusion of the Work ...... 169

7.2 Future Work ...... 170

LIST OF TABLES

Table 1 SAE EV Charging Power Level ...... 3

Table 2 Charging technologies of popular makes and models ...... 4

Table 3 V2G Critical SAE Standards ...... 9

Table 4 System Parameters ...... 38

Table 5 Ratios of RAC / RDC for an isolated solid round wire (H) in terms of a value (X) ...... 85

Table 6 Frequency vs recommended Litz Wire ...... 86

Table 7 Constant k vs N ...... 87

Table 8 E100/60/28 effective core parameters ...... 88

Table 9 List of curve fitting points ...... 92

LIST OF FIGURES

Fig. 1 Global EV annual stock in thousands...... 1

Fig. 2 Slow and fast charger numbers 2007 – 2015...... 2

Fig. 3 AC level-1 changer examples...... 6

Fig. 4 AC level-2 changer examples...... 7

Fig. 5 DC fast changer examples...... 8

Fig. 6 Classification of AC level-2 EV charger topologies...... 10

Fig. 7 Non-isolated single-stage AC/DC...... 11

Fig. 8 Single-phase, single-stage, bidirectional and isolated DAB AC/DC converter topology.12

Fig. 9 A single-phase bidirectional isolated AC-DC converter...... 13

Fig. 10 Typical topologies of PFC...... 14

Fig. 11 Non-isolated DC-DC converter topology...... 15

Fig. 12 Isolated DC/DC converter topology...... 16

Fig. 13 Simplified system block diagram of a conventional on-board two-stage EV charger.17

Fig. 14 The single-phase single-stage AC/DC converter with PFC utilized for the EV on- board charger...... 18

Fig. 15 DAB topology...... 20

Fig. 16 SPS modulation of DAB...... 22

Fig. 17 ZVS region for the SPS control...... 26

Fig. 18 DPS modulation of DAB...... 27

xii

Fig. 19. (a)ZVS region under different v1: v2 ratio k; (b) transferred power (per unit value) corresponds to a different ZVS region under the same switching frequency...... 31

Fig. 20 VSF-DPS control@4kW...... 36

Fig. 21 VSF-DPS [email protected]...... 36

Fig. 22 Flow chart of VSF-DPS control over one line period...... 37

Fig. 23 The waveforms of control variables D1(t), D2(t), fs(t), primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the one line period. ....39

Fig. 24 Zoom-in waveforms of primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the four switching period...... 39

Fig. 25 ZVS checking of primary side switch P1, P3, and secondary side switch S1, S3 during the DPS region...... 40

Fig. 26 ZVS checking of primary side switch P1, P3, and secondary side switch S1, S3 during the saturation region...... 41

Fig. 27 Grid-side current, power, voltage, and battery voltage using proposed VSF-DPS [email protected]...... 42

Fig. 28 VSF-SDPS control@4kW...... 46

Fig. 29 Flow chart of VSF-SDPS control over the one line period...... 47

Fig. 30 VSF-SPS control@4kW...... 49

Fig. 31 The operation time of each operation mode in terms of percentage under different loads. Vout = 400V...... 50

Fig. 32 The operation time of each operation mode in terms of percentage under the constant-current charging mode. (a) Irms=15A; (b) Irms=35A...... 51

xiii

Fig. 33 (a)The waveforms of control variables D1(t), D2(t), fs(t), primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the one line period; (b)

SPS1 region; (c) DPS region; (d) SPS2 region...... 53

Fig. 34 ZVS checking of the primary side switch P1, P3, and secondary side switch S1, S3 during (a) SPS1 region; (b) DPS region; (c) SPS2 region...... 54

Fig. 35 Grid-side current, power, voltage, and battery voltage using the proposed VSF-SDPS algorithm...... 55

Fig. 36 The simulation waveforms of grid current iin (1)VSF-DPS method; (2)VSF-SDPS method...... 56

Fig. 37 THD comparison of VSF-DPS method and light load performance enhanced VSF-

SDFS method...... 56

Fig. 38 Single-stage AC/DC converter controlled by DSP TMS320F28335...... 57

Fig. 39 Software flowchart for the DSP controller unit...... 59

Fig. 40 Time-Base Counter Synchronization schematic...... 60

Fig. 41 High inductor current pulse caused by ePWM signal abnormal using the up-down mode ePWM configuration...... 61

Fig. 42 An ePWM external synchronization event waveforms in the up-down mode with lag phase-shift changing...... 62

Fig. 43 An ePWM external synchronization event waveforms in the up-down mode with the lead phase-shift changing...... 63

Fig. 44 An ePWM external synchronization event waveforms in the up-down mode, frequency changing, lead phase-shift...... 64

xiv

Fig. 45 An ePWM external synchronization event waveforms in up-down mode, frequency changing, lag phase-shift...... 65

Fig. 46 An ePWM external synchronization event waveforms in up mode with lead phase- shift changing...... 67

Fig. 47 An ePWM external synchronization event waveforms in up mode with lag phase-shift changing...... 68

Fig. 48 Prototype of the indirect matrix converter based on-board charger...... 69

Fig. 49 The experiment waveforms of vin and iin over three line period...... 70

Fig. 50 The waveforms of the VSF-SDPS control primary and secondary side transformer voltage vp and vs, and leakage inductance current iL...... 71

Fig. 51 The zoomed in waveforms of VSF-SDPS control primary and secondary side transformer voltage vp and vs, and leakage inductance current iL @total transferred power

200Wrms...... 73

Fig. 52 The waveforms of the VSF-SPS control primary and secondary side transformer voltage vp and vs, and leakage inductance current iL @200Wrms...... 77

Fig. 53 E100/60/28 core half...... 88

Fig. 54 Typical B-H loops...... 90

Fig. 55 Specific power loss as a function of peak flux density with frequency as a parameter.91

Fig. 56 VSF-DSF control loss breakdown@ Vg = 208VAC, Vo = 400VDC, fsa=500kHz,

Lδ=12uH...... 94

Fig. 57 Loss percentage of total power using the VSF-DFS control...... 95

Fig. 58 VSF-SDSF control loss breakdown@ Vg = 208VAC, Vo = 400VDC, fsa=500kHz,

Lδ=12uH...... 96

Fig. 59 Loss percentage of total power using the VSF-SDFS control...... 97

Fig. 60 Efficiency with different fsa and Lδ @7kW...... 99

Fig. 61 Efficiency v.s. Lδ under different fsa scenarios...... 100

Fig. 62 Contour plots of efficiency of the VSF-SDFS control method under different load condition with Vin=208VAC, Vout=400VDC (a)8kW; (b)7kW; (c)6kW; (d)5kW; (e)4kW;

(f)3kW; (g)2kW...... 101

Fig. 63 The simplified DAB circuit...... 108

Fig. 64 Vds and Ids of switch Sp1@vg=208VAC, vo=400VDC, Cb=500uF, Lδ=100uH,

Rδ=1mohm...... 116

Fig. 65 Time-varying full-order DAB state-space model...... 118

Fig. 66 iL simulation results of a state space model and a switching model over 2 line period@ Cb=1mF, Lδ=12uH, Rδ=10mohm...... 119

Fig. 67 iL simulation results of a state space model and a switching model over 8 switching periods@ Cb=1mF, Lδ=12uH, Rδ=10mohm...... 120

Fig. 68 FFT analysis of iL simulation results of switching model@ Cb=1mF, Lδ=12uH,

Rδ=10mohm...... 121

Fig. 69 FFT analysis of iL simulation results of the state space model@ Cb=1mF, Lδ=12uH,

Rδ=10mohm...... 122

Fig. 70 Bode plot of vg to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm...... 123

Fig. 71 Bode plot of vo to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm...... 123

xvi

Fig. 72 Bode plot of d to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm...... 124

Fig. 73 Bode plot of fs to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm...... 124

Fig. 74 iL simulation results of the state space model and switching model over the 2 line period@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm...... 125

Fig. 75 FFT analysis of iL simulation results of switching model@ Cb=0.5mF, Lδ=12uH,

Rδ=10mohm...... 127

Fig. 76 FFT analysis of the iL simulation results of the state space model@ Cb=0.5mF,

Lδ=12uH, Rδ=10mohm...... 128

Fig. 77 Bode plot of vg to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm...... 129

Fig. 78 Bode plot of vo to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm...... 129

Fig. 79 Bode plot of d to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm...... 130

Fig. 80 Bode plot of fs to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm...... 130

Fig. 81 iL simulation results of the state space model and the switching model over the 2 line period@ Cb=1mF, Lδ=12uH, Rδ=1mohm...... 131

Fig. 82 FFT analysis of the iL simulation results of the switching model @ Cb=1mF,

Lδ=12uH, Rδ=1mohm...... 133

Fig. 83 FFT analysis of the iL simulation results of the state space model @ Cb=1mF,

Lδ=12uH, Rδ=1mohm...... 134

Fig. 84 Bode plot of vg to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm ...... 135

Fig. 85 Bode plot of vo to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm ...... 135

Fig. 86 Bode plot of d to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm...... 136

Fig. 87 Bode plot of fs to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm...... 136

xvii

Fig. 88 iL experiment waveform (blue line) over the two line period@ Cb=1mF, Lδ=12uH. 137

Fig. 89 (a) iL experiment waveform used for FFT analysis (b)FFT analysis of iL experiment waveform...... 138

Fig. 90 Bode plot of vg to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm...... 139

Fig. 91 Bode plot of vo to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm...... 140

Fig. 92 Bode plot of d to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm...... 140

Fig. 93 Bode plot of fs to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm...... 141

Fig. 94 Conventional two stage fast charger design...... 143

Fig. 95 Conventional 3 phase modular fast charger design...... 144

Fig. 96 Conventional modular AC/DC/DC fast charger design...... 145

Fig. 97 Proposed modular AC/DC fast charger design...... 146

Fig. 98 Proposed ISOP modular designed high-efficiency 50kW fast charger topology for electric vehicles...... 148

Fig. 99 Control variables D(t) and fs(t) over the line period for the grid voltage when transferring 200W...... 152

Fig. 100 Flow chart of the VSF-SPS control over the one line period...... 153

Fig. 101 αβ coordinate to dq coordinate transformation...... 155

Fig. 102 dq coordinate to αβ coordinate transformation...... 156

Fig. 103 Voltage transformation from αβ coordinate to dq coordinate...... 158

Fig. 104 Current transformation from αβ coordinate to dq coordinate...... 159

Fig. 105 Voltage loops and current loop with feedforward signals...... 160

Fig. 106 Simulation result of three module ISOP system with only open loop control...... 162

xviii

Fig. 107 Simulation result of the three module ISOP system with only the proposed close loop control...... 164

Fig. 108 ZVS checking of the module 1 primary side switch P1, P3, and the secondary side switch S1, S3...... 165

Fig. 109 ZVS checking of the module 2 primary side switch P1, P3, and the secondary side switch S1, S3...... 166

Fig. 110 ZVS checking of the module 3 primary side switch P1, P3, and the secondary side switch S1, S3...... 167

xix

Chapter 1. Introduction

1.1 Electrical Vehicle Charger Classification and Standards

Interest in electric vehicles (EV) has been reinvigorated in recent decades because of higher petroleum prices and the effects of pollution, which has resulted in a lowered dependence on petroleum, which in turn has resulted in markedly reduced emissions from internal combustion engines. The reports [1] and [2] by Electric Vehicles Initiative (EVI) illustrates the growth since 2005 in EV sales on a global scale. In fact there has been such an increase that sales skyrocketed from 2010 to 2015. According to Fig. 1 the increase has been

50 fold.

1400

1200

1000

800 15 15 (thousands) - 600

400

200 Stock2005 0 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015

Battery electric cars Plug-in hybrid electric cars

Fig. 1 Global EV annual stock in thousands.

A fundamental component for the EV vehicle's performance is the EV charger. The number of public accessible charger number is increasing rapidly. See Fig. 2. It can be classified differently depending on the point of view. For example, according to the external electric power source, it is classified as an AC and DC charger. It can be classified as a three- phase or single-phase charger when considered as a phase number. It can also be classified as an on-board and off-board charger when considering the charger location. Finally, it is possible to classify it as a level 1, level 2 and level 3 chargers when the power level is taken into account. It can be classified as slow charger and fast charger when considering the charging speed.

Slow and fast charger numbers 2007 - 2015 200000 180000

160000

140000 120000 100000 80000

60000 Numberofstock units 40000 20000 0 2007 2008 2009 2010 2011 2012 2013 2014 2015

Publicly accessible slow charger Publicly accessible fast charger

Fig. 2 Slow and fast charger numbers 2007 – 2015.

Table 1 reviews the current status and implementation of EV battery chargers, power levels, and charging infrastructure according to the Society of Automotive Engineers (SAE)

EV DC Charging Power Levels[3]–[7]. AC level 3 charges faster and DC level 1/2/3 fast charging is not finalized yet. Other EV DC Fast Charging standards include CHAdeMO,

CCS, SAE Combo, Tesla Supercharger, etc.

Table 1 SAE EV Charging Power Level

Nominal Power Maximum Charging Supply Location Typical Use Level Current Time Voltage 1.08 kW 12 A typically provided 4-11 hrs with PEV used for 120V AC, On emergency AC level 1 1-phase 1.44kW 16 A Vehicle purposes when 11-36 hrs there is only a 120V outlet available 208V to 3.3 kW 16 A 1-4 hrs On charging at private AC level 2 240V AC, 6.6 kW 32 A 2-6 hrs Vehicle or public outlets 1-phase ≤14.4 kW ≤80 A 2-3 hrs AC level 3 208V to commercial, 50 kW 240A Off (Not 600V AC, analogous to a Vehicle finalized) 3-phase 100 kW 480A filling station DC level 1 Garage or 200V to Off 22min – 1.2 (Not ≤36 kW ≤80A DC dedicated charging 450V DC Vehicle hrs finalized) station DC level 2 Garage or 200V to Off (Not ≤90 kW ≤200A DC dedicated charging 10-20min 450V DC Vehicle finalized) station DC level 3 Garage or 200V to Off (Not ≤ 240 kW ≤400A DC dedicated charging <10min 450V DC Vehicle finalized) station

Based on SAE J1772 stander, the definitions of AC level 1/2/3 and DC level 1/2/3 EV charger are listed below: [3]

AC Level 1 – EVs and hybrid vehicles are charged by being connected to a conventional grounded outlet. The on-board charger will be equipped with a single phase AC supply network which will be able to accept a charge. Table 1 lists the power supply capabilities that are required;

AC Level 2 – This can be used in both public and private sites and will be configured with a dedicated AC EV/PHEV system setup. The EV setup will be supplied with an on- board charger using a single phase AC power supply. Table 1 lists the power supply capabilities that are required;

AC Level 3 – This can be used in both public and private sites and will be configured with a dedicated EV system setup. The EV setup will be supplied with an on-board AC charger with a minimum of 208 volts and 240 volts AC with a 400 amp maximum;

DC Level 1/2/3 – In private or public sites this will use a dedicated (DC) EV/PHEV supply setup to provide charging from a suitable off-board charger.[3]

By the end of 2015, the primary on-board charger is AC level-2. Some EV models on market are accessible to DC fast charge stations. The charging technologies of popular makes and models are given in Table 2.[8][9]

Table 2 Charging technologies of popular makes and models

US Price (After Fed 100% EV / Max AC Charge DC Fast Electric Car Model Tax Credit In PHEV (L2) Charging Parentheses) Audi A3 e-tron PHEV $37,900 ($33,200) 3.3 kW - Audi Q7 e-tron PHEV - 3.3 kW - BMW 225xe Active Tourer PHEV - 3.7 kW - BMW 330e PHEV - 3.7 kW - BMW i3 100% Electric $42,400 ($34,900) 7.4 kW SAE Combo

Table 2 Continued

Ford C-Max Energi PHEV $31,770 ($27,763) 3.3 kW - Ford Fusion Energi PHEV $33,900 ($29,893) 3.3 kW - Ford Focus Electric 100% Electric $29,170 ($21,670) 6.6 kW - Honda Accord Plug-In PHEV $39,780 ($36,154) 6.6 kW - Hybrid Hyundai Sonata Plug-in PHEV - 3.3 kW - Hybrid Kia Soul EV 100% Electric $33,700 ($26,200) 6.6 kW CHAdeMO Mercedes B-Class Electric 100% Electric $41,450 ($33,950) 10 kW - / B250e Mercedes C350e PHEV - 3.7 kW - Mercedes GLE500e PHEV - 3.6 kW - Mercedes S550e PHEV $95,650 ($90,950) 3.6 kW - Mitsubishi i-MiEV 100% Electric $22,995 ($15,495) 3.3 kW CHAdeMO Mitsubishi Outlander Plug- PHEV - 3.7 kW - In 3.6 kW / 6.6 Nissan LEAF 24 kWh 100% Electric $29,010 ($21,510) CHAdeMO kW Nissan LEAF 30 kWh 100% Electric $34,200 ($26,700) 6.6 kW CHAdeMO Peugeot iOn 100% Electric - 3.3 kW - Porsche Cayenne S E- 3.6 kW / 7.2 PHEV $77,200 ($71,864) - Hybrid kW Porsche Panamera S E- PHEV $96,100 ($91,348) 3 kW - Hybrid Renault Twizy 100% Electric - 2.2 kW - Renault Zoe 100% Electric - 22-43 kW - Smart Electric Drive 100% Electric $25,000 3.3 kW - Tesla Model S 70/70D 100% Electric $70,000 ($62,500) 10 kW / 20 kW Tesla/CHAdeMO Tesla Model S 85/85D 100% Electric $80,000 ($72,500) 10 kW / 20 kW Tesla/CHAdeMO Tesla Model S 90/90D 100% Electric $83,000 ($75,500) 10 kW / 20 kW Tesla/CHAdeMO Tesla Model S P85D 100% Electric $100,000 ($92,500) 10 kW / 20 kW Tesla/CHAdeMO Tesla Model S P90D 100% Electric $103,000 ($95,500) 10 kW / 20 kW Tesla/CHAdeMO Tesla Model X 70D 100% Electric $80,000 ($72,500) 12 kW / 18 kW Tesla/CHAdeMO Tesla Model X 90D 100% Electric $95,500 ($88,000) 12 kW / 18 kW Tesla/CHAdeMO Tesla Model X P90D 100% Electric $115,500 ($108,000) 12 kW / 18 kW Tesla/CHAdeMO Toyota Prius Plug-In PHEV $29,990 ($27,490) 3.3 kW - 3.6 kW / 7.2 Volkswagen e-Golf 100% Electric $28,995 ($21,495) SAE Combo kW Volkswagen e-Up! 100% Electric - 3.6 kW - Volkswagen Golf GTE PHEV - 3.6 kW - Volkswagen Passat GTE PHEV - 3.6 kW - Volvo S90 Plug-In PHEV - 3.6 kW - Volvo V60 Plug-In PHEV - 3.6 kW - Volvo XC90 T8 PHEV $69,100 ($64,500) 3.6 kW - BMW i3 REx REx $46,250 ($38,750) 7.4 kW SAE Combo BMW i8 PHEV $135,700 ($131,907) 3.7 kW - Volvo V60 Plug-In PHEV - 3.6 kW - Volvo XC90 T8 PHEV $69,100 ($64,500) 3.6 kW - BMW i3 REx REx $46,250 ($38,750) 7.4 kW SAE Combo

Table 2 continued

BMW X5 xDrive40e PHEV $63,095 ($59,095) 3.5 kW - BYD e6 100% Electric - 3.3 kW - Cadillac CT6 Plug-In Hybrid PHEV - 3.3 kW - Cadillac ELR PHEV $65,000 ($57,500) 3.3 kW - Cadillac ELR Sport PHEV - 3.3 kW - Chevy Spark EV 100% Electric $25,995 ($18,495) 3.3 kW SAE Combo Chevy Volt (2015) PHEV $34,345 ($26,845) 3.3 kW - Chevy Volt (2016) PHEV $33,170 ($25,670) 3.3 kW - Chrysler Pacifica PHEV Fiat 500e 100% Electric $32,300 ($24,800) 6.6 kW -

Some AC level-1 charger, AC level-2 charger and DC fast charger examples are shown in Fig. 3, Fig. 4 and Fig. 5 respectively.

(1)Standard Nissan Leaf Charger (2)Pass and Seymour L1EVSE Level 1

Portable Electric Vehicle Charger

Fig. 3 AC level-1 changer examples.

(1)Bosch EL-51253 Power Max 30 (2)GE WattStation Wall Mount Amp Electric Vehicle Charging Station EV Charger - Indoor/Outdoor, with 18' Cord Plug In (7.2kW Level-2)

Fig. 4 AC level-2 changer examples.

(1)Tesla DC fast chargers

(2)ABB DC fast chargers

Fig. 5 DC fast changer examples.

For safety reason, the Vehicle-to-grid (V2G) Critical SAE Standards listed in Table 3 should be followed: [5][6]

Table 3 V2G Critical SAE Standards

SAE J Title Scope Status General requirements for the electric vehicle conductive charge system and coupler for use in North America. Define a common electric vehicle SAE Electric Vehicle Published SAE conductive charging system architecture including Conductive Charge January, J1772™ operational requirements and the functional and Coupler 2010 dimensional requirements for the vehicle inlet and mating connector.

Energy Transfer System for Electric Vehicles-- Describes the total EV-ETS (Energy Transfer SAE Part 1: Functional Published System) and allocates requirements to the EV or J2293/1 Requirements and July, 2008 EVSE for the various system architectures. System Architectures

Energy Transfer System for Electric Vehicles-- Describes the SAE J1850-compliant SAE Part 2: Functional Published communication network between the EV and J2293/2 Requirements and July, 2008 EVSE for this application (ETS Network). System Architectures

Determination of the Maximum Available Describes a test procedure for rating peak power of Power from a SAE the Rechargeable Energy Storage System (RESS) Published Rechargeable Energy J2758 used in a combustion engine Hybrid Electric April, 2007 Storage System on a Vehicle (HEV). Hybrid Electric Vehicle

Recommended Practice for Measuring the Sets recommended practices for measuring the Exhaust Emissions and SAE Exhaust Emissions and Fuel Economy of Hybrid- Published Fuel Economy of J1711 Electric Vehicles, Including Plug-in Hybrid June, 2010 Hybrid-Electric Vehicles. Vehicles

Definition of the Utility Factor for Plug-In Describes the equation for calculating the total fuel SAE Hybrid Electric and energy consumption rates of a Plug-In Hybrid WIP J2841 Vehicles Using Electric Vehicle (PHEV). National Household Travel Survey Data

1.2 Review of AC Level 2 On-board Electrical Vehicle Charger

AC level-2 charger is the primary type of on-board EV charger on market. The topologies of AC level-2 EV charger can be divided into two categories: single stage topology and two-stage topology, and each of them can be further divided into non-isolated and isolated types. The classification of AC level-2 charger topologies is shown in Fig. 6.

Fig. 6 Classification of AC level-2 EV charger topologies.

Even though there is some literature that studied using non-isolation AC/DC converters as EV chargers, isolated two-stage AC/DC topologies are the mainstream due to the safety reasons. Single-stage isolated AC/DC topology is a new research approach with

the potential for high efficiency and high power density and has attracted lots of attention recently.[4], [5], [10]–[13]

1.2.1 Single–stage AC Level 2 On-board Electrical Vehicle Charger

A non-isolated single-stage AC/DC topology is studied in Ref[14] which is derived from direct AC/DC conversion theory. The number of inductors is decreased; however the number of switches increased and the efficiency is slightly lower as the trade-off. The topology is shown in Fig. 7.

AC Battery

Fig. 7 Non-isolated single-stage AC/DC.

Ref[15] proposed a single-stage isolated DAB AC/DC converter with a constant frequency, both duty cycle and phase-shift control strategy. The first stage is changed from a full-bridge rectifier into an unfolding bridge which works with 60Hz line frequency. The main problem with this implementation is the complexity of the control algorithm. All of the

phase-shift and duty cycle are calculated off-line by Matlab under various voltage and load conditions. The topology is shown in Fig. 8.

Unfolding bridge

AC Battery

Fig. 8 Single-phase, single-stage, bidirectional and isolated DAB AC/DC converter topology.

As shown in Fig. 9, a single-phase bidirectional isolated AC/DC converter with

Power Factor Correction (PFC) is proposed, which consists of a half-bridge on the AC side and a full-bridge on the DC side to accomplish single-stage power conversion[16]. A variable frequency and dual-phase-shift control is implemented to realize PFC and ZVS. However, due to the frequency saturation, the THD performance is not satisfied under light-load condition.

AC Battery

Fig. 9 A single-phase bidirectional isolated AC-DC converter.

1.2.2 Two–stage AC Level 2 On-board Electrical Vehicle Charger

The two-stage topology is the most popular AC level-2 on-board EV charger approach due to its high power rate, high reliability and straight forward control algorithm.

The charger consists of the front end PFC and a DC-DC converter. For the PFC stage, a variety of topologies and control methods have been developed to reach a unity power factor.

The following high-frequency isolated DC/DC converter is usually operated with a soft- switching control to eliminate the switching loss.

As a key section, the PFC stage rectifies the input AC voltage to a regulated DC link bus voltage, and achieves the power factor correction function at the same time. Various PFC topologies have been proposed. Several typical PFC topologies are shown in Fig. 10.[4], [5],

[12], [17]–[23]

AC AC DC Bus DC Bus

(a) Unidirectional boost PFC (b) Symmetrical two-device unidirectional boost PFC

AC AC DC Bus DC Bus

(e) Half-bridge bidirectional boost PFC (f) Full-bridge bidirectional boost PFC

Fig. 10 Typical topologies of PFC.

The second stage is a DC/DC converter which is utilized to transmit power and regulate the output voltage for battery charging.

Generally, non-isolated DC-DC converters have the advantages of simple structure, high efficiency, low cost, high reliability, etc. In Ref[13], some non-isolated DC-DC topologies are considered for this application, which topologies are shown in Fig. 11. The commonly used non-isolated DC-DC topologies can be divided into five categories: half-

bridge converter, Cuk converter, cascaded half-bridge converter, SEPIC converter and interleaved half-bridge converter.

Battery DC Bus Battery DC Bus

(a) Half-bridge converter (b) Cuk converter

DC Bus Battery DC Bus Battery

Battery

(e) Interleaved half-bridge converter

Fig. 11 Non-isolated DC-DC converter topology.

However, most AC level 2 on-board chargers are using DAB or LLC high frequency isolated DC-DC topologies, which have high efficiency and high power density. High efficiency can be achieved due to the convenient implementation of soft-switching technology.[4], [5], [12], [20], [23]–[29]

DAB consists of two active bridges linked by a high frequency transformer. The typical DAB DC-DC converter topologies are shown in Fig. 12 (a). The transformer leakage

inductor is used to transfer power. The conventional DAB control is a constant switching frequency and a single-phase-shift or dual-phase-shift control. A duty cycle control is also proposed to increase the ZVS range or voltage conventional ratio. [4][15]

An LLC resonant converter has been widely used in a distributed power system. The typical LLC DC/DC converter topologies are shown in Fig. 12 (b). The advantages of an

LLC converter include: ZVS capability for zero to full load range, high efficiency and low voltage stress on a secondary rectifier.[29] However, LLC topologies provide many variations leading to high control and design complexity. [29][30]

DC Bus Battery

(a) isolated DAB DC/DC converter

DC Bus Battery

(b) isolated LLC DC/DC converter

Fig. 12 Isolated DC/DC converter topology.

1.2.3 Single-stage AC Level 2 On-board Electrical Vehicle Charger

The DAB topology is widely used for isolated DC/DC converters, which offers the inherent bidirectional power flow capability, electrical isolation, high reliability and ease of realizing the soft-switching control. For the design shown in Fig. 13, when using the conventional constant-switching-frequency single-phase-shift (CSF-SPS) DAB control, a large DC link bus capacitor is unavoidable to handle the instantaneous transfer of power.

Meanwhile the CSF-SPS control suffers from several drawbacks, i.e., low light-load efficiency, large circulating current and limited soft switching range. [31][32]To overcome these drawbacks, various modulations of DAB converters have been proposed. SPS, DPS and hybrid modulation with a constant or variable switching frequency modulation are developed to minimize the circulating current and enlarge the soft switching range[31]–[40]. However, it’s very difficult to achieve a full-power-range ZVS, realize PFC and keep a low circulating current at the same time. Besides most control algorithms have a very high complexity for implementation.

DC Link bus capacitor Input filter Output filter

Isolated ZVS AC/DC PFC Vg DC/DC Battery Boost Converter Converter

ePWMs ePWMs

Sensor Sensor Digital Controller

Fig. 13 Simplified system block diagram of a conventional on-board two-stage EV charger.

To further increase the system efficiency and power density, an isolated AC/DC converter with a smaller number of stages was proposed in [16], which eliminates the large

DC link bus capacitor and realizes the ZVS turn-on for all switches by using a VSF-DPS control. The problem for such a topology lies in the utilization of the back-to-back connected switches, which increases the system cost and control complexity. In [36], a single-stage, single-phase AC/DC converter was proposed to avoid the back-to-back switches, as shown in

Fig. 14. The front-end is only a 60Hz full-wave rectifier, which converts the 60Hz sinusoidal voltage to a 120Hz single-polarity DC voltage. No bulky DC link bus capacitor is needed.

The second stage is an isolated high-frequency DAB based DC/DC converter. The control algorithms proposed in [16] and [36] contain three independent control variables, i.e., phase- shift between primary side H-bridge and secondary side H-bridge, phase-shift between two legs of the secondary side and the switching frequency. Due to the limitation of the highest switching frequency, all present control algorithms lead to frequency saturation around the zero-crossing points of the grid voltage, resulting in the loss of ZVS or the input-current distortion especially at light-load operation.

vg vin vp vs

Lg Lo

if Sr1 Sr3 Sp1 Sp3 Ss1 Ss3 Vo

vg vin vp Lf vs Cin Co Ro Sr2 Sr4 Sp2 Sp4 Ss2 Ss4

Silicon E-Mode MOSFET GaN HEMTs

Fig. 14 The single-phase single-stage AC/DC converter with PFC utilized for the EV on-board charger.

1.3 Dissertation outline

The scope of this dissertation is organized as follows:

Chapter 2 presents thoroughly an analysis of both the SPS modulation and DPS modulation. The ZVS constrains of both the SPS and DPS are analyzed under zero load conditions to full load conditions.

Chapter 3 presents a novel VSF-DPS control and a light load performance enhanced

VSF-SDPS control, which realizes PFC without losing ZVS and suppresses the circulating current in the DAB stage. Theoretical analysis, simulation validation and experiment validation are presented. The digital control implementation of the variable frequency and phase-shift technique is discussed.

Chapter 4 presents the semiconductor loss breakdown and magnetic loss breakdown of a VSF-SDFS control. A practical transformer design method is proposed. The system parameters, saturation switching frequency and leakage inductance are designed based on a whole system efficiency optimization.

Chapter 5 presents a time-varying full-order state-space model of DAB topology, which is more suitable for variable frequency control than the conventional first-order model.

Both theoretical analysis and simulation verifications are conducted to validate the proposed full- order state space modeling technique.

Chapter 6 proposes an input-series-output-parallel modular topology for an EV fast charger. A novel variable switching frequency system control method is proposed to achieve voltage and energy balance among each of the modules.

Chapter 7 concludes the major contributions of the dissertation and proposes future work.

Chapter 2. Dual-active-bridge Single-phase-shift,

Dual-phase-shift Modulation and Zero-voltage-

switching Operation Conditions Analysis

A basic DAB topology is shown in Fig. 15. There is some previous research that thoroughly analyzed DAB characteristics[11], [42]–[58]. As the two prevalent control strategies for the dual-active-bridge (DAB) converter, the single-phase-shift (SPS) and dual-phase-shift

(DPS) modulation, both could realize zero-voltage-switching (ZVS) and turn-on although their ZVS boundaries are different. Understanding the ZVS boundaries of both controls is the precondition for any possible improvement.

vin vp vs

if P1 P3 S1 S3 Vo

Vin vin vp Lδ vs Cin Co Ro P2 P4 S2 S4

Fig. 15 DAB topology.

2.1 Single-phase-shift Modulation of Dual-active-bridge Control

2.1.1 Single-phase-shift Modulation Theoretical Analysis

The basic gate signals and voltages of the SPS modulation are shown in Fig. 16. D(t) is the phase shift ratio between the primary side H-bridge and secondary side H-bridge. Here

D(t) = ϴshift/(2π). The phase shift ratio D(t), the gate signal of DAB, the transformer primary and secondary side voltage vp(t) , vs(t) and the leakage inductance current iL(t) over a single switching period Ts are shown in Fig. 16. All switches are modulated with a 50% duty ratio and a top switch is complemented with the bottom switch. The gate signal P1 and S3 (or P4 and S2) are shifted in phase. Both vp and vs are square waveform and there is ϴshift phase difference between them.[59][60]

iL v (t) vs o vp vg(t)

-vg(t)

-vo(t) 0 D * T s Ts/2 Ts

t0 t1 t2 t3 t4

Fig. 16 SPS modulation of DAB.

The transformer leakage inductance current iLsps(t) under SPS modulation is given in

(2.1), with the input voltage v1, output voltage v2, phase shift D, and switching frequency fs.

The leakage inductance current at all switching moments are given in (2.2). All the parameters are reflected to the primary side of the transformer.

v  v v  v  (4  D 1) 1 2 t  1 2 t  t  t  L 4  f  L 0 1   s  v  v v  v  (4  D 1)  1 2 t  1 2 t  t  t  L 4  f  L 1 2 i (t)   s  (2.1) Lsps  v  v 3 v  v  (4  D 1)  1 2 1 2 t  t2  t  t3  L 4  fs  L   v1  v2 3 v1  v2  (4  D  3)  t  t3  t  t4  L 4  fs  L

 v  v  (4  D 1) i (t )  1 2  Lsps 0  4  f  L  s  v  (4  D 1)  v i (t )  1 2  Lsps 1 4  f  L  s   v1  v2  (4  D 1) iLsps (t 2 )  (2.2) 4  f  L  s  v  (4  D 1)  v i (t )  1 2  Lsps 3  4  f  L  s  v  v  (4  D 1) i (t )  1 2  Lsps 4   4  f s  L

The transferred instantaneous power with SPS control over one switching period Ts is given in (2.3).

v v (1 / )  /  1 2 shift shift v1 v2 (1 2 D)  D pt (t)    2 f  L f  L  s  s  (2.3)  where D  shift  2

2.1.2 Zero Voltage Switching Analysis

To realize ZVS for the switches, a negative iLsps(t0) is a must. However, not only the current polarity but also the current value needs special attention. The inductor current should be large enough to charge/discharge the switch junction capacitance, which is the precondition to realize the ZVS. Based on the law of conservation of energy, the minimal

v1 v2 current required to achieve ZVS is is1  for the primary side, and is2  for L L Ceq Ceq the secondary side. Ceq is the equivalent capacitance of one bridge leg.

To realize the ZVS for the primary side, we need:

iLsps(t0 )  is1 (2.4)

For the secondary-side ZVS operation, we need:

iLsps(t1)  is2 (2.5)

Condition (2.2), (2.4) and (2.5) result in a minimal control variable D given by (2.6).

 D  (1 k  4 fs  k  Ceq  L ) / 4 k 1  (2.6) D  (k 1 4 f  C  L ) / 4 k 1  s eq 

v1(t) Where k(t)  . v1(t) is a 120Hz single-polarity DC waveform after the front-end v2 (t) rectifier, changing from 0 to the peak grid voltage and v2(t) is the battery voltage. In this paper the DC-bus voltage is always lower than the output voltage, i.e., k<1. Therefore:

D  (1 k  4 fs k  Ceq  L )/ 4 (2.7)

Meanwhile:

0  D  0.5 (2.8)

The ZVS region under different k is shown in Fig. 17, which is independent of switching frequency fs. For different k, the minimal value of phase shift D is marked with the dash line. With a specific k value, DAB will lose ZVS if the control variable D is less than

Dmin(k). It should be noticed that if D is larger than 0.25 (90º), the ZVS is secured at all the time. However, operating in the D>0.25 region, DAB generates more reactive power than the

D<0.25 region when same active power is transferred. If selecting D only from the dash line, the minimal circulating current is guaranteed and there is only very limited reactive power generated to maintain ZVS, therefore in the conventional SPS control only the D<0.25 region is used. However, with a certain fs, if we want to transfer ultra-low power, in the D<0.25 region, the DAB will lose ZVS and run into a hard switching mode, thus the system must operate in the D>0.25 region to secure ZVS. In this paper especially at light load, such a feature will be utilized.

k=1 k=0.8 k=0.6 k=0.4 k=0.2 k=0

Soft Switching Dmin

Hard Switching

Fig. 17 ZVS region for the SPS control.

2.2 Dual-phase-shift Modulation of Dual-active-bridge Control

2.2.1 Dual-phase-shift Modulation Theoretical Analysis

To describe the dual-phase-shift control algorithm mathematically, two control variables phase-shift D1 and D2 are introduced which are relative to the switching period Ts.

Fig. 18 shows the gate signal of DAB, the transformer primary and secondary side voltage vp(t) , vs(t) and the leakage inductance current iL(t) over a single switching period Ts. The gate signals of P1 and P4 (or P2 and P3) are always at 50% duty cycle, therefore, the primary side voltage of transformer is a square waveform. The gate signals of S1 and S3 (or S2 and S4) are phase shifted, therefore the secondary side voltage of a transformer emerges as a three-level

waveform instead of the two-level square wave under the conventional single-phase-shift control. The definitions of the phase-shift D1, D2 are illustrated in Fig. 18. All the parameters are reflected to the primary side of the transformer.

if v (t) vs o vp vg(t)

-vg(t)

-vo(t) D1*Ts D2*Ts 0 Ts/2 Ts

t0 t1 t2 t3 t4 t5 t6

Fig. 18 DPS modulation of DAB.

The transformer leakage inductance current iLdps(t) is given in (2.9) with the input voltage v1, output voltage v2, phase shift D1 and D2, and switching frequency fs. It should be noticed that v1, v2, D1, D2, and Fs are time dependent variables of line frequency.

v  v v  v  (2  D  4  D 1) 1 2  t  1 2 2 1 t  t  t  L 4  f  L 0 1   s  v v  v  (2  D 1)  1  t  1 2 2 t  t  t  1 2 L 4  f s  L v  v v  v  (2  D  4  D 1)  1 2  t  1 2 2 1 t  t  t  L 4  f  L 2 3 i (t)   s  Ldps  v  v 3  v  v  (2  D  4  D  1) (2.9)  1 2 1 2 2 1  t  t3  t  t 4  L 4  f s  L   v1 3  v1  v2  (2  D2 1)   t  t 4  t  t5  L 4  f s  L

 v1  v2 3  v1  v2  (2  D2  4  D1  3)   t  t5  t  t 6  L 4  f s  L

Leakage inductance current values at the switching instants are given in (2.10).

 v  v (4 D  2 D 1) i (t )  1 2 1 2  Ldps 0  4 f  L  s  v (4 D 1)  v (1 2 D ) i (t )  1 1 2 2  Ldps 1 4 f  L  s  v (4 D  4 D 1)  v (1 2 D ) i (t )  1 1 2 2 2  Ldps 2 4 f  L  s   v1  v 2 (4 D1  2 D2 1) i Ldps (t 3 )  (2.10) 4 f  L  s   v1 (4 D1 1)  v 2 (1 2 D2 ) i (t )   Ldps 4  4 f  L  s  v (4 D  4 D 1)  v (1 2 D ) i (t )  1 1 2 2 2  Ldps 5  4 f s  L  v  v (4 D  2 D 1)  1 2 1 2 i Ldps (t 6 )    4 f s  L

The transferred instantaneous power over one switching period Ts is given in (2.11).

2 2 v1  v2  (4  D1  4  D1  D2  2  D2  2  D1  D2 ) pt (t)  (2.11)  2  f s  L

There are three degrees of freedom that can be used to control the instantaneous power pt(t): phase-shift D1, phase-shift D2, and switching frequency fs(t). And there are infinite combinations of (D1, D2, fs) for the same transferred instantaneous power, which gives us the capability to meet the ZVS requirement over the line period while achieving a unity power factor.

2.2.2 Zero Voltage Switching Analysis

To simplify the analysis, the turn ratio of a transformer is assumed to be 1:1, and v1(t)

<= v2(t). To achieve ZVS for all switches during one half-cycle of the switching period, some energy stored in the leakage inductance is required to discharge the switch junction capacitance. Therefore, the primary side switches ZVS constrain is:

iL (t0 )  0 (2.12)

And the secondary side switches ZVS constrains are:

iL (t1 )  0  (2.13) iL (t2 )  0

Conditions (2.10), (2.12) and (2.13) result in the ZVS constrains:

k  4 D1  2 D2 1  0 (a)  (4 D1 1)k 1 2 D2  0 (b) (2.14)  (4 D1  4 D2 1)k 1 2 D2  0 (c)

v where k is the ratio of the referred input voltage to the output voltage, namely k  1 v2

. v1(t) is the 120Hz single-polarity DC waveform after the front-end rectifier, changing from

0 to peak grid voltage; v2(t) is the battery voltage which is assumed to be constant.

To maintain the symmetric current waveform of the leakage inductance and meet the requirement of switching sequence in Fig. 18, D1 and D2 should follow the conditions of:

 D1  0  D2  0 (2.15)  1 D  D   1 2 2

The ZVS region under different k is shown in Fig. 19(a), which only depends on the combination of (D1, D2), and is independent with switching frequency fs. The transferred power with ratio k over each corresponding ZVS region under the same switching frequency is shown in Fig. 19(b). The dominant factor to determine transferred power p(t) is the input voltage v1(t). When v1(t) is zero, no matter what (D1, D2) combination is chosen, p(t) is always zero; when v1(t) goes larger, the power surface goes higher. With a certain v1(t), a different combination (D1, D2) will lead to different transferred power, and the maximum power happens when D1=0.25 and D2=0.

Since the ZVS region is only related to phase-shift D1 and D2 under a specific k ratio, and has nothing to do with switching frequency fs at all, the phase-shift D1 and D2 can be used to keep ZVS over the line period. With a certain (k, D1, D2) combination, the transferred power is determined by switching frequency fs, therefore, the switching frequency can be considered as a time-dependent control variable to achieve a unity power factor.

(a)

(b)

Fig. 19. (a)ZVS region under different v1: v2 ratio k; (b) transferred power (per unit value) corresponds to a different ZVS region under the same switching frequency.

2.3 Conclusion

In this chapter, the two modulation methods of a DAB converter, the SPS and DPS, are analyzed thoroughly. The ZVS constrains of both the SPS and DPS are analyzed under zero to full load conditions, while input voltage varies from 0 to peak.

Chapter 3. Variable-switching-frequency and

Single-phase-shift/ Dual-phase-shift Control

Algorithm of Single-phase Single-stage AC/DC

Isolated Converter

3.1 Variable Frequency and Dual-phase-shift Based Control Algorithm

of Single-phase Single-stage AC/DC Isolated Converter

3.1.1 Theoretical Analysis

 To reach the unity power factor, assume the grid voltage vg (t)  V1 sin( t) , the grid

 *   2 current ig (t)  I1 sin( t), and the reference power p (t) V1  I1 sin ( t) . After the front-

 end rectifier, the voltage and current reference can be expressed as v1(t)  V1  | sin( t) | , and

 i1(t)  I1  | sin( t) |.

In Ref[16], a variable-switching-frequency and dual-phase-shift (VSF-DPS) method is implemented. According to the analysis of the DPS modulation shown in Fig. 18, there are various combinations of (D1, D2, fs) leading to the same instantaneous power. The basic ideas for the VSF-DPS are: (1) using D1 and D2 to maintain ZVS turn-on; (2) using fs to achieve

unity power factor; (3) D2 depends on D1 to make sure iL(t1)=iL(t3), iL(t4)=iL(t6), therefore, the

ZVS constrains are simplified.

To realize ZVS for the switches, a negative iL (t0) is a must. The inductor current should be large enough to charge/discharge the switch junction capacitance, which is the precondition to realize ZVS. Based on the law of energy conservation, the minimal current

v1 v2 required to achieve ZVS is is1  for the primary side, and is2  for the L L Ceq Ceq secondary side. Ceq is the equivalent capacitance of one bridge leg. v1 is the DAB input voltage, v2 is the DAB output voltage.

The minimal inductor current of the AC/DC system is shown below:

     v1 v2  I s  max ,  (3.1)  L L   C C   eq eq 

Therefore, the minimal phase-shift D1 is given by the equation (3.2), where Δ is a small positive safe margin to generate enough reactive power to discharge the junction capacitor.

2  I s  L  f sa D1    (3.2) v1  v2

In order to guarantee iL(t1)=iL(t3), iL(t4)=iL(t6), D1 and D2 must meet constrain (3.3):

D2  0.5 D1  0.5v1  2 D1 v1 /v2 (3.3)

The transferred instantaneous power over the one switching period Ts is

2 2 v1 v2 (4 D1  4 D1  D2  2 D2  2 D1  D2 ) pt (t)  , which should be equal to the  2 fs  L

*   2 instantaneous power reference p (t) V1  I1 sin ( t).

Therefore, we can derive the instantaneous switching frequency as shown in (3.4).

2 2 v1 v2 (4 D1  4 D1  D2  2 D2  2 D1  D2 ) f s  * (3.4)  2 p (t) L

However, the theoretical switching frequency at the zero crossing point of grid voltage is infinity. So a saturation switching frequency fsa is set. When the grid voltage goes to near zero, fs(t) calculated from (3.4) will be clamped to the maximal switching frequency fsa, which is 500kHz in this paper.

The operation region when switching frequency saturated is named “Sat region”, and the normal operation region is named “DPS”. The control signals D1, D2, and fs over one grid period are shown in Fig. 20 and Fig. 21. The grid voltage is 208Vrms, the output voltage is 400 VDC and total transferred power is 4kW in Fig. 20. The grid voltage is 208Vrms, the output voltage is 400 VDC and total transferred power is 7.2kW in Fig. 21.

D1 fs / Hz D2

t / S

Fig. 20 VSF-DPS control@4kW.

D1 fs / Hz D2

t / S

Fig. 21 VSF-DPS [email protected].

With the same grid voltage and battery voltage, the switching frequency region is much larger under light load conditions than heavy load conditions. The frequency saturation leads to a very large THD under light load conditions. A novel light load performance enhanced control algorithm is proposed in chapter 3.2 to solve this problem.

The flow chart of VSF-DPS control is shown in Fig. 22.

DPS calculation D1, D2, fs0

If fs0< fsa Yes No

fs = fs0 fs = fsa

End

Fig. 22 Flow chart of VSF-DPS control over one line period.

3.1.2 Simulation Result

Simulation waveform is shown in Fig. 23 and Fig. 24 . The simulation software is

Matlab/Simulink. The system parameters are shown in Table 4. The input voltage is 208VAC, the output voltage is 400VDC and the operation power is 7.2kW.

Table 4 System Parameters

Symbol Quantity Value fg Mains frequency 60Hz fs Switching frequency 100kHz…500kHz vg Grid voltage 208Vrms

vo Battery voltage 300Vdc…450Vdc

Lg, Lo Inductor 5uH

Cin, Co Capacitor 10uF

Ceq Switch junction capacitor 1nF

L Transformer leakage inductance 12uH

R Transformer ACR 20mohm

1:n Transformer turn ratio 1:1

Fig. 23 illustrates D1(t), D2(t), fs(t), primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the one-line period. The zoomed in waveforms are shown in Fig. 24. vp is a square waveform, and vs is a three-level waveform corresponding to the DPS control, which are consistent with the analysis shown in Fig. 18.

fs / Hz

Fig. 23 The waveforms of control variables D1(t), D2(t), fs(t), primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the one line period.

vp/V

vs/V

iL/A

Fig. 24 Zoom-in waveforms of primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the four switching period.

Fig. 25 checks the ZVS results during the DPS region, and Fig. 26 checks the ZVS results during the Sat region. All the switches of the primary side and secondary side can achieve the ZVS turn-on over the whole line period. Note when the switch is on, the current it is negative, indicating the ZVS turn-on. Therefore the turn-on loss is negligible.

ZVS turn-on

Fig. 25 ZVS checking of primary side switch P1, P3, and secondary side switch S1, S3 during the DPS region.

ZVS turn-on

Fig. 26 ZVS checking of primary side switch P1, P3, and secondary side switch S1, S3 during the saturation region.

The PFC and THD performance are also simulated in Matlab/Simulink, according to the parameters given in Table 4. The input voltage is 208VAC, and the output voltage is

400VDC. Operation power is 7.2kW. Simulated grid side current, power, voltage, and battery voltage are shown in Fig. 27, which illustrates the instantaneous input current Iin and its reference Iref, input power Pin and its reference Pref, grid voltage vg, output current io and battery voltage vo over the one-line period. The unity power factor is achieved. Due to the

switching frequency saturation, around the grid voltage zero crossing point, there is a clear distortion of input grid current.

Iin/A Iin_ref/A

Pin/W Pin_ref/W

vg/V

vo/V

Fig. 27 Grid-side current, power, voltage, and battery voltage using proposed VSF-DPS [email protected].

Due to reasons of confidentiality, the full load experiment waveforms are presented in

[61] which are not included in this dissertation. The input voltage is 220VAC, the output voltage is 400VDC and the operation power is 7.2kW. Overall system efficiency is ~98%.

3.2 Light Load Performance Enhanced Hybrid Variable Switching

Frequency and Single-phase-shift and Dual-phase-shift Control

Algorithm

3.2.1 Theoretical Analysis

 To reach the unity power factor, assume the grid voltage isvg (t)  V1 sin( t) , the

 *   2 grid current is ig (t)  I1 sin( t), and the reference power is p (t) V1  I1 sin ( t). After the front-end rectifier, the voltage and current reference can be expressed as

  v1(t)  V1  | sin( t) | , and i1(t)  I1  | sin( t) |.

In this chapter, a hybrid variable switching frequency and single-phase-shift and dual- phase-shift (VSF-SDPS) method is proposed combining the SPS and DPS together to optimize the system efficiency and THD performance. [62]

For the DPS modulation, there is a special provision for DPS modulation that D2 equals zero, thereby, the control strategy is degraded to the SPS modulation. As our control strategy design rule, under the premise of ensuring ZVS and PFC, we will try to use as much

SPS as possible, because the wider effective pulse of SPS at the secondary side will help us decrease the leakage inductance RMS current and increase the system efficiency.

With the DPS modulation, there are various combinations of (D1, D2, fs) leading to the same instantaneous power. The SPS is a degraded DPS modulation method (D1, 0, fs).

The basic idea for the hybrid VSF-SDPS is: (1) during high instantaneous grid voltage time, keep D2=0, select D1 from dash line in Fig. 17 and use fs to meet the instantaneous power

requirement, therefore, ZVS can be achieved as well as the minimal reactive power; (2) when fs is saturated, select (D1, D2) from (2.14)(a) the boundary to meet the instantaneous power requirement, therefore, ZVS can be achieved as well as the minimal reactive power; (3) when there is no solution for (2), keep D2=0, select D1 from [0.25, 0.5] the region shown in Fig. 17, therefore, ZVS can be achieved, however, more reactive power will be generated.

Not only ZVS will be realized, but also the circulating current of the transformer will be reduced. Under such a control strategy, during most of the operation time the system is controlled by the VSF-SPS, generating minimal circulating current to achieve the highest efficiency. The details of the VSF-SDPS method is presented below.

When operated at the SPS control, the system control variables are determined by the equation (3.5).

 D1 (t)  (1 k  4 f s k  Ceq  L ) / 4    D2 (t)  0 (3.5)   v v (1 2 D ) D f (t)  1 2 1 1  s  pt  L

Where δ is a small positive safe margin to generate enough reactive power to discharge the junction capacitor.

When the grid voltage goes to near zero, fs(t) will be clamped to the maximum switching frequency fsa, which is 500kHz in this paper. Therefore, another solution is to introduce phase shift D2, shown as (3.6).

  1 m(t) D (t)  (1  k  2 D )  1 2 4 v2  * 8 p  f  L 2 2   ( t sa   v   (t) 2  2  (t) k v  k 2 v )  k 2 2 2 D2 (t)  (3.6)  2v2    f (t)  f  s sa  

Where m(t)  4 fsa  L is1(t)  4v2   , and  is a positive safety allowance to maintain ZVS.

However, D2 in (3.6) does not always have a real solution. Thus the DPS control in

(3.6) should be combined with the SPS control to realize full range ZVS and PFC. In (3.7), to keep ZVS as well as deliver the ultra-low power, D1 goes to [0.25, 0.5], which means generating more reactive power and less active power to keep ZVS. Such a solution has low efficiency. In this case:

 * 1 1 pt  f sa  L D1 (t)     4 16 2v1 v2   D2 (t)  0 (3.7)  

 f s (t)  f sa 

The region of (3.5) is named as SPS1, the region of (3.6) is named as DPS, and the region of (3.7) is named as SPS2. Here we will utilize all three regions together within a one- line period, as shown in Fig. 28. Here the grid voltage is 208VAC, the output voltage is 400

VDC and total transferred power is 4kW. The flow chart of VSF-SDPS control is shown in

Fig. 29.

D1 fs / Hz

t / S

Fig. 28 VSF-SDPS control@4kW.

SPS1 calculation D1_SPS1, 0, fs_SPS1

Yes If fs_SPS1 < fsa No

D = D 1 1_SPS1 DPS calculation D2 = 0 D1_DPS, D2_DPS, fs_DPS fs = fs_SPS1

If D2_DPS real && Yes (8.b) satisfied No

D = D 1 1_DPS SPS2 calculation D2 = D2_DPS D1_SPS2, 0, fs_SPS2 fs = fsa

D1 = D1_SPS2 D2 = 0 fs = fsa

End

Fig. 29 Flow chart of VSF-SDPS control over the one line period.

Compared with the VSF-DPS control method in chapter 3.1, when the switching frequency is fs< fsa, the phase-shift between the two legs of a secondary side is set to zero, which evolves the control into the VSF-SPS control, not only decreasing the control

complexity but also reducing the leakage inductance RMS current. When fs= fsa, the control strategy is changed to the VSF-DPS, especially around the zero-crossing point, which will control the instantaneous power and resolve the current distortion. Thus, the proposed control method can realize both ZVS and PFC over the whole line period under all-load conditions.

It is worthwhile to point out that the DPS is not a necessary region to realize both

ZVS and PFC; however, it can greatly reduce the reactive power and increase the system efficiency. Only with the SPS1 and SPS2 modulation, the ZVS and PFC could also be guaranteed over the whole line period. For this VSF-SPS control, D1(t) and fs(t) over the line period for the grid voltage is 208Vrms, output voltage is 400 VDC and total transferred power of 4kWrms is shown.

It is worthwhile to point out that DPS is not a necessary region to realize both ZVS and PFC; however, it can greatly reduce the reactive power and increase the system efficiency. Only with the SPS1 and SPS2 modulation, the ZVS and PFC could also be guaranteed over the whole line period. For this VSF-SPS control, D1(t) and fs(t) over the line period for the grid voltage is 208Vrms, output voltage is 400 VDC and total transferred power of 4kWrms is shown in Fig. 30.

When the switching frequency is saturated, the system operation mode will be switched from the SPS1 to SPS2 to maintain ZVS. However, compared with the DPS modulation, the SPS2 operation mode generates much more reactive power and sacrifices the system efficiency. Therefore the DPS is introduced in the proposed VSF-SDPS method to reduce the system’s reactive power, especially under light load conditions.

D1 fs / Hz

t / S

Fig. 30 VSF-SPS control@4kW.

Fig. 31 shows the operation time of the SPS1, SPS2 and DPS in terms of percentage over the one line period under different loads. The output voltage keeps 400V. Input voltage is 208VAC and the output voltage is 400VDC all the time. It can be clearly seen that when the system operates at medium or heavy loads, i.e., 3.5kW ~7.2W, the weight of DPS is 5%-

10%, the weight of the SPS2 is similar to the DPS, and the SPS1 takes most of the time.

Under light-load conditions, the DPS percentage increases rapidly. Under ultra-light load conditions, even only with the SPS1 modulation, the system can achieve ZVS and PFC at all times because the input voltage v1(t) is ultra-low and becomes the dominate factor of transferred power. In this case, the DPS and SPS2 are not necessary and the system will operate only with the SPS1 modulation to decrease the control complexity. All of the mode switches happened automatically by following the flow chart in Fig. 29.

Fig. 31 The operation time of each operation mode in terms of percentage under different loads. Vout = 400V.

Fig. 32 (a) and (b) show the operation time of the SPS1, SPS2 and DPS in terms of percentage under the constant-current charging mode with the input current being 15A and

35A, respectively. Under light- or medium-load conditions, the DPS has a larger percentage.

With the constant charging current, the percentage of the DPS control increases with the battery voltage going up.

Because the typical percentage of the DPS varies between 5%-40%, it is worth it to involve the DPS modulation to minimize the reactive power and increase the system efficiency, especially under light- or medium-load conditions, even though the control complexity will be increased a little bit.

Constant current mode Vg 208 VAC, Irms=15A 100% 10% 10% 11% 12% 12% 13% 14% 90% 15% 8% 9% 10% 10% 11% 80% 11% 12% 13% 70%

60%

50% DPS

40% 82% 81% 79% 78% SPS2 77% 76% 74% 73% 30% SPS1

Percntageperiodlineof 20%

10%

0% 300 320 340 360 380 400 420 440 Voltage / V

(a)

Constant current mode Vg 208 VAC, Irms=35A 100% 5% 5% 6% 6% 7% 7% 7% 8% 3% 3% 90% 3% 3% 4% 4% 4% 4%

80%

70%

60%

50% DPS 92% 91% 91% 90% 90% 89% 89% 88% 40% SPS2

30% SPS1

Percntageperiodlineof 20%

10%

0% 300 320 340 360 380 400 420 440 Voltage / V

(b)

Fig. 32 The operation time of each operation mode in terms of percentage under the constant-current charging mode. (a) Irms=15A; (b) Irms=35A.

3.2.2 Simulation Result

Simulation waveform is shown in Fig. 33 (a) ~ (d). The input voltage is 208VAC, the output voltage is 400VDC and the operation power is 2kW. Fig.13 (a) illustrates D1(t), D2(t), fs(t), primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the one line period. The zoomed in waveforms of the SPS1 are shown in Fig.

33 (b), of the DPS in Fig. 33 (c) and of the SPS2 in Fig. 33 (d). In Fig. 33 (b) and Fig. 33

(d), due to the SPS control, both vp and vs are square waveforms, which are consistent with the theoretical analysis shown in Fig. 28. In Fig. 33 (c), vp is a square waveform, and vs is a three-level waveform which corresponds to the DPS control, which are consistent with the analysis shown in Fig. 18.

D1, D2

(a)

vp / V

vs / V

iL / A

(b) (c) (d)

Fig. 33 (a)The waveforms of control variables D1(t), D2(t), fs(t), primary and secondary side transformer voltage vp and vs, and leakage inductance current iL over the one line period; (b) SPS1 region; (c) DPS region; (d) SPS2 region.

Fig. 34 checks the ZVS results during the SPS1, DPS and SPS2 operational regions.

All the switches of the primary side and secondary side can achieve ZVS turn-on over the whole line period. Note when the switch is on, the current is negative, indicating the ZVS turn-on. Therefore the turn-on loss is negligible.

ZVS turn-on ZVS turn-on

(a) (b)

ZVS turn-on

(c)

Fig. 34 ZVS checking of the primary side switch P1, P3, and secondary side switch S1, S3 during (a) SPS1 region; (b) DPS region; (c) SPS2 region.

The PFC and THD performance are simulated in Matlab/Simulink according to the parameters given in Table I. The input voltage is 208VAC, and the output voltage is 400VDC.

Operational power is 2kW. Simulated grid-side current, power, voltage, and battery voltage are shown in Fig. 35, which illustrates the instantaneous, input current Iin, input power Pin

and its reference Pref and its reference Iref, grid voltage vg, output current io and battery voltage vo over the one line period. The unity power factor is achieved.

Iin, Iref

Pin, Pref

Fig. 35 Grid-side current, power, voltage, and battery voltage using the proposed VSF-SDPS algorithm.

Comparison of the VSF-DPS and VSF-SDPS control methods are shown in Fig. 36.

There is a remarkable current distortion around the grid voltage zero-crossing point using the

VSF-DPS method. There is no current distortion for the VSF-SDPS methods. The input current THD comparison is done in Fig. 37. The proposed method has a much better input current THD than all of the power ranges.

VRef[2]SF-DPS 20 Current distortion 0

/ A

i -20 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 VF-DPSVSF-SDPS 20 No Current distortion 0

/ A

i -20 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 VF-SPStime / S 20 Fig. 36 The simulation waveforms of grid current i (1)VSF-DPS method; (2)VSF-SDPS method. 0 in

/ A

i -20 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 time /S

60.00% THD 50.00%

40.00%

30.00% VSF-SDPS 20.00% VSF-DPS

10.00%

0.00% 1kW 3kW 5kW 7kW Power

Fig. 37 THD comparison of VSF-DPS method and light load performance enhanced VSF-SDFS method.

3.3 DSP Implementation and Experiment Result

3.3.1 Digital Control Implementation Using DSP TMS320F28335

Texas Instruments (TI) C2000 DSP TMS320F28335 is implemented for the digital control of the VSF-DFS control. The controller design schematic is shown in Fig. 38. A

Controller Area Network (CAN bus) is a utilized to communicate with a host computer.

EPWM1 A/B EPWM3 A/B EPWM5 A/B EPWM2 A/B EPWM4 A/B EPWM6 A/B

Full Full Serial Full Filter Bridge Bridge Filter Inductor Bridge Of Of & Grid Load Transfor Side Side mer STY139N65M5 GS66516T GS66516T Grid 60kHz 150kHz~500kHz Load

ADCINA4 EPW1 A/B Unfolding Vg ADC_Vin PLL ePWM1&2 bridge control update EPW2 A/B

` EPW3 A/B ADCINA0 Vin ADC_Vin PWMDRV_2ch EPW4 A/B

EPW5 A/B ADCINA1 Iin ADC_Iin PWMDRV_3ch EPW6 A/B D1, D2, Fs ADCINA2 generator EPW5 A/B Vo ADC_Vo PWMDRV_3ch EPW6 A/B

ADCINA3 Io ADC_Io

Start-up & Protection

DSP CAN BUS

GPIO 61 -70

LED Array

Fig. 38 Single-stage AC/DC converter controlled by DSP TMS320F28335.

There are three interrupts: one ePWM interrupt, epwm1_timer_isr; two CPU-timer interrupts, cpu_timer0_isr and cpu_timer1_isr. The software flowchart for the DSP controller unit is shown in Fig. 39.

The most critical interrupt is epwm1_timer_isr, which is utilized to start the ADC conversion and realize the VSF-SDFS control and update the Enhanced Pulse Width

Modulator (ePWM) module. The interrupt requests are issued at every 3rd event. Since the switching frequency changes from 100kHz to 500kHz in this paper, the interrupt time varies from 6us to 30us.

The cpu_timer0_isr is utilized to realize the phase lock loop (PLL) calculation, system protection and CAN communication. The interrupt request is issued every 100us. The cpu_timer1_isr is utilized to debug and test. The interrupt request is issued every 10ms.

Start (Main)

Initialize interrupt Pietable & enable interrupts Initialize ePWM, ADC, CaN, timer

cpu_timer0_isr cpu_timer1_isr System check (100us) (10ms)

Digital filter Other test function epwm1_timer_isr (every 3rd event)

Do system protection Check system protection flag Update protection flag Read ADC

Normal Abnormal

Return Shut down CaN communication VF_SDFS calculation

PLL Update D1, D2, Fs

Check system protection flag Check system protection flag

Normal Abnormal Normal Abnormal Return Shut down Return Shut down

Fig. 39 Software flowchart for the DSP controller unit.

Considering there is one phase-shift between the primary side H-bridge and another phase-shift between two lags of the secondary side H-bridge, the time-base counter synchronization signal is needed to globally synchronize all enabled ePWM modules to the time-base clock (TBCLK). The time-base counter synchronization scheme for DSP

TMS320F28335 is shown in Fig. 40. [63]

Fig. 40 Time-Base Counter Synchronization schematic.

Changing switching frequency and multiple phase-shifts at the same time is a key feature of the VSF-DFS control algorithm. To realize this function, the DSP TSM320F28335 ePWM configuration needs special attention paid to it.

An abnormal wide pulse might appear at the phase-shift changing event and lead to a high current pulse which will damage the devices. The experiment waveform of this scenario is shown in Fig. 41. This abnormal wide pulse is inevitable when the ePWM modules use the up-down count mode.

Inductor current pulse vs Inductor current

vp Caused by abnormal ePWM

Fig. 41 High inductor current pulse caused by ePWM signal abnormal using the up-down mode ePWM configuration.

Seeing Fig. 42, the duty cycle is a fixed 50% based on the VSF-DFS control algorithm, therefore, CMPA = TBPRD/2. When the lag phase-shift changes from degree A

(90º

TBPHS_2(TBPHS_2< CMPA) , and the action-qualifier submodule triggered event CTR =

CMPA is skipped. When the lag phase-shift changes from degree A (0º

(90º

The lead phase-shift change scenario can be analyzed in a similar way. When the lead phase-shift changes from degree A (0º

(90º

TBPRD(value)

CMPA

UP UP UP UP CTR_dir

DOWN DOWN DOWN

EPWMxSYNCI

TBPRD(value)

45 degree lag CMPA To 135 degree lag

UP UP UP UP CTR_dir

DOWN DOWN DOWN

ePWM2

135 degree lag to 45 degree lag

UP UP UP UP

DOWN DOWN DOWN DOWN DOWN

ePWM3

Wide pulse

Fig. 42 An ePWM external synchronization event waveforms in the up-down mode with lag phase-shift changing.

TBPRD(value)

CMPA

UP UP UP UP CTR_dir

DOWN DOWN DOWN

ePWM1

EPWMxSYNCI

TBPRD(value)

45 degree lead CMPA To 135 degree lead

UP UP UP UP UP CTR_dir

DOWN DOWN DOWN DOWN

ePWM2

Wide pulse

TBPRD(value) 135 degree lead CMPA to 45 degree lead

UP UP UP

DOWN DOWN DOWN DOWN

ePWM3

Fig. 43 An ePWM external synchronization event waveforms in the up-down mode with the lead phase-shift changing.

Switching frequency changing has no contribution to this abnormally wide pulse problem. The specific analysis is shown below in Fig. 44 and Fig. 55.

TBPRD(value)

CMPA

EPWMxSYNCI

TBPRD(value)

CMPA 45 degree lead

UP UP UP UP CTR_dir

DOWN DOWN DOWN DOWN

ePWM2

135 degree lead

UP UP UP UP

DOWN DOWN DOWN DOWN DOWN

ePWM3

Fig. 44 An ePWM external synchronization event waveforms in the up-down mode, frequency changing, lead phase-shift.

TBPRD(value)

CMPA

EPWMxSYNCI

TBPRD(value)

CMPA 45 degree lag

UP UP UP UP CTR_dir

DOWN DOWN DOWN DOWN

ePWM2

135 degree lag

UP UP UP UP UP

DOWN DOWN DOWN DOWN DOWN DOWN ePWM3

Fig. 45 An ePWM external synchronization event waveforms in up-down mode, frequency changing, lag phase-shift.

In our application, all of the scenarios shown in Fig. 42 and Fig. 43 could happen.

Therefore, if the up-down mode is utilized, the abnormal wide pulse is inevitable. The

solution is using the combination of the up-mode and the down-mode instead of the up-down mode.

It is similar with the up-down mode analysis, using up mode, the lead phase-shift changes from degree A (0º

(0º

47. Using down mode, the result is reversed.

TBPRD(value)

CMPB

CMPA

ePWM1

EPWMxSYNCI

TBPRD(value) CMPB 45 degree lead CMPA To CMPA 135 degree lead

ePWM2

Wide pulse

TBPRD(value) CMPB 135 degree lead CMPA to 45 degree lead CMPA

ePWM3

Fig. 46 An ePWM external synchronization event waveforms in up mode with lead phase-shift changing.

TBPRD(value)

CMPB

CMPA

ePWM1

EPWMxSYNCI

TBPRD(value) CMPB 45 degree lag CMPA To CMPA 135 degree lag

ePWM2

TBPRD(value) CMPB 135 degree lag CMPA to 45 degree lag CMPA

ePWM3

Wide pulse

Fig. 47 An ePWM external synchronization event waveforms in up mode with lag phase-shift changing.

Therefore, when the lead phase-shift changes from degree A (0º

(90º

changes from degree A (0º

3.3.2 VSF-SDPS Control Experiment Result

The prototype of the isolated indirect matrix converter based 7.2kW on-board EV- charger is shown in Fig. 48. The top-cooled GaN devices GS66516T are under the heat sink.

The charger dimension without the output active filter is 171.2*261.4*48mm3 yielding a power density of 3.43kW/L.

Transformer Inductance

Heat sink

DAB board Front-end and passive component board Control board

Fig. 48 Prototype of the indirect matrix converter based on-board charger.

Since the proposed control algorithm is good at the light-load performance improvement, a 200W test was first carried out, as shown in Fig. 49. Under this ultra-light load, there is remarkable current distortion around the grid voltage zero-crossing point using the VSF-DPS method. However, there is no current distortion using the proposed VSF-SDPS control method. The experimental results match the theoretical analysis.

Large current distortion

Vin

Iin

(a) VSF-DSF

No current distortion

Vin

Iin

(b) proposed VSF-SDPS

Fig. 49 The experiment waveforms of vin and iin over three line period.

Fig. 50 (a) and (b) illustrates the simulation and experiment waveforms of the VSF-

SDPS method, respectively illustrating the primary and secondary side transformer voltage vp and vs, and leakage inductance current iL. The experiment result matches the simulation result well.

(a) VSF-SDPS control, simulation

SPS1 DPS DPS SPS2 SPS2

(b) VSF-SDPS control, experiment

Fig. 50 The waveforms of the VSF-SDPS control primary and secondary side transformer voltage vp and vs, and leakage inductance current iL.

The zoomed in waveforms of the SPS1, DPS and SPS2 region are shown in Fig. 51

(a), (b) and (c) respectively.

Fig. 51 The zoomed in waveforms of VSF-SDPS control primary and secondary side transformer voltage vp and

vs, and leakage inductance current iL @total transferred power 200Wrms.

ZVS

(a) SPS1 vp vs iL

ZVS

(b) DPS

vp vs iL

ZVS

In the regions of the SPS1 and SPS2, both of the primary and secondary side transformer voltages vp and vs are square waveforms. During the dead band, the body diode of the switch is turned on adding a small plateau on vp or vs, indicating ZVS. The phase shift in the SPS2 region is much larger than the SPS1 region, because more reactive power is generated for the low power operation.

In the DPS region, the primary-side transformer voltage vp is a square wave and the secondary side voltage vs is a three-level waveform. Similar to the analysis above, ZVS is secured in the DPS region too.

Fig. 52 (a) and (b) illustrate the simulation and experimental waveforms of the VSF-

SPS method, respectively. The experiment result matches the simulation result well.

Comparing the VSF-SDPS control to the VSF-SPS control described in Fig. 30, there is an obvious current decrease during the DPS region using the VSF-SDPS control and no such region using the VSF-SPS control, which indicates a lower rms iL current is using the DPS control.

(a) VSF-SPS control, simulation

SPS1

SPS2 SPS2

(b) VSF-SPS control, experiment

Fig. 52 The waveforms of the VSF-SPS control primary and secondary side transformer voltage vp and vs, and

leakage inductance current iL @200Wrms.

3.4 Conclusion

In this chapter, two variable-frequency controls, the VSF-DPS and VSF-SDPS, are proposed for the presented single-stage AC/DC topology, which can reach the unity power factor and maintain ZVS at the same time. Comparing to the VSF-DPS control, the VSF-SDPS method significantly improved the THD performance under light load conditions. The theoretical analysis, simulation result and experiment result are provided. The digital controller implementation and limitation using the DSP TMS320F28335 for variable- frequency and phase-shift control is discussed.

Chapter 4. Power loss breakdown and system

optimization

4.1 Semiconductor loss

Considering the semiconductor loss, it can be divided into 6 parts: primary side conduction loss, primary side dead band loss, primary side switching loss, secondary side conduction loss, secondary side dead band loss and secondary side switching loss. The semiconductor loss of the DAB is calculated according to the parameters given in Table 4.

4.1.1 VSF-DFS control semiconductor loss

For the DPS control, the primary side and secondary side conduction loss can be calculated from (4.1) - (4.3), respectively. Here Rdson is the channel resistance of one switch, iL is the leakage inductance current, and Tdb is the dead-band time.

1   T db 2 fsw ( ) (4.1) ePcon _ sps( )  eScon_ sps( )  2 Rdson  iLsps(t, ) dt 

1   T db 2 fsw ( ) (4.2) ePcon _ dps( )  eScon_ dps( )  2 Rdson  iLdps(t, ) dt 

 Tg PPcon  PScon  2 Rdson  ePcon ( ) Tg 1 (4.3)    fsw ( )

The switching energy can be calculated using (4.4). The parameter α is estimated from the GaN Devices double pulse test experiment.

1 e  V  I t   V  I (4.4) sw 2 DS Ds on DS Ds

For the DPS, the primary side and secondary side switching energy in the one switching period are shown in (4.5) and (4.6), respectively.

ePsw_ dps  2 (iLdps(t0 ,)(v1())  iLdps(t3,)v1()) (4.5)

eSsw_ dps   (iLdps(t1 ,)  v2 ()  iLdps(t4 ,)  (v2 ())  iLdps(t5 ,)  (v2 ())) (4.6)

Therefore, the average switching power loss is shown in (4.7).

 Tg 1 P  e ( )  T sw  sw g (4.7) 1 f ( )    sw f sw ( )

The dead band loss for the one switching can be calculated using (4.8). The parameter

β is estimated from the double pulse test result, and the dead-band time is 200ns.

edb    IDs (4.8)

For the DPS, the primary and secondary side dead-band energy in the one switching period is shown in (4.9) and (4.10), respectively.

ePdb_ dps()  2  (| iLsps(t0 ,) |  | iLsps(t3,) |) (4.9)

eSdb_ sps()   (| iLsps(t1,) |  | iLsps(t2 ,) |  | iLsps(t4 ,) |  | iLsps(t5,) |) (4.10)

Therefore the average dead-time loss power over the one line period is shown in

(4.11).

 Tg 1 Pdb   edb( ) Tg (4.11) 1 f ( )    sw f sw ( )

4.1.2 VSF-SDFS control semiconductor loss

For both the SPS and DPS, the primary side and secondary side conduction loss can be calculated using (4.12) - (4.14), respectively. Here Rdson is the channel resistance of the one switch, iL is the leakage inductance current, and Tdb is the dead-band time.

1   T db 2 fsw ( ) (4.12) ePcon _ sps( )  eScon_ sps( )  2 Rdson  iLsps(t, ) dt 

1   T db 2 fsw ( ) (4.13) ePcon _ dps( )  eScon_ dps( )  2 Rdson  iLdps(t, ) dt 

 Tg PPcon  PScon  2 Rdson  ePcon ( ) Tg 1 (4.14)    fsw ( )

The switching energy can be calculated using (4.15). The parameter α is estimated from the double pulse test data.

1 e  V  I t   V  I (4.15) sw 2 DS Ds on DS Ds

For the SPS, the primary side and secondary side switching energy in the one switching period are shown in (4.16) and (4.17), respectively.

ePsw_ sps()  2 (iLsps(t0 ,)(v1())  iLsps(t2 ,)v2 ()) (4.16)

eSsw_ sps()  2 (iLsps(t1,)v2 ()  iLsps(t3,)(v2 ())) (4.17)

For the DPS, the primary side and secondary side switching energy in the one switching period are shown in (4.18) and (4.19), respectively.

ePsw_ dps  2 (iLdps(t0 ,)(v1())  iLdps(t3,)v1()) (4.18)

eSsw_ dps   (iLdps(t1 ,)  v2 ()  iLdps(t4 ,)  (v2 ())  iLdps(t5 ,)  (v2 ())) (4.19)

Therefore the average switching power loss is shown in (4.20).

 Tg 1 Psw   esw( )  Tg (4.20) 1 f ( )    sw f sw ( )

The dead band loss for the one switching can be calculated using (4.21). The parameter β is estimated from the DPT, and the dead-band time is 200ns.

edb    IDs (4.21)

For the SPS, the primary and secondary side dead-band energy in the one switching period is shown in (4.22) and (4.23), respectively.

ePdb_ sps()  2  (| iLsps(t0 ,) |  | iLsps(t2 ,) |) (4.22)

eSdb_ sps()  2  (| iLsps(t1,) |  | iLsps(t3,) |) (4.23)

For the DPS, the primary and secondary side dead-band energy in the one switching period is shown in (4.24) and (4.25), respectively.

ePdb_ dps()  2  (| iLsps(t0 ,) |  | iLsps(t3,) |) (4.24)

eSdb_ sps()   (| iLsps(t1,) |  | iLsps(t2 ,) |  | iLsps(t4 ,) |  | iLsps(t5,) |) (4.25)

Therefore the average dead-time loss power over the one line period is

 Tg 1 Pdb   edb( ) Tg (4.26) 1 f ( )    sw f sw ( )

4.2 Magnetic Loss

Besides the semiconductor loss, the magnetic loss is also a major part of the total loss and has a significant impact on the system efficiency. In this application, there are three challenges to accurately calculate the total magnetic loss. First, due to the variable operation frequency, the total magnetic loss during the one switching period is variable with the switching frequency changing. Second, the nonlinear load makes the magnetic loss hard to estimate. Third, the transformer is very hard to optimize since the operation frequency various from 100kHz to 500kHz, which is relatively large.

In this section, a fast and practical transformer loss calculation approach is proposed for the VSF-SDFS control method. There are 4 assumptions: 1) the core material should be applicable for high frequency design (100-500kHz); 2) the transformer turn ratio is 1:1; 3) by using the proper Litz wire, the eddy current losses are low; 4) in the one switching period, the transformer current is assumed to be a pure sinusoidal current with the same Irms to the actual transformer current.

There are two major types of transformer losses, no load loss and load loss as shown in (4.27). [64]–[67] In the following sections, they will be calculated separately.

(4.27) PT  PNL  PLL

4.2.1 No Load Loss

No load loss (core loss or excitation loss) appears because of the electromagnetic flus

[64] passing through the core varies all the time. No Load loss PNL depends on the peak AC flux density ΔB, operation frequency f, and the volume of the core Vc, which can be described by the generalized Steinmetz equation (GSE) (4.28). [66] [67] Where k, α and β are the Steinmetz parameters, which are given or curve fitted by the manufacturer’s datasheet.

^   (4.28) PNL  k fill ,cVc  k  f  B

4.2.2 Load Loss

Load loss (impedance loss) can be divided into the ohmic copper loss (I2R loss) and

the stray loss. [64]–[67] The total load loss PL can be stated as shown in equation (4.29).

2 (4.29) PL  I RDC  PEC  POSL

Where PEC is the winding eddy-current loss and POSL is the other stray loss.

The total load loss PL can also be stated by the ac winding resistance RAC:

2 (4.30) RAC  PL / I

In a decent transformer design, the load loss is close to the no load loss:

(4.31) PL  PNL

To distribute the allowed load loss among primary and secondary windings, a coefficient αi is introduced:

(4.32) N i  I rms,i  i  n N  I  i rms,i i1

(4.33) PL,i i  PL

Where PL,i is the load loss of the ith winding, Irms,i is the RMS current of the ith winding.[66]

In our design, the transformer turn ratio is intentionally designed to 1:1 in order to simplify the ZVS condition and decrease the control complexity. Therefore, the relationship of primary winding load loss PLP, the secondary winding load loss PLS and the total load loss can be described as the equation in (4.34):

1 P  P  P (4.34) Lp Ls 2 L

In this application, since the switching frequency is relatively high (150kHz –

500kHz), we use the Litz wire for our transformer design.

The empirical data of ratios of AC resistance to DC resistance for an isolated solid round wire (H) in terms of a value (X) are shown in Table 5. [68][69]

Table 5 Ratios of RAC / RDC for an isolated solid round wire (H) in terms of a value (X)

X 0 0.5 0.6 0.7 0.8 0.9 1.0

H 1.0000 1.0003 1.0007 1.0012 1.0021 1.0034 1.005

The individual wire gauge can be chosen from Table 6 provided by the manufacturer based on the operating frequency. [68][69]

Table 6 Frequency vs recommended Litz Wire

FREQUENCY RECM’D NOM, DIA, DC RES SINGLE STAND

WIRE GAUGE OVER COPPER OHMS/M’ (MAX) Rac/Rdc “H”

(D1)

60Hz to 1kHz 28 AWG 0.0126 66.37 1.0000

1kHz to 10kHz 30 AWG 0.0100 105.82 1.0000

10kHz to 20kHz 33AWG 0.0071 211.7 1.0000

20kHz to 50kHz 36AWG 0.0050 431.9 1.0000

50kHz to 100kHz 38AWG 0.0040 681.90 1.0000

100kHz to 200kHz 40AWG 0.0031 1152.3 1.0000

200kHz to 350kHz 42AWG 0.0025 1801.0 1.0000

350kHz to 850kHz 44AWG 0.0020 2873.0 1.0003

850kHz to 1.4MHz 46AWG 0.0016 4544.0 1.0003

1.4MHz to 2.8MHz 48AWG 0.0012 7285.0 1.0003

After the wire gauge and the particular Litz wire construction has been chosen from

Table 6 and the manufacturer’s product list, the ratio of Rac to Rdc of this Litz wire can be determined from the equation in (4.35). [68][69]

R N  D (4.35) ac  H  K ( 1 )2 G Rdc D0

Where:

H is from Table 5;

G is the eddy-current basis factor which is determined by equation (4.36);

N is the number of strands in one Litz cable;

D1 is the diameter of one strand over the copper in inches, which can be found in

Table 6;

D0 is the diameter of the finished cable over the strands in inches which can be found in the manufacturer’s Litz wire product datasheet;

K is the constant depending on N, which can be found in Table 7. [68][69]

4  D  f  (4.36) G   1     10.44 

Table 7 Constant k vs N

N 3 9 27 Infinity

K 1.55 1.84 1.92 2

4.2.3 Design Example

Because most of the time the operation frequency is between 150kHz to 200kHz, we choose the core E100/60/28-3C95 from the FERROXCUBE[70]. Based on the datasheet, the effective core parameters of E100/60/28 core sets are shown in Table 8. [70] The dimensions of the E100/60/28 core half are shown in Fig. 53.

Table 8 E100/60/28 effective core parameters

Symbol Parameter Value Unit

Core factor (C1) 0.371 mm-1 I / A

3 Ve Effective volume 202000 mm

Ie Effective length 274 mm

2 Ae Effective area 738 mm

2 Amin Minimum area 692 mm m Mass of core half 493 g

Fig. 53 E100/60/28 core half.

Therefore, the transformer core effective area AeT is:

4 2 (4.37) AeT  Ae  7.3810 m

The transformer core window area AwT is:

73.15 27.5  46.85 (4.38) A  2  1000 1000  2.139103 m2 wT 1000 2

The transformer core effective length LeT is:

3 (4.39) LeT  le  27410 m

The transformer core effective volume VeT is:

4 3 (4.40) VeT Ve  2.02210 m

Based on the 3C95 material datasheets [70] and [71], the typical B-H loops are shown in Fig. 54.

Fig. 54 Typical B-H loops.

Design of the peak ac flux density ΔB = 300mT. Based on the VSF-SDFV control method in previous sections, the maximum voltage across primary winding is Vpt_pk =

294.156V, and the minimal operation frequency is around 100 kHz. Therefore, the maximum volt-seconds applied during the positive portion of the waveform is:

V (4.41)   pt_ pk 1.471103V  S 2 f sw _ min

The turn of the primary winding is:

 (4.42) N p   3.322  3 2B AeT

Since the turn ratio is 1:1, the turn of the secondary winding is:

(4.43) Ns  N p  3

Based on the 3C95 material datasheets [70] and [71], the specific power loss as a function of peak flux density with frequency as a parameter is shown in Fig. 55.

Fig. 55 Specific power loss as a function of peak flux density with frequency as a parameter.

The Steinmetz parameters k, α and β are curve fitted by the manufacturer’s datasheet.

The list of curve fitting points and the curve fitting results are listed below. [64], [66], [72]

Table 9 List of curve fitting points

B(mT) 30 40 90 50 70 200 90 200 300

Pv(kW/m3) 30 70 500 20 50 1000 30 300 1000 f(kHz) 400 400 400 200 200 200 100 100 100

7 k  5.038310 (4.44)   1.584    2.466

So the no load loss over the line period with variable frequency can be calculated by the generalized Steinmetz equation (4.28).

For the Litz wire design, we choose 42 AWG from Table 6 because our operation frequency is from 100kHz to 500kHz. We assume the transformer window utilization is 0.7.

The circular area of one Litz cable is:

A 0.7 (4.45) Circular _ area  wT  2.495104 m2  3.867105 mil 2 N p  N s

From the litz wire type table provide by the manufacturer, a Litz wire 6(5x5/28/24) is chosen in this application.[68]

Thus, based on this equation (4.35):

(4.46) D1 2 f sw 4 Rac  Rdc [H  K(N ) (D1 ) ] D0 10.44

2  0.0025  f sw  0.468[1.0003 24200  (0.0025 ) 4 ]ohm /1000 ft  0.0287  10.44

The AC resistance of primary side and secondary side are shown in equation (4.47) and (4.48) respectively:

3.28084 (4.47) R  L  N  R  ohm ac_ p eT p ac 1000

3.28084 (4.48) R  L  N  R  ohm ac_ s eT s ac 1000

We assume during one switching period, the transformer current RMS value is Irms(t), then the load loss of the transformer is:

2 (4.49) Pload (t)  I rms (t) (Rac_ p  Rac_ s )

4.3 Full Load Loss Breakdown

4.3.1 VSF-DFS control loss breakdown

In this section, the system parameters are designed according to Table 4. Based on equations (4.12) ~ (4.49), the semiconductor loss break down of the proposed VSF-DPS control method is shown in Fig. 56. The efficiency increases gradually with the increasing of the power level. From 2kW to 8kW, the efficiency is 92.79% - 95.78%. Semiconductor loss is slightly smaller than magnetic loss, at around 42.6% to 48.6%. In this case, the peak efficiency achieved is at full load. The no load loss of the transformer is the largest loss factor. To reduce no load loss, the transformer must increase its core size and leads to lower the power density of the whole system.

Fig. 56 VSF-DSF control loss breakdown@ Vg = 208VAC, Vo = 400VDC, fsa=500kHz, Lδ=12uH.

In Fig. 57, each type of power loss is expressed as a percentage of the total transferred power. As the total power is increased, the average switching frequency is decreased, therefore, the primary conduction loss, primary switching loss, secondary switching loss, primary deadband loss, secondary deadband loss, transformer no load loss and load loss are decreased. Meanwhile, the secondary conduction loss is increased. Thus, the whole system efficiency is almost constant when the total power is around or higher than the nominal power of 7.2kW. In this case, the no load loss is significantly larger than any other losses.

Fig. 57 Loss percentage of total power using the VSF-DFS control.

4.3.2 VSF-SDFS control loss breakdown

In this section, the system parameters are designed according to Table 4. Based on equations (4.12) ~ (4.49), the semiconductor loss break down of the proposed VSF-DPS control method is shown in Fig. 56. The efficiency increases gradually with the increasing of the power level. From 2kW to 8kW the efficiency is 89.15% - 95.18%. Semiconductor loss is relatively larger than magnetic loss, at around 50% to 59.7%. In this case, the peak efficiency achieved is at full load. The no load loss of the transformer is the largest loss factor. To reduce no load loss, the transformer must increase its core size and this leads to a lower power density of the whole system.

Compared with the VSF-DFS control, the VSF-SDFS control has a slightly lower efficiency, at around 3% at light load conditions, and at about 5% around medium and heavy

load conditions. Because of using the VSF-SDFS control, more reactive power is intentionally generated in order to achieve the unity power factor.

Fig. 58 VSF-SDSF control loss breakdown@ Vg = 208VAC, Vo = 400VDC, fsa=500kHz, Lδ=12uH.

In Fig. 59 , each type of power loss is expressed as a percentage of total transferred power. As the total power is increased, the average switching frequency is decreased, therefore the primary conduction loss, primary switching loss, secondary switching loss,

primary deadband loss, secondary deadband loss, transformer no load loss and load loss are decreased. Meanwhile, the secondary conduction loss is increased. Thus, the whole system efficiency is almost constant when the total power around or higher than the nominal power is 7.2kW. In this case, the no load loss is slightly larger than any other losses.

Fig. 59 Loss percentage of total power using the VSF-SDFS control.

4.4 System optimization

In this application, the system efficiency not only depends on the hardware design, but also depends on the control algorithm. There are two key parameters, saturation switching frequency fsa and transformer leakage inductance Lδ, that can be utilized to optimize the whole system efficiency. In this section, we optimize the system based on the

VSF-SDFS control method.

Based on the equations (3.5) (3.6)and (3.7), we can find the saturation fsa will change the percentage of the SPS1, SPS2 and DPS modulation, it therefore influences the average operational frequency and the average current RMS value. With higher fsa, the regions of the

DPS and SPS2 are smaller, therefore there is less reactive power generated. Meanwhile, the average switching frequency fsa is higher.

Based on the equations (2.1) and (2.9), we can find the leakage inductance Lδ will directly influence the switching frequency. The higher Lδ corresponds to the lower switching frequency fs.

The system efficiency at full-load is 7kW, Vin 208VAC, Vout 400VDC, with different saturation frequency fsa and leakage inductance Lδ are shown in Fig. 60. The highest efficiency is achieved at around Lδ ∊ (11uH, 15uH), and fsa ∊ (200kHz, 400kHz). Compared to leakage inductance Lδ, the saturation frequency fsa has a much smaller influence. It should be pointed out that when fsa is less than 200kHz and Lδ is smaller than 6uH, the whole system efficiency decreases dramatically.

Fig. 60 Efficiency with different fsa and Lδ @7kW.

The relationship between full-load efficiency and the leakage inductor Lδ under different fsa scenarios is shown in Fig. 61. The efficiency goes up rapidly with the increasing

Lδ, however, when Lδ is larger than 8uH, further increasing Lδ it won’t have much influence on the system efficiency; when Lδ is larger than 16uH, the system efficiency has slightly decreased, with Lδ increasing. With the same Lδ, the higher fsa will lead to higher system efficiency.

1.2

0.8

0.6

fsa=200000Hz

efficiency 0.4 fsa=250000Hz fsa=300000Hz 0.2 fsa=350000Hz fsa=400000Hz fsa=450000Hz 0 fsa=500000Hz

-0.2 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Lf / H -5 x 10

Fig. 61 Efficiency v.s. Lδ under different fsa scenarios.

The contour plots of the system efficiency from 8kW to 2kW are shown in Fig. 62

(a) – (g). With the comprehensive consideration of the system efficiency, device limit and power density limit in this application, an optimized design for the VSF-SDFS control should be:

(4.50)  fsa [350kHz,500kHz]  L [12uH,14uH ]

100

Fig. 62 Contour plots of efficiency of the VSF-SDFS control method under different load condition with Vin=208VAC, Vout=400VDC (a)8kW; (b)7kW; (c)6kW; (d)5kW; (e)4kW; (f)3kW; (g)2kW.

101

5 x 10 8kW efficiency 5

0.95

0.93 0.935 0.945 4.5 0.94

0.93

0.95 3.5 0.95

0.94

0.935 0.945

Fsa / Hz

0.95 2.50.925

0.935 0.945 0.93 0.94 0.95

2 0.5 1 1.5 2 leakage inductance / H -5 x 10 (a)

5 x 10 7kW efficiency 5

0.95

4.5 0.93 0.94

0.93 0.95 3.5 0.95

0.94

Fsa / Hz

0.92 3

2.5 0.95 0.91

0.93 0.94 0.95

2 0.5 1 1.5 2 leakage inductance / H -5 x 10 (b)

102

5 x 10 6kW efficiency 5

0.92 4.5 0.91 0.93 0.94

0.91 0.93 3.5 0.92

0.94

Fsa / Hz

0.9 0.95

2.50.89

0.88 0.91 0.92 0.93 0.94

0.95

2 0.5 1 1.5 2 leakage inductance / H -5 x 10 (c)

5 x 10 5kW efficiency 5

4.5 0.9

0.92 0.94

3.50.88

0.92 0.9

Fsa / Hz

0.94 3

0.86

2.5 0.84 0.88 0.9 0.92 0.94

2 0.5 1 1.5 2 leakage inductance / H -5 x 10 (d)

103

5 x 10 4kW efficiency 5

4.5 0.85

0.9 4

3.5

Fsa / Hz 0.85

3 0.9

0.8

2.5 0.75 0.85 0.9 2 0.5 1 1.5 2 leakage inductance / H -5 x 10 (e)

5 x 10 3kW efficiency 5

0.85 4.5 0.8

0.9

0.75 4

3.5 0.7

0.85

Fsa / Hz 0.8

0.9

3 0.75 0.65

0.6 2.50.55

0.7 0.5 0.85 0.8 0.9

2 0.5 1 1.5 2 leakage inductance / H -5 x 10 (f)

104

5 x 10 2kW efficiency 5

0.5

0.6

0.7 0.8

4.5 0.9

0.4

0.5 3.5 0.6

0.7 0.8

Fsa / Hz 0.9

0.4 3

0.3

2.5

0.5 0.6 0.7 0.8 0.9

2 0.5 1 1.5 2 leakage inductance / H -5 x 10 (g)

105

4.5 Conclusion

In this chapter, a detailed semiconductor loss breakdown and magnetic loss breakdown are presented. A practical transformer design example is proposed for the VSF-

SDPS control. The system optimization under different load conditions is discussed. A switching frequency saturation fsa and leakage inductance optimized design is derived based on the system loss breakdown.

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Chapter 5. Full-order State-space Modeling of

Variable-switching-frequency and Phase-shift

Dual-active-bridge Control and the System

Dynamic Analysis Considering the Influence of

DC Blocking Capacitance

The DAB DC/DC converter is a key component in electric vehicles to manage power flow. Its averaged model and the small-signal model have been studied in-depth for decades.[59], [60], [73]–[76]Although these models can handle the constant-frequency DAB control well, they overlook the influence of the DC blocking capacitor and assume there is no DC offset of the inductor current, which actually has a big influence on ZVS conditions using variable-frequency control.

It is different from the conventional constant-frequency and phase-shift control, in which input voltage and output voltage are limited into a very narrow operational range, in this paper, the DAB input voltage is a rectified sinusoidal waveform which keeps changing from 0 to peak. Therefore, with the proposed VSF-SDFS control, there always are sinusoidal excitations coming from the DAB input voltage and the control variables, switching frequency and phase-shift. In this case, the DC blocking capacitor’s influence is not

107

negligible and there will be a low frequency oscillation of inductor current. Since the inductor current is designed to only have a high switching frequency current component, in the one switching period, the low frequency oscillation performance is like a DC offset and may lead to losing the ZVS. Therefore, a full-order continuous time average model of the

DAB is proposed in this chapter, and the influence of the DC blocking capacitor has been taken into consideration. [77]

5.1 Full-order Continuous Time Average Modeling of Dual-active-bridge

Using Time-varying-state-space Method

The proposed single-stage AC/DC converter with the PFC utilized for the EV on- board charger shown in Fig. 14 can be simplified into Fig. 63. In order to simplify the analysis, the semiconductors are assumed to be ideal switches, where no conduction resistance is concerned. The transformer is shown as its equivalent leakage inductance Lδ and winding resistance Rf, and its turn ratio is 1:1. The DC blocking capacitance is Cb. The voltages on the two sides of the transformer are v1, and v2, respectively. The grid voltage is

Vg and the battery voltage is Vo. The control method is a VSF-SPS control.

vb iL Sp1 Sp3 Cb Ss1 Ss3 Rδ Ro Rg v1 vp Lδ vs v2 C1 C2

Vg Vo Sp2 Sp4 Ss2 Ss4

Fig. 63 The simplified DAB circuit.

108

The voltage at the transformer input side, vp, can only have two states: 1) +Vg when transistors Sp1 and Sp4 are ON; and 2) − Vg when transistors Sp2 and Sp3 are ON. The voltage at the transformer output side, vs, can only have two states: 1) +Vo when transistors Ss2 and

Ss3 are ON; and 2) − Vo when transistors Ss1 and Ss4 are ON. Therefore,

v p (t)  S1 (t)Vg (5.1)

(5.2) vs (t)  S2 (t)Vo

where the switching function at input bridge, S1(t), is:

 Ts 1 0  t  S (t)  2 (5.3) 1  T 1 s  t  T  2 s

and the switching function at output bridge, S2(t), is:



1 0  t  d Ts  1 S2 (t)  1 d Ts  t  (d  ) Ts (5.4)  2 1 1 (d  ) T  t  T  2 s s

where Ts is the switching period which varies over the line period.

If we select the input capacitor voltage v1, output capacitor voltage vs, transformer current iL and DC blocking capacitor voltage, vb , as state variables, then the state equations of a DAB converter can be derived as:

109

dv1 1 vg  v1   [  s1 iL ] (a) dt C R  1 g dv 1 v  v 2  [s i  2 g ] (b)  dt C 2 L R  2 o (5.5) di  L 1  [s1 v1  R iL  vb  s2 v2 ] (c)  dt L dv i  b  L (d)  dt Cb

Equations (5.5) are time-varying and nonlinear. The next step is to apply averaging to derive a linear model. The fundamental idea behind averaging is to represent a state variable, x(τ), during the interval t ≤τ ≤t+ T, using its’ Fourier series:

 jkw  x( )   x  (t)e s  k (5.6) k

Where s  2f s , and is a complex number  x k (t) is the kth coefficient in the Fourier series:

1 tT  jks   x k (t)  x( )e d t T (5.7) 1 tT 1 tT  x( )cos(k s )d  j x( )sin(k s )d T t T t

The generalized averaging model uses more terms in the Fourier series to represent more details in the model. In this paper, we use both k =0 and k = ±1 terms in the Fourier series to represent the averages of the DAB state variables iL and vb. Since the input capacitor and output capacitor are relatively large, in order to simplify the analysis, the dynamic of the input voltage v1 and output voltage v2 are not taken into consideration in this chapter. The derivate of state variables and switching functions are shown below:

110

iL (t)  iL 0  iLs  sin(ws t)  iLc  cos(ws t)  vb (t)  vb 0  vbs  sin(ws t)  vbc  cos(ws t)  (5.8) S (t)  S  sin(ws t)  S  cos(ws t)  1 1s 1c  S 2 (t)  S 20  S 2s  sin(ws t)  S 2c  cos(ws t)

Applying (5.3) and (5.4) into (5.7), then comparing with (5.8), we can get the coefficients below:

4 S  (5.9) 1s 

(5.10) S1c  0

4cos(2D) S  (5.11) 2s 

4sin(2D) S  (5.12) 2c 

According to Ref [74], the derivative of the kth coefficient for the variable x is:

d d  x  (t)  x  (t)  jk  x  (t) (5.13) dt k dt k s k

d Where  x  is the average of the differential of a state variable x. dt k

The kth coefficient of the product of the two variables x and y is:

 xy 0  x 0  y 0 2( x 1R  y 1R   x 1I  y 1I ) (5.14)

And the derivatives of the first order coefficient terms for variable x and y are:

 xy 1R  x 0  y 1R   x 1R  y 0 (5.15)

 xy 1I  x 0  y 1I   x 1I  y 0 (5.16)

111

Where the subscripts “R” mean the real parts of the complex number and the subscripts “I” mean the imaginary parts of a complex number.

Applying Fourier series (5.13) - (5.16) into state-space equations (5.5.c) and (5.5.d), the zero and 1st coefficients of the state variables iL and vb are:

diL0 1  (R iL0  vb0 ) (5.17) dt L

diLs 1 (5.18)  (S1s v1  R iLs  vbs  S2s v2 )  siLs dt L 1 4 4cos(2d)  ( v1  R iLs  vbs  v2 )  siLs L  

diLc 1 (5.19)  (S1c v1  R iLc  vbc  S2cv2 ) siLc dt L 1 4sin(2d)  (R iLc  vbc  v2 ) siLc L 

dvb0 1  iL0 (5.20) dt Cb

dvbs 1  iLs svbc (5.21) dt Cb

dvbc 1  iLc svbs (5.22) dt Cb

Organize (5.17) - (5.22) and we can get the state space equations:

112

 R 1     0 0 0 0  L L       1  0 0  i   0 0 0 0 0   L0    iL0     Cb 0 0         vb0 v 4  4  cos(2   d) R 1  b0      0 0    0    s   i   L L  iLs   L   L  v1  Ls                 4  sin(2   d)    (5.23) R 1 i v i  Lc  0  2   Lc   0 0   s  0        L    L L  v     v bs  bs   1     0 0   v     0 0 0 0  s   bc    vbc C 0 0    b    1  0 0 0   0   s   Cb 

In (5.23), when there is a small perturbation in d, v1 and v2, the state variables iL0, vb0, iLs, iLc, vbs, and vbc will deviate from their steady states. Define the deviations of control variables and state variables as:

v1  Vg  vg (5.24)

(5.25) v2  Vo  vo

(5.26) iL0  IL0  iL0

(5.27) iLs  ILs  iLs

(5.28) iLc  ILc  iLc

(5.29) vb0 Vb0  vb0

(5.30) vbs Vbs  vbs

(5.31) vbc Vbc  vbc

(5.32) vbc Vbc  vbc

d  D  d (5.33)

(5.34) s Ws  s

113

Where capital variables represent steady states, and ∆ variables mean small- signal states. Substitute (5.24) - (5.34) into state space equations (5.23), and organize the linearized state space equations into a matrix DC model (5.35) and a small-signal model (5.36).

 R 1     0 0 0 0  L L       1   0 0  0 0 0 0 0 I 0    L0    Cb 0 0         0 R 1 Vb0 4  4  cos(2   d)    0 0     0      0 s I    L   L  V   L L  Ls   g           4  sin(2   d)     (5.35) R 1 I V 0  Lc  0  o   0 0   s  0       L L     L 0     Vbs      1     0 0  0 V   0 0 0 0  s  bc     C  0 0  b    1  0 0 0   0   s   Cb 

 R 1     0 0 0 0  L L       1  0 0 0 0  i   0 0 0 0 0   L0  iL0      C  0 0 0 0    b      vb0 v 4  4  cos(2   D) 8sin(2   D) V v  R 1  b0  o g     0 0  W  0   I  s   Lc   i   L L  iLs   L   L   L  vo Ls                 4 sin(2   D) 8 cos(2   D) V  (5.36) R 1 i o   i  Lc  0  I s  Lc   0 0 Ws  0    Ls     L   L      L L  v      d v bs   bs      1   0 0 Vbc 0   0 0 0 0 W v    s   bc   vbc C 0 0 V 0    b   bs  1  0 0 0 W 0   s   Cb 

The dynamic of iL0 and vb0 can be decoupled from the rest of system as shown in the equation (5.35), which is a standard state space model of a series RLC circuit[78]. Equation

(5.35) indicates there is a resonant oscillation caused by the DC blocking capacitor and the transformer leakage inductor.

 R 1        i L L iL0   L0        (5.37)  1 v  v   0   b0   b0     Cb 

114

The Eigen values of the matrix (5.37) are:

R R 2 4      L L 2 C  L (5.38)     b  1,2 2

The resonant frequency is:

2 1 R 4 r  2  (5.39) 2 L Cb  L

1 L When R  is very low, the electric quality factor Q  is relatively high, R C indicating low damping and a more serious oscillation which may lead to losing ZVS. As shown in Fig. 64, the purple line and blue line are Vds and Ids waveform of the switch Sp1 respectively. The simulation conditions are: vg=208VAC, vo=400VDC, Lδ=100uH,

Cb=500uF and Rδ=1mohm. There is a clear low frequency oscillation of iL. In a single switching period, the low frequency oscillation performs like a DC offset and may lead to losing ZVS.

115

(a) (b)

Fig. 64 Vds and Ids of switch Sp1@vg=208VAC, vo=400VDC, Cb=500uF, Lδ=100uH, Rδ=1mohm.

Therefore, the DC blocking capacitance and transformer winding resistance need to be designed carefully. There is a high Q value when the value of Rδ and Cb are low. The higher the Q value is, the more likely the system will lose ZVS. A high Rδ value can effectively dampen the low frequency oscillation, however, there is more copper loss of the transformer.

5.2 Time-varying Full-order Dual-active-bridge Modeling of Variable-

switching-frequency Single-phase-shift Control in Matlab/Simulink

In this paper we are considering the VSF DAB control, since the input voltage is a regulated sin waveform, the whole system is time-varying. A time-varying full-order DAB modeling of the VSF-SPS control is presented as (5.40), and the parameters are shown in

(5.41) - (5.45). The model schematic in the Matlab/Smulink is shown in Fig. 65.

116

 x(t)  A(t)x(t)  B(t)u(t) (5.40) y(t)  C(t)x(t)  D(t)u(t)

iL0    v v  b0   g  i   v  x   Ls  , u   o  , y  i  i  i sin(W t)  i cos(W t) (5.41)   L L0 Ls s Lc s iLc  s   v  d  bs    vbc 

 R f 1    0 0 0 0  L L  f f   1  0 0 0 0 0  C   b  R 1  0 0  f W  0   L s L  A   f f  (5.42) R 1  0 0 W  f 0    s L L   f f   1  0 0 0 0 Ws  Cb   1   0 0 0 Ws 0   Cb 

 0 0 0 0   0 0 0 0   4  4  cos(2   D) 8  sin(2   D) V   o  I Lc   L f   L f   L f  B    (5.43) 4  sin(2   D) 8  cos(2   D) Vo  0  I Ls     L f   L f   0 0 V 0   bc   0 0 Vbs 0 

C  0 0 sin(Wst) cos(Wst) 0 0 (5.44)

D  0 0 0 0 (5.45)

117

Fig. 65 Time-varying full-order DAB state-space model.

The transfer function can be solved from the state space model[79]:

Y(s) H(s)   C(sI  A)1 B  D (5.46) U(s)

In this paper, since the transfer function is too complex to be presented as an analytical solution, it will be analyzed as a numerical solution under variable cases in chapter

5.3.

5.3 Simulation Result and Analysis

In this chapter, the simulation result of a time-varying full order DAB model is compared to the switching model simulation result under different test conditions using the simulation software Matlab/Simulink. The resonant frequency was gotten from a theoretical analysis, a time-varying full order model simulation and a switching model simulation respectively.

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5.3.1 Case 1 @Cb=1mF, Lδ=12uH, Rδ=10mohm

In case 1, the grid voltage vg is 208V AC, battery voltage is 400V DC, and the total transferred power is 4kW. DC blocking capacitance is 1mF, transformer leakage inductance is 12uH and the transformer winding resistance is 10mohm. The theoretical resonant frequency is:

R 2 4   L2 C L (5.47) f   b  1451Hz r 4

The iL simulation results of a state space model and a switching model over 2 line period are shown in Fig. 66, and a zoomed in waveform over 8 switching period is shown in

Fig. 67. The discrete sample rate is 333kHz, which is the same with the experiment shown in chapter 3. The iL simulation result of the state space model approximates the result of a switching model very well.

iL of switching model

iL of state space model

Comparison of iL of state space model and switching model

Fig. 66 iL simulation results of a state space model and a switching model over 2 line period@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

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iL of switching model

iL of state space model

Fig. 67 iL simulation results of a state space model and a switching model over 8 switching periods@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

The FFT analysis of the iL simulation result of the switching model is shown in Fig.

68. From the FFT analysis, we find that the switching frequency components, with the VSF-

SPS control, which is from 150kHz to 500kHz, dominate the iL waveform. At the same time, there are clearly low frequency components. Seeing the zoom-in FFT spectrum at 3rd plot in

Fig. 68, we find the peak amplitude happened at around 1500Hz. The above theoretical analysis result of 1450Hz is verified by the switching model simulation.

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Fig. 68 FFT analysis of iL simulation results of switching model@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

The FFT analysis of the iL simulation result of the state space model is shown in Fig.

69. The FFT analysis result is similar with the switching model. From the zoom-in FFT spectrum at the 3rd plot in Fig. 69, we find the peak amplitude happened at around 1500H, which corresponds to both theoretical analysis and switching model simulations. The FFT amplitude of the state space model result has some differences with the switching model simulation result, since the state space model only utilizes zero and first order terms.

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Fig. 69 FFT analysis of iL simulation results of the state space model@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

The transfer function can be solved from the state space model with the equation in

(5.46). The discrete bode plot of vg to iL transfer function, vo to iL transfer function, d to iL transfer function and fs to iL transfer function are shown in Fig. 70 to Fig. 73 respectively

(time-step is 30us). All of the bode plots clearly show the resonant frequency at 1.46kHz, which matches the theoretical analysis and simulation result.

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H vg iL bode plot 0

-10 System: H_vg_iL_d Frequency (Hz): 1.46e+03 Magnitude (dB): -8.68

-20

-30

Magnitude (dB) Magnitude -40

-50

-60

-70 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 70 Bode plot of vg to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

H vo iL bode plot -10

-20 System: H_vo_iL_d Frequency (Hz): 1.46e+03 Magnitude (dB): -18.9

-30

-40

Magnitude (dB) Magnitude -50

-60

-70

-80 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 71 Bode plot of vo to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

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H d iL bode plot -90

System: H_d_iL_d -100 Frequency (Hz): 1.44e+03 Magnitude (dB): -96.7

-110

-120

Magnitude (dB) Magnitude -130

-140

-150

-160 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 72 Bode plot of d to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

H ws iL bode plot 50

System: H_w s_iL_d Frequency (Hz): 1.44e+03 Magnitude (dB): 49

Magnitude (dB) Magnitude

-10 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 73 Bode plot of fs to iL transfer function@ Cb=1mF, Lδ=12uH, Rδ=10mohm.

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5.3.2 Case 2 @Cb=0.5mF, Lδ=12uH, Rδ=10mohm

In case 2, the grid voltage vg is 208V AC, battery voltage is 400V DC, and the total transferred power is 4kW. The DC blocking capacitance is 0.5mF, transformer leakage inductance is 12uH and the transformer winding resistance is 10mohm. The theoretical resonant frequency is:

R 2 4   L2 C L (5.48) f   b   2054Hz r 4

The iL simulation results of the state space model and switching model over the 2 line period is shown in Fig. 74. The discrete sample rate is 333kHz, which is the same with the experiment shown in chapter 3. The iL simulation result of the state space model approximates the result of the switching model very well.

Fig. 74 iL simulation results of the state space model and switching model over the 2 line period@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm.

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The FFT analysis of iL simulation result of the switching model is shown in Fig. 75.

From the FFT analysis, we find that the switching frequency components, with the VSF-SPS control, which is from 150kHz to 500kHz, dominate the iL waveform. At the same time, there are clearly low frequency components. Seeing the zoom-in FFT spectrum at 3rd plot of Fig.

75, we find the peak amplitude happened at around 2000Hz. The above theoretical analysis result of 2054Hz is verified by the switching model simulation.

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Fig. 75 FFT analysis of iL simulation results of switching model@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm.

The FFT analysis of the iL simulation result of the state space model is shown in Fig.

76. The FFT analysis result is similar with the switching model. From the zoom-in FFT spectrum at the 3rd plot in Fig. 76, we find the peak amplitude happened at around 2000H which corresponds to both the theoretical analysis and switching model simulation. The FFT

127

amplitude of the state space model result has some differences with the switching model simulation result, since the state space model only utilizes zero and first order terms.

Fig. 76 FFT analysis of the iL simulation results of the state space model@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm.

The transfer function can be solved from the state space model with the equation in

(5.46). The discrete bode plot of vg to iL transfer function, vo to iL transfer function, d to iL transfer function and fs to iL transfer function are shown in Fig. 77 to Fig. 80 respectively

128

(time-step is 30us). All of the bode plots clearly show the resonant frequency at 2.05kHz, which matches the theoretical analysis and simulation result.

H vg iL bode plot 0

System: H_vg_iL_d -10 Frequency (Hz): 2.05e+03 Magnitude (dB): -5.66

-20

-30

Magnitude (dB) Magnitude -40

-50

-60

-70 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 77 Bode plot of vg to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm.

H vo iL bode plot -10

System: H_vo_iL_d -20 Frequency (Hz): 2.03e+03 Magnitude (dB): -16.2

-30

-40

Magnitude (dB) Magnitude -50

-60

-70

-80 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 78 Bode plot of vo to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm.

129

H d iL bode plot -90

System: H_d_iL_d Frequency (Hz): 2.03e+03 -100 Magnitude (dB): -94.1

-110

-120

Magnitude (dB) Magnitude -130

-140

-150

-160 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 79 Bode plot of d to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm.

H ws iL bode plot 60

50 System: H_w s_iL_d Frequency (Hz): 2.05e+03 Magnitude (dB): 52

Magnitude (dB) Magnitude 20

-10 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 80 Bode plot of fs to iL transfer function@ Cb=0.5mF, Lδ=12uH, Rδ=10mohm.

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5.3.3 Case 3 @Cb=1mF, Lδ=12uH, Rδ=1mohm

In case 3, the grid voltage vg is 208V AC, battery voltage is 400V DC, and the total transferred power is 4kW. The DC blocking capacitance is 1 mF, the transformer leakage inductance is 12uH, and the transformer winding resistance is 1mohm. The theoretical resonant frequency is:

R 2 4   L2 C L (5.49) f   b   1453Hz r 4

The iL simulation results of state space model and switching model over the 2 line period is shown in Fig. 81. The discrete sample rate is 333kHz which is the same with the experiment shown in chapter 3. The iL simulation result of the state space model approximates the result of the switching model very well.

Fig. 81 iL simulation results of the state space model and the switching model over the 2 line period@ Cb=1mF, Lδ=12uH, Rδ=1mohm.

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The FFT analysis of the iL simulation result of the switching model is shown in Fig.

82. From the FFT analysis, we find that the switching frequency components, with the VSF-

SPS control, which is from 150kHz to 500kHz, dominate the iL waveform. At the same time, there are clearly low frequency components. Seeing the zoom-in FFT spectrum at the 3rd plot in Fig. 82, we find the peak amplitude happened at around 1400Hz. The above theoretical analysis result 1453Hz is verified by the switching model simulation.

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Fig. 82 FFT analysis of the iL simulation results of the switching model @ Cb=1mF, Lδ=12uH, Rδ=1mohm.

The FFT analysis of the iL simulation result of the state space model is shown in Fig.

83. The FFT analysis result is similar with the switching model. From the zoom-in FFT spectrum at the 3rd plot of Fig. 83, we find the peak amplitude happened at around 1400H which corresponds to both the theoretical analysis and switching model simulation. The FFT

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amplitude of the state space model result has some differences with the switching model simulation result, since the state space model only utilizes zero and first order terms.

Fig. 83 FFT analysis of the iL simulation results of the state space model @ Cb=1mF, Lδ=12uH, Rδ=1mohm.

The transfer function can be solved from the state space model with the equation in

(5.46). The discrete bode plot of vg to iL transfer function, vo to iL transfer function, d to iL

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transfer function and fs to iL transfer function are shown in Fig. 84 to Fig. 87 respectively

(time-step is 30us). All of the bode plots clearly show the resonant frequency at 1.46kHz, which matches the theoretical analysis and simulation result.

H vg iL bode plot 10 System: H_vg_iL_d Frequency (Hz): 1.46e+03 0 Magnitude (dB): 9.23

-10

-20

-30

-40

Magnitude (dB) Magnitude -50

-60

-70

-80

-90 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 84 Bode plot of vg to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm

H vo iL bode plot 0 System: H_vo_iL_d Frequency (Hz): 1.46e+03 -10 Magnitude (dB): -0.972

-20

-30

-40

-50

Magnitude (dB) Magnitude -60

-70

-80

-90

-100 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 85 Bode plot of vo to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm

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H d iL bode plot -70

-80 System: H_d_iL_d Frequency (Hz): 1.46e+03 Magnitude (dB): -78.9 -90

-100

-110

-120

Magnitude (dB) Magnitude -130

-140

-150

-160

-170 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 86 Bode plot of d to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm.

H ws iL bode plot 80

System: H_w s_iL_d 60 Frequency (Hz): 1.46e+03 Magnitude (dB): 66.9

Magnitude (dB) Magnitude

-20

-40 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 87 Bode plot of fs to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=1mohm.

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5.4 Experiment Result

Fig. 88 shows the experiment waveform of iL. The grid voltage vg is 208V AC, battery voltage is 400V DC, and the total transferred power is 4kW. DC blocking capacitance is 1mF, transformer leakage inductance is 12uH.

The iL experiment waveform (blue line) over the two line period is shown in Fig. 88.

Fig. 88 iL experiment waveform (blue line) over the two line period@ Cb=1mF, Lδ=12uH.

Importing the experiment data into Matlab and doing the FFT analysis for iL over the one line period is shown in Fig. 89. From the FFT analysis, we find that the switching frequency components, which are distributed from 150kHz to 500kHz, dominate the iL waveform. At the same time, there are clearly low frequency components. Seeing the zoom- in FFT spectrum, we find the peak amplitude happened at around 250Hz. Based on

137

theoretical analysis, we can derive that the equivalent transformer winding resistor is around

220ohm.

iL iL / A

-10

-20

-30

-40

-50 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 t / S

(a)

(b)

Fig. 89 (a) iL experiment waveform used for FFT analysis (b)FFT analysis of iL experiment waveform.

138

Applying the parameters Cb=1mF, Lδ=12uH, and Rδ=220mohm into the state space model, we can get the discrete bode plot of vg to iL transfer function, vo to iL transfer function, d to iL transfer function and fs to iL transfer function which are shown in Fig. 84 to Fig. 87 respectively (time-step is 30us). All of the bode plots show the resonant frequency at around

1kHz.

Since the Q factor is much lower under this experiment condition than the simulation conditions in chapter 4.3, because of larger equivalent transformer winding resistor, the overshoot shown in bode plot is much smaller than the simulation result. Therefore, the error is relatively larger than the simulation result.

H vg iL bode plot -28

System: H_vg_iL_d Frequency (Hz): 1.06e+03 Magnitude (dB): -28.2

-30

-32

-34

Magnitude (dB) Magnitude -36

-38

-40

-42 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 90 Bode plot of vg to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm.

139

H vo iL bode plot -38

System: H_vo_iL_d Frequency (Hz): 1.07e+03 Magnitude (dB): -38.5 -40

-42

-44

Magnitude (dB) Magnitude -46

-48

-50

-52 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 91 Bode plot of vo to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm.

H d iL bode plot -116

System: H_d_iL_d Frequency (Hz): 1.09e+03 Magnitude (dB): -117 -118

-120

-122

Magnitude (dB) Magnitude -124

-126

-128

-130 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 92 Bode plot of d to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm.

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H ws iL bode plot 30

System: H_w s_iL_d Frequency (Hz): 1.04e+03 Magnitude (dB): 29.4 28

Magnitude (dB) Magnitude 22

16 2 3 4 5 10 10 10 10 Frequency (Hz)

Fig. 93 Bode plot of fs to iL transfer function @ Cb=1mF, Lδ=12uH, Rδ=200mohm.

5.5 Conclusion

In this chapter, a full-order state-space model of the DAB converter is proposed.

Compared to the conventional first-order DAB converter model, the full-order is much more suitable for VSF control, which will introduce a line frequency component into the system. A thoroughly mathematical derivation and analysis of the full-order state-space model is presented. The effectiveness of the proposed model is validated by simulation results and experiment results. This model is not only useful for fast simulation and estimation, but also very practical for good system design which involves the VSF control.

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Chapter 6. Variable Switching Frequency Control

for Input-Series-Output-Parallel Modular EV

Fast Charging Stations

With the rapid growth of the electrical vehicle market, the needs of fast charging stations have come to light. Fast charging technology is becoming the key for EVs to compete with conventional vehicles in terms of convenience through the shortening of the charging period. Based on the charging time, the EV chargers can be divided into three categories:

1. Slow chargers, which are normally home chargers. It usually takes 8 hours to

charge the battery from 20% state of charge (SOC) to 80% SOC;

2. Normal chargers, which are normally parking lot chargers. It usually takes 4 hours

to charge the battery from 20% SOC to 80% SOC;

3. Fast chargers, which are normally fast charging stations. It only takes 30 minutes

to charge the battery from 20^ SOC to 80% SOC.[80]

A conventional single phase fast charger design like Fig. 94, employs a two-stage design, i.e., a front-end PFC stage + an isolated DC/DC converter [4][5]. With a three phase system the first stage is a three phase AC/DC rectifier, converting the three-phase grid

142

voltage to a fixed DC bus voltage. The second stage is the same as the single phase design, an isolated DC/DC converter. [81][82] A high voltage device must be used in this topology.

DC Link bus capacitor Input filter Output filter Isolated AC/DC PFC ZVS Vg Boost DC/DC Battery Converter Converter

ePWMs ePWMs Sensor Sensor Digital Controller

Fig. 94 Conventional two stage fast charger design.

For the three phase system, another popular topology is shown in Fig. 95. There are three modules. Each module corresponds to one phase. For each module there are two stages:

AC/DC PFC front end + isolated DC/DC converters. The output terminals for each module are paralleled together. [80]

143

DC Link bus capacitor Input filter Output filter AC/DC PFC Isolated Boost DC/DC Converter Converter

ePWMs ePWMs Sensor Sensor Digital Controller

a DC Link bus capacitor Input filter Output filter

b AC/DC PFC Isolated Boost DC/DC Battery c Converter Converter

ePWMs ePWMs Sensor Sensor Digital Controller

DC Link bus capacitor Input filter Output filter AC/DC PFC Isolated Boost DC/DC Converter Converter

ePWMs ePWMs Sensor Sensor Digital Controller

Fig. 95 Conventional 3 phase modular fast charger design.

Another type of modular design topology is an input-series-output-parallel

AC/DC/DC topology as shown in Fig. 96. As shown in references [83], [84] and [85], the

ISOP AC/DC/DC converter consists of a cascaded full-bridge AC/DC PFC as the first stage and an output paralleled DC/DC isolated converter in the DC/DC as the second stage. This design guarantees the modularity very well. All of the modules are exactly the same and stackable. A low voltage device can be implemented into this topology due to the low input

144

voltage of each module. [80] However, the DC link bus capacitor is not negligible and increases the total system cost.

DC Link bus capacitor Input filter Output filter AC/DC PFC Isolated Boost DC/DC Converter Converter

ePWMs ePWMs Sensor Sensor Digital Controller

DC Link bus capacitor Input filter Output filter AC/DC PFC Isolated Boost DC/DC Battery

AC Converter Converter

ePWMs ePWMs Sensor Sensor Digital Controller

...... DC Link bus capacitor Input filter Output filter AC/DC PFC Isolated Boost DC/DC Converter Converter

ePWMs ePWMs Sensor Sensor Digital Controller

Fig. 96 Conventional modular AC/DC/DC fast charger design.

A conventional fast charger design employs silicon devices with a relatively low switching frequency resulting in bulky passive components and low power density. In this paper, a novel modular designed ISOP AC/DC topology is proposed as shown in Fig. 97. It has the power-factor-correction (PFC) and zero-voltage-switching (ZVS) functions over the

145

full-load range. By reducing one power stage and eliminating the large DC link capacitor, a high efficiency and high power density are achieved. Such topology can be used as a modular building block to scale up to 50kW by serial connecting the input terminals and paralleling output terminals. A novel energy-balanced variable switching frequency control for such input-series-output-parallel (ISPO) modular designed is proposed.

Small filtering capacitor Input filter Output filter PFC+ Unfolding Isolated bridge DC/DC Converter

ePWMs ePWMs Sensor Sensor Digital Controller

Small filtering capacitor Input filter Output filter PFC+ Unfolding Isolated bridge DC/DC Battery AC Converter

ePWMs ePWMs Sensor Sensor Digital Controller

...... Small filtering capacitor Input filter Output filter PFC+ Unfolding Isolated bridge DC/DC Converter

ePWMs ePWMs Sensor Sensor Digital Controller

Fig. 97 Proposed modular AC/DC fast charger design.

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6.1 Input-Series-Output-Parallel Modular Topology and Operation

The ISOP DC/DC system garnered a lot of attention recently due to the scalability.

Series inputs can naturally handle the high voltage. The paralleled outputs provide the capability of driving a heavy load. The key feature of the ISOP DC/DC system control is the input voltage and output current balance, which has been thoroughly studied in references

[80], [82], and [84]–[91]. The LLC and DAB DC/DC converters are the most popular topology for a single module, because of the easy implementation of soft switching technology and the capability of isolation. However, the fixed switching frequency limited their operational range.

There were some studies about the ISOP AC/AC system in recent years[94]. It’s very similar to the ISOP DC/DC system. With a conventional fixed switching frequency control, the input voltage to output ratio of the LLC and DAB are limited to a very narrow range, therefore, the AC/AC system can share almost the same control algorithm with the ISOP

DC/DC system.

In reference [83], an AC/DC ISOP topology is proposed. There are two stages in each module: the AC/DC PFC converter + DC/DC converter. The first stage is a must, because the second stage DC/DC converter can only handle the almost fixed input voltage. Therefore, the bulky and costly DC link capacitors are a must.

In this chapter, a novel AC/DC ISOP DAB based modular design is proposed[95].

Different from what is referenced in [83], each module only has a single stage, only an unfolding bridge + a DC/DC DAB converter. No large DC link bus capacitors are needed. To

147

reach a higher charging power, e.g., 2.4kVAC/50 kW, ten such 230VAC/7.2kW charging modules can be connected in a series at the input side and in parallel at the output sides, as shown in Fig. 98. In this way we can maintain the high-power density, high-efficiency and high-power operations simultaneously.

v1in v1p v1s

Lg L12

i1f S1r1 S1r3 S1p1 S1p3 S1s1 S1s3

v1 L1f C1in v1in v1p v1s C1o

S1r2 S1r4 S1p2 S1p4 S1s2 S1s4

Silicon E-Mode MOSFET GaN HEMTs Power Module 1

v2in v2p v2s

L22

i2f S2r1 S2r3 S2p1 S2p3 S2s1 S2s3

v2 L2 C2in v2in v2p f v2s C2 o VB vg S2r2 S2r4 S2p2 S2p4 S2s2 S2s4

Power Module 2

v2in v2p v2s

LN2

iNf SNr1 SNr3 SNp1 SNp3 SNs1 SNs3

vN CNin vNin vNp LNf vNs CNo

SNr2 SNr4 SNp2 SNp4 SNs2 SNs4

Power Module N

Fig. 98 Proposed ISOP modular designed high-efficiency 50kW fast charger topology for electric vehicles.

148

There are two challenges for the proposed ISOP DAB based modular design. First, the input voltage balance and the output current balance must be guaranteed. Second, for each module, the DAB converter must deal with a very large input voltage range from 0 to peak.

As in the analysis in chapters 2-4, a variable switching frequency control is implemented for the single stage DAB based AC/DC module. To simplify the control algorithm, we only use the single phase shift modulation in this chapter.

For modules 1 to N, the transferred instantaneous power P1 to PN can be presented as shown in the equation (6.1):

 v (t)V (1 2D (t))  D (t) (6.1) P(t)  in 1 B 1 1  v (t)i (t)  V i (t)  1 f (t) L in 1 in B out1  sw1 1  v (t)V (1 2D (t))  D (t) P (t)  inN B N N  v (t)i (t)  V i (t)  N f (t) L inN in B outN  swN N

Where vini(t) is the input voltage for module i , iouti(t) is the output current for module i , Di(t) is the phase shift of module i, fswi(t) is the switching frequency for module i, iin(t) is the input current at time instant t. Li is the leakage inductance of module i. VB is the battery voltage.

To achieve the constrain of (6.1), for each module, the phase shift and switching frequency must satisfy the following constrain:

(1 2D (t))  D (t) (1 2D (t))  D (t) i (t) 1 1  ... N N  in (6.2) fsw1 (t) L1 fswN (t) LN VB

149

Otherwise, the total power will be delivered by one module and all of the other modules deliver only zero power as shown in equation (6.3). Where vg(t) is the grid voltage and Ptlt(t) is the total transferred power at time t. This case is unacceptable.

  vin 1 (t)  ... vini1 (t)  vini1 (t)  ... vinN (t)  0  vini (t)  vg (t) (6.3)  Ptlt (t) iin (t)  v (t)  g

The key feature to control the Input-Series-Output-Parallel (ISOP) modular designed fast charger is the input voltage balance. The input current is the same for all modules, as is the output voltage. Assuming open loop control, if the charging module’s parameters are not exactly the same, eventually there is only one module that can deliver power, and all of the other modules have zero input voltage.

Therefore, if we want to achieve energy balance among all of the modules, the input voltage and output current of all the modules needs to be balanced. We assume the grid voltage is vg(t) and the current reference is ig(t):

vg (t) Vg sin(2 g t) (6.4)

ig (t)  I g sin(2 g t) (6.5)

The control targets for each power module are:

 v (t) V v (t)  g  g sin(2   t)  k N N g k  1,2,..., N (6.6)   ik (t)  ig (t)  I g sin(2  g t)

150

From the control point of view, the system control signals must meet the requirement shown in (6.7):

(1 2D (t))  D (t) (1 2D (t))  D (t) i (t) 1 1  ... N N  g (6.7) fsw1 (t)  L1 f swN (t)  LN VB

Similar to the analysis in chapter 4, a simplified VSF-SPS control method is used for each module’s control. During most of the operation time, the system is controlled as shown in (6.8) to maintain minimal reactive power and achieve the highest efficiency. δ is a positive safe margin to guarantee enough reactive power thereby maintaining ZVS. Control modulation (6.8) is named SPS1 in this chapter.

D(t)  (1 k  4 f  k  C  L )/ 4    s eq   v v (1 2 D)  D (6.8) f (t)  1 2  s  pt  L

However, the theoretical value of fs becomes infinity when the grid voltage goes to zero. We set the upper limit of device’s switching frequency as 500kHz in this paper. To keep the ZVS at ultra-low power, the phase shift D must go to 0.25-0.5 region (90º-180º), i.e., generating more reactive power and less active power. In this case, the control variables can be presented as in (6.9). The modulation is named SPS2 in this paper.

 1 1 p *  f  L D(t)    t sa   4 16 2v v (6.9)  1 2  f s (t)  f sa

Based on (6.7), (6.8) and (6.9), it’s easy to get the only solution for the whole ISOP system. The control variables of the VSF-SPS method over the line period for the grid are shown in Fig. 99.

151

D fs / Hz

t / S

Fig. 99 Control variables D(t) and fs(t) over the line period for the grid voltage when transferring 200W.

The flow chart of the VSF-SPS control over the one line period is shown in Fig. 100.

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SPS1 calculation D1_SPS1, 0, fs_SPS1

Yes If fs_SPS1 < fsa No

SPS2 calculation D = D_SPS1 D = D_SPS2 fs = fs_SPS1 fs = fs_SPS2

End

Fig. 100 Flow chart of the VSF-SPS control over the one line period.

6.2 System Control Strategy for Input-Series–Output-Parallel Modular

Designed Fast Charging Station

6.2.1 Single-phase DQ Transformation

With regards to the single phase AC/DC or DC/AC system controller design, the aforementioned research works from references [96]–[100] to apply a single-phase dq synchronous reference frame, in order to achieve zero error tracking for the grid sinusoidal

AC current or voltage by the simple proportional integral (PI) controllers. In our system, the single phase dq transformation is applied to achieve a better THD performance.

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To expend the original idea of a three phase system dq0 transformation into the single phase system dq transformation, the orthogonal imaginary coordinate should be introduced.

The single phase dq transformation theory is to have 2 variables, the real measured sinusoidal voltage/current single and the imaginary 90 degree phase shift voltage/current. The imaginary single has the exact same frequency and amplitude characteristics with the real signal, and the only difference is there is a 90 degree phase lead. [96]–[100]

We assume the sinusoidal signal we want to transfer to dq synchronous reference frame is x, which can be present as shown in equation (6.10):

(6.10) x(t)  X sin(2 g t )

The single in imaginary coordinate is:

 x (t)  X sin(2  t   ) (6.11) im g 2

Therefore, in αβ coordinate, the variables are:

x(t)  X sin( t )  g   (6.12) x (t)  X sin( t   )  im g 2

Based on the equation in (6.13), the singles in αβ coordinate can be transferred to the dq coordinate.

x  sin( t)  cos( t) x  d  g g (6.13) x  cos( t) sin( t)    q   g g xim 

Apply the equation in (6.12) into the equation in (6.13) and it’s easy to get:

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X sin( t ) x sin( t)  cos( t)  g   d   g g  (6.14)        x cos( t) sin( t) X sin( t   )  q   g g  g 2 

x  X cos() d  (6.15) x     q   X sin()

Equation (6.15) indicates that both xd and xq are a constant value after the dq transformation, which can be easily tracked by the PI controller.

The αβ coordinate to dq coordinate transform diagram is shown in Fig. 101:

ωt PLL x αβ d x

xq dq 90º

Fig. 101 αβ coordinate to dq coordinate transformation.

The inverse transformation is given by the equation in (6.16). The dq coordinate to αβ coordinate transform diagram is shown in Fig. 102:

x sin( t) cos( t) x     g g  d  (6.16)     x   cos( t) sin( t) x     g g  q 

155

ωt PLL α dq x

xd β

xq αβ

Fig. 102 dq coordinate to αβ coordinate transformation.

6.2.2 Voltage and Current Control Loop Design

To build the ISOP system, we need to consider variations in each module’s parameters, e.g. slightly different transformer turn ratios. This is the key to realize the power

[101] balance among all modules . Assume the grid voltage is vg(t) and the current reference is ig(t).

(6.17) vg (t) Vg sin(2 g t)

(6.18) ig (t)  I g sin(2 g t)

The control targets for each power module are:

 v (t) V v (t)  g  g sin(2  t)  k N N g k 1,2,...,N (6.19)  i (t)  i (t)  I sin(2  t)  k g g g

156

The ISOP system controller contains N control loops: n-1 of them are used to adjust the module input voltage, and the last one is used to adjust the input current. Therefore, each module will be controlled to have the same input voltage Vg/N with the same input current ig.

Once the module input voltage is balanced, the power will be balanced as well.

Both the voltage reference and current reference are sinusoidal and it is very hard to achieve a satisfactory dynamic performance by only using a conventional PID controller.

Therefore, based on the analysis in section 6.2.1, the dq coordinate is applied in this paper, to realize the zero-error tracking for the grid fundamental-frequency AC signal. It is different from the three phase systems, the single-phase system needs to create an imaginary variable through shifting the original signal (voltage/current) by 90º. Then the original and shifted signals are converted to dq frame from αβ coordinates.

There are at least N voltage sensors that are needed. One of the voltage sensors is utilized to sense the grid voltage. The grid voltage information is utilized by the PLL block to get the frequency and phase information. The other N-1 voltage sensors are utilized to sense the input voltage of module 1 to N-1. The input voltages of modules 1 to N-1 are needed by voltage loops 1 to N-1. The voltage transformations from αβ coordinate to dq, coordinate control blocks are shown in Fig. 103.

157

sign sign

v ωt g PLL v αβ gd

vgq dq 90º

ωt vdN-1

v ... gN-1 dq vqN-1 ωt ωt vd2 vg2 αβ vd1 vg1 vd2 vd1 dq 90º

Fig. 103 Voltage transformation from αβ coordinate to dq coordinate.

There is only one current sensor needed, which is utilized to sense the grid current.

The grid current information is needed by the current loop. The current transformations from

αβ coordinate to dq coordinate control blocks are shown in Fig. 104:

158

ωt i αβ gd ig

igq dq 90º ωt i αβ gd_ref ig_ref

igq_ref dq 90º

Fig. 104 Current transformation from αβ coordinate to dq coordinate.

Both input voltage and current adopt feedback and feed-forward control. The feedforward signals are fs and D, calculated by using the VSF-SPS control in Section II. Because the ZVS conditions are only determined by the phase-shift D and independent of the switching frequency fs, we added an additional PI loop to control the switching frequency fs, and use the open loop calculated phase-shift D to secure ZVS. As shown in Fig. 105, only fs is used as the closed-loop control variable. The phase-shift D is determined by the open loop calculation.

159

i vgd / N PID gd_ref PID V_PI I_PI controllor kd controllor d sign sign -ωCin -ωLin vkd igd sign sign ωCin ωLin i vkq gq sign sign vgq / N PID igq_ref PID V_PI I_PI controllor kq controllor q sign sign

V loop controller for module 1 to N-1 I loop controller for module N

α V_PIkd dq fswk fsw0 Frequency fsw0 β & Phase-shift For module 1 to N-1 vg / N αβ Feedforward V_PIkq D Signal ig_ref Generator α I_PId dq fswN fsw0 β For module N Feedforward controller I_PIq αβ using VSF-SPS modulation dq to αβ transformation

Fig. 105 Voltage loops and current loop with feedforward signals.

6.3 Simulation Result

As an example, the SIOP system has 3 modules, which have purposely differentiated transformer turn ratios of 1:1.1, 1:1 and 1:1.05, respectively. Other parameters of each module are shown in Table 4. The nominal power for a single module is 7.2kW. The grid voltage is 624 Vrms AC. The output voltage is 400V DC. From 0 to 2/60s, the total transferred power is 0.7 at full load, which is 15.12kW total. From 2/60s to 4/60s, the total transferred power increases to full load, which is 21.6kW total.

160

The simulation result of the three module ISOP system with only open loop control is shown in Fig. 106. The first subfigure shows the transferred power of module 1, 2, 3 and the reference power. The second subfigure shows the input voltage of module 1, 2, 3 and the reference input voltage for one module. The third subfigure shows the input grid current and its reference. The fourth subfigure shows the output current of each module and the output current reference. The fifth subfigure shows the switching frequency of each module. The sixth subfigure shows the single-phase-shift of each module. All of the modules have same switching frequency and phase-shift due to the open loop control.

161

Fig. 106 Simulation result of three module ISOP system with only open loop control.

From the simulation result shown in Fig. 106, we find finally module 1 has delivered all of the power, and its input voltage equals the grid voltage. The other modules’ input voltages are all zero, and at the same time they only delivery zero power. Whenever the grid

162

voltage goes to zero, the controller naturally restarts and tries to find a system stable point, then it eventually goes to the scenario that only one module delivers power.

The simulation result of the same ISOP system with a proposed close loop control is shown in Fig. 107. The first subfigure shows the transferred power of module 1, 2, 3 and the reference power. The second subfigure shows the input voltage of module 1, 2, 3 and the reference input voltage for one module. The third subfigure shows the input grid current and its reference. The fourth subfigure shows the output current of each module and the output current reference. The fifth subfigure shows the switching frequency of each module. The sixth subfigure shows the single-phase-shift of each module.

All of the modules have the same phase-shifts. The switching frequencies of the three modules are different, controlled by the proposed closed loop. The simulation result validates the proposed close loop control strategy, which balances the power of each module very well.

All of the three modules deliver the same power with the same input voltage and the same output current. Unity power factor is achieved.

163

Fig. 107 Simulation result of the three module ISOP system with only the proposed close loop control.

Fig. 108, Fig. 109 and Fig. 110 check the ZVS results of module 1, 2 and 3 respectively. All the switches of the primary side and secondary side can achieve ZVS turn-

164

on over the whole line period. Note when the switch is on the current is negative, indicating the ZVS turn-on.

ZVS turn-on

Fig. 108 ZVS checking of the module 1 primary side switch P1, P3, and the secondary side switch S1, S3.

165

ZVS turn-on

Fig. 109 ZVS checking of the module 2 primary side switch P1, P3, and the secondary side switch S1, S3.

166

ZVS turn-on

Fig. 110 ZVS checking of the module 3 primary side switch P1, P3, and the secondary side switch S1, S3.

6.4 Conclusion

In this chapter, a DAB based modular designed ISOP single phase topology is proposed. By using a novel VSF-SPS modulation, unity power factor and ZVS of each module are secured for the whole-load range. A novel system energy balanced control with single phase dq transformation for such an ISOP system is proposed for a fast EV charging

167

station. The energy balance, the PFC and ZVS performance of the proposed system control algorithm is validated by both theoretical analysis and simulation.

168

Chapter 7. Conclusion and Future Work

7.1 Conclusion of the Work

This paper presents a framework for the proposed novel single stage AC level-2 on-board electrical vehicle charger which directly converts the grid AC to DC and eliminates the DC link capacitor thereby increasing the system efficiency and power density. The advanced variable-frequency control techniques, the ZVS analysis and the state space modeling of the presented single-stage AC/DC topology are proposed.

Chapter 1 reviews the EV charger classification and standards. Existing AC level-2 on- board EV charger topology and control are included for comparison.

Chapter 2 presents an analysis of ZVS conditions in-depth for both of the SPS modulation and DPS modulation controls under different load conditions. This analysis is the key feature to realize unity power factor and ZVS by a single-stage AC/DC topology.

Chapter 3 proposes two variable-frequency controls, the VSF-DPS and VSF-SPS for the presented single-stage AC/DC topology, which can reach the unity power factor and maintain

ZVS at the same time. Compared to the VSF-DPS control, a hybrid VSF-SDPS method is proposed by combining the SPS and DPS together to optimize the system efficiency and improve the THD performance. The theoretical analysis, simulation result and experiment results are provided. The enhanced light load performance of the VSF-SDPS control is verified by both the simulation and experiment. The digital controller implementation and

169

limitation using the DSP TMS320F28335 for variable-frequency and phase-shift control is discussed.

Chapter 4 presents the semiconductor loss and magnetic loss breakdown. A practical transformer design example was presented. Based on loss breakdown, the system optimization is analyzed thoroughly under different load conditions.

Chapter 5 proposes an improved time-varying, full-order state space model of the

DAB converter, which carefully considers the possible influence of the DC current blocking capacitor. Both theoretical analysis and simulation verifications are conducted to validate the proposed full-order state space modeling technique. The experimental results also verify the effectiveness of the small-signal model derived from theoretical analysis and simulation. This state space model is not only useful for fast simulation of the variable frequency control, but is also very meaningful for the system optimal trade-off design between a good ZVS performance and efficiency.

Chapter 6 proposes an ISOP DAB based AC/DC topology which is designed as an

EV fast charging station. A system energy balanced control algorithm with single phase dq transformation is proposed to achieve the energy balance among modules. The theoretical analysis and simulation results are presented. The PFC and ZVS of each module are guaranteed.

7.2 Future Work

The future work of this research topic includes the following items:

170

1. The VSF-SPS or VSF-SDFS control applied to medium voltage solid state

transformer(SST) which converts high voltage AC to low voltage 240/120V

AC[102];

2. A further system optimization and transformer design considering the power

density and cost;

3. A distributed control of the ISOP system.

171

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