Genesis Mega Drive Pal Mega Cd/Sega Cd

ll(riiA" SERVICE MANUAL GENESIS MEGA DRIVE PAL MEGA CD/SEGA CD

NO. 010

ISSUED APRIL, 1994

CONTENTS

GENESIS VA7 PARTS SPECIFICATJONS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 2

MEGA DRIVE PAL VA6.5 PARTS SPECIFICATIONS · · · · · · · · · · · · · · · · · · · · · · · - · · · · · - · - · · 11

MEGA CD / SEGA CD PARTS SPECIFICATIONS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 22

This manual contains IC specification to be added to the manuals issued previously.

Sega Enterprises, Ltd. GENESIS

PARTS SPECIFICATIONS IC1 16/32•bit Microprocessor_ IC MC68HCOOOFN8 IC H068HCOOOCP8

■ Top View & Pin Layout ■ Signal Description

ADDRESS BU s VCC(2) . >A2 3-A1 D13 GND(2} . Dl4 DATA BUS CLK D15 )01 5-D

BERFI ~ IPLg SYSTEM {-RESET,,. _ IPL1 INTERRUPT CONTROL - - CONTROL ~ HALT_ - IPTI }

■ Description No.!Pin Namei11ol Function No. Pin Name 1/0 Function No. Pin Name 1101 Function I i D, I 23 VPA ! Vailo peripheral .address 46 Ars I 2 I Ds ! 24 BERR ! Bus error 47 A16 3 D2 illO Data bus 25 IPL,, 48 A11 0 Address bus 4 D1 26 IPL, I Interrupt control 49 Ais 5 Do 27 IPL 50 Ai9 6 AS 0 Address strobe 28 FC2 51 Aro 7 UDS 0 Upper data strobe 29 FC 1 0 Processor status 52 Yee - Power supply 8 LOS 0 Lower data strobe 30 FC=o 53 A21 9 R/W 0 Read/Write 31 NC - 54 A22 0 Address bus Data transfer 32 A, 55 Azg 10 DTACK I Acknowledge 33 56 Vss A2 - GND 11 BG 0 Bus grant 34 A3 57 Vss 12 BGACK I Bus grant 11cknowledge 35 A, 58 Dis 13 BR I Bus request 36 A5 59 o,. 14 Vee - Power supply 37 ~ 60 D1.~ 15 i CLK I Clock 38 A1 61 012 0 Address bus 16 V,;,_, 39 As 62 D11 - GND I 7 ! V,;,_~ 40 Ag 63 Dio 1/0 Data bus 18 NC - Not connected 41 Aio 64 09 19 HALT 1/0 Halt 42 A11 65 Ds 20 RES 1/0 Reset 43 A12 66 07 21 VMA 0 Vaild memory address 44 A1s 67 06 22 E 0 Enable 45 Au 68 0;;

-2- GENESIS

IC2/3 32768 Word x Sblt CMOS Pseudo-Static RAM IC HM65256BLFP-10 IC TC51832FL-10

■ Top View & Pin Layout ■ Pin name

Pin Name Function VDD R/W A0-Al4 Address input Read/write input •13 R/W Aa Output enable Ag OE/RESH input/refresh input All OE/flFSH CE Chip enable input 1 Aw I/Ol-1/08 Data input/output cl Yoo Power supply GND Ground

■ Block Diagram

1 COLUMN DECODER

1/01-1/08

ROW ADDRESS BUFFl:R (BJ MEMORY ARRAY

256X128X8 REFRESH COUNTER (B)

REFRESH REFRESH CONTROLLER TIMER

-3- GENESIS

IC4 ZODA Central Processing Unit IC ZBOA 315-0041

■ Top View & Pin Layout ■ Description

Pin Pin Name 1/0 Function 0 A10 30-40 A0--A15 3-STATEO System address bus. As 1-5 Ag 15-12 00-07 3-STATEf/O System data bus. A7 7-10 A6 6 CLOCK I Receives a +5V single-phase clock signal. A5 A4 Active ·'Low". If the input/output device issues a signal A3 tha I requests an interrupt to the 280 CPU and lhe 05 A2 16 INT I interrupt enable flag is zero, this interrupt request is Ce accepted at the end of the instruction that is currently in +5V Ao progress. GND Active "Low". This is an interrupt request that has RFsH priority over INT and cannot be inhibited by the Co ;;rr software. NM! is always accepted, and when the instruc• " 17 NM! 1 01 RESET lion that is currently in progress finishes, interrupt iNT §"O'ffia processing is started and the Z80 CPU automatically NMi 7 WAIT starts from address 0066H. HALT 8 BUSAK Active "Low". This indicates that the HALT instrac1ion hffiEa 1 W1i is being executed. ExecUles the NOP instruction inter- 18 HALT 0 IORCl nally and also refRshes memory. The halt state is released by RESET. NMI or INT (when enabled). Active "Low". This indicates that the address bus outputs 19 MREQ 3-STATEO 1he effective memoiy addn:ss for memory rcad/wri1e. Active "Low". This indicates that the low-order 8 bits of the address bus output effective addresses of the in- 20 IORQ 3-STATE 0 put/output device for the rud/write operation with this device. This is output together with Ml during an interrupt response to indicate the response. Active "Low". This indica.1es the timing with which data 21 RD 3-STATEO from the memory or inpuUou1pu1 device is read. Active ''Low". This indicates that !he cffec1ive da1a to be 22 WR 3-STATEO writtcn to the memory or input/output device the add~s of which is specified is- on the data b\lS. When the bu.s ~ucst is acknowledged, this informs the 23 BUSAK 0 bus master which outputs the bus n:quesl that the sys1em bus can be controlled. Active "Low". Signal to infonn the CPU thac the mcmol)' or inpuVoutJ)Ut device the address of which is 24 WAIT I specified is not ready lo send data. The CPU is waiting when this signal is input. Active "Low". This has priority over NMJ and is accepted at the end of the machine cycle that is currently 25 BUSRQ I in progress. This is set to "Low" when a bus master other than the CPU wants 10 control the system bus. Active "Low". This resets the interrupt enable flag, interrupt vector ~gister and memory refresh ~gister of 26 RESET i the program counter to set the interrupt mode lo mode 0, thus initializing the Z80 CPU. Active "Low". This indicates that the machine cycle 27 Ml 0 being executed is an OP code fetch cycle. Active "Low". This indicates thal the address for refreshing the dynamic RAM is output to the low-order 7 28 RFSH 0 bits of the address bus. MREQ also goes "Low" at this time.

-4- GENESIS

IC5 65536 bit Static CMOS RAM IC UPD4364G-15L IC MB8464A-B0 IC MBB464A-10LL

■ Top view & Pin Layout ■ Block Diagram ------. Vee A5 Aft BS.538 BIT WE Al A, ADDRESS ROW (258 X 258) CE2 A11 BUFFER DECODER MEMORY CELL As A,o ARRAY A1, Ag A12 Au or A ~A : ADDRESS INPUT 1/0 ---+----i INPUT 0 12 1 OUTPUT 1Arn DATA OE : OUTPUT ENABLE INPUT CONTROL 1/0~,---+---r+-tCONTROL ct, 1/01-1/0~: DATA IN/OUTPUT Vee : +5V POWER SUPPLY 1 1107 CE,. CE,: CHIP ENABLE I, 2 INPUT 1 1/06 GNO :GROUND 1 1105 WE' : WRITE ENABLE INPUT : NO CONNECTION CE1 1 1104 NC ce'i "'1..----...... r- ol------:::::u_.; ~--1.~_r------'

■ Operation Mode CE, CE2 at WE' MODE OUTPUT STATE POWER SUPPLY CURRENT H X X X Non-select lse X L X X (Power down) High impedance L H H H Output disable L H L H Read DotIT lcc11 L H X L Write D1~

IC6 CUSTOM IC IC CUSTOM CHIP SGE FC1004 IC CUSTOM CHIP SGE FC1004 IC CUSTOM CHIP SGE FC1004 315-5487-R 837-5487-01 R 315-5487-0IR

■ Top View & Pin Layout

20B 157

158

52 105

53 104

■ Description Pin Pin Function No. Name 1/0 Function No. Name 1/0 1 SDO 5 SD4 2 SDl 6 sos l Dual port RAM interface: signals. I Dual port RAM interface signals. 3 SD2 7 SD6 4 SD3 8 SD7

-5- GENESIS

Pin; Pin Name 1/0 Function Name 1/0 Function No. No. I 9 SEI .. 59 j ZRES 1/0 280 interface signals. I 60 10 I SEO I ZBAK I 11 SC 61 I NM! 0 ! 280 interface signals. 12 RASl 62 l ZBR 0 Dual port RAM interface signals. !/0 I 3 CASI 63 i WAIT )4 WEI i 64 EOE 0 P-SRAM interface. 15 WEO 65 NOE I 16 OE! I 66 ZRAM I 0 SRAM interface. I 1-;- RD0 I 6i REF I 18 RDI 68 CAS2 ; 1/0 Dual po" RAM interface signals. 19 RD2 I 69 RAS2 20 RD3 I ! 70 ASEL 21 VSS I - I GND 71 ROM 0 22 RD4 i 72 FDC ' i 23 RDS ; 73 FDWR 24 RD6 74 CEO • 25 RD7 75 ' TIME 26 ADO I 76 CART l I I ~ 27 ADl , .. I 1Al4 0 I I uo Dual pon RAM interface signals. 28 AD2 78 WRES I 29 AD3 79 D!SK 1/0 30 AD4 ' 80 VDD - Power supply. 31 ADS 81 TESTO 1/0 Test signal. (Set to "O" certainly.) 32 AD6 82 TEST! Test signals. 33 AD7 83 TEST2 I (These pins scr to all open.) 34 VIDEOAVSS - 84 TEST3 35 .R (ANALOG) 85 PCO 36 IG (ANALOG) 0 VIDEO+PSG 86 PCJ 37 8 (ANALOG) 87 PC2 38 IVIDEOAVDD - 88 PC3 1/0 Joy pad interface. 39 YS 0 89 PC4 40 SP/\/8 1/0 90 PCS 41 VSYNC 0 91 PC6 42 CSYNC 1/0 VIDEO+-PSG 92 vss - GND 43 HSYNC 1/0 93 PBO 44 VDD - Power supply. 94 PBI 45 M3 95 PB2 I 46 NTSC 96 PB3 47 VPA 97 PB4 48 HALT 0 98 PBS · 49 RESET 68000 interface signals. 99 PB6 1/0 Joy pad Interface. 50 FC0 100 PAO I 51 FCI 10! PAI 52 MREQ 1/0 280 interface signals. 102 PAZ 53 VSS - ONO 103 PA3 54 AUSS - 104 PA4 55 MOR 0 I05 PAS PM 56 MOL - 106 PA6 57 SOUND - 107 JAP 1/0 58 SOUND IIO Use this pin set to open certainty. 108 FRES

-6- GENESIS

Pin Name Function Pin j Name 1/0 Function No. 110 I No. 109 zv 159 VA6 110 vz : 1/0 Use this pin set to open cenainly. 160 VA7 111 10 16] VAS l 12 : ZA0 ! 162 VA9 113 ZAI 163 VAlO I I 4 ZA2 )64 VAi I 115 ZA3 165 VAl2

I l 6 I ZA4 166 VA13 I I 7 ZAS : 167 VAl4 1/0 68CXJO address bus. 118 ZA6 168 VAIS 119 i ZA7 169 VAl6 LIO Z80 address bU5. I 120 I ZA8 170: VA17 ; 12] ! ZA9 i 171 I VAIS 122 I ZA10 I 172: VAJ9 123 ZAl I I 173 VA20 124 ZAl2 i 174 VA21 125 ZAJ3 175 VA22 126 ZAJ4 ; 116 I VA23 ; 127 ZAIS I ]77 SOUND - 128 SRES 178 PSG {ANALOG) 0 VIDEO+PSG I ! 129; SELi 179 $OUND AVSS - 130 CLK l/0 680'.X) interface signals. 180 vss - GND : 131 SBCR 0 VIDEO+PSG 181 INT 0 Z80 interface signals. 132 ZCLK 1/0 I Z80 interface signals. 182 BR 0 133 vss - GND 183 BGACK 1/0 134 I MCLK I 184 BG I 68(X)) interface signals. 135 EDCLK 1/0 185 IPLI 0

136 VDD - _I Power supply. 186 !PL2 ! 137 V[X) 187 !ORQ 0 138 VDJ 188 ZRD I 280 interface signals. 139 VD2 189 ZWR 1/0 ' 140 VD3 190 M! I 141 VD4 191 AS 142 VD5 192 UDS 143 VD6 193 LOS 1/0 6800Cl interface signals. 144 VD7 194 R/W 1/0 68CXXl data bus. 145 VO8 195 DTAK 146 VO9 196 UWR 0 P-SRAM interface. 147 VOI0 197 LWR 1/0 148 VDJJ 198 CASO 1/0 149 VDl2 199 RASO 0 P-SRAM interface. 150 VOJ3 200 zoo 151 VDl4 201 ZDI 152 VO15 202 2D2 153 VSS - GND 203 203 1/0 280 data bus. 154 VAl 204 ZD4 155 VAZ 205 ZDS 156 VA3 I/0 68CXXJ address bus. 206 ZD6 157 VA4 207 ZD7 158 VAS 208 VDD - Power supply. -7- GENESIS

IC7/8 65536 Word x 4bit Dynamic RAM

IC MSM4C264L-12 IC MSM4C264L-15 IC UPD41264V-12 IC MB81461-12 IC HM53461ZP-12 IC TMS4461-12SDL IC V53C261Z1O IC KM424C64Z-10 IC MSM51 C262-1 0ZS IC KM424C64Z-12

■ Outside View ■ Pin Layout

■ Block Diagram

W0 /I00 WRITE ROW DECODER ENABLE Ao DATA w,110 1 MASK/DATA IN/OUTPUT A, I BUFFER W2 110 2 (A-PORT) REGISTER A2 102,ROW (25f. X -4) W1 1101

As ADDRESS INPUT LINE 258LINE Ai DECODER

A;, 25!1K MEMORY CELL A5

ADDRESS SERIAL SIOi IN/OllTPUT POINTER SIOz (P·PORT)

LINE ADDRESS S10~ STROBE INPUT

AOW ADDRESS CAS STROBE INPUT cd5VJ WRITE BAR BITM'RITE WB/WE C)v ENABLE INCi. INPUT CLOCK OSCILLATOR 9v~ DATA TANSFER/ 15'1'/oE· OUPUT ENABLE OUTPUT

SERIAL CONTROL INPUT SC

SERIAL ENABLE INPUT ff

I I Ill....- -- ... - • - - - ... - • - ... ---- .. - - = - -- = ---- ~ = - - -•

-8- GENESIS

IC9/10 Quad Operational Ampllfier

IC LM324

■ Top View ■ Pin Layout

0 14 8 OUTI 1 14 OUT4

111

+IN 1 l0 I

.., +IN 2

0Ui2 7 ...._ ___,

IC11 RGB Encoder

IC CXA1145M-T6

■ Top View

■ Pin Layout

::, <..J 0 Cl. - -·sZ 0 !! ;':_ u = u ~~ 'i' = ~ oz ~-.:,::, t;:S ..c::, > = ='-" ~ ~o 0 "" "" ;;: ~- Ll w

- 9 - GENESIS

IC12

IC UPC7805HF

■ Top View ■ Block Diagram

:------,------~----~------,__--.------.------01~1

\ Ql4 0 ~~, ;;-~rn Ql6 Q9 . J Q17 •---r.. a13 I I R11 ~ I.JO I

IN GNDOUT R2C 'ro1

Gll Ql2

I fa: Q3 i I I

- 10 - MEGA DRIVE PAL

PARTS SPECIFICATIONS IC1 16/32-blt Microprocessor IC SCN6BOOOC8N64 IC MCBBOOOPB

■ Top View & Pin Layout ■ Signal Description

ADDRESS BU s VCC(21 >A2 3•A1 GN012l DATA BUS CLK Dio - )DI 5-DO D11 D12 AS D13 FC STATUS inc;' BUS CONTROL 0 15 { FC2 SCHS8000 GND _ofACK MICRO· - Az3 PROCESSOR E _p M11800 - A21 VMA BUS PERIPHERAL ARBITRATION Vee CON'TROL VPA !!ACK } CONTROL HALT 17 A20 r ~ ~1 A19 ffi VMA A1a SYSTEM TPL, INTERRUPT E Ai, CONTROL {=· CONTROL HALT J1iIT } VPA I A16 =

~ Al!i i15I2 Au IPL 1 1 A13 IPl..a A12 FC2 A11 FC1 Aio FC 0 Ag Al Aa Az A7 A3 1 Ar; A4 As

■ Description No. Pin Name 110 Function No. Pin Name t/0 Function No. Pin Name 110 Function I o. 22 BERR I Bus error 44 Au, 2 Ds 23 IPL,., 45 A,1 3 D2 1/0 Data bus 24 IPL, I lntemipt control 46 A1B 0 Address bus 4 D1 25 IPL. 47 Arn 5 Do 26 FCi 48 A20 6 AS 0 Address strobe 27 FC1 0 Processor status 49 Vee - Power supply 7 UDS 0 Upper data strobe 28 FC.o 50 A21 8 LOS 0 Lower data strobe 29 Ai 51 A22 a Address bus 9 R/W a Read/write 30 A2 52 A.,.. Data transfer 31 A:i 53 v.,_., GND 10 DTACK I - Acknowledge 32 A4 54 D15 11 BG 0 Bus gran1 33 As S5 D1,1 12 BGACK I Bus grant adcnowlcdge 34 At; 56 013 13 BR l Bus request 35 A1 57 D12 14 Yee - Power supply 36 A11 0 Address bus 58 D11 15 CLK I Clock 37 A11 59 D10 1/0 Data bus 16 Yss - GND 38 Arn 60 0g 17 HALT l/0 Halt 39 A11 61 Ds 18 RESET 1/0 Reset 40 A12 62 0., 19 VMA 0 Vaild memory address 41 A13 63 D,, 20 E 0 Enable 42 Au 64 D!; 21 VPA 1/0l Vaild peripheral address 43 A,,;

- 11 - MEGA DRIVE PAL

IC2/3 32768 Word x Sblt CMOS Pseudo•Statlc RAM JC HM65256BSP-15 IC UP04?832C-15 IC TC51832-12

■ Top View & Pin Layout ■ Pin Name

Pin Name Function A0~AJ4 Address input

Alo WE Write enable input As OE/RFSH Output enable Ag input/refresh input A11 OE/RFSH CE Chip enable input

1A10 1/01-1/08 Data input/output CE Vee Power supply GND Ground

■ Block Diagram OE/(RFSHJ CE WE

REFRESH REFERENCE REFRESH INNER ADDRESS VOLTAGE OSCILLATOR CLOCK CONTROLLER COUNTER GENERATOR GENERATOR

1/0 BUFFER 1/01

Ao 1 024 SENS AMP 1/0 BUFFER 1/02

1/0 BUFFER 1/03 A1

MEMORY ARRAY l{O BUFFER 1/04

l{O BUFFER 1/05 As COLUMN ADDRESS 1/0 BUFFER 1/05 BUFFER 1/0 BUS

A14 COLUMN DECODER 1/0 BUFFER 1/07

1/0 BUFFER I/Os

- 12 - MEGA DRIVE PAL

IC4 IC CUSTOM CHIP UPD92271 Pans No. : 315-5433

■ Top View 120 81

121 80

160 41

■ Pin Name No. Pin Name No. i Pin Name No. Pin Name No. Pin Name I VDD 41 I GND 81 VDD 121 i GND 2 MCLK 42 GND 82 A07 122 GND 3 CART 43 ZA4 83 A08 123 VCLK

4 ZRMM 44 I ZA3 84 A09 124 XM3 s XREF 45 I ZA2 85 AIO 125 XAS 6 XMl 46 ZAJ 86 Al I 126 LDS 7 ZRSS 47 ZA0 87 Al2 127 UDS 8 XZBR 48 QA4 88 A13 128 RWO 9 WAI 49 QA6 89 Al4 129 I DTK IO ZBAK 50 ! QA0 90 AIS 130 BG II zww 51 OAI 91 Al6 131 BGA 12 ZRR 52 QA2 92 Al7 132 BR 13 IREQ 53 QA3 93 Al8 133 HALT 14 MRQ 54 QA5 94 Al9 134 VRES 15 XNM! 55 QB4 95 A20 135 XVPA 16 ZDI 56 086 96 A21 136 FC0 17 zoo 57 QB0 97 A22 137 FC! 18 ZD7 58 OBI 98 A23 138 lXXJ 19 GND 59 082 99 GND 139 DOI 20 VDD 60 083 100 VDD 140 002 21 GND 61 OBS IOI HL 141 003 22 ZCLK 62 QCO 102 XFDW 142 004 23 WRES 63 QC! 103 XFOC 143 DOS 24 202 64 QC2 104 XDIS 144 D06 25 206 65 QC3 105 FRES 145 007 26 ZDS 66 QC4 106 VOPM 146 008 27 2D3 67 QC5 107 XROM 147 009 28 204 68 QC6 108 ASEL 148 Dl0 29 ZAF 69 TST0 109 XTIM 149 DI l 30 ZAE 70 TSTI 110 RAS2 150 Dl2 31 ZAD 71 TST2 ll l CAS2 151 D13 32 ZAC 72 XJAP 112 XOEO 152 D14 33 ZAB 73 A0J 113 CASO 153 DIS 34 ZAA 74 A02 114 SRES 154 NTS 35 ZA9 75 A03 115 XCED IS5 HSYC 36 ZA8 76 A04 116 XLWR 1S6 SOUN 37 ZA7 77 A05 117 IA14 157 INTA 38 ZA6 78 A06 118 XNOE 158 EDCK 39 ZA5 79 GND 119 XEOE 159 GND 40 VDD 80 GND 120 VDD 160 GND

- 13 - MEGA DRIVE PAL

IC6 ZSOA Central Processing Unit

ICZSOA Parts No. : 315..Q041

■ Top View & Pin Layout ■ Description

Pin Pin Name 1/0 Function 0 A10 30-40 3.$TATE 0 System address bus. A~ 1-5 AO-AlS A~ 15-12 D0-07 3-STATEl/0 System data bus. A1 7-10 A& 6 CLOCK I Receives a +SV single-phase clock signal. A; A~ Active "Low". If the input/output device issues a signal requests D3 A3 that an interrupt to the Z80 CPU and the 16 INT I intenupt enable flag is zero, this interrupt request is accepted at tlte end of the instruction that is currently in Ao progress. GND Active "Low", This is an interrupt request that has ~ priority over INT and cannot be inhibited by the Ml software. NMi is always accepted, and when the instruc- 17 NMi I 01 !!i"E'sEi' tion that is currently in progress finishes, interrupt TRT I BUSFlQ processing is started and the ZSO CPU automatically m;rr WAIT stans from address 0066H. HALT I BUSAK Active "Low". This indicated that the HALT instruction MAEO WA is being executed. Executes the NOP instruction inter- 18 HAIT 0 IOAQ t J!fD nally and also refreshes memory. The halt state is released by RESET. NMi or iITT (when enabled). Active "Low". This indicated that the address bus outputs 19 MREQ 3-STATE 0 the effective memory address for memoey read/write:. Active "Low". This indica.tcs that the low-or~kr 8 bits of the address bus output effective addresses of the in- 20 IORQ 3-STATE 0 put/outpul device for the read/write operation with this device. This is output together with Ml during an interrupt response to indicate the resoonse. Active "Low". This indicates the timing with which data 21 RD 3-STATE 0 from the memory or input/ou1put device is read. Active "Low". This indicates that the effective data to be 22 WR 3-STATE 0 written to the memoiy or inpul/output device the address of which is specified is on the data bus. When the: bus request is acknowledged, this infonns the 23 BUSAK 0 bus master which outputs the: bus request that the system bus can be controlled. Active "Low". Signal to inform the: CPU that the memory or input/output device the address of which is 24 WAIT l specified is not ready to send data. The CPU is waiting when this signal is input.

Active "Low". This has priority over NMI and IS accepted at the end of the machine cycle that is currently 25 BUSRQ I in progress. This is set to "Low" when a bus master other than the CPU wants to control the: system bus. Active "Low". This resets the interrupt enable flag, !nterrupt vector register and memory refresh register of 26 RESET I the program counter 10 set the interrupt mode to mode 0, thus initializing the ZBO CPU. Active "Low". This indicates that the machine cycle 27 Ml 0 being executed is an OP code: fetch cycle. Active .. Low~. This indicates that the address for refreshing the dynamic RAM is output to the low-order 7 28 RFSH 0 bits of the address bus. MREQ also goes "Low" at this time.

- 14 - MEGA DRIVE PAL

IC7 65536 bit Static CMOS RAM IC UPD4168C·20 IC UPD4168C-15 IC UPD4168C-15-SG IC UPD4364C-15 IC UPO4364CX IC MB8464A-15l IC TMM2064·15 IC TMM2063-12 IC HM6264L-120 IC KM6264BL-12 OIP600 IC KM6264BLS-12l DIP300 IC HM6265L-9D IC HY6264LP-15 IC KM4264L-15

■ Top View & Pin Layout ■ Block Diagram

Vee WE 115.536 BIT (258 X 256) CE2 MEMORY CELL As ARRAY Ag A11 OE A0-A 12 : ADDRESS INPUT 110 1 INPUT 1A10 OE : OUTPUT ENABLE INPUT DATA 110~-----+---.-+--lCOITTROL c'E1 110 1-1/0~: DATA IN/OUTPUT V cc : +5V POWER SUPPLY

CE 1• CE2 : CHIP ENABLE 1, 2 INPUT ADDRESS GND : GROUNO BUFFER WE : WAITE ENABLE INPUT NC : NO CONNECTION CE1 CE2 OE WE ----'-==i.J------...J

■ Operation Mode CE1 I CE2 OE ~ MODE OUTPUT STATE POWER SUPPLY CURRENT H X X X Non-select JS!I X L X X (Power down) High impedance L H i' H H Output disabli; L H j L H Read Dou-r lccA L H X L Write D1~

ICB CUSTOM IC 1C CUSTOM CHIP YM7101 Parts No. : 315-5313

■ Top View & Pin Layout

128 97

32 I 65

34 64

- 15 - MEGA DRIVE PAL

■ Description

I No. I Pin Name j 1/0 Function No. Pin Name 1/0 Function

I S00 'i 50 SBCR 0 Sub carrier output (4.47/3.58MHz clock} 2 SD 1 51 CLK0 0 Z80 CPU clock (3.58MHz) 3 SD2 52 MCK I Mas1cr clock input (53.7MHz). 4 S03 53 EOCK 1/0 Dot dock input/output (1J.4/l0.7MHz). I VRAM serial data bus. 5 S04 54 VDD I Digital VDD.

6 S05 55 CD 0 ., 5D6 56 CD 1

8 S08 57 CO2

9 SE 1 58 CD3 10 I SEo 59 CD4 I 11 I SC 60 CD5 12 RAS 1 61 CD6 0 VRAM strobe/control. 13 CAS 1 62 CD7 1/0 CPU data bus. 14 WE1 63 CD8 15 WEo 64 CD9 16 OE 1 65 CO10 17 GND I - GND 66 co 11 18 RD0 67 CD12

19 RO 1 68 CD13 20 RD2 69 CO14 21 RD3 70 CD15 1/0 VRAM data bus. 22 RD4 71 CA0

23 RD5 72 CA 1

24 RO6 73 CA2 25 RO7 74 CA 3

26 AGC - RGB analog GNO. 75 CA4 27 R (ANWNG) 76 CA5 28 G (ANLONG) 0 Lim:ar RGB output. 77 CA6 29 B (ANLDNG) 78 CA7 30 AVC - RGB analog VDO. 79 CA8 31 AD0 80 CAg

32 AO1 81 CA10 33 AO2 82 CA11 1/0 CPU address bus. 34 A03 83 CA12 1/0 VRAM address/data bus. 35 AD4 84 CA13 36 AO5 85 CA 14 37 A06 86 CA1s 38 AD7 87 CA15 39 VS 0 Transparent output. 88 CA11 40 SPA/8 1/0 Sprite timing 1/0. 89 CA1s 41 VSYNC 0 CRT Vsync out/dot clock out. 90 CA19 42 CSYNC 1/0 VIDEO-t-PSG 91 CAzo 43 HSYNC 1/0 CRT HSYNC input/output 92 CA21 44 HL I Light pen detect 93 CA22 45 SELo I CPU select (680Cl0/Z80) 94 AYS I Sound analog GNO. 46 PAL l CRT select (NTSC/PAL) 95 SOUND 0 Sound analog output. 47 RESET l Initial reset input. % AGS I Sound analog YOO.

48 SEL 1 l 68000 CPU clock (CLKI) I/0 control. 97 GND l Digital GND.

49 CLK 1 1/0 68000 CPU clock (7.67MHz) 98 INT 0 zao interface.

- 16 - MEGA DRIVE PAL

No. Pin Name I 110 Function No. Pin Name 1/0 Function 99 BR 0 114 DTAK 1/0 68(0) interface. 100 BGAK I vo 680::0 interlace. 115 UWR I IOI BG I I 116 LWR 102 MREQ I Z80 interface. 117 OEO 0 Work RA.M strobe control.

103 INTAK I 118 CAS 0 104 IPL 1 680::0 interface. 119 RAS 0 0 105 IPL2 120 RA0

106 I IORQ 121 RA 1 107 I RD 122 RA2 l ZBO interface. 108 1 WR 123 RAa Work RAM (DRAM) address/color 0 109 j Ml 124 RA4 code output. 110 AS 115 RA5 111 UDS 126 RA6 I 680::0 interface. 112 LOS 127 RA7 113 RM' 128 VDD I Digital VDD.

- 17 - MEGA DRIVE PAL

IC9/10 65536 Word x 4bit Dynamic RAM

IC M5M4C264L-12 IC MSM4C264L-15 IC UPD41264V-12 IC MB81461-12 IC HM53461 ZP-12 IC TMS4461 -12SDL IC V53C261Z10 IC KM424C64Z-10 IC MSM51 C262-1 OZS

■ Outside View ■ Pln Layout

W,,.'10, W:.,.'1O SE 3 $102 SIO, SC '-'ss SI0 1 ~!REH: Wc:,110 0 W 1/l0 1 WS/'IJE RAS A; Vee A, A, CAS

■ Block Diagram ,------, , I LINE OR ROW ADDRESS EIUFFER / ,------~,,------~ 11 W 0 110 0 WRITE ..----+-- ROW DECODER ENABLE Au 3 ~------,..------DATA 1 w, 110, I MASK ,'DATA A, EIUFFER w21102 IN/OUTPUT ,-----.::..., (A-PORT)

1024AOW (256 x 4) W, /10 3 REGISTER

ADDRESS INPUT LINE 25BUNE DECODER

I 2561< MEMORY CELL i a

25e X 4 DATA REGISTER

SERIAL ADDRESS SERIAL POINTER SlO, IN/OUTPUT IN/OUTPUT SI02 (P-PORT) LINE ADDRESS STROBE INPUT

RO\.'! ADDRESS STROBE INPUT

WRITE BAR BIT/WRITE ENABLE IND!. INPUT CLOCK OSCILLATOR DATA TRNSFER/ OUTPUT ENABLE

SERIAL CONTROL INPUT SC

SERIAL ENABLE INPUT SE ...... -- . - . - . ------. - -- -·

- 18 - MEGA DRIVE PAL

IC11 FM Sound Source/DA Converter

ICYM2612

■ Top View & Pin Layout

¢M

Vee

A Vee

MOR

■ Description No. I Pin Name 1/0 Function I GND - I Ground pin. 2 Do 3 D1 4 D2 5 03 1/0 8-bit bidirectional data bus. Communicates data with the processor. 6 04 7 05 8 D6 9 D1 10 TEST 1/0 Pin to 1cs1 this LSI. Do not connect. 11 IC l Initializes the internal register. 12 GND - Ground pin. Interrupt signal issued from the two timers. When the time programmed into the timer 13 IRQ 0 has elapsed, this goes low. Output with open drain. Control the DO - 07 daia bus. cs RD WR Al AO Details Writes register addresses of timers. etc. 0 1 0 0 0 14 cs Writes register addresses of channels 1-3. Writes register data of timers, etc. 0 1 0 D l I Writes register data of channels I -3. 0 I 0 1 0 Writes register addresses of channels 4-6. 15 WR 0 1 0 1 l Writes register data of channels 4-6. 16 RD 0 0 l 0 0 Reads staluscs. 17 Aa l X X X X 00 - D7 arc set to high-impedance. 18 A1 19 AGND - Ground pin. 20 MOR 0 Two-channel analog outputs. These are output with a source follower. 21 MOL 22 A Vee - +SV power supply pins. 23 24 IP M Vee I Master clock input.

- 19 - MEGA DRIVE PAL

IC13 RGB Encoder

IC CXA1145P

■ Top View

24 13

■ Pin Layout

--:...J § ~ o._ <'...) u D 0 _,_C, z z C,,.,. D 23~ o:z .,,_-z to- ~ C!J ="' = =a, >< "' ,.,_ §~ ""~ :> "' ':i "' "" u w

IC14 Dual Operational Ampllfler JC LM35B ■ Top View ■ Pin Layout

4 VDD

vcc B

- 20 - MEGA DRIVE PAL

IC15,17 Three Terminal Regulator

IC MA7805UC IC_M_C7805CT

■ Top View ■ Block Diagram

[>f'\11 0 "" QU J~, !m Q16. ~9 I i f.ll7 Q!3 f-----( Rlo I . ~l2

115 RP R1l IN GNDOUT tm WIP\JT 01 ~- f.lll Ql2 t'" R, C3 '

- 21 - MEGA CD I SEGA CD

PARTS SPECIFICATION IC1 16/32-Blt Microprocessor

IC MC68HC000FN12 IC HD68HC000CP-12 IC TMP68HCO00T-12

■ Top View & Pin Layout ■ Signal Description

ADDRESS SUs VCC{2J_ },\23·A1 D13 GND(2l- . Dt• DATA BUS CLK . . D15 >01 5-00 OND . Vee GND AS CLK A2J - QND "22 FCO R/W ONO PROCESSOR FC1 UDS , ASYNCHRONOUS NC STATUS BUS CONTROL FC2 ~ FiX[T "20 {~ 1'Effl" Al9 MCUHCOOO oi'ACK VMA A1B E Al7 E BA iil!I - - . mm M8800 vm: BG BUS Jl5[1 PERIPHERAL ARBITRATION IJ5IT CONTROL { = VPA_ BGACK CONTROL

{ mM_ - iPLo SYSTEM _RESET- - iPCT INTERRUPT CONTROL CONTROL HALT_ - iPII }

■ Description No. Pin Name 1/0 Function No. Pin Name 1/0 Function No. Pin Name 1/0 Function l D, 23 VPA I Valid Peripheral Add= 46 A,s 2 o~ 24 BERR I Bus Error 47 A,s 3 D2 1/0 Data Bus 25 IPL, 48 A,1 0 Address Bus 4 D, 26 IPL, I ln1errupt Control 49 A1A 5 Do 27 IPL,-, so A19 6 AS 0 Address Strobe 28 FC. 51 A20 7 UDS 0 Upper Data Strobe 29 FC1 0 Processor Status 52 Vee - Power Supply 8 LOS 0 Lower Data S1robc 30 FCo 53 A!:11 9 R/W 0 Read/Write 31 N.C - 54 An 0 Address Bus Dau Transfer 32 A1 55 Al>lll 10 DTACK I Acknowledge 33 A2 56 VAA - GND II BG 0 Bus Gran! 34 A:,\ 57 Vs.,;, 12 BGACK I Bus Grant Acknowledge 35 A.t. 58 Dis 13 BR I Bus Request 36 As 59 D14 14 Vee - Power Supply 37 A5 60 D,s 15 CLK I Clock 38 A7 61 D12 0 Address Bus 16 Vss 39 62 Di, - GND AB 17 v~~ 40 Ag 63 Din 1/0 Da1a Bus 18 NC - Not Connected 41 Arn 64 DQ 19 HALT 1/0 Halt 42 All 65 DA 20 RES 1/0 Reset 43 A12 66 D-, 21 VMA 0 Valid Memory Address 44 A1:1 67 o~ 22 E 0 Enable 45 A,. 68 [h_

- 22 - MEGA CD I SEGA CD

IC2 CUSTOM CHIP MCE2 No. 1/0 Pin Name No. 1/0 Pin Name Pans No. : 315-5548 85 - Vs.~ 147 V. 86 I IIRQ 148 1/0 809 ■ Top View 87 I IDXM 149 1/0 8010 156 105 88 I !COCK 150 1/0 BOil 89 0 OXPCM 151 1/0 8012 90 I IDTEN 152 1/0 8013 157 I 104 91 I [WAIT 153 I 1/0 8014 0 0 ! 92 0 OHRD 154 Vs.s 93 I !INT 155 110 BOIS !t4 0 I OCDC 156 110 ' BPRA0 95 0 OPROE 157 1/0 BPRAl 96 - Yss 158 110 BPRA2 97 - Ynn 159 1/0 BPRA3 1 53 0 98 0 OC2LR 160 1/0 BPRA4 99 I !Al9 161 1/0 BPRA5 52 100 I IAl8 162 !/0 BPRA6 IOI I IA17 163 1/0 BPRA7 I IA16 164 V ■ Description 102 103 I IA15 165 V No. 1/0 Pin Name No. 1/0 Pin Name 104 I IAJ4 166 1/0 BPRA8 I 0 OCK25 43 - I Vnr, 105 1/0 BAl3 167 0 OPRRAS 2 0 OBRAM 44 0 OOWE 106 1/0 BA12 168 0 OPRCAS 3 - V~s 45 l/0 BOADO l07 - v~<; 169 0 OPRUWE 4 I OXBROM 46 l/0 BOADl 108 1/0 8All 170 0 OPRLWE 5 I !ROM 47 1/0 BOAD2 109 1/0 BAlO 171 1/0 !VAi 6 I ICASO 48 1/0 BOAD3 110 1/0 BA9 172 1/0 IVA2 7 ! ILWR 49 1/0 BOAD4 111 1/0 BA8 173 1/0 IVA3 8 l JUWR 50 - V55 112 l/0 BA7 174 1/0 JVA4 9 I !ASEL 51 1/0 BOADS 113 1/0 8A6 175 1/0 !VAS lO - Yoo 52 1/0 BOAD6 I 14 - Yno 176 V l 1 I IRAS2 53 1/0 BOAO7 115 1/0 BAS 177 I/0 IVA6 12 J ICAS2 54 1/0 BODS 116 1/0 BA4 178 1/0 IVA7 13 I IFDC 55 1/0 BOD9 117 1/0 BA3 179 1/0 !VAS 14 I IFRES 56 1/0 BO010 118 1/0 BA2 180 1/0 JVA9 15 I - Yss 57 1/0 BOD11 I 19 - Vs.<; 181 1/0 !VAID 16 0 OERES 58 1/0 80012 120 1/0 BAJ 182 1/0 IVA! I 17 1/0 BEADO 59 1/0 BOD13 121 I IFC0 183 V 18 1/0 BEAD! 60 - Vss 122 I IFCI 184 1/0 IYAl2 19 1/0 BEAD2 61 - Yno 123 0 OJPLD 185 1/0 IVA13 20 1/0 BEAD3 62 1/0 B0014 124 0 OIPLI 186 1/0 1VAl4 21 1/0 BEAD4 63 1/0 B0D15 125 0 OIPL..2 187 1/0 !VAIS 22 1/0 BEADS 64 0 OLEDR 126 0 OVPA 188 1/0 JVAl6 23 1/0 BEAD6 65 0 OLEDG 127 0 ORESET ]89 V 24 1/0 BEAD7 66 0 OLATCH 128 0 OHALT 190 I IVA17 25 1/0 BEDS 67 0 OSHTT 129 0 OCLK 191 1/0 BVDO 26 - V55 68 0 OATI 130 - Vss 192 1/0 BVDI 27 - Yoo 69 0 OOTM 131 - Ynn 193 l/0 BVO2 28 l/0 BED9 70 I iWFCK 132 0 ODTACK 194 1/0 BVD3 29 1/0 BEDIO 71 I !SCOR 133 I IRXW 195 1/0 BVD4 30 1/0 BEOll 72 - Vss 134 I IXLDS 196 1/0 BVD5 31 1/0 BEDl2 73 I ISBSO 135 I IXUDS 197 1/0 BVD6 32 110 BEO!3 74 0 OEXCK 136 I IXAS 198 1/0 BVD7 33 1/0 BED14 75 I ILRCK 137 VO BOO 199 1/0 BVD8 34 1/0 BEDl5 76 I IDATA 138 1/0 80] 200 35 0 OERAS 77 I IC2PO 139 1/0 802 201 V 36 0 OECAS 78 J,0 BOB3 !40 1/0 803 202 1/0 BVD9 37 0 OEOE 79 - Ynn 141 1/0 8D4 203 1/0 BVD\O 38 - Yss 80 1/0 8D82 142 - Vss 204 1/0 BVDll 39 0 OEWE 81 1/0 BOB! 143 1/0 BDS 205 1/0 8VD12 40 0 OORAS 82 1/0 BOBO 144 1/0 8D6 206 1/0 BVDI3 41 0 OOCAS 83 0 OHOCK 145 1/0 8D7 207 1/0 BVDl4 42 0 (X)QE 84 I ICK50 146 1/0 BO8 208 1/0 BVDIS

- 23 - MEGA CD I SEGA CD

IC3 PCM Sound Source IC RFSC164A Parts No. : 315-5476A

■ Top View & Pin Layout

RAMA7 LRCLK 0AC1R 0AC1L DAC3 DATA

RAMA3 RAMA2 RAMAl RAMAO CSB A12 A11 AIO

■ Block Diagram

RAMJU4 RtlMA,3 AAIM12 ltAMAII RAMAIO RAMA9 RAMA8 RAMA7 RAMA6 HHEIINAL ADDRESS RAMA:; MEMORY POINTER RAMA4 RAWA3 IIAMA2 RAMAi DCA RAt,!AO WAVE OATA RAMAX RAMA07 R"'-MC 111 RAM4D6 RAMC28 _o, RAMA loll"-0 RAMA04 RAMA03 RAMA02 RA.MADI RAMAOO

.,______. 1-----.rL~:~Tl~M~l~NG~jCOfl~~~TIWL~!~]~::::::::::::::~~:::;: 1;:~r---::::.l~-==;~=~--KIM~$i::R16.1.. DAC I/~ "ICU:I acu; L...______,t-----t,01.RCLK t-----.o TEST!o---,+ TEST2o--+ T£ST3o--+ t--t------

- 24 - MEGA CD I SEGA CD

■ Description (IC3)

Pin Pin I Name 1/0 Function Name Function No. No. 1/0 I 78 I Al2 75 RAMAi Low address signals of the SRAM & 0 I Al I 76 RAMA0 I MROM. 80 AID 42 I RAMAX 0 LSB address signal of the MROM A9 High order 32k byte SRAM & MROM 61 RAMC2B 0 2 A8 I select si.enal. Low order 32k byte SRAM & MRO/v1 3 A7 60 RAMClB 0 select si1rnal. 1--4_.j__A_6__ 1 I Address signals from µ. P. Signal to write data to the pseudo 5 I AS 63 RAMWEB 0 SRAM or SRAM. 6 ' A4 Signal to read data from the pseudo A3 62 RAMOEB 0 SRAM. SRAM or MROM. 8 A2 31 DAC7 9 Al 32 i DAC6 10 AO Multiplex signals of "R'' and ''L" data 33 DACS 0 21 07 output m the parallel DAC. 34 DAC4 22 D6 37 DAC3 23 D5 29 SHL 0 DAC7•3 "L" data sample/hold signal. 24 I D4 !JO Data bus signals with µ P. 30 SHR 0 DACi-3 "R" data sample/hold signal. 25 D3 Signal obtained by sampling and 26 D2 39 DAC7R 0 holding the DAC7 output at SHR. 27 DI Signal obtained by sampling and 28 DO DAC7L 0 38 i holding the DAC7 output at SHL 77 CSB , Chip select signal from µ P. I Word clock signal output to the serial 13 ROB I Read signal from µ. P. 41 I WCLKI 0 DAC. 14 WRB Write signal from µ P. LR clock signal output to the serial 44 RAMAD7 When connected to a pseudo $RAM, 40 LRCLK 0 DAC. 45 RA.MAD6 these pins provide multiplex signals of Digital audio data signal output to the 46 ; RAMAD5 the low order address/data to the 36 DATA 0 serial DAC. 47 RAMAD4 SRAM, and when connected to an 1/0 MROM, these pins provide data input Bit clock signal output to the serial 48 i RAMAD3 35 BCLK 0 signal from the MROM. DAC. 49 I RAMAD2 When connected to an SRAM, these 64 RESETS j ! Reset signal 50 RAMADI pins also provide data bus signals to the An external crystal oscillator JS 51 RAMAOO SRAM. - 70 XIN I I connected. 53 RAMAl4 71 XOUT 0 A clock signal is input to XIN directly. 54 RAMA13 55 RAMAl2 16 TEST! Test signal inpUts. Normally, fixed at High order address signals of the SRAM "L". 56 RA/i.1Al l 0 17 &MROM. TEST2 I 57 RAMAIO However. TEST2 is fixed at "H" when 58 RAMA9 18 TEST3 an MROM or SRAM is used. 59 RAMAS 12 65 RAMA7 19 1---- vcc - Power supply pins. 66 RAMA6 43 67 RAMA5 Low address signals of the SRAM & 69 0 -- 68 RAMA4 MROM. 15 ~ 73 RAMA3 ,___52 GND - Ground pins. 74 RAMA2 72 Note: The interface with !he serial DAC is formed in the MSB initial mode.

- 25 - MEGA CD I SEGA CD

ICS CMOS Dynamic RAM IC UPD424270LE-i 0

■ Top View & Pin Layout

GND 11011:; 11015 l!Ol'I Input State Output l/04 U01a Operation Mode RAS CAS LW State Vee GND uw 11012 H H D : D Open Standby I/Ou H L H ! H Valid Standby lf010 L L H H Valid Read cycle 1108 1 l/09 L L L2) L 2) Open Early wrice cycle NC L L L 2) L 2) Underlined Delayed write cycle NC L L H--+L H_..L Valid Read modified wri1e cycle CAS L H D D Open RAS onlv refresh cvcle 'oE H-LI L D D Open CAS before /RAS refresh cvc!e A6 L H ...... L H H Valid High-speed page mode read cycle L H---,.L i L2) L 2) Open High-speed page mode early write cycle ¾ L H-LI L2) L 2) Underlined High-speed page mode delayed write cycle A5 L H--+L : H---+L H---,.L I Valid High-speed page mode read modified write cycle A4 Note: H=High(inac1ivc), L=Low(activc), D=Don't care. 1 GNO

IC6 Battery Back~up IC MB3790

■ Top View & Pin Layout ■ Block Diagram

ALAAM 1 e

ALARM2 7 GND i

Cf VII.Ar.I V!ATI

- 26 - MEGA CD I SEGA CD

IC 7/8 65536 Word.x-16bit Dynamic RAM

IC TC511664BZ-B0 IC TC511664ZB0

■ Top View & Pin Layo_ut ■ Pin Name

A0-A7 i Address Input

1/010 RAS I R(}W Address Strobe 11012 CA.S Column Address Strobe uw Read/Upper Bit \\'rite input L\.V Read/Lower Bil V.' rite Inpm

OE Output Enable 1/01-1/016 Data 1/0 Yee Power Supply ( +5V) Vss Ground AO N.C. Nol Connected A4 N.C. 1 Vss AS N.C. 7 CAS

1/02 1/04 l.'06 1/06 1!010 1/01:2 1/014 t/016 1/01 1/03 1/05 I.I07 I/Oil 1/011 1/013 1/015 C O O O O O O O O O O t l I t

CLOCK No.2 GAS GENERATOR

COLUMN COLUMN ADDRESS DECODER BUFFER 8 AO SENSE AMP, REFRESH A1 110 GATE CONTROLLER A2 A3 A4 REFRESH A5 COUNTER (8) a: UJ A6 :1: 0 oo A7 ROW ADDRESS a: (.) UJ 256 X 256 X 16 BUFFER (8) C

CLOCK No.1 SUB STRAIGHT BIAS AAS GENERATOR GENERATOR

- 27 - MEGA CD I SEGA CD

IC9 S•Clrcults Non•lnvertlng Bus Trancelver

IC 74HC245 ■ Top View & Pin Layout OUTPUT ENABLE G

Al A3 A4 AS AB

IC10/11 Bblt CMOS Pseudo Static RAM IC TCS 1832AF l• 1 0 IC TC51832Fl-10

■ Top View & Pin Layout ■ Pin Configuration and Pin Description

Vee Symbol Pin Name R/W

A13 A,-A,. Address Input As R/\1/ Rt:ad /Wri1e Input Ag A11 OE/ RFSH Output Enable / Refresh OE/RFSH CE Chip Enable 1Aio CE 1/0,-1/0, Data Inpu! / Output

■ Block Diagram

Voo GNO 7 COLUMN DECODER

1/01-1/08

ROW ADDRESS BUFFER (8) MEMORY ARRAY

256 X 128 X 8 REFRESH COUNTER (B)

REFRESH REFRESH CONTROLLER TIMER

- 28 - MEGA CD I SEGA CD

IC13 CD-ROM LSI IC LC8951

■ TopView 64 41

■ Description I No. ' 1/0 Pin Name No. 1/0 Pin Name No. 1/0 Pin Name No. 1/0 I Pin Name I - v._._ 21 l/0 103 41 i - Vss 61 0 ' ffip 2 0 RA6 22 1/0 I 102 42 1/0 D3 62 0 i RCS 3 0 RA7 23 1/0 I IOI 43 1/0 D4 63 0 1 HDE 4 0 RAS 24 - ! Yss 44 1/0 D5 64 - v

IC14/15/16 64k(8k x 8)blt Static RAM IC MB8464A-90 IC M B8464A-80 IC MB8464A-10LL PF-G-BND

■ Top View & Pin Layout ■ Block Diagram --OVce --0 GNO Vee WE" Al2 > CS2 C :11:1 C 0 "-s m:11:1 :e en 0 A9 Ao-A12 :Address inputs cn Ill ( MEMORYCELLARRAY n ) 2sex32xa A11 1/0 1-110 6 :Data inputs/outputs 0 •C 0 o[ m CS 1 :Chip select 1 ~ I m :ti t A10 CS2 :Chip select 2 ~ :ti A5 CS 1 OE :Output enable cs 1 I/Oil WE :Write enable A,_ 1 1f07 Vee :Power supply (-i-5V) DDRES 1/0 GATE. COLUMN GNO :Ground I BUFFER DECODER Ao NC :Not connected cs OE INPUT INPUT/OUTPUT cs BUFFER BUFFER WE cs

CS 1~ CS2 CS

- 29 - MEGA CD I SEGA CD

IC17 2•Circult D-type Flip-flop IC 74AC74 IC74VHC74

■ Top View & Pin Layout

IC1/2 18Blt Digital Filter & 16B!t D/A Converter IC LC78B1 M - C IC7883KM

■ Top View

------·-·-· 1

0 1 ·-·-----·-·-·-·--•--•-•-• I

■ Description

Pin Name 110 l Function Pin Name 1/0 Function I CHJOUT 0 ! DAC CH-1 output. 14 EMPH2 I De-emphasis setting pins. 2 VrcfH - j Reference voltage "H" input. 15 EMPHl 3 AVDD - Power supply of analog circuits. 16 DIN I Double/Nonna! speed switching pin. 4 DYDO - Power supply of digi1al circuits. 17 SOC:2 Input source select inputs. I 5 BLCK I Bit clock. 18 SOC! (PULL-DOWN) Digital audio data input. Operation mode setting pin. 19 MODE I 6 DATA I Input from the MSB in 1he bit serial (PULL-DOWN) state. 20 Test pins. (nonnally, set to "L") TEST r L/R clock input. 21 (PULL-DOWN) 7 LRCK I LRCK= "H" CHI - Ground of digital circuits. LRCK= "L" CH2 22 DGND - 8 TEST I Test pin. (normally, set to "L") Clock output. Attenua1or data input. Input from the 23 CLKOUT 0 392Fs: l /Z XOlIT 9 ATT I LSB in the bit serial state. 384Fs, 448Fs, 512Fs: XOUT lO SHIFr l Attenuator data transfer clock. input. 24 XIN I Cl)'Stal oscillator input. ll LATCH I Attenuator data latch clock input. 25 XOUT 0 Crystal osci1\ator output. Initializing signal input. 26 AGND - Ground of analog circuits. 12 IN!TB l (normally, set to "H") 27 VrefL - Reference voltage "L" input. 13 TEST I Test pin. (nonnally, scr to "L") 28 CH20UT 0 DAC CH-2 output.

- 30- MEGA CD I SEGA CD

IC3/4/5 Quad Operational Amplifier IC UPC844G2

■ Top View ■ Pin Layout 14 B 4 5 6 7 VCC

VDD 14 13 12 11

IC6 3-Termlnal Voltage Regulator IC UPC2405HF

■ Front View

1 2 3

INPUT/ GNDt ""OUTPUT

- 31 - IIU