ll(riiA" SERVICE MANUAL GENESIS MEGA DRIVE PAL MEGA CD/SEGA CD NO. 010 ISSUED APRIL, 1994 CONTENTS GENESIS VA7 PARTS SPECIFICATJONS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 2 MEGA DRIVE PAL VA6.5 PARTS SPECIFICATIONS · · · · · · · · · · · · · · · · · · · · · · · - · · · · · - · - · · 11 MEGA CD / SEGA CD PARTS SPECIFICATIONS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 22 This manual contains IC specification to be added to the manuals issued previously. Sega Enterprises, Ltd. GENESIS PARTS SPECIFICATIONS IC1 16/32•bit Microprocessor_ IC MC68HCOOOFN8 IC H068HCOOOCP8 ■ Top View & Pin Layout ■ Signal Description ADDRESS BU s VCC(2) . >A2 3-A1 D13 GND(2} . Dl4 DATA BUS CLK D15 )01 5-D<l QND GND AS CLK A.23 FCO QND A22 Rfw :: QND A21 PROCESSOR FC1 u5s ASYNCHRONOUS NC vcc STATUS ) FC2 i"7'ra" BUS CONTROL HA["t" A20 { RESET A.19 MCHHCOOO DTACK vMi A18 - e A.17 VPA A16 E BR m'iii A.15 M8800 - VM°A BUS l'l'Li" PERIPHERAL ~ ) AABITFIATION irn" CONTROL WA_ _iiGACK'- CONTROL BERFI ~ IPLg SYSTEM {-RESET,,. _ IPL1 INTERRUPT CONTROL - - CONTROL ~ HALT_ - IPTI } ■ Description No.!Pin Namei11ol Function No. Pin Name 1/0 Function No. Pin Name 1101 Function I i D, I 23 VPA ! Vailo peripheral .address 46 Ars I 2 I Ds ! 24 BERR ! Bus error 47 A16 3 D2 illO Data bus 25 IPL,, 48 A11 0 Address bus 4 D1 26 IPL, I Interrupt control 49 Ais 5 Do 27 IPL 50 Ai9 6 AS 0 Address strobe 28 FC2 51 Aro 7 UDS 0 Upper data strobe 29 FC 1 0 Processor status 52 Yee - Power supply 8 LOS 0 Lower data strobe 30 FC=o 53 A21 9 R/W 0 Read/Write 31 NC - 54 A22 0 Address bus Data transfer 32 A, 55 Azg 10 DTACK I Acknowledge 33 56 Vss A2 - GND 11 BG 0 Bus grant 34 A3 57 Vss 12 BGACK I Bus grant 11cknowledge 35 A, 58 Dis 13 BR I Bus request 36 A5 59 o,. 14 Vee - Power supply 37 ~ 60 D1.~ 15 i CLK I Clock 38 A1 61 012 0 Address bus 16 V,;,_, 39 As 62 D11 - GND I 7 ! V,;,_~ 40 Ag 63 Dio 1/0 Data bus 18 NC - Not connected 41 Aio 64 09 19 HALT 1/0 Halt 42 A11 65 Ds 20 RES 1/0 Reset 43 A12 66 07 21 VMA 0 Vaild memory address 44 A1s 67 06 22 E 0 Enable 45 Au 68 0;; -2- GENESIS IC2/3 32768 Word x Sblt CMOS Pseudo-Static RAM IC HM65256BLFP-10 IC TC51832FL-10 ■ Top View & Pin Layout ■ Pin name Pin Name Function VDD R/W A0-Al4 Address input Read/write input •13 R/W Aa Output enable Ag OE/RESH input/refresh input All OE/flFSH CE Chip enable input 1 Aw I/Ol-1/08 Data input/output cl Yoo Power supply GND Ground ■ Block Diagram 1 COLUMN DECODER 1/01-1/08 ROW ADDRESS BUFFl:R (BJ MEMORY ARRAY 256X128X8 REFRESH COUNTER (B) REFRESH REFRESH CONTROLLER TIMER -3- GENESIS IC4 ZODA Central Processing Unit IC ZBOA 315-0041 ■ Top View & Pin Layout ■ Description Pin Pin Name 1/0 Function 0 A10 30-40 A0--A15 3-STATEO System address bus. As 1-5 Ag 15-12 00-07 3-STATEf/O System data bus. A7 7-10 A6 6 CLOCK I Receives a +5V single-phase clock signal. A5 A4 Active ·'Low". If the input/output device issues a signal A3 tha I requests an interrupt to the 280 CPU and lhe 05 A2 16 INT I interrupt enable flag is zero, this interrupt request is Ce accepted at the end of the instruction that is currently in +5V Ao progress. GND Active "Low". This is an interrupt request that has RFsH priority over INT and cannot be inhibited by the Co ;;rr software. NM! is always accepted, and when the instruc• " 17 NM! 1 01 RESET lion that is currently in progress finishes, interrupt iNT §"O'ffia processing is started and the Z80 CPU automatically NMi 7 WAIT starts from address 0066H. HALT 8 BUSAK Active "Low". This indicates that the HALT instrac1ion hffiEa 1 W1i is being executed. ExecUles the NOP instruction inter- 18 HALT 0 IORCl nally and also refRshes memory. The halt state is released by RESET. NMI or INT (when enabled). Active "Low". This indicates that the address bus outputs 19 MREQ 3-STATEO 1he effective memoiy addn:ss for memory rcad/wri1e. Active "Low". This indicates that the low-order 8 bits of the address bus output effective addresses of the in- 20 IORQ 3-STATE 0 put/output device for the rud/write operation with this device. This is output together with Ml during an interrupt response to indicate the response. Active "Low". This indica.1es the timing with which data 21 RD 3-STATEO from the memory or inpuUou1pu1 device is read. Active ''Low". This indicates that !he cffec1ive da1a to be 22 WR 3-STATEO writtcn to the memory or input/output device the add~s of which is specified is- on the data b\lS. When the bu.s ~ucst is acknowledged, this informs the 23 BUSAK 0 bus master which outputs the bus n:quesl that the sys1em bus can be controlled. Active "Low". Signal to infonn the CPU thac the mcmol)' or inpuVoutJ)Ut device the address of which is 24 WAIT I specified is not ready lo send data. The CPU is waiting when this signal is input. Active "Low". This has priority over NMJ and is accepted at the end of the machine cycle that is currently 25 BUSRQ I in progress. This is set to "Low" when a bus master other than the CPU wants 10 control the system bus. Active "Low". This resets the interrupt enable flag, interrupt vector ~gister and memory refresh ~gister of 26 RESET i the program counter to set the interrupt mode lo mode 0, thus initializing the Z80 CPU. Active "Low". This indicates that the machine cycle 27 Ml 0 being executed is an OP code fetch cycle. Active "Low". This indicates thal the address for refreshing the dynamic RAM is output to the low-order 7 28 RFSH 0 bits of the address bus. MREQ also goes "Low" at this time. -4- GENESIS IC5 65536 bit Static CMOS RAM IC UPD4364G-15L IC MB8464A-B0 IC MBB464A-10LL ■ Top view & Pin Layout ■ Block Diagram ------. Vee A5 Aft BS.538 BIT WE Al A, ADDRESS ROW (258 X 258) CE2 A11 BUFFER DECODER MEMORY CELL As A,o ARRAY A1, Ag A12 Au or A ~A : ADDRESS INPUT 1/0 ---+----i INPUT 0 12 1 OUTPUT 1Arn DATA OE : OUTPUT ENABLE INPUT CONTROL 1/0~,---+---r+-tCONTROL ct, 1/01-1/0~: DATA IN/OUTPUT Vee : +5V POWER SUPPLY 1 1107 CE,. CE,: CHIP ENABLE I, 2 INPUT 1 1/06 GNO :GROUND 1 1105 WE' : WRITE ENABLE INPUT : NO CONNECTION CE1 1 1104 NC ce'i "'1..----.......r- ol-------:::::u_.; ~--1.~_r-------------' ■ Operation Mode CE, CE2 at WE' MODE OUTPUT STATE POWER SUPPLY CURRENT H X X X Non-select lse X L X X (Power down) High impedance L H H H Output disable L H L H Read DotIT lcc11 L H X L Write D1~ IC6 CUSTOM IC IC CUSTOM CHIP SGE FC1004 IC CUSTOM CHIP SGE FC1004 IC CUSTOM CHIP SGE FC1004 315-5487-R 837-5487-01 R 315-5487-0IR ■ Top View & Pin Layout 20B 157 158 52 105 53 104 ■ Description Pin Pin Function No. Name 1/0 Function No. Name 1/0 1 SDO 5 SD4 2 SDl 6 sos l Dual port RAM interface: signals. I Dual port RAM interface signals. 3 SD2 7 SD6 4 SD3 8 SD7 -5- GENESIS Pin; Pin Name 1/0 Function Name 1/0 Function No. No. I 9 SEI .. 59 j ZRES 1/0 280 interface signals. I 60 10 I SEO I ZBAK I 11 SC 61 I NM! 0 ! 280 interface signals. 12 RASl 62 l ZBR 0 Dual port RAM interface signals. !/0 I 3 CASI 63 i WAIT )4 WEI i 64 EOE 0 P-SRAM interface. 15 WEO 65 NOE I 16 OE! I 66 ZRAM I 0 SRAM interface. I 1-;- RD0 I 6i REF I 18 RDI 68 CAS2 ; 1/0 Dual po" RAM interface signals. 19 RD2 I 69 RAS2 20 RD3 I ! 70 ASEL 21 VSS I - I GND 71 ROM 0 22 RD4 i 72 FDC ' i 23 RDS ; 73 FDWR 24 RD6 74 CEO • 25 RD7 75 ' TIME 26 ADO I 76 CART l I I ~ 27 ADl , ..I 1Al4 0 I I uo Dual pon RAM interface signals. 28 AD2 78 WRES I 29 AD3 79 D!SK 1/0 30 AD4 ' 80 VDD - Power supply. 31 ADS 81 TESTO 1/0 Test signal. (Set to "O" certainly.) 32 AD6 82 TEST! Test signals. 33 AD7 83 TEST2 I (These pins scr to all open.) 34 VIDEOAVSS - 84 TEST3 35 .R (ANALOG) 85 PCO 36 IG (ANALOG) 0 VIDEO+PSG 86 PCJ 37 8 (ANALOG) 87 PC2 38 IVIDEOAVDD - 88 PC3 1/0 Joy pad interface. 39 YS 0 89 PC4 40 SP/\/8 1/0 90 PCS 41 VSYNC 0 91 PC6 42 CSYNC 1/0 VIDEO+-PSG 92 vss - GND 43 HSYNC 1/0 93 PBO 44 VDD - Power supply. 94 PBI 45 M3 95 PB2 I 46 NTSC 96 PB3 47 VPA 97 PB4 48 HALT 0 98 PBS · 49 RESET 68000 interface signals. 99 PB6 1/0 Joy pad Interface. 50 FC0 100 PAO I 51 FCI 10! PAI 52 MREQ 1/0 280 interface signals.