EXHIBIT F

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From Wikipedia, the free encyclopedia ARM The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was known as the Advanced RISC Machine, and before that as the Acorn RISC Machine. Designer ARM Holdings The ARM architecture is the most widely used 32-bit ISA in terms of numbers produced.[1][2] They were Bits 32-bit originally conceived as a processor for desktop personal computers by , a market now dominated by the x86 family used by IBM PC compatible computers. The relative simplicity of ARM processors Introduced 1983 made them suitable for low power applications. This has made them dominant in the mobile and embedded Version ARMv7 electronics market as relatively low cost and small microprocessors and microcontrollers. Design RISC As of 2007, about 98 percent of the more than one billion mobile phones sold each year use at least one ARM Type Register-Register processor.[3] As of 2009, ARM processors account for approximately 90% of all embedded 32-bit RISC processors. ARM processors are used extensively in consumer electronics, including PDAs, mobile phones, Encoding Fixed digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard Branching Condition code drives and routers. Endianness Bi

The ARM architecture is licensable. Companies that are currently or formerly ARM licensees include Alcatel- Extensions NEON, Thumb, Jazelle, VFP Lucent, Apple Inc., Atmel, Broadcom, Cirrus Logic, Digital Equipment Corporation, Freescale, Intel (through DEC), LG, Marvell Technology Group, NEC, NVIDIA, NXP (previously Philips), Oki, Qualcomm, Samsung, Registers Sharp, ST Microelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha and ZiiLABS. 16 ARM processors are developed by ARM and by ARM licensees. Prominent examples of ARM Holdings ARM processor families include the ARM7, ARM9, ARM11 and Cortex. Examples of ARM processors developed by major licensees include DEC StrongARM, Freescale's i.MX, Marvell (formerly Intel) XScale, NVIDIA's Tegra, ST-Ericsson Nomadik, Qualcomm's Snapdragon, and the Texas Instruments OMAP product line.

Contents

1 History 1.1 Acorn RISC Machine: ARM2 1.2 Apple, DEC, Intel: ARM6, StrongARM, XScale 1.3 Licensing growth 2 ARM cores 3 Architecture 3.1 Instruction set 3.1.1 RISC features 3.1.2 Conditional execution 3.1.3 Other features 3.1.4 Pipelines and other implementation issues 3.1.5 Coprocessors 3.2 Thumb 3.3 Debugging 3.4 DSP enhancement instructions 3.5 Jazelle 3.6 Thumb-2 3.7 Thumb Execution Environment (ThumbEE) 3.8 Advanced SIMD (NEON) 3.9 VFP 3.10 Security Extensions (TrustZone) 3.11 No-execute page protection 4 ARM licensees 4.1 Approximate licensing costs 5 Unix-like support 5.1 5.2 BSD 5.3 Solaris 6 See also 7 References 8 External links

History

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After achieving some success with the BBC Micro computer, Acorn Computers Ltd considered how to move on from the relatively simple MOS Technology 6502 processor to address business markets like the one that would soon be dominated by the IBM PC, launched in 1981. The (ABC) plan required a number of second processors to be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were unsuitable, and the 6502 was not powerful enough for a graphics based user interface.

Acorn would need a new architecture, having tested all of the available processors and found them wanting. Acorn then seriously considered designing its own processor, and their engineers came across papers on the Berkeley RISC project. They felt it showed that if a class of graduate students could create a competitive 32-bit processor, then Acorn would have no problem. A trip to the Western Design Center in Phoenix showed Acorn engineers Steve Furber and Sophie Wilson that they did not need massive resources and state-of-the-art R&D facilities.

Wilson set about developing the instruction set, writing a simulation of the processor in BBC Basic that ran on a BBC Micro with a 6502 second processor. It convinced the Acorn engineers that they were on the right track. Before they could go any further, however, they would need more resources. It was time for Wilson to approach Acorn's CEO, Hermann Hauser, and explain what was afoot. Once the go-ahead had been given, a small team was put together to implement Wilson's model in hardware.

Acorn RISC Machine: ARM2

The official Acorn RISC Machine project started in October 1983. VLSI Technology, Inc were chosen as silicon partner, since they already supplied Acorn with ROMs and some custom chips. The design was led by Wilson and Furber, with a key design goal of achieving low-latency input/output (interrupt) handling like the MOS Technology 6502 used in Acorn's existing computer designs. The 6502's memory access architecture had allowed developers to produce fast machines without the use of costly direct memory access hardware. VLSI produced the first ARM silicon on 26 April 1985 – it worked first time and came to be known as ARM1 by April 1985.[4] The first "real" production systems named ARM2 were available the following year. A Conexant ARM processor used mainly in routers Its first practical application was as a second processor to the BBC Micro, where it was used to develop the simulation software to finish work on the support chips (VIDC, IOC, MEMC) and to speed up the operation of the CAD software used in developing ARM2. Wilson subsequently coded BBC Basic in ARM assembly language, and the in-depth knowledge obtained from designing the instruction set allowed the code to be very dense, making ARM BBC Basic an extremely good test for any ARM emulator. The original aim of a principally ARM-based computer was achieved in 1987 with the release of the .

Such was the secrecy surrounding the ARM CPU project that when Olivetti were negotiating to take a controlling share of Acorn in 1985, they were not told about the development team until after the negotiations had been finalised. In 1992 Acorn once more won the Queen's Award for Technology for the ARM.

The ARM2 featured a 32-bit data bus, a 26-bit (64 Mbyte) address space and sixteen 32-bit registers. Program code had to lie within the first 64 Mbyte of the memory, as the program counter was limited to 26 bits because the top 6 bits of the 32-bit register served as status flags. The ARM2 was possibly the simplest useful 32-bit microprocessor in the world, with only 30,000 transistors (compare the transistor count with Motorola's six-year older 68000 model with around 70,000 transistors). Much of this simplicity comes from not having microcode (which represents about one-quarter to one-third of the 68000) and, like most CPUs of the day, not including any cache. This simplicity led to its low power usage, while performing better than the Intel 80286.[5] A successor, ARM3, was produced with a 4KB cache, which further improved performance.

Apple, DEC, Intel: ARM6, StrongARM, XScale

In the late 1980s Apple Computer and VLSI Technology started working with Acorn on newer versions of the ARM core. The work was so important that Acorn spun off the design team in 1990 into a new company called Advanced RISC Machines Ltd. For this reason, ARM is sometimes expanded as Advanced RISC Machine instead of Acorn RISC Machine. Advanced RISC Machines became ARM Ltd when its parent company, ARM Holdings plc, floated on the London Stock Exchange and NASDAQ in 1998.[6]

The new Apple-ARM work would eventually turn into the ARM6, first released in early 1992. Apple used the ARM6-based ARM 610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM 610 as the main CPU in their Risc PC computers. DEC licensed the ARM6 architecture (which caused some confusion because they also produced Alpha microprocessors)[citation needed] and produced the StrongARM. At 233 MHz this CPU drew only 1 Watt of power (more recent versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their aging i960 line with the StrongARM. Intel later developed its own high performance implementation known as XScale which it has since sold to Marvell.

Licensing growth

The ARM core has remained largely the same size throughout these changes. ARM2 had 30,000 transistors, while the ARM6 grew to only 35,000. ARM's business has always been to sell IP cores, which licensees use to create microcontrollers and CPUs based on this core. The most successful implementation has been the ARM7TDMI with hundreds of millions sold. The idea is that the Original Design Manufacturer combines the ARM core with a number of optional parts to produce a complete CPU, one that can be built on old semiconductor fabs and still deliver substantial performance at a low cost. Atmel has been a precursor design center in the ARM7TDMI-Based Embedded System.

ARM licensed about 1.6 billion cores in 2005. In 2005, about 1 billion ARM cores went into mobile phones.[7] As of January 2008, over 10 billion ARM cores have been built, and iSuppli predicts that 5 billion a year will ship in 2011.[8]

The architecture supported on smartphones, personal digital assistants and other handheld devices is ARMv5. XScale and ARM926 processors are ARMv5TE, and are now more numerous in high-end devices than the StrongARM, ARM9TDMI and ARM7TDMI based ARMv4 processors, but lower-end devices may use older cores with lower licensing costs. ARMv6 processors represented a step up in performance from standard ARMv5 cores, and are used in some cases, but Cortex processors (ARMv7) now provide faster and more power-efficient options than all those previous generations. Cortex-A targets applications processors, as needed by smartphones that previously used ARM9 or ARM11. Cortex-R targets real-time applications, and Cortex-M targets microcontrollers.

In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based on Intel Atom.[9]

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ARM cores

ARM provides a nice summary of the numerous vendors who implement ARM cores in their design (see the 2003 Line Card (http://www.arm.com/support /0141_5LineCard.pdf) ). KEIL also provides a somewhat newer nice summary of vendors of ARM based processors (http://www.keil.com/dd/parms/arm.htm) .

Architecture Cache Typical MIPS @ Family Core Feature In application Version (I/D)/MMU MHz ARMv1 ARM Evaluation System second processor for ARM1 ARM1 None (obsolete) BBC Micro Architecture 2 ARMv2 added the MUL 4 MIPS @ 8 MHz ARM2 None Acorn Archimedes, Chessmachine (obsolete) (multiply) 0.33 DMIPS/MHz instruction Integrated MEMC ARM2 (MMU), Graphics and IO processor. ARMv2a ARM250 Architecture 2a None, MEMC1a 7 MIPS @ 12 MHz Acorn Archimedes (obsolete) added the SWP and SWPB (swap) instructions. First use of a ARMv2a 12 MIPS @ 25 MHz ARM3 ARM2a processor cache 4K unified Acorn Archimedes (obsolete) 0.50 DMIPS/MHz on the ARM. v3 architecture first to support addressing 32 bits 3DO Interactive Multiplayer, Zarlink GPS ARM60 None 10 MIPS @ 12 MHz of memory (as Receiver opposed to 26 bits) ARMv3 As ARM60, cache ARM6 (obsolete) and coprocessor ARM600 bus (for FPA10 4K unified 28 MIPS @ 33 MHz floating-point unit). As ARM60, 17 MIPS @ 20 MHz ARM610 cache, no 4K unified Acorn Risc PC 600, Apple Newton 100 series 0.65 DMIPS/MHz coprocessor bus. ARM700 8 KB unified 40 MHz Acorn Risc PC prototype CPU card ARM710 As ARM700 8 KB unified 40 MHz Acorn Risc PC 700 40 MHz ARM710a As ARM700 8 KB unified Acorn Risc PC 700, Apple eMate 300 0.68 DMIPS/MHz As ARM710a, ARMv3 ARM7100 8 KB unified 18 MHz Psion Series 5 ARM7 integrated SoC. (obsolete) As ARM710a, ARM7500 4 KB unified 40 MHz Acorn A7000 integrated SoC. As ARM7500, "FE" Added FPA 56 MHz ARM7500FE 4 KB unified Acorn A7000+ Network Computer and EDO memory 0.73 DMIPS/MHz controller. Game Boy Advance, Nintendo DS, iPod, Lego 3-stage pipeline, 15 MIPS @ 16.8 MHz NXT, Atmel AT91SAM7, Juice Box, NXP ARM7TDMI(-S) none Thumb 63 DMIPS @ 70 MHz Semiconductors LPC2000 and LH754xx (http://www.standardics.nxp.com/products/lh7/) As ARM7TDMI, 8 KB unified, Psion Series 5mx, Psion Revo/Revo ARM710T 36 MIPS @ 40 MHz cache MMU Plus/Diamond Mako ARMv4T 8 KB unified, Zipit Wireless Messenger, NXP Semiconductors As ARM7TDMI, MMU with Fast ARM7TDMI ARM720T 60 MIPS @ 59.8 MHz LH7952x (http://www.standardics.nxp.com cache Context Switch /products/lh7/) Extension As ARM7TDMI, ARM740T MPU cache 5-stage pipeline, Thumb, Jazelle ARMv5TEJ ARM7EJ-S none DBX, Enhanced DSP instructions

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Apple Newton 2x00 series, Acorn Risc PC, 16 KB/16 KB, 203 MHz SA-110 Rebel/Corel Netwinder, Chalice CATS, Psion MMU 1.0 DMIPS/MHz Netbook StrongARM ARMv4 LART (computer), Intel Assabet, Ipaq H36x0, As SA-110, 16 KB/16 KB, SA-1110 233 MHz Balloon2, Zaurus SL-5x00, HP Jornada 7xx, integrated SoC MMU Jornada 560 series, Palm Zire 31 5-stage pipeline, static branch 8 KB unified, 84 MIPS @ 72 MHz ARM8 ARMv4 [10] prediction, double- Acorn Risc PC prototype CPU card ARM810 MMU 1.16 DMIPS/MHz bandwidth memory 5-stage pipeline, ARM9TDMI none Thumb Armadillo, Atmel AT91SAM9, GP32, GP2X 16 KB/16 KB, (first core), Tapwave Zodiac (Motorola i. MMU with FCSE MX1), Hewlet Packard HP-49/50 Calculators, As ARM9TDMI, ARM920T (Fast Context 200 MIPS @ 180 MHz Sun SPOT, Cirrus Logic EP9302, EP9307, cache Switch EP9312, EP9315, Samsung S3C2442 (HTC [12] ARM9TDMI ARMv4T Extension)[11] TyTN, FIC Neo FreeRunner ), Samsung S3C2410 (TomTom navigation devices)[13] NXP Semiconductors LH7A40x As ARM9TDMI, 8 KB/8 KB, ARM922T (http://www.standardics.nxp.com/products caches MMU /lh7a/) As ARM9TDMI, 4 KB/4 KB, GP2X (second core), Meizu M6 Mini ARM940T caches MPU Player[14][15] Thumb, Enhanced variable, tightly Nintendo DS, Nokia N-Gage, Canon PowerShot ARM946E-S DSP instructions, coupled A470, Canon EOS 5D Mark II[16], Conexant caches memories, MPU 802.11 chips, Samsung S5L2010 Thumb, Enhanced ARMv5TE ARM966E-S no cache, TCMs [17] DSP instructions ST Micro STR91xF, includes Ethernet NXP Semiconductors LPC2900 ARM968E-S As ARM966E-S no cache, TCMs (http://www.standardics.nxp.com/products /lpc2000/lpc29xx/) Mobile phones: Sony Ericsson (K, W series); Siemens and Benq (x65 series and newer); LG Arena; Texas Instruments OMAP1710, OMAP1610, OMAP1611, OMAP1612, OMAP-L137, OMAP-L138; Qualcomm MSM6100, MSM6125, MSM6225, MSM6245, MSM6250, MSM6255A, MSM6260, ARM9E MSM6275, MSM6280, MSM6300, MSM6500, MSM6800; Freescale i.MX21, i.MX27, Atmel Thumb, Jazelle variable, TCMs, 220 MIPS @ AT91SAM9, NXP Semiconductors LPC3000 ARMv5TEJ ARM926EJ-S DBX, Enhanced MMU 200 MHz, (http://www.standardics.nxp.com/products DSP instructions /lpc3000/) , GPH Wiz, Marvell Feroceon (ex.: SheevaPlug), NEC C10046F5-211-PN2-A SoC – undocumented core in the ATi Hollywood graphics chip used in the Wii,[18] Samsung S3C2412 used in Squeezebox Duet's Controller. Squeezebox Radio; NeoMagic MiMagic Family MM6, MM6+, MM8, MTV; Buffalo TeraStation Live (NAS); Telechips TCC7801, TCC7901;ZiiLABS' ZMS-05 . Clockless no caches, ARMv5TE ARM996HS processor, as TCMs, MPU ARM966E-S 6-stage pipeline, Thumb, Enhanced 32 KB/32 KB, ARM1020E DSP instructions, MMU ARMv5TE (VFP) 16 KB/16 KB, ARM10E ARM1022E As ARM1020E MMU Thumb, Jazelle DBX, Enhanced variable, MMU ARMv5TEJ ARM1026EJ-S Western Digital MyBook II World Edition DSP instructions, or MPU (VFP)

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