The Essential Guide to Data Conversion

Analog-to-Digital Converter AC Performance Specifications Analog Input/Output Configurations

The Essential Guide to Data conversion SNR (Signal-to-Noise Ratio, dB or dBFS) FULL-SCALE (()FS) The ratio of the RMS value of the measured output signal (peak or full VIN scale) to the RMS sum of all other spectral components excluding the first UNIPOLAR SINGLE-ENDED FS 6 harmonics and DC. 0V Single-ended signalingis most common. INPUT SIGNAL LEVEL (CARRIER) RMSSignal = (FSR / 2) / √(2), RMSNoise = Qn = q / √(12) Example: UnipolarDifferential (n –1) VIN− Differential signals measure the difference in voltage between the “Real-World” Sampled Data Systems Consist of ADCs and DACs Time Domain DAC Output SNR(dB) = RMSSignal / RMSNoise = 20 ×log(2 × √6)) = 6.02 ×n + 1.76 UNIPOLAR DIFFERENTIAL VIN+ VIN– FS VIN+ 1.5V positive and negative input terminals. SFDR (dBFS) VIN+ The inputs are 180 degrees out of phase with each other. SINAD (Signal-to-Noise Ratio and Distortion, dB) 0V SFDR (dBc) 1V p-p ANALOG DIGITAL The ratio of the RMS signal amplitude to the RMS value of the sum of all +FS/2 Many benefits in using differential inputs. GLITCH dB VIN Vcm OVERSHOOT CLOCK / DATA Clock to output delay other spectral components including harmonics, but excluding DC. BIPOLAR SINGLE-ENDED Vcm= 1 VDC 1V FEEDTHROUGH IMPULSE 0V + Input transient reduction ENERGY SINAD (dB) = –20 ×log (√(10(–SNRW/O DIST/10) + 10(THD/10))) – 1V p-p Input noise reduction ADC Group delay due to DAC propagation delay −FS/2 Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) ENOB (BITS) = (SINAD –1.76 + 20 ×log (FSR/Actual FSR)) / 6.02 NON-IDEAL WORST SPUR LEVEL VIN– 050.5V Signal swing is doubled allow DSPs to interact with real-world signals. Settling time VIN− +FS/2 SENSOR CHANNEL DSP MEMORY RESPONSE THD (Total Harmonic Distortion, dBc) BIPOLAR DIFFERENTIAL Pseudo differential is a single-ended/differential hybrid. Real-world signals are continuous (analog) signals. SETTLING DNL ERROR 1LSB 0V Measured relative to output signal alone Separation of signal ground from ADC ground for the ADC conversion Pressure sensor ERROR The ratio of the RMS sum of the first 6 harmonics to the RMS value of the VIN+

T −FS/2 DAC BAND Time between when signal leaves ±0.5 LSB error band to when it measured fundamental. VIN(adc) = VIN+ –VIN–= 2 V p-p

PU Consider ADC common-mode requirements Vcm= (Vp + Vn) / 2. Temperaturese sensoensorre, ettcc. IDEAL (–2ND HAR/20) 2 (–3RD HAR/20) 2 (–6TH HAR/20) 2 T remains within ±0.5 LSB error band of final value THD (–dB)=) = 20 × log(g (√((√((10 ) +(+ (1100 ) +(+… (1100 ) ) Consider differential common-mode requirements RESPONSE NONLINEAR VIN+

OU PSEUDO DIFFERENTIAL

DE The ADC converts VIN+ –VIN–.

G Real-world signal processing allows for efficient and cost effective E AL U U O SLEWING FS T L SFDR (Spurious-Free Dynamic Range, dB or dBFS)

OG Slew rate GI extraction of information from a signal.

VA LOW DC DI

ANAL VIN− AL AMPLIT Signal amplitude Defined as maximum rate of change of voltage or current at output f The ratio of the RMS value of the peak signal amplitude (or full-scale) to INPUT 0, DC FREQUENCY s 0V TIME TIME AN the RMS value of the amplitude of the peak spurious spectral component.

Phase, etc. C 2 CLOCK / DATA Specifiedad assV V/se/secc or A/sec dependingdependingo onnD DACAC outpuoutputts stagtagee The peak spurious component may or may not be a harmonic. ADC SAMPLEDSAMPLED AND DAC RECONSTRUCTED DA FEEDTHROUGH QUANTIZED WAVEFORM WAVEFORM Digital information differs from real-world information in two important Typically measured for full-scale step size with 10% to 90% error band respects…it is sampled, and it is quantized. Both of these restrict how muchih inftformatiidon a diiigittlal silignal can contitain. CLOCK TO Glitch impulse energy OUTPUT DELAY CdCaused by unequal propagation dldelays within DAC CODE = CODE = CODE = CODE = CODE = ZEROSCALE ZEROSCALE MIDSCALE MIDSCALE MIDSCALE + 1 Often measured for midscale LSB transition (011..111 to 100..000) What Resolution Do I Need? Dynamic Range vs. Signal-to-Noise Ratio Requirements TIME T1 T2 T3 T4 T5 Measured as “area” of glitch impulse with units p/nV-s or p/nA-s Oversampling Relaxes Requirements on Baseband Antialiasing Filter Converter Resolution, INL, and DNL Dynamic Range (DR) is the difference in level between the highest signal Oversampling Relaxes Requirements on Baseband Antialiasing Filter peak that can be reproduced byyy the system and the amplitude of the Signal-to-NiNoise RtRatiio (SNR) itis thhe difference in lllevel btbetween the RMS Frequency Domain DAC Output highest spectral component of the noise floor. signal level and the RMS level of the noise floor, except the first six DR provides amplitude range so the converter can “see” the signal of interest. harmonics and DC. ADC FULL-SCALE (dBFS) 0 Converter resolutionr epresentst he analog signal at an umbero fd iscrete levels Converter DR is limited by SFDR and, theoretically, by its resolution. A B SNR limits the capability offt thhe IDEAL or steps. 20 N=12 BITS f CiConsiddier using analilog gain tito increase DR capability oftf thhte system. converter to see “small” signals. #OFFFT PTS a fs – fa fa Kfs– fa M=4096 The smallest resolvable signal is 1 Least Significant Bit (LSB), which is equal FULL-SCALE Sinc(x) FS = 245.76MSPS FS Converter SNRis, theoretically, 40 74dB=6.02N+1.76dB=SNR FS to FS/8 in this example. –x dB FROM FULL-SCALE (dBFS) BINSPA CING = IDEAL Generally an antialiasing filter is required on the analog front end of an ADC. 4096 7/8 SINC ATTENUATION DAC’s time domain step response (zero-order hold) modifies DAC limited by its resolution. ItIntegralNl Nonlinearity (INL)i) is a measure oftf thhe maximum dideviation iLin LSSBBs, from –3.9dBc @ FDAC/2 frequency response If the sampling frequency is not much greater than the max input frequency f , then ) 60 a Quantization noise of an 6/8 INL a straight line passing through negative full-scale and positive full-scale. dB FUNDAMENTA L the requirements on an antialiasing filter can be severe, as in (A). DYNAMIC RMSQUANTIZATIONNOISE LEVEL

DAC output signals are attenuated by sin(πf/fdac)/(π f/fdac) envelope RANGE ideal ADC will have an E( 74dB

Good INL is required for open-loop systems and many closed-loop systems. DESIRED SIGNAL IMAGES G SIGNAL 80 5/8 DNL The dotted regions indicate where the dynamic range can be limited by signals SNR= 6.02N + 1.76 (dB), UD M DYNAMIC VGA ADC IT 33dB =10log () DR AMPLITUDE AMPLITUDE 10 2 =FFTNOISEFLOOR (PER BIN) Differential Nonlinearityy( (DNL) is the difference between the actual step size and Harmonics outside the bandwidth of interest. RANGE AAF N = Number of bits. PL M 100 4/8 the ideal 1 LSB change between two adjacent codes. A ACTUAL Created by DAC’s static and dynamic nonlinearities SIGNAL CHAIN Effective Number of Bits 107dB 1 LSB ANALO DNLerror results in: Oversampling relaxes the requirements of the analog antialiasing filter as ANALO G (ENOB) is calculated from SNR: 120 3/8 SFDR (dBc) FREQUENCY FREQUENCY shown in (B). F QUANTIZATION Smaller or larger step sizes than the ideal Images ENOB = (SNR–1.76) / 6.02 (bits). S

(dB) 2 UNCERTAINTY B) DAC CLOCK FEEDTHROUGH Sigma-deltaca convertersonvertersa arree aag goodood example. 78 =10log10(FS/2)=NOISEFLOOR(PERHz)

(d nd rd

Additive noise/spursb eyondt he effectso fq uantization 2/8 2 AND 3 Duplicate of the desired signal (and its DAC induced harmonics) at BITS 140 NON-MONOTONIC de Example: 10-bit ADC with an FSR = 4 V p-p has an LSB = 3.9 mV p-p or 4/2 .

tu 152dB li ITUDE HARMONICS A DAC is monotonic if its output increases or remains the same for an increment p higher Nyquist zones Outputs of DACs need filtering also, and these are called “anti-imaging” 1/8 Therefore, 4 V / 3.9 mV = 1024 codes. This can also be expressed in dB or 20 ×log 160 Am DESIRED SIGNAL in the digital code, i.e., DNL > –1 LSB(a key requirement in a control system). filters. They serve essentially the same purpose as the antialiasing filter (1024) = 60 dB. FREQUENCY(Hz) AMPL 2nd AND 3rd IMAGE HARMONICS Images are predicted by sampling theory f f Conversely, a DAC is nonmonotonic if the output decreases for an increment s s Kfs Kfs ahead of an ADC. 000 001 010 011 100 101 11 0 111 000 001010 011100 101110 111 in theed digitaigitall code. SFDR 2 2 DIGITAL INPUT An ADC has no missing codes if the input voltage is swept over the entire input NSDD( (dBm/HzdBm/Hz) Measured with single-tone output in first Nyquist band (unit is dBc) STOPBAND AT TENUATION = DR STOPBANDATTENUATION = DR DIGITAL range and all output code combinations appear at the converter output. A DNL TRANSITION BAND: fa to fs – fa TRANSITION BAND: fa to Kfs – fa error of > –0.99 LSB guarantees that the converter will have no missing codes. Difference between single-tone amplitude to the next highest spurious tone CORNER FREQUENCY: fa CORNER FREQUENCY: fa FDAC/2 FDAC Noise Spectral Density (NSD) Quantization: Converter Circuits FREQUENCFrequency Y Integration of the noise floor in a small frequency band (unit is The Size of a Least Significant Bit (LSB) Converter Errors (Unipolar) dBm/Hz or nV/rtHz) DAC Amplifier Coupled Circuit DAC Definitions 500Ω POSITIVE VDD GAIN AND GAIN ERROR FULL-SCALE AV DD OFFSET Zero-Code Error is the measured output voltage from VOUT of the DAC ERROR NEGATIVE ERROR when zero code (all zeros) is loaded to the DAC register. Nyquist’s Criteria Theoretical SNR and ENOB Due to Jitter vs. Full-scale Sinewave Analog Input Frequency 225Ω GAIN ERROR VOLTA GE IOUTB RESOLUTION N2N ppmFS% FS dBFS Zero-Code Error is typically expressed in LSBs. (2 V/10 V FS) DAC AMP 225Ω IOUTA DAC Offset Error is a measure of the difference between the actual VOUT 2-bit40.5/2.5 V250,000 25 –12 GND OUTPUT Theoretical SNR and ENOB Due to Jitter vs. Full-Scale Sine Wave VOLTA GE OUTPUT and the ideal VOUT in the linear region of the transfer function. Offset error COPT AVSS 4-bit16125/625 mV 62,500 6.25 –24 ROPT AVDD AlAnalog ItInput Frequency 25Ω 25Ω ACTUAL VOLTA GE can be negative or positive in the DAC and output amplifier. AMPLITUDE 6-bit6431.3/156 mV 15,625 1.56 –36 1kΩ IDEAL ACTUAL Offset Errorir isst typicallyypically expresseexpressedd in mV or mA. 500Ω IDEAL 130 8-bit 256 7.8/39.1m1 mVV 3906 0.39 –48 fa IMAGE ZERO-CODE DAC Gain Error is a measure of the span error of the DAC. It is the deviation 10-bit 1024 2/9.77 mV 9770.098 –60 ERROR RMSJITTER TOTA L JITTER = t j (RMS) The total amount of jitter is dependent on in slope of the actual DAC transfer characteristic from the ideal. NYQUISTZONE1 120 (BASEBAND) Undersampledanalog signal fa sampled @ Fs has images theee effectivffectiveae apertureperture jitterjitter within the 12-bit 4096 0.49/2.44 mV 2440.024 –72 Gain Errosor is usuallyey expressedessed as apa peecrceetntageageo of tethe full-scaaele ragangee. 0.125 ps 1 POSITIVE (l(alii)ases) at|t | ± KF ± f |K|, K = 050.5, 111, 1.5 … 11 0 converter, as well as the external jitter 14-bit 16,384 122/610 µV 61 0.0061 –84 ADC Amplifier Coupled Circuit DAC CODE OFFSET s a 0.25 ps SNR = 20log π DAC CODE FREQUENCY 10 2 ftj Full-Scale Erroris a measure of the output error when full-scale code 0 0.5 ps 16 BITS generated by the sampling clock circuit. 16-bit 65,536 30.5/153 µV 15 0.0015 –96 AMP-AVDD NYQUISTZONE2 0.5Fs 100 AV DD DRVDD (0xFFFF) is loaded into the DAC register. Ideally, the output should be VREF A signal with a maximum frequency fa must be sampled at a rate These terms are root sum squared to determine 18-bit 262,144 7.6/38 µV 40.0004 –108 1 ps 205Ω − 1 LSB. (Full-Scale Error = Offset Error + Gain Error) B Fs > 2fa or information about the signal will be lost because of thete totaotall amountto offj jitteitterra appliedpplied to thees signaignall 24Ω 0.1µF 33Ω d 90 2 ps 14 BITS 20-bit 1,048,576 1.9/9.54 µV 10.0001 –120 VIN+ BUFFERED OR Full-Scale Error is typically expressed as a percentage of the full-scale range. UNBUFFERED ADC aliasing. chain. ANALOG 200Ω dV 22-bit 4,194,304 0.47/2.38 µV 0.24 0.000024 –132 INPUT +VS IN 10kΩ 10kΩ GAIN AND Deadband Errors, DACs with integrated output amplifiers will have 80 62Ω VOCM 12 BITS TOTA L JITTER = 24-bit 16,777,216 11 9/596 nV*0.060.000006 –144 G=UNITY REQUIRED FOR 2p RC OFFSET Aliasing occurs whenever F < 2f . ENOB UNBUFFERED ADC DEADBAND CODES performance degradation, deadbands, at codes outside of the linear region s a 0.1µF 10kΩ 200Ω ERROR NYQUISTZONE3 NR (ADC APERTURE JITTER) 2 + (SAMPLING CLOCK JITTER) 2 –VS 10kΩ ADCINTERNAL Fs 70 *600 nV is the Johnson Noise in a 10 kHz BW of a 2.2 kΩ resistor @ 25°C. 33Ω INPUTZ of ththee output amplifier. S AMPLIFIER 27Ω The concept of aliasing is widely used in communications 10 BITS 24Ω VIN– FULL-SCALE FOOTROOM The number of deadband codes depends on the DAC output voltage span, the Remember: 10 bits and 10 V FS yields an LSB of 10 mV, 1000 ppm, or 0.1%. 0.1µF OUTPUT 60 ERROR VCM ERROR headroom and footroom of the amplifier, and the power supply rails used. applications such as direct IF-to-digital conversion. (All other values may be calculated by powers of 2.) 205Ω VOLTA GE ZERO-CODE fa VOLTAGE In this example, if a 12-bit ENOB, 74 dB SNR ACTUAL NEGATIVE ERROR 0.1µF OFFSET 50 is desired for the design with an analog IDEAL ADCCe Definitotions A signal that has frequency components between fa and fb must be sampled at a rate F > 2 (f –f) in order to prevent alias inpuinputtf frequencrequencyyo off1 10000 MHztz, thenhent thhee total ADC Offset Error is the deviation of the first code transition, for example NYQUISTZONE4 1.5Fs s b a 40 jitter required must be 0.5 ps or less. (000…000) to (000…001) from the ideal (AGND + 1 LSB). Offset error is components from overlapping the signal frequencies. NEGATIVE typically expressed in LSBs. 30 OFFSET DAC CODE ADC Gain Error is the deviation of the last code transition, for example 110 100 1000 ENCODE (111…110) to (111…111) from the ideal (V –1 LSB) after the offset error is REF 2Fs adjusted out. Gain error for an ADC does not include the reference error FULL-SCALE ANALOG INPUT FREQUENCY IN MHz dt andid isst typicallyypically expressedexpressedi inn LSBs.

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